drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15d.h"
  29 #include "soc15_common.h"
  30 #include "mmsch_v1_0.h"
  31
  32 #include "vega10/soc15ip.h"
  33 #include "vega10/UVD/uvd_7_0_offset.h"
  34 #include "vega10/UVD/uvd_7_0_sh_mask.h"
  35 #include "vega10/VCE/vce_4_0_offset.h"
  36 #include "vega10/VCE/vce_4_0_default.h"
  37 #include "vega10/VCE/vce_4_0_sh_mask.h"
  38 #include "vega10/NBIF/nbif_6_1_offset.h"
  39 #include "vega10/HDP/hdp_4_0_offset.h"
  40 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  41 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  42
  43 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  44 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int uvd_v7_0_start(struct amdgpu_device *adev);
  47 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  48 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  49
  50 /**
  51  * uvd_v7_0_ring_get_rptr - get read pointer
  52  *
  53  * @ring: amdgpu_ring pointer
  54  *
  55  * Returns the current hardware read pointer
  56  */
  57 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
  62 }
  63
  64 /**
  65  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware enc read pointer
  70  */
  71 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         if (ring == &adev->uvd.ring_enc[0])
  76                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
  77         else
  78                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
  79 }
  80
  81 /**
  82  * uvd_v7_0_ring_get_wptr - get write pointer
  83  *
  84  * @ring: amdgpu_ring pointer
  85  *
  86  * Returns the current hardware write pointer
  87  */
  88 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
  89 {
  90         struct amdgpu_device *adev = ring->adev;
  91
  92         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
  93 }
  94
  95 /**
  96  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware enc write pointer
 101  */
 102 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         if (ring->use_doorbell)
 107                 return adev->wb.wb[ring->wptr_offs];
 108
 109         if (ring == &adev->uvd.ring_enc[0])
 110                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
 111         else
 112                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
 113 }
 114
 115 /**
 116  * uvd_v7_0_ring_set_wptr - set write pointer
 117  *
 118  * @ring: amdgpu_ring pointer
 119  *
 120  * Commits the write pointer to the hardware
 121  */
 122 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 123 {
 124         struct amdgpu_device *adev = ring->adev;
 125
 126         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 127 }
 128
 129 /**
 130  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the enc write pointer to the hardware
 135  */
 136 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         if (ring->use_doorbell) {
 141                 /* XXX check if swapping is necessary on BE */
 142                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 143                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 144                 return;
 145         }
 146
 147         if (ring == &adev->uvd.ring_enc[0])
 148                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
 149                         lower_32_bits(ring->wptr));
 150         else
 151                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
 152                         lower_32_bits(ring->wptr));
 153 }
 154
 155 /**
 156  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 157  *
 158  * @ring: the engine to test on
 159  *
 160  */
 161 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 162 {
 163         struct amdgpu_device *adev = ring->adev;
 164         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 165         unsigned i;
 166         int r;
 167
 168         if (amdgpu_sriov_vf(adev))
 169                 return 0;
 170
 171         r = amdgpu_ring_alloc(ring, 16);
 172         if (r) {
 173                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 174                           ring->idx, r);
 175                 return r;
 176         }
 177         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 178         amdgpu_ring_commit(ring);
 179
 180         for (i = 0; i < adev->usec_timeout; i++) {
 181                 if (amdgpu_ring_get_rptr(ring) != rptr)
 182                         break;
 183                 DRM_UDELAY(1);
 184         }
 185
 186         if (i < adev->usec_timeout) {
 187                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 188                          ring->idx, i);
 189         } else {
 190                 DRM_ERROR("amdgpu: ring %d test failed\n",
 191                           ring->idx);
 192                 r = -ETIMEDOUT;
 193         }
 194
 195         return r;
 196 }
 197
 198 /**
 199  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 200  *
 201  * @adev: amdgpu_device pointer
 202  * @ring: ring we should submit the msg to
 203  * @handle: session handle to use
 204  * @fence: optional fence to return
 205  *
 206  * Open up a stream for HW test
 207  */
 208 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 209                                        struct dma_fence **fence)
 210 {
 211         const unsigned ib_size_dw = 16;
 212         struct amdgpu_job *job;
 213         struct amdgpu_ib *ib;
 214         struct dma_fence *f = NULL;
 215         uint64_t dummy;
 216         int i, r;
 217
 218         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 219         if (r)
 220                 return r;
 221
 222         ib = &job->ibs[0];
 223         dummy = ib->gpu_addr + 1024;
 224
 225         ib->length_dw = 0;
 226         ib->ptr[ib->length_dw++] = 0x00000018;
 227         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 228         ib->ptr[ib->length_dw++] = handle;
 229         ib->ptr[ib->length_dw++] = 0x00000000;
 230         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 231         ib->ptr[ib->length_dw++] = dummy;
 232
 233         ib->ptr[ib->length_dw++] = 0x00000014;
 234         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 235         ib->ptr[ib->length_dw++] = 0x0000001c;
 236         ib->ptr[ib->length_dw++] = 0x00000000;
 237         ib->ptr[ib->length_dw++] = 0x00000000;
 238
 239         ib->ptr[ib->length_dw++] = 0x00000008;
 240         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 241
 242         for (i = ib->length_dw; i < ib_size_dw; ++i)
 243                 ib->ptr[i] = 0x0;
 244
 245         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 246         job->fence = dma_fence_get(f);
 247         if (r)
 248                 goto err;
 249
 250         amdgpu_job_free(job);
 251         if (fence)
 252                 *fence = dma_fence_get(f);
 253         dma_fence_put(f);
 254         return 0;
 255
 256 err:
 257         amdgpu_job_free(job);
 258         return r;
 259 }
 260
 261 /**
 262  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 263  *
 264  * @adev: amdgpu_device pointer
 265  * @ring: ring we should submit the msg to
 266  * @handle: session handle to use
 267  * @fence: optional fence to return
 268  *
 269  * Close up a stream for HW test or if userspace failed to do so
 270  */
 271 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 272                                  bool direct, struct dma_fence **fence)
 273 {
 274         const unsigned ib_size_dw = 16;
 275         struct amdgpu_job *job;
 276         struct amdgpu_ib *ib;
 277         struct dma_fence *f = NULL;
 278         uint64_t dummy;
 279         int i, r;
 280
 281         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 282         if (r)
 283                 return r;
 284
 285         ib = &job->ibs[0];
 286         dummy = ib->gpu_addr + 1024;
 287
 288         ib->length_dw = 0;
 289         ib->ptr[ib->length_dw++] = 0x00000018;
 290         ib->ptr[ib->length_dw++] = 0x00000001;
 291         ib->ptr[ib->length_dw++] = handle;
 292         ib->ptr[ib->length_dw++] = 0x00000000;
 293         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 294         ib->ptr[ib->length_dw++] = dummy;
 295
 296         ib->ptr[ib->length_dw++] = 0x00000014;
 297         ib->ptr[ib->length_dw++] = 0x00000002;
 298         ib->ptr[ib->length_dw++] = 0x0000001c;
 299         ib->ptr[ib->length_dw++] = 0x00000000;
 300         ib->ptr[ib->length_dw++] = 0x00000000;
 301
 302         ib->ptr[ib->length_dw++] = 0x00000008;
 303         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 304
 305         for (i = ib->length_dw; i < ib_size_dw; ++i)
 306                 ib->ptr[i] = 0x0;
 307
 308         if (direct) {
 309                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 310                 job->fence = dma_fence_get(f);
 311                 if (r)
 312                         goto err;
 313
 314                 amdgpu_job_free(job);
 315         } else {
 316                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 317                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 318                 if (r)
 319                         goto err;
 320         }
 321
 322         if (fence)
 323                 *fence = dma_fence_get(f);
 324         dma_fence_put(f);
 325         return 0;
 326
 327 err:
 328         amdgpu_job_free(job);
 329         return r;
 330 }
 331
 332 /**
 333  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 334  *
 335  * @ring: the engine to test on
 336  *
 337  */
 338 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 339 {
 340         struct dma_fence *fence = NULL;
 341         long r;
 342
 343         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 344         if (r) {
 345                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 346                 goto error;
 347         }
 348
 349         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
 350         if (r) {
 351                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 352                 goto error;
 353         }
 354
 355         r = dma_fence_wait_timeout(fence, false, timeout);
 356         if (r == 0) {
 357                 DRM_ERROR("amdgpu: IB test timed out.\n");
 358                 r = -ETIMEDOUT;
 359         } else if (r < 0) {
 360                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 361         } else {
 362                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 363                 r = 0;
 364         }
 365 error:
 366         dma_fence_put(fence);
 367         return r;
 368 }
 369
 370 static int uvd_v7_0_early_init(void *handle)
 371 {
 372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 373
 374         if (amdgpu_sriov_vf(adev))
 375                 adev->uvd.num_enc_rings = 1;
 376         else
 377                 adev->uvd.num_enc_rings = 2;
 378         uvd_v7_0_set_ring_funcs(adev);
 379         uvd_v7_0_set_enc_ring_funcs(adev);
 380         uvd_v7_0_set_irq_funcs(adev);
 381
 382         return 0;
 383 }
 384
 385 static int uvd_v7_0_sw_init(void *handle)
 386 {
 387         struct amdgpu_ring *ring;
 388         struct amd_sched_rq *rq;
 389         int i, r;
 390         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 391
 392         /* UVD TRAP */
 393         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
 394         if (r)
 395                 return r;
 396
 397         /* UVD ENC TRAP */
 398         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 399                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
 400                 if (r)
 401                         return r;
 402         }
 403
 404         r = amdgpu_uvd_sw_init(adev);
 405         if (r)
 406                 return r;
 407
 408         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 409                 const struct common_firmware_header *hdr;
 410                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 411                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 412                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 413                 adev->firmware.fw_size +=
 414                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 415                 DRM_INFO("PSP loading UVD firmware\n");
 416         }
 417
 418         ring = &adev->uvd.ring_enc[0];
 419         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 420         r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
 421                                   rq, amdgpu_sched_jobs);
 422         if (r) {
 423                 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 424                 return r;
 425         }
 426
 427         r = amdgpu_uvd_resume(adev);
 428         if (r)
 429                 return r;
 430         if (!amdgpu_sriov_vf(adev)) {
 431                 ring = &adev->uvd.ring;
 432                 sprintf(ring->name, "uvd");
 433                 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 434                 if (r)
 435                         return r;
 436         }
 437
 438         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 439                 ring = &adev->uvd.ring_enc[i];
 440                 sprintf(ring->name, "uvd_enc%d", i);
 441                 if (amdgpu_sriov_vf(adev)) {
 442                         ring->use_doorbell = true;
 443
 444                         /* currently only use the first enconding ring for
 445                          * sriov, so set unused location for other unused rings.
 446                          */
 447                         if (i == 0)
 448                                 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 449                         else
 450                                 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 451                 }
 452                 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 453                 if (r)
 454                         return r;
 455         }
 456
 457         r = amdgpu_virt_alloc_mm_table(adev);
 458         if (r)
 459                 return r;
 460
 461         return r;
 462 }
 463
 464 static int uvd_v7_0_sw_fini(void *handle)
 465 {
 466         int i, r;
 467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 468
 469         amdgpu_virt_free_mm_table(adev);
 470
 471         r = amdgpu_uvd_suspend(adev);
 472         if (r)
 473                 return r;
 474
 475         amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 476
 477         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 478                 amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
 479
 480         return amdgpu_uvd_sw_fini(adev);
 481 }
 482
 483 /**
 484  * uvd_v7_0_hw_init - start and test UVD block
 485  *
 486  * @adev: amdgpu_device pointer
 487  *
 488  * Initialize the hardware, boot up the VCPU and do some testing
 489  */
 490 static int uvd_v7_0_hw_init(void *handle)
 491 {
 492         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 493         struct amdgpu_ring *ring = &adev->uvd.ring;
 494         uint32_t tmp;
 495         int i, r;
 496
 497         if (amdgpu_sriov_vf(adev))
 498                 r = uvd_v7_0_sriov_start(adev);
 499         else
 500                 r = uvd_v7_0_start(adev);
 501         if (r)
 502                 goto done;
 503
 504         if (!amdgpu_sriov_vf(adev)) {
 505                 ring->ready = true;
 506                 r = amdgpu_ring_test_ring(ring);
 507                 if (r) {
 508                         ring->ready = false;
 509                         goto done;
 510                 }
 511
 512                 r = amdgpu_ring_alloc(ring, 10);
 513                 if (r) {
 514                         DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 515                         goto done;
 516                 }
 517
 518                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 519                         mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 520                 amdgpu_ring_write(ring, tmp);
 521                 amdgpu_ring_write(ring, 0xFFFFF);
 522
 523                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 524                         mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 525                 amdgpu_ring_write(ring, tmp);
 526                 amdgpu_ring_write(ring, 0xFFFFF);
 527
 528                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 529                         mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 530                 amdgpu_ring_write(ring, tmp);
 531                 amdgpu_ring_write(ring, 0xFFFFF);
 532
 533                 /* Clear timeout status bits */
 534                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
 535                         mmUVD_SEMA_TIMEOUT_STATUS), 0));
 536                 amdgpu_ring_write(ring, 0x8);
 537
 538                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
 539                         mmUVD_SEMA_CNTL), 0));
 540                 amdgpu_ring_write(ring, 3);
 541
 542                 amdgpu_ring_commit(ring);
 543         }
 544
 545         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 546                 ring = &adev->uvd.ring_enc[i];
 547                 ring->ready = true;
 548                 r = amdgpu_ring_test_ring(ring);
 549                 if (r) {
 550                         ring->ready = false;
 551                         goto done;
 552                 }
 553         }
 554
 555 done:
 556         if (!r)
 557                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 558
 559         return r;
 560 }
 561
 562 /**
 563  * uvd_v7_0_hw_fini - stop the hardware block
 564  *
 565  * @adev: amdgpu_device pointer
 566  *
 567  * Stop the UVD block, mark ring as not ready any more
 568  */
 569 static int uvd_v7_0_hw_fini(void *handle)
 570 {
 571         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 572         struct amdgpu_ring *ring = &adev->uvd.ring;
 573
 574         if (!amdgpu_sriov_vf(adev))
 575                 uvd_v7_0_stop(adev);
 576         else {
 577                 /* full access mode, so don't touch any UVD register */
 578                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 579         }
 580
 581         ring->ready = false;
 582
 583         return 0;
 584 }
 585
 586 static int uvd_v7_0_suspend(void *handle)
 587 {
 588         int r;
 589         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 590
 591         r = uvd_v7_0_hw_fini(adev);
 592         if (r)
 593                 return r;
 594
 595         return amdgpu_uvd_suspend(adev);
 596 }
 597
 598 static int uvd_v7_0_resume(void *handle)
 599 {
 600         int r;
 601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 602
 603         r = amdgpu_uvd_resume(adev);
 604         if (r)
 605                 return r;
 606
 607         return uvd_v7_0_hw_init(adev);
 608 }
 609
 610 /**
 611  * uvd_v7_0_mc_resume - memory controller programming
 612  *
 613  * @adev: amdgpu_device pointer
 614  *
 615  * Let the UVD memory controller know it's offsets
 616  */
 617 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 618 {
 619         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 620         uint32_t offset;
 621
 622         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 623                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 624                         lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 625                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 626                         upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 627                 offset = 0;
 628         } else {
 629                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 630                         lower_32_bits(adev->uvd.gpu_addr));
 631                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 632                         upper_32_bits(adev->uvd.gpu_addr));
 633                 offset = size;
 634         }
 635
 636         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 637                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 638         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 639
 640         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 641                         lower_32_bits(adev->uvd.gpu_addr + offset));
 642         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 643                         upper_32_bits(adev->uvd.gpu_addr + offset));
 644         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 645         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 646
 647         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 648                         lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 649         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 650                         upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 651         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 652         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
 653                         AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 654
 655         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 656                         adev->gfx.config.gb_addr_config);
 657         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 658                         adev->gfx.config.gb_addr_config);
 659         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 660                         adev->gfx.config.gb_addr_config);
 661
 662         WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 663 }
 664
 665 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 666                                 struct amdgpu_mm_table *table)
 667 {
 668         uint32_t data = 0, loop;
 669         uint64_t addr = table->gpu_addr;
 670         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 671         uint32_t size;
 672
 673         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 674
 675         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 676         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 677         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 678
 679         /* 2, update vmid of descriptor */
 680         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 681         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 682         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 683         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 684
 685         /* 3, notify mmsch about the size of this descriptor */
 686         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 687
 688         /* 4, set resp to zero */
 689         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 690
 691         WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
 692         adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
 693         adev->uvd.ring_enc[0].wptr = 0;
 694         adev->uvd.ring_enc[0].wptr_old = 0;
 695
 696         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 697         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 698
 699         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 700         loop = 1000;
 701         while ((data & 0x10000002) != 0x10000002) {
 702                 udelay(10);
 703                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 704                 loop--;
 705                 if (!loop)
 706                         break;
 707         }
 708
 709         if (!loop) {
 710                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 711                 return -EBUSY;
 712         }
 713
 714         return 0;
 715 }
 716
 717 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 718 {
 719         struct amdgpu_ring *ring;
 720         uint32_t offset, size, tmp;
 721         uint32_t table_size = 0;
 722         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 723         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 724         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 725         struct mmsch_v1_0_cmd_end end = { {0} };
 726         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 727         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 728
 729         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 730         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 731         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 732         end.cmd_header.command_type = MMSCH_COMMAND__END;
 733
 734         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 735                 header->version = MMSCH_VERSION;
 736                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 737
 738                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 739                         header->uvd_table_offset = header->header_size;
 740                 else
 741                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 742
 743                 init_table += header->uvd_table_offset;
 744
 745                 ring = &adev->uvd.ring;
 746                 ring->wptr = 0;
 747                 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 748
 749                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
 750                                                    0xFFFFFFFF, 0x00000004);
 751                 /* mc resume*/
 752                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 753                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 754                                                     lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 755                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 756                                                     upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 757                         offset = 0;
 758                 } else {
 759                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 760                                                     lower_32_bits(adev->uvd.gpu_addr));
 761                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 762                                                     upper_32_bits(adev->uvd.gpu_addr));
 763                         offset = size;
 764                 }
 765
 766                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 767                                             AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 768                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
 769
 770                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 771                                             lower_32_bits(adev->uvd.gpu_addr + offset));
 772                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 773                                             upper_32_bits(adev->uvd.gpu_addr + offset));
 774                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 775                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 776
 777                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 778                                             lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 779                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 780                                             upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 781                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 782                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
 783                                             AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 784
 785                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 786                 /* mc resume end*/
 787
 788                 /* disable clock gating */
 789                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
 790                                                    ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 791
 792                 /* disable interupt */
 793                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 794                                                    ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 795
 796                 /* stall UMC and register bus before resetting VCPU */
 797                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 798                                                    ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 799                                                    UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 800
 801                 /* put LMI, VCPU, RBC etc... into reset */
 802                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 803                                             (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 804                                                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 805                                                        UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 806                                                        UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 807                                                        UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 808                                                        UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 809                                                        UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 810                                                        UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 811
 812                 /* initialize UVD memory controller */
 813                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
 814                                             (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 815                                                        UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 816                                                        UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 817                                                        UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 818                                                        UVD_LMI_CTRL__REQ_MODE_MASK |
 819                                                        0x00100000L));
 820
 821                 /* take all subblocks out of reset, except VCPU */
 822                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 823                                             UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 824
 825                 /* enable VCPU clock */
 826                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
 827                                             UVD_VCPU_CNTL__CLK_EN_MASK);
 828
 829                 /* enable master interrupt */
 830                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 831                                                    ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 832                                                    (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 833
 834                 /* clear the bit 4 of UVD_STATUS */
 835                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
 836                                                    ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 837
 838                 /* force RBC into idle state */
 839                 size = order_base_2(ring->ring_size);
 840                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 841                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 842                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
 843
 844                 ring = &adev->uvd.ring_enc[0];
 845                 ring->wptr = 0;
 846                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
 847                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 848                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
 849
 850                 /* boot up the VCPU */
 851                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
 852
 853                 /* enable UMC */
 854                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 855                                                                                    ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 856
 857                 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
 858
 859                 /* add end packet */
 860                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 861                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 862                 header->uvd_table_size = table_size;
 863
 864         }
 865         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 866 }
 867
 868 /**
 869  * uvd_v7_0_start - start UVD block
 870  *
 871  * @adev: amdgpu_device pointer
 872  *
 873  * Setup and start the UVD block
 874  */
 875 static int uvd_v7_0_start(struct amdgpu_device *adev)
 876 {
 877         struct amdgpu_ring *ring = &adev->uvd.ring;
 878         uint32_t rb_bufsz, tmp;
 879         uint32_t lmi_swap_cntl;
 880         uint32_t mp_swap_cntl;
 881         int i, j, r;
 882
 883         /* disable DPG */
 884         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
 885                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 886
 887         /* disable byte swapping */
 888         lmi_swap_cntl = 0;
 889         mp_swap_cntl = 0;
 890
 891         uvd_v7_0_mc_resume(adev);
 892
 893         /* disable clock gating */
 894         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
 895                         ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 896
 897         /* disable interupt */
 898         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 899                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 900
 901         /* stall UMC and register bus before resetting VCPU */
 902         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 903                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 904                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 905         mdelay(1);
 906
 907         /* put LMI, VCPU, RBC etc... into reset */
 908         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 909                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 910                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 911                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 912                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 913                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 914                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 915                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 916                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 917         mdelay(5);
 918
 919         /* initialize UVD memory controller */
 920         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
 921                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 922                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 923                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 924                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 925                 UVD_LMI_CTRL__REQ_MODE_MASK |
 926                 0x00100000L);
 927
 928 #ifdef __BIG_ENDIAN
 929         /* swap (8 in 32) RB and IB */
 930         lmi_swap_cntl = 0xa;
 931         mp_swap_cntl = 0;
 932 #endif
 933         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 934         WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 935
 936         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 937         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
 938         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 939         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
 940         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
 941         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
 942
 943         /* take all subblocks out of reset, except VCPU */
 944         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 945                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 946         mdelay(5);
 947
 948         /* enable VCPU clock */
 949         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
 950                         UVD_VCPU_CNTL__CLK_EN_MASK);
 951
 952         /* enable UMC */
 953         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 954                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 955
 956         /* boot up the VCPU */
 957         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
 958         mdelay(10);
 959
 960         for (i = 0; i < 10; ++i) {
 961                 uint32_t status;
 962
 963                 for (j = 0; j < 100; ++j) {
 964                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 965                         if (status & 2)
 966                                 break;
 967                         mdelay(10);
 968                 }
 969                 r = 0;
 970                 if (status & 2)
 971                         break;
 972
 973                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 974                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 975                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 976                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 977                 mdelay(10);
 978                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 979                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 980                 mdelay(10);
 981                 r = -1;
 982         }
 983
 984         if (r) {
 985                 DRM_ERROR("UVD not responding, giving up!!!\n");
 986                 return r;
 987         }
 988         /* enable master interrupt */
 989         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 990                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 991                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 992
 993         /* clear the bit 4 of UVD_STATUS */
 994         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
 995                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 996
 997         /* force RBC into idle state */
 998         rb_bufsz = order_base_2(ring->ring_size);
 999         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1000         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1001         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1002         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1003         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1004         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1005         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1006
1007         /* set the write pointer delay */
1008         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1009
1010         /* set the wb address */
1011         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1012                         (upper_32_bits(ring->gpu_addr) >> 2));
1013
1014         /* programm the RB_BASE for ring buffer */
1015         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1016                         lower_32_bits(ring->gpu_addr));
1017         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1018                         upper_32_bits(ring->gpu_addr));
1019
1020         /* Initialize the ring buffer's read and write pointers */
1021         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1022
1023         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1024         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1025                         lower_32_bits(ring->wptr));
1026
1027         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1028                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1029
1030         ring = &adev->uvd.ring_enc[0];
1031         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1032         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1033         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1034         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1035         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1036
1037         ring = &adev->uvd.ring_enc[1];
1038         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1039         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1040         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1041         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1042         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1043
1044         return 0;
1045 }
1046
1047 /**
1048  * uvd_v7_0_stop - stop UVD block
1049  *
1050  * @adev: amdgpu_device pointer
1051  *
1052  * stop the UVD block
1053  */
1054 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1055 {
1056         /* force RBC into idle state */
1057         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
1058
1059         /* Stall UMC and register bus before resetting VCPU */
1060         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1061                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1062                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1063         mdelay(1);
1064
1065         /* put VCPU into reset */
1066         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
1067                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1068         mdelay(5);
1069
1070         /* disable VCPU clock */
1071         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
1072
1073         /* Unstall UMC and register bus */
1074         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1075                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1076 }
1077
1078 /**
1079  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1080  *
1081  * @ring: amdgpu_ring pointer
1082  * @fence: fence to emit
1083  *
1084  * Write a fence and a trap command to the ring.
1085  */
1086 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1087                                      unsigned flags)
1088 {
1089         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1090
1091         amdgpu_ring_write(ring,
1092                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1093         amdgpu_ring_write(ring, seq);
1094         amdgpu_ring_write(ring,
1095                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1096         amdgpu_ring_write(ring, addr & 0xffffffff);
1097         amdgpu_ring_write(ring,
1098                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1099         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1100         amdgpu_ring_write(ring,
1101                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1102         amdgpu_ring_write(ring, 0);
1103
1104         amdgpu_ring_write(ring,
1105                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1106         amdgpu_ring_write(ring, 0);
1107         amdgpu_ring_write(ring,
1108                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1109         amdgpu_ring_write(ring, 0);
1110         amdgpu_ring_write(ring,
1111                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1112         amdgpu_ring_write(ring, 2);
1113 }
1114
1115 /**
1116  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1117  *
1118  * @ring: amdgpu_ring pointer
1119  * @fence: fence to emit
1120  *
1121  * Write enc a fence and a trap command to the ring.
1122  */
1123 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1124                         u64 seq, unsigned flags)
1125 {
1126         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1127
1128         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1129         amdgpu_ring_write(ring, addr);
1130         amdgpu_ring_write(ring, upper_32_bits(addr));
1131         amdgpu_ring_write(ring, seq);
1132         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1133 }
1134
1135 /**
1136  * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
1137  *
1138  * @ring: amdgpu_ring pointer
1139  *
1140  * Emits an hdp flush.
1141  */
1142 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1143 {
1144         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
1145                 mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
1146         amdgpu_ring_write(ring, 0);
1147 }
1148
1149 /**
1150  * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
1151  *
1152  * @ring: amdgpu_ring pointer
1153  *
1154  * Emits an hdp invalidate.
1155  */
1156 static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1157 {
1158         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
1159         amdgpu_ring_write(ring, 1);
1160 }
1161
1162 /**
1163  * uvd_v7_0_ring_test_ring - register write test
1164  *
1165  * @ring: amdgpu_ring pointer
1166  *
1167  * Test if we can successfully write to the context register
1168  */
1169 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1170 {
1171         struct amdgpu_device *adev = ring->adev;
1172         uint32_t tmp = 0;
1173         unsigned i;
1174         int r;
1175
1176         WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1177         r = amdgpu_ring_alloc(ring, 3);
1178         if (r) {
1179                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
1180                           ring->idx, r);
1181                 return r;
1182         }
1183         amdgpu_ring_write(ring,
1184                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1185         amdgpu_ring_write(ring, 0xDEADBEEF);
1186         amdgpu_ring_commit(ring);
1187         for (i = 0; i < adev->usec_timeout; i++) {
1188                 tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID);
1189                 if (tmp == 0xDEADBEEF)
1190                         break;
1191                 DRM_UDELAY(1);
1192         }
1193
1194         if (i < adev->usec_timeout) {
1195                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1196                          ring->idx, i);
1197         } else {
1198                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1199                           ring->idx, tmp);
1200                 r = -EINVAL;
1201         }
1202         return r;
1203 }
1204
1205 /**
1206  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1207  *
1208  * @ring: amdgpu_ring pointer
1209  * @ib: indirect buffer to execute
1210  *
1211  * Write ring commands to execute the indirect buffer
1212  */
1213 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1214                                   struct amdgpu_ib *ib,
1215                                   unsigned vm_id, bool ctx_switch)
1216 {
1217         amdgpu_ring_write(ring,
1218                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1219         amdgpu_ring_write(ring, vm_id);
1220
1221         amdgpu_ring_write(ring,
1222                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1223         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1224         amdgpu_ring_write(ring,
1225                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1226         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1227         amdgpu_ring_write(ring,
1228                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1229         amdgpu_ring_write(ring, ib->length_dw);
1230 }
1231
1232 /**
1233  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1234  *
1235  * @ring: amdgpu_ring pointer
1236  * @ib: indirect buffer to execute
1237  *
1238  * Write enc ring commands to execute the indirect buffer
1239  */
1240 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1241                 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1242 {
1243         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1244         amdgpu_ring_write(ring, vm_id);
1245         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1246         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1247         amdgpu_ring_write(ring, ib->length_dw);
1248 }
1249
1250 static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
1251                                 uint32_t data0, uint32_t data1)
1252 {
1253         amdgpu_ring_write(ring,
1254                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1255         amdgpu_ring_write(ring, data0);
1256         amdgpu_ring_write(ring,
1257                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1258         amdgpu_ring_write(ring, data1);
1259         amdgpu_ring_write(ring,
1260                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1261         amdgpu_ring_write(ring, 8);
1262 }
1263
1264 static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
1265                                 uint32_t data0, uint32_t data1, uint32_t mask)
1266 {
1267         amdgpu_ring_write(ring,
1268                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1269         amdgpu_ring_write(ring, data0);
1270         amdgpu_ring_write(ring,
1271                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1272         amdgpu_ring_write(ring, data1);
1273         amdgpu_ring_write(ring,
1274                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1275         amdgpu_ring_write(ring, mask);
1276         amdgpu_ring_write(ring,
1277                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1278         amdgpu_ring_write(ring, 12);
1279 }
1280
1281 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1282                                         unsigned vm_id, uint64_t pd_addr)
1283 {
1284         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1285         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1286         uint32_t data0, data1, mask;
1287         unsigned eng = ring->vm_inv_eng;
1288
1289         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1290         pd_addr |= AMDGPU_PTE_VALID;
1291
1292         data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
1293         data1 = upper_32_bits(pd_addr);
1294         uvd_v7_0_vm_reg_write(ring, data0, data1);
1295
1296         data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1297         data1 = lower_32_bits(pd_addr);
1298         uvd_v7_0_vm_reg_write(ring, data0, data1);
1299
1300         data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1301         data1 = lower_32_bits(pd_addr);
1302         mask = 0xffffffff;
1303         uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1304
1305         /* flush TLB */
1306         data0 = (hub->vm_inv_eng0_req + eng) << 2;
1307         data1 = req;
1308         uvd_v7_0_vm_reg_write(ring, data0, data1);
1309
1310         /* wait for flush */
1311         data0 = (hub->vm_inv_eng0_ack + eng) << 2;
1312         data1 = 1 << vm_id;
1313         mask =  1 << vm_id;
1314         uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1315 }
1316
1317 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1318 {
1319         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1320 }
1321
1322 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1323                          unsigned int vm_id, uint64_t pd_addr)
1324 {
1325         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1326         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1327         unsigned eng = ring->vm_inv_eng;
1328
1329         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1330         pd_addr |= AMDGPU_PTE_VALID;
1331
1332         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1333         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
1334         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1335
1336         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1337         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1338         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1339
1340         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1341         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1342         amdgpu_ring_write(ring, 0xffffffff);
1343         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1344
1345         /* flush TLB */
1346         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1347         amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
1348         amdgpu_ring_write(ring, req);
1349
1350         /* wait for flush */
1351         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1352         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1353         amdgpu_ring_write(ring, 1 << vm_id);
1354         amdgpu_ring_write(ring, 1 << vm_id);
1355 }
1356
1357 #if 0
1358 static bool uvd_v7_0_is_idle(void *handle)
1359 {
1360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1361
1362         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1363 }
1364
1365 static int uvd_v7_0_wait_for_idle(void *handle)
1366 {
1367         unsigned i;
1368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370         for (i = 0; i < adev->usec_timeout; i++) {
1371                 if (uvd_v7_0_is_idle(handle))
1372                         return 0;
1373         }
1374         return -ETIMEDOUT;
1375 }
1376
1377 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1378 static bool uvd_v7_0_check_soft_reset(void *handle)
1379 {
1380         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1381         u32 srbm_soft_reset = 0;
1382         u32 tmp = RREG32(mmSRBM_STATUS);
1383
1384         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1385             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1386             (RREG32_SOC15(UVD, 0, mmUVD_STATUS) &
1387                     AMDGPU_UVD_STATUS_BUSY_MASK))
1388                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1389                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1390
1391         if (srbm_soft_reset) {
1392                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1393                 return true;
1394         } else {
1395                 adev->uvd.srbm_soft_reset = 0;
1396                 return false;
1397         }
1398 }
1399
1400 static int uvd_v7_0_pre_soft_reset(void *handle)
1401 {
1402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403
1404         if (!adev->uvd.srbm_soft_reset)
1405                 return 0;
1406
1407         uvd_v7_0_stop(adev);
1408         return 0;
1409 }
1410
1411 static int uvd_v7_0_soft_reset(void *handle)
1412 {
1413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1414         u32 srbm_soft_reset;
1415
1416         if (!adev->uvd.srbm_soft_reset)
1417                 return 0;
1418         srbm_soft_reset = adev->uvd.srbm_soft_reset;
1419
1420         if (srbm_soft_reset) {
1421                 u32 tmp;
1422
1423                 tmp = RREG32(mmSRBM_SOFT_RESET);
1424                 tmp |= srbm_soft_reset;
1425                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1426                 WREG32(mmSRBM_SOFT_RESET, tmp);
1427                 tmp = RREG32(mmSRBM_SOFT_RESET);
1428
1429                 udelay(50);
1430
1431                 tmp &= ~srbm_soft_reset;
1432                 WREG32(mmSRBM_SOFT_RESET, tmp);
1433                 tmp = RREG32(mmSRBM_SOFT_RESET);
1434
1435                 /* Wait a little for things to settle down */
1436                 udelay(50);
1437         }
1438
1439         return 0;
1440 }
1441
1442 static int uvd_v7_0_post_soft_reset(void *handle)
1443 {
1444         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445
1446         if (!adev->uvd.srbm_soft_reset)
1447                 return 0;
1448
1449         mdelay(5);
1450
1451         return uvd_v7_0_start(adev);
1452 }
1453 #endif
1454
1455 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1456                                         struct amdgpu_irq_src *source,
1457                                         unsigned type,
1458                                         enum amdgpu_interrupt_state state)
1459 {
1460         // TODO
1461         return 0;
1462 }
1463
1464 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1465                                       struct amdgpu_irq_src *source,
1466                                       struct amdgpu_iv_entry *entry)
1467 {
1468         DRM_DEBUG("IH: UVD TRAP\n");
1469         switch (entry->src_id) {
1470         case 124:
1471                 amdgpu_fence_process(&adev->uvd.ring);
1472                 break;
1473         case 119:
1474                 amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1475                 break;
1476         case 120:
1477                 if (!amdgpu_sriov_vf(adev))
1478                         amdgpu_fence_process(&adev->uvd.ring_enc[1]);
1479                 break;
1480         default:
1481                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1482                           entry->src_id, entry->src_data[0]);
1483                 break;
1484         }
1485
1486         return 0;
1487 }
1488
1489 #if 0
1490 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1491 {
1492         uint32_t data, data1, data2, suvd_flags;
1493
1494         data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL);
1495         data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
1496         data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL);
1497
1498         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1499                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1500
1501         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1502                      UVD_SUVD_CGC_GATE__SIT_MASK |
1503                      UVD_SUVD_CGC_GATE__SMP_MASK |
1504                      UVD_SUVD_CGC_GATE__SCM_MASK |
1505                      UVD_SUVD_CGC_GATE__SDB_MASK;
1506
1507         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1508                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1509                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1510
1511         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1512                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1513                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1514                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1515                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1516                         UVD_CGC_CTRL__SYS_MODE_MASK |
1517                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1518                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1519                         UVD_CGC_CTRL__REGS_MODE_MASK |
1520                         UVD_CGC_CTRL__RBC_MODE_MASK |
1521                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1522                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1523                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1524                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1525                         UVD_CGC_CTRL__MPC_MODE_MASK |
1526                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1527                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1528                         UVD_CGC_CTRL__WCB_MODE_MASK |
1529                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1530                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1531                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1532                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1533         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1534                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1535                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1536                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1537                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1538         data1 |= suvd_flags;
1539
1540         WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data);
1541         WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0);
1542         WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
1543         WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2);
1544 }
1545
1546 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1547 {
1548         uint32_t data, data1, cgc_flags, suvd_flags;
1549
1550         data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE);
1551         data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
1552
1553         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1554                 UVD_CGC_GATE__UDEC_MASK |
1555                 UVD_CGC_GATE__MPEG2_MASK |
1556                 UVD_CGC_GATE__RBC_MASK |
1557                 UVD_CGC_GATE__LMI_MC_MASK |
1558                 UVD_CGC_GATE__IDCT_MASK |
1559                 UVD_CGC_GATE__MPRD_MASK |
1560                 UVD_CGC_GATE__MPC_MASK |
1561                 UVD_CGC_GATE__LBSI_MASK |
1562                 UVD_CGC_GATE__LRBBM_MASK |
1563                 UVD_CGC_GATE__UDEC_RE_MASK |
1564                 UVD_CGC_GATE__UDEC_CM_MASK |
1565                 UVD_CGC_GATE__UDEC_IT_MASK |
1566                 UVD_CGC_GATE__UDEC_DB_MASK |
1567                 UVD_CGC_GATE__UDEC_MP_MASK |
1568                 UVD_CGC_GATE__WCB_MASK |
1569                 UVD_CGC_GATE__VCPU_MASK |
1570                 UVD_CGC_GATE__SCPU_MASK |
1571                 UVD_CGC_GATE__JPEG_MASK |
1572                 UVD_CGC_GATE__JPEG2_MASK;
1573
1574         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1575                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1576                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1577                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1578                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1579
1580         data |= cgc_flags;
1581         data1 |= suvd_flags;
1582
1583         WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data);
1584         WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
1585 }
1586
1587 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1588 {
1589         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1590
1591         if (enable)
1592                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1593                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1594         else
1595                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1596                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1597
1598         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1599 }
1600
1601
1602 static int uvd_v7_0_set_clockgating_state(void *handle,
1603                                           enum amd_clockgating_state state)
1604 {
1605         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1606         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1607
1608         uvd_v7_0_set_bypass_mode(adev, enable);
1609
1610         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1611                 return 0;
1612
1613         if (enable) {
1614                 /* disable HW gating and enable Sw gating */
1615                 uvd_v7_0_set_sw_clock_gating(adev);
1616         } else {
1617                 /* wait for STATUS to clear */
1618                 if (uvd_v7_0_wait_for_idle(handle))
1619                         return -EBUSY;
1620
1621                 /* enable HW gates because UVD is idle */
1622                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1623         }
1624
1625         return 0;
1626 }
1627
1628 static int uvd_v7_0_set_powergating_state(void *handle,
1629                                           enum amd_powergating_state state)
1630 {
1631         /* This doesn't actually powergate the UVD block.
1632          * That's done in the dpm code via the SMC.  This
1633          * just re-inits the block as necessary.  The actual
1634          * gating still happens in the dpm code.  We should
1635          * revisit this when there is a cleaner line between
1636          * the smc and the hw blocks
1637          */
1638         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1639
1640         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1641                 return 0;
1642
1643         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1644
1645         if (state == AMD_PG_STATE_GATE) {
1646                 uvd_v7_0_stop(adev);
1647                 return 0;
1648         } else {
1649                 return uvd_v7_0_start(adev);
1650         }
1651 }
1652 #endif
1653
1654 static int uvd_v7_0_set_clockgating_state(void *handle,
1655                                           enum amd_clockgating_state state)
1656 {
1657         /* needed for driver unload*/
1658         return 0;
1659 }
1660
1661 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1662         .name = "uvd_v7_0",
1663         .early_init = uvd_v7_0_early_init,
1664         .late_init = NULL,
1665         .sw_init = uvd_v7_0_sw_init,
1666         .sw_fini = uvd_v7_0_sw_fini,
1667         .hw_init = uvd_v7_0_hw_init,
1668         .hw_fini = uvd_v7_0_hw_fini,
1669         .suspend = uvd_v7_0_suspend,
1670         .resume = uvd_v7_0_resume,
1671         .is_idle = NULL /* uvd_v7_0_is_idle */,
1672         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1673         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1674         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1675         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1676         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1677         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1678         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1679 };
1680
1681 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1682         .type = AMDGPU_RING_TYPE_UVD,
1683         .align_mask = 0xf,
1684         .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
1685         .support_64bit_ptrs = false,
1686         .vmhub = AMDGPU_MMHUB,
1687         .get_rptr = uvd_v7_0_ring_get_rptr,
1688         .get_wptr = uvd_v7_0_ring_get_wptr,
1689         .set_wptr = uvd_v7_0_ring_set_wptr,
1690         .emit_frame_size =
1691                 2 + /* uvd_v7_0_ring_emit_hdp_flush */
1692                 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
1693                 34 + /* uvd_v7_0_ring_emit_vm_flush */
1694                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1695         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1696         .emit_ib = uvd_v7_0_ring_emit_ib,
1697         .emit_fence = uvd_v7_0_ring_emit_fence,
1698         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1699         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1700         .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
1701         .test_ring = uvd_v7_0_ring_test_ring,
1702         .test_ib = amdgpu_uvd_ring_test_ib,
1703         .insert_nop = amdgpu_ring_insert_nop,
1704         .pad_ib = amdgpu_ring_generic_pad_ib,
1705         .begin_use = amdgpu_uvd_ring_begin_use,
1706         .end_use = amdgpu_uvd_ring_end_use,
1707 };
1708
1709 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1710         .type = AMDGPU_RING_TYPE_UVD_ENC,
1711         .align_mask = 0x3f,
1712         .nop = HEVC_ENC_CMD_NO_OP,
1713         .support_64bit_ptrs = false,
1714         .vmhub = AMDGPU_MMHUB,
1715         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1716         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1717         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1718         .emit_frame_size =
1719                 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1720                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1721                 1, /* uvd_v7_0_enc_ring_insert_end */
1722         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1723         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1724         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1725         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1726         .test_ring = uvd_v7_0_enc_ring_test_ring,
1727         .test_ib = uvd_v7_0_enc_ring_test_ib,
1728         .insert_nop = amdgpu_ring_insert_nop,
1729         .insert_end = uvd_v7_0_enc_ring_insert_end,
1730         .pad_ib = amdgpu_ring_generic_pad_ib,
1731         .begin_use = amdgpu_uvd_ring_begin_use,
1732         .end_use = amdgpu_uvd_ring_end_use,
1733 };
1734
1735 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1736 {
1737         adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs;
1738         DRM_INFO("UVD is enabled in VM mode\n");
1739 }
1740
1741 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1742 {
1743         int i;
1744
1745         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1746                 adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1747
1748         DRM_INFO("UVD ENC is enabled in VM mode\n");
1749 }
1750
1751 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1752         .set = uvd_v7_0_set_interrupt_state,
1753         .process = uvd_v7_0_process_interrupt,
1754 };
1755
1756 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1757 {
1758         adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1759         adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs;
1760 }
1761
1762 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1763 {
1764                 .type = AMD_IP_BLOCK_TYPE_UVD,
1765                 .major = 7,
1766                 .minor = 0,
1767                 .rev = 0,
1768                 .funcs = &uvd_v7_0_ip_funcs,
1769 };