drivers/net/phy/at803x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/at803x.c
   4  *
   5  * Driver for Qualcomm Atheros AR803x PHY
   6  *
   7  * Author: Matus Ujhelyi <[email protected]>
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <linux/module.h>
  12 #include <linux/string.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/ethtool_netlink.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/regulator/of_regulator.h>
  18 #include <linux/regulator/driver.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/of.h>
  21 #include <linux/phylink.h>
  22 #include <linux/sfp.h>
  23 #include <dt-bindings/net/qca-ar803x.h>
  24
  25 #define AT803X_SPECIFIC_FUNCTION_CONTROL        0x10
  26 #define AT803X_SFC_ASSERT_CRS                   BIT(11)
  27 #define AT803X_SFC_FORCE_LINK                   BIT(10)
  28 #define AT803X_SFC_MDI_CROSSOVER_MODE_M         GENMASK(6, 5)
  29 #define AT803X_SFC_AUTOMATIC_CROSSOVER          0x3
  30 #define AT803X_SFC_MANUAL_MDIX                  0x1
  31 #define AT803X_SFC_MANUAL_MDI                   0x0
  32 #define AT803X_SFC_SQE_TEST                     BIT(2)
  33 #define AT803X_SFC_POLARITY_REVERSAL            BIT(1)
  34 #define AT803X_SFC_DISABLE_JABBER               BIT(0)
  35
  36 #define AT803X_SPECIFIC_STATUS                  0x11
  37 #define AT803X_SS_SPEED_MASK                    GENMASK(15, 14)
  38 #define AT803X_SS_SPEED_1000                    2
  39 #define AT803X_SS_SPEED_100                     1
  40 #define AT803X_SS_SPEED_10                      0
  41 #define AT803X_SS_DUPLEX                        BIT(13)
  42 #define AT803X_SS_SPEED_DUPLEX_RESOLVED         BIT(11)
  43 #define AT803X_SS_MDIX                          BIT(6)
  44
  45 #define QCA808X_SS_SPEED_MASK                   GENMASK(9, 7)
  46 #define QCA808X_SS_SPEED_2500                   4
  47
  48 #define AT803X_INTR_ENABLE                      0x12
  49 #define AT803X_INTR_ENABLE_AUTONEG_ERR          BIT(15)
  50 #define AT803X_INTR_ENABLE_SPEED_CHANGED        BIT(14)
  51 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED       BIT(13)
  52 #define AT803X_INTR_ENABLE_PAGE_RECEIVED        BIT(12)
  53 #define AT803X_INTR_ENABLE_LINK_FAIL            BIT(11)
  54 #define AT803X_INTR_ENABLE_LINK_SUCCESS         BIT(10)
  55 #define AT803X_INTR_ENABLE_LINK_FAIL_BX         BIT(8)
  56 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX      BIT(7)
  57 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE  BIT(5)
  58 #define AT803X_INTR_ENABLE_POLARITY_CHANGED     BIT(1)
  59 #define AT803X_INTR_ENABLE_WOL                  BIT(0)
  60
  61 #define AT803X_INTR_STATUS                      0x13
  62
  63 #define AT803X_SMART_SPEED                      0x14
  64 #define AT803X_SMART_SPEED_ENABLE               BIT(5)
  65 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK     GENMASK(4, 2)
  66 #define AT803X_SMART_SPEED_BYPASS_TIMER         BIT(1)
  67 #define AT803X_CDT                              0x16
  68 #define AT803X_CDT_MDI_PAIR_MASK                GENMASK(9, 8)
  69 #define AT803X_CDT_ENABLE_TEST                  BIT(0)
  70 #define AT803X_CDT_STATUS                       0x1c
  71 #define AT803X_CDT_STATUS_STAT_NORMAL           0
  72 #define AT803X_CDT_STATUS_STAT_SHORT            1
  73 #define AT803X_CDT_STATUS_STAT_OPEN             2
  74 #define AT803X_CDT_STATUS_STAT_FAIL             3
  75 #define AT803X_CDT_STATUS_STAT_MASK             GENMASK(9, 8)
  76 #define AT803X_CDT_STATUS_DELTA_TIME_MASK       GENMASK(7, 0)
  77 #define AT803X_LED_CONTROL                      0x18
  78
  79 #define AT803X_PHY_MMD3_WOL_CTRL                0x8012
  80 #define AT803X_WOL_EN                           BIT(5)
  81 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET         0x804C
  82 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET        0x804B
  83 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET        0x804A
  84 #define AT803X_REG_CHIP_CONFIG                  0x1f
  85 #define AT803X_BT_BX_REG_SEL                    0x8000
  86
  87 #define AT803X_DEBUG_ADDR                       0x1D
  88 #define AT803X_DEBUG_DATA                       0x1E
  89
  90 #define AT803X_MODE_CFG_MASK                    0x0F
  91 #define AT803X_MODE_CFG_BASET_RGMII             0x00
  92 #define AT803X_MODE_CFG_BASET_SGMII             0x01
  93 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM      0x02
  94 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM      0x03
  95 #define AT803X_MODE_CFG_BX1000_CONV_50OHM       0x04
  96 #define AT803X_MODE_CFG_BX1000_CONV_75OHM       0x05
  97 #define AT803X_MODE_CFG_FX100_RGMII_50OHM       0x06
  98 #define AT803X_MODE_CFG_FX100_CONV_50OHM        0x07
  99 #define AT803X_MODE_CFG_RGMII_AUTO_MDET         0x0B
 100 #define AT803X_MODE_CFG_FX100_RGMII_75OHM       0x0E
 101 #define AT803X_MODE_CFG_FX100_CONV_75OHM        0x0F
 102
 103 #define AT803X_PSSR                             0x11    /*PHY-Specific Status Register*/
 104 #define AT803X_PSSR_MR_AN_COMPLETE              0x0200
 105
 106 #define AT803X_DEBUG_ANALOG_TEST_CTRL           0x00
 107 #define QCA8327_DEBUG_MANU_CTRL_EN              BIT(2)
 108 #define QCA8337_DEBUG_MANU_CTRL_EN              GENMASK(3, 2)
 109 #define AT803X_DEBUG_RX_CLK_DLY_EN              BIT(15)
 110
 111 #define AT803X_DEBUG_SYSTEM_CTRL_MODE           0x05
 112 #define AT803X_DEBUG_TX_CLK_DLY_EN              BIT(8)
 113
 114 #define AT803X_DEBUG_REG_HIB_CTRL               0x0b
 115 #define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U     BIT(10)
 116 #define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE   BIT(13)
 117 #define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN       BIT(15)
 118
 119 #define AT803X_DEBUG_REG_3C                     0x3C
 120
 121 #define AT803X_DEBUG_REG_GREEN                  0x3D
 122 #define   AT803X_DEBUG_GATE_CLK_IN1000          BIT(6)
 123
 124 #define AT803X_DEBUG_REG_1F                     0x1F
 125 #define AT803X_DEBUG_PLL_ON                     BIT(2)
 126 #define AT803X_DEBUG_RGMII_1V8                  BIT(3)
 127
 128 #define MDIO_AZ_DEBUG                           0x800D
 129
 130 /* AT803x supports either the XTAL input pad, an internal PLL or the
 131  * DSP as clock reference for the clock output pad. The XTAL reference
 132  * is only used for 25 MHz output, all other frequencies need the PLL.
 133  * The DSP as a clock reference is used in synchronous ethernet
 134  * applications.
 135  *
 136  * By default the PLL is only enabled if there is a link. Otherwise
 137  * the PHY will go into low power state and disabled the PLL. You can
 138  * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
 139  * enabled.
 140  */
 141 #define AT803X_MMD7_CLK25M                      0x8016
 142 #define AT803X_CLK_OUT_MASK                     GENMASK(4, 2)
 143 #define AT803X_CLK_OUT_25MHZ_XTAL               0
 144 #define AT803X_CLK_OUT_25MHZ_DSP                1
 145 #define AT803X_CLK_OUT_50MHZ_PLL                2
 146 #define AT803X_CLK_OUT_50MHZ_DSP                3
 147 #define AT803X_CLK_OUT_62_5MHZ_PLL              4
 148 #define AT803X_CLK_OUT_62_5MHZ_DSP              5
 149 #define AT803X_CLK_OUT_125MHZ_PLL               6
 150 #define AT803X_CLK_OUT_125MHZ_DSP               7
 151
 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
 153  * but doesn't support choosing between XTAL/PLL and DSP.
 154  */
 155 #define AT8035_CLK_OUT_MASK                     GENMASK(4, 3)
 156
 157 #define AT803X_CLK_OUT_STRENGTH_MASK            GENMASK(8, 7)
 158 #define AT803X_CLK_OUT_STRENGTH_FULL            0
 159 #define AT803X_CLK_OUT_STRENGTH_HALF            1
 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER         2
 161
 162 #define AT803X_DEFAULT_DOWNSHIFT                5
 163 #define AT803X_MIN_DOWNSHIFT                    2
 164 #define AT803X_MAX_DOWNSHIFT                    9
 165
 166 #define AT803X_MMD3_SMARTEEE_CTL1               0x805b
 167 #define AT803X_MMD3_SMARTEEE_CTL2               0x805c
 168 #define AT803X_MMD3_SMARTEEE_CTL3               0x805d
 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN        BIT(8)
 170
 171 #define ATH9331_PHY_ID                          0x004dd041
 172 #define ATH8030_PHY_ID                          0x004dd076
 173 #define ATH8031_PHY_ID                          0x004dd074
 174 #define ATH8032_PHY_ID                          0x004dd023
 175 #define ATH8035_PHY_ID                          0x004dd072
 176 #define AT8030_PHY_ID_MASK                      0xffffffef
 177
 178 #define QCA8081_PHY_ID                          0x004dd101
 179
 180 #define QCA8327_A_PHY_ID                        0x004dd033
 181 #define QCA8327_B_PHY_ID                        0x004dd034
 182 #define QCA8337_PHY_ID                          0x004dd036
 183 #define QCA9561_PHY_ID                          0x004dd042
 184 #define QCA8K_PHY_ID_MASK                       0xffffffff
 185
 186 #define QCA8K_DEVFLAGS_REVISION_MASK            GENMASK(2, 0)
 187
 188 #define AT803X_PAGE_FIBER                       0
 189 #define AT803X_PAGE_COPPER                      1
 190
 191 /* don't turn off internal PLL */
 192 #define AT803X_KEEP_PLL_ENABLED                 BIT(0)
 193 #define AT803X_DISABLE_SMARTEEE                 BIT(1)
 194
 195 /* disable hibernation mode */
 196 #define AT803X_DISABLE_HIBERNATION_MODE         BIT(2)
 197
 198 /* ADC threshold */
 199 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD         0x2c80
 200 #define QCA808X_ADC_THRESHOLD_MASK              GENMASK(7, 0)
 201 #define QCA808X_ADC_THRESHOLD_80MV              0
 202 #define QCA808X_ADC_THRESHOLD_100MV             0xf0
 203 #define QCA808X_ADC_THRESHOLD_200MV             0x0f
 204 #define QCA808X_ADC_THRESHOLD_300MV             0xff
 205
 206 /* CLD control */
 207 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7         0x8007
 208 #define QCA808X_8023AZ_AFE_CTRL_MASK            GENMASK(8, 4)
 209 #define QCA808X_8023AZ_AFE_EN                   0x90
 210
 211 /* AZ control */
 212 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL       0x8008
 213 #define QCA808X_MMD3_AZ_TRAINING_VAL            0x1c32
 214
 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB     0x8014
 216 #define QCA808X_MSE_THRESHOLD_20DB_VALUE        0x529
 217
 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB     0x800E
 219 #define QCA808X_MSE_THRESHOLD_17DB_VALUE        0x341
 220
 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB     0x801E
 222 #define QCA808X_MSE_THRESHOLD_27DB_VALUE        0x419
 223
 224 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB     0x8020
 225 #define QCA808X_MSE_THRESHOLD_28DB_VALUE        0x341
 226
 227 #define QCA808X_PHY_MMD7_TOP_OPTION1            0x901c
 228 #define QCA808X_TOP_OPTION1_DATA                0x0
 229
 230 #define QCA808X_PHY_MMD3_DEBUG_1                0xa100
 231 #define QCA808X_MMD3_DEBUG_1_VALUE              0x9203
 232 #define QCA808X_PHY_MMD3_DEBUG_2                0xa101
 233 #define QCA808X_MMD3_DEBUG_2_VALUE              0x48ad
 234 #define QCA808X_PHY_MMD3_DEBUG_3                0xa103
 235 #define QCA808X_MMD3_DEBUG_3_VALUE              0x1698
 236 #define QCA808X_PHY_MMD3_DEBUG_4                0xa105
 237 #define QCA808X_MMD3_DEBUG_4_VALUE              0x8001
 238 #define QCA808X_PHY_MMD3_DEBUG_5                0xa106
 239 #define QCA808X_MMD3_DEBUG_5_VALUE              0x1111
 240 #define QCA808X_PHY_MMD3_DEBUG_6                0xa011
 241 #define QCA808X_MMD3_DEBUG_6_VALUE              0x5f85
 242
 243 /* master/slave seed config */
 244 #define QCA808X_PHY_DEBUG_LOCAL_SEED            9
 245 #define QCA808X_MASTER_SLAVE_SEED_ENABLE        BIT(1)
 246 #define QCA808X_MASTER_SLAVE_SEED_CFG           GENMASK(12, 2)
 247 #define QCA808X_MASTER_SLAVE_SEED_RANGE         0x32
 248
 249 /* Hibernation yields lower power consumpiton in contrast with normal operation mode.
 250  * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
 251  */
 252 #define QCA808X_DBG_AN_TEST                     0xb
 253 #define QCA808X_HIBERNATION_EN                  BIT(15)
 254
 255 #define QCA808X_CDT_ENABLE_TEST                 BIT(15)
 256 #define QCA808X_CDT_INTER_CHECK_DIS             BIT(13)
 257 #define QCA808X_CDT_LENGTH_UNIT                 BIT(10)
 258
 259 #define QCA808X_MMD3_CDT_STATUS                 0x8064
 260 #define QCA808X_MMD3_CDT_DIAG_PAIR_A            0x8065
 261 #define QCA808X_MMD3_CDT_DIAG_PAIR_B            0x8066
 262 #define QCA808X_MMD3_CDT_DIAG_PAIR_C            0x8067
 263 #define QCA808X_MMD3_CDT_DIAG_PAIR_D            0x8068
 264 #define QCA808X_CDT_DIAG_LENGTH                 GENMASK(7, 0)
 265
 266 #define QCA808X_CDT_CODE_PAIR_A                 GENMASK(15, 12)
 267 #define QCA808X_CDT_CODE_PAIR_B                 GENMASK(11, 8)
 268 #define QCA808X_CDT_CODE_PAIR_C                 GENMASK(7, 4)
 269 #define QCA808X_CDT_CODE_PAIR_D                 GENMASK(3, 0)
 270 #define QCA808X_CDT_STATUS_STAT_FAIL            0
 271 #define QCA808X_CDT_STATUS_STAT_NORMAL          1
 272 #define QCA808X_CDT_STATUS_STAT_OPEN            2
 273 #define QCA808X_CDT_STATUS_STAT_SHORT           3
 274
 275 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 276 MODULE_AUTHOR("Matus Ujhelyi");
 277 MODULE_LICENSE("GPL");
 278
 279 enum stat_access_type {
 280         PHY,
 281         MMD
 282 };
 283
 284 struct at803x_hw_stat {
 285         const char *string;
 286         u8 reg;
 287         u32 mask;
 288         enum stat_access_type access_type;
 289 };
 290
 291 static struct at803x_hw_stat at803x_hw_stats[] = {
 292         { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
 293         { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
 294         { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
 295 };
 296
 297 struct at803x_priv {
 298         int flags;
 299         u16 clk_25m_reg;
 300         u16 clk_25m_mask;
 301         u8 smarteee_lpi_tw_1g;
 302         u8 smarteee_lpi_tw_100m;
 303         bool is_fiber;
 304         bool is_1000basex;
 305         struct regulator_dev *vddio_rdev;
 306         struct regulator_dev *vddh_rdev;
 307         struct regulator *vddio;
 308         u64 stats[ARRAY_SIZE(at803x_hw_stats)];
 309 };
 310
 311 struct at803x_context {
 312         u16 bmcr;
 313         u16 advertise;
 314         u16 control1000;
 315         u16 int_enable;
 316         u16 smart_speed;
 317         u16 led_control;
 318 };
 319
 320 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
 321 {
 322         int ret;
 323
 324         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 325         if (ret < 0)
 326                 return ret;
 327
 328         return phy_write(phydev, AT803X_DEBUG_DATA, data);
 329 }
 330
 331 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 332 {
 333         int ret;
 334
 335         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 336         if (ret < 0)
 337                 return ret;
 338
 339         return phy_read(phydev, AT803X_DEBUG_DATA);
 340 }
 341
 342 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
 343                                  u16 clear, u16 set)
 344 {
 345         u16 val;
 346         int ret;
 347
 348         ret = at803x_debug_reg_read(phydev, reg);
 349         if (ret < 0)
 350                 return ret;
 351
 352         val = ret & 0xffff;
 353         val &= ~clear;
 354         val |= set;
 355
 356         return phy_write(phydev, AT803X_DEBUG_DATA, val);
 357 }
 358
 359 static int at803x_write_page(struct phy_device *phydev, int page)
 360 {
 361         int mask;
 362         int set;
 363
 364         if (page == AT803X_PAGE_COPPER) {
 365                 set = AT803X_BT_BX_REG_SEL;
 366                 mask = 0;
 367         } else {
 368                 set = 0;
 369                 mask = AT803X_BT_BX_REG_SEL;
 370         }
 371
 372         return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
 373 }
 374
 375 static int at803x_read_page(struct phy_device *phydev)
 376 {
 377         int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 378
 379         if (ccr < 0)
 380                 return ccr;
 381
 382         if (ccr & AT803X_BT_BX_REG_SEL)
 383                 return AT803X_PAGE_COPPER;
 384
 385         return AT803X_PAGE_FIBER;
 386 }
 387
 388 static int at803x_enable_rx_delay(struct phy_device *phydev)
 389 {
 390         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
 391                                      AT803X_DEBUG_RX_CLK_DLY_EN);
 392 }
 393
 394 static int at803x_enable_tx_delay(struct phy_device *phydev)
 395 {
 396         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
 397                                      AT803X_DEBUG_TX_CLK_DLY_EN);
 398 }
 399
 400 static int at803x_disable_rx_delay(struct phy_device *phydev)
 401 {
 402         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 403                                      AT803X_DEBUG_RX_CLK_DLY_EN, 0);
 404 }
 405
 406 static int at803x_disable_tx_delay(struct phy_device *phydev)
 407 {
 408         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
 409                                      AT803X_DEBUG_TX_CLK_DLY_EN, 0);
 410 }
 411
 412 /* save relevant PHY registers to private copy */
 413 static void at803x_context_save(struct phy_device *phydev,
 414                                 struct at803x_context *context)
 415 {
 416         context->bmcr = phy_read(phydev, MII_BMCR);
 417         context->advertise = phy_read(phydev, MII_ADVERTISE);
 418         context->control1000 = phy_read(phydev, MII_CTRL1000);
 419         context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 420         context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 421         context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 422 }
 423
 424 /* restore relevant PHY registers from private copy */
 425 static void at803x_context_restore(struct phy_device *phydev,
 426                                    const struct at803x_context *context)
 427 {
 428         phy_write(phydev, MII_BMCR, context->bmcr);
 429         phy_write(phydev, MII_ADVERTISE, context->advertise);
 430         phy_write(phydev, MII_CTRL1000, context->control1000);
 431         phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 432         phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 433         phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 434 }
 435
 436 static int at803x_set_wol(struct phy_device *phydev,
 437                           struct ethtool_wolinfo *wol)
 438 {
 439         int ret, irq_enabled;
 440
 441         if (wol->wolopts & WAKE_MAGIC) {
 442                 struct net_device *ndev = phydev->attached_dev;
 443                 const u8 *mac;
 444                 unsigned int i;
 445                 static const unsigned int offsets[] = {
 446                         AT803X_LOC_MAC_ADDR_32_47_OFFSET,
 447                         AT803X_LOC_MAC_ADDR_16_31_OFFSET,
 448                         AT803X_LOC_MAC_ADDR_0_15_OFFSET,
 449                 };
 450
 451                 if (!ndev)
 452                         return -ENODEV;
 453
 454                 mac = (const u8 *) ndev->dev_addr;
 455
 456                 if (!is_valid_ether_addr(mac))
 457                         return -EINVAL;
 458
 459                 for (i = 0; i < 3; i++)
 460                         phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
 461                                       mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
 462
 463                 /* Enable WOL function */
 464                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
 465                                 0, AT803X_WOL_EN);
 466                 if (ret)
 467                         return ret;
 468                 /* Enable WOL interrupt */
 469                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
 470                 if (ret)
 471                         return ret;
 472         } else {
 473                 /* Disable WoL function */
 474                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
 475                                 AT803X_WOL_EN, 0);
 476                 if (ret)
 477                         return ret;
 478                 /* Disable WOL interrupt */
 479                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
 480                 if (ret)
 481                         return ret;
 482         }
 483
 484         /* Clear WOL status */
 485         ret = phy_read(phydev, AT803X_INTR_STATUS);
 486         if (ret < 0)
 487                 return ret;
 488
 489         /* Check if there are other interrupts except for WOL triggered when PHY is
 490          * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
 491          * be passed up to the interrupt PIN.
 492          */
 493         irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
 494         if (irq_enabled < 0)
 495                 return irq_enabled;
 496
 497         irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
 498         if (ret & irq_enabled && !phy_polling_mode(phydev))
 499                 phy_trigger_machine(phydev);
 500
 501         return 0;
 502 }
 503
 504 static void at803x_get_wol(struct phy_device *phydev,
 505                            struct ethtool_wolinfo *wol)
 506 {
 507         int value;
 508
 509         wol->supported = WAKE_MAGIC;
 510         wol->wolopts = 0;
 511
 512         value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL);
 513         if (value < 0)
 514                 return;
 515
 516         if (value & AT803X_WOL_EN)
 517                 wol->wolopts |= WAKE_MAGIC;
 518 }
 519
 520 static int at803x_get_sset_count(struct phy_device *phydev)
 521 {
 522         return ARRAY_SIZE(at803x_hw_stats);
 523 }
 524
 525 static void at803x_get_strings(struct phy_device *phydev, u8 *data)
 526 {
 527         int i;
 528
 529         for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
 530                 strscpy(data + i * ETH_GSTRING_LEN,
 531                         at803x_hw_stats[i].string, ETH_GSTRING_LEN);
 532         }
 533 }
 534
 535 static u64 at803x_get_stat(struct phy_device *phydev, int i)
 536 {
 537         struct at803x_hw_stat stat = at803x_hw_stats[i];
 538         struct at803x_priv *priv = phydev->priv;
 539         int val;
 540         u64 ret;
 541
 542         if (stat.access_type == MMD)
 543                 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
 544         else
 545                 val = phy_read(phydev, stat.reg);
 546
 547         if (val < 0) {
 548                 ret = U64_MAX;
 549         } else {
 550                 val = val & stat.mask;
 551                 priv->stats[i] += val;
 552                 ret = priv->stats[i];
 553         }
 554
 555         return ret;
 556 }
 557
 558 static void at803x_get_stats(struct phy_device *phydev,
 559                              struct ethtool_stats *stats, u64 *data)
 560 {
 561         int i;
 562
 563         for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
 564                 data[i] = at803x_get_stat(phydev, i);
 565 }
 566
 567 static int at803x_suspend(struct phy_device *phydev)
 568 {
 569         int value;
 570         int wol_enabled;
 571
 572         value = phy_read(phydev, AT803X_INTR_ENABLE);
 573         wol_enabled = value & AT803X_INTR_ENABLE_WOL;
 574
 575         if (wol_enabled)
 576                 value = BMCR_ISOLATE;
 577         else
 578                 value = BMCR_PDOWN;
 579
 580         phy_modify(phydev, MII_BMCR, 0, value);
 581
 582         return 0;
 583 }
 584
 585 static int at803x_resume(struct phy_device *phydev)
 586 {
 587         return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
 588 }
 589
 590 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
 591                                             unsigned int selector)
 592 {
 593         struct phy_device *phydev = rdev_get_drvdata(rdev);
 594
 595         if (selector)
 596                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 597                                              0, AT803X_DEBUG_RGMII_1V8);
 598         else
 599                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 600                                              AT803X_DEBUG_RGMII_1V8, 0);
 601 }
 602
 603 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
 604 {
 605         struct phy_device *phydev = rdev_get_drvdata(rdev);
 606         int val;
 607
 608         val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
 609         if (val < 0)
 610                 return val;
 611
 612         return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
 613 }
 614
 615 static const struct regulator_ops vddio_regulator_ops = {
 616         .list_voltage = regulator_list_voltage_table,
 617         .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
 618         .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
 619 };
 620
 621 static const unsigned int vddio_voltage_table[] = {
 622         1500000,
 623         1800000,
 624 };
 625
 626 static const struct regulator_desc vddio_desc = {
 627         .name = "vddio",
 628         .of_match = of_match_ptr("vddio-regulator"),
 629         .n_voltages = ARRAY_SIZE(vddio_voltage_table),
 630         .volt_table = vddio_voltage_table,
 631         .ops = &vddio_regulator_ops,
 632         .type = REGULATOR_VOLTAGE,
 633         .owner = THIS_MODULE,
 634 };
 635
 636 static const struct regulator_ops vddh_regulator_ops = {
 637 };
 638
 639 static const struct regulator_desc vddh_desc = {
 640         .name = "vddh",
 641         .of_match = of_match_ptr("vddh-regulator"),
 642         .n_voltages = 1,
 643         .fixed_uV = 2500000,
 644         .ops = &vddh_regulator_ops,
 645         .type = REGULATOR_VOLTAGE,
 646         .owner = THIS_MODULE,
 647 };
 648
 649 static int at8031_register_regulators(struct phy_device *phydev)
 650 {
 651         struct at803x_priv *priv = phydev->priv;
 652         struct device *dev = &phydev->mdio.dev;
 653         struct regulator_config config = { };
 654
 655         config.dev = dev;
 656         config.driver_data = phydev;
 657
 658         priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
 659         if (IS_ERR(priv->vddio_rdev)) {
 660                 phydev_err(phydev, "failed to register VDDIO regulator\n");
 661                 return PTR_ERR(priv->vddio_rdev);
 662         }
 663
 664         priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
 665         if (IS_ERR(priv->vddh_rdev)) {
 666                 phydev_err(phydev, "failed to register VDDH regulator\n");
 667                 return PTR_ERR(priv->vddh_rdev);
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
 674 {
 675         struct phy_device *phydev = upstream;
 676         __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
 677         __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
 678         DECLARE_PHY_INTERFACE_MASK(interfaces);
 679         phy_interface_t iface;
 680
 681         linkmode_zero(phy_support);
 682         phylink_set(phy_support, 1000baseX_Full);
 683         phylink_set(phy_support, 1000baseT_Full);
 684         phylink_set(phy_support, Autoneg);
 685         phylink_set(phy_support, Pause);
 686         phylink_set(phy_support, Asym_Pause);
 687
 688         linkmode_zero(sfp_support);
 689         sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
 690         /* Some modules support 10G modes as well as others we support.
 691          * Mask out non-supported modes so the correct interface is picked.
 692          */
 693         linkmode_and(sfp_support, phy_support, sfp_support);
 694
 695         if (linkmode_empty(sfp_support)) {
 696                 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
 697                 return -EINVAL;
 698         }
 699
 700         iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
 701
 702         /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
 703          * interface for use with SFP modules.
 704          * However, some copper modules detected as having a preferred SGMII
 705          * interface do default to and function in 1000Base-X mode, so just
 706          * print a warning and allow such modules, as they may have some chance
 707          * of working.
 708          */
 709         if (iface == PHY_INTERFACE_MODE_SGMII)
 710                 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
 711         else if (iface != PHY_INTERFACE_MODE_1000BASEX)
 712                 return -EINVAL;
 713
 714         return 0;
 715 }
 716
 717 static const struct sfp_upstream_ops at803x_sfp_ops = {
 718         .attach = phy_sfp_attach,
 719         .detach = phy_sfp_detach,
 720         .module_insert = at803x_sfp_insert,
 721 };
 722
 723 static int at803x_parse_dt(struct phy_device *phydev)
 724 {
 725         struct device_node *node = phydev->mdio.dev.of_node;
 726         struct at803x_priv *priv = phydev->priv;
 727         u32 freq, strength, tw;
 728         unsigned int sel;
 729         int ret;
 730
 731         if (!IS_ENABLED(CONFIG_OF_MDIO))
 732                 return 0;
 733
 734         if (of_property_read_bool(node, "qca,disable-smarteee"))
 735                 priv->flags |= AT803X_DISABLE_SMARTEEE;
 736
 737         if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
 738                 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
 739
 740         if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
 741                 if (!tw || tw > 255) {
 742                         phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
 743                         return -EINVAL;
 744                 }
 745                 priv->smarteee_lpi_tw_1g = tw;
 746         }
 747
 748         if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
 749                 if (!tw || tw > 255) {
 750                         phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
 751                         return -EINVAL;
 752                 }
 753                 priv->smarteee_lpi_tw_100m = tw;
 754         }
 755
 756         ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
 757         if (!ret) {
 758                 switch (freq) {
 759                 case 25000000:
 760                         sel = AT803X_CLK_OUT_25MHZ_XTAL;
 761                         break;
 762                 case 50000000:
 763                         sel = AT803X_CLK_OUT_50MHZ_PLL;
 764                         break;
 765                 case 62500000:
 766                         sel = AT803X_CLK_OUT_62_5MHZ_PLL;
 767                         break;
 768                 case 125000000:
 769                         sel = AT803X_CLK_OUT_125MHZ_PLL;
 770                         break;
 771                 default:
 772                         phydev_err(phydev, "invalid qca,clk-out-frequency\n");
 773                         return -EINVAL;
 774                 }
 775
 776                 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
 777                 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
 778
 779                 /* Fixup for the AR8030/AR8035. This chip has another mask and
 780                  * doesn't support the DSP reference. Eg. the lowest bit of the
 781                  * mask. The upper two bits select the same frequencies. Mask
 782                  * the lowest bit here.
 783                  *
 784                  * Warning:
 785                  *   There was no datasheet for the AR8030 available so this is
 786                  *   just a guess. But the AR8035 is listed as pin compatible
 787                  *   to the AR8030 so there might be a good chance it works on
 788                  *   the AR8030 too.
 789                  */
 790                 if (phydev->drv->phy_id == ATH8030_PHY_ID ||
 791                     phydev->drv->phy_id == ATH8035_PHY_ID) {
 792                         priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
 793                         priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
 794                 }
 795         }
 796
 797         ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
 798         if (!ret) {
 799                 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
 800                 switch (strength) {
 801                 case AR803X_STRENGTH_FULL:
 802                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
 803                         break;
 804                 case AR803X_STRENGTH_HALF:
 805                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
 806                         break;
 807                 case AR803X_STRENGTH_QUARTER:
 808                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
 809                         break;
 810                 default:
 811                         phydev_err(phydev, "invalid qca,clk-out-strength\n");
 812                         return -EINVAL;
 813                 }
 814         }
 815
 816         /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
 817          * options.
 818          */
 819         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 820                 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
 821                         priv->flags |= AT803X_KEEP_PLL_ENABLED;
 822
 823                 ret = at8031_register_regulators(phydev);
 824                 if (ret < 0)
 825                         return ret;
 826
 827                 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
 828                                                           "vddio");
 829                 if (IS_ERR(priv->vddio)) {
 830                         phydev_err(phydev, "failed to get VDDIO regulator\n");
 831                         return PTR_ERR(priv->vddio);
 832                 }
 833
 834                 /* Only AR8031/8033 support 1000Base-X for SFP modules */
 835                 ret = phy_sfp_probe(phydev, &at803x_sfp_ops);
 836                 if (ret < 0)
 837                         return ret;
 838         }
 839
 840         return 0;
 841 }
 842
 843 static int at803x_probe(struct phy_device *phydev)
 844 {
 845         struct device *dev = &phydev->mdio.dev;
 846         struct at803x_priv *priv;
 847         int ret;
 848
 849         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 850         if (!priv)
 851                 return -ENOMEM;
 852
 853         phydev->priv = priv;
 854
 855         ret = at803x_parse_dt(phydev);
 856         if (ret)
 857                 return ret;
 858
 859         if (priv->vddio) {
 860                 ret = regulator_enable(priv->vddio);
 861                 if (ret < 0)
 862                         return ret;
 863         }
 864
 865         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 866                 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 867                 int mode_cfg;
 868                 struct ethtool_wolinfo wol = {
 869                         .wolopts = 0,
 870                 };
 871
 872                 if (ccr < 0) {
 873                         ret = ccr;
 874                         goto err;
 875                 }
 876                 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
 877
 878                 switch (mode_cfg) {
 879                 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
 880                 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
 881                         priv->is_1000basex = true;
 882                         fallthrough;
 883                 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
 884                 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
 885                         priv->is_fiber = true;
 886                         break;
 887                 }
 888
 889                 /* Disable WOL by default */
 890                 ret = at803x_set_wol(phydev, &wol);
 891                 if (ret < 0) {
 892                         phydev_err(phydev, "failed to disable WOL on probe: %d\n", ret);
 893                         goto err;
 894                 }
 895         }
 896
 897         return 0;
 898
 899 err:
 900         if (priv->vddio)
 901                 regulator_disable(priv->vddio);
 902
 903         return ret;
 904 }
 905
 906 static void at803x_remove(struct phy_device *phydev)
 907 {
 908         struct at803x_priv *priv = phydev->priv;
 909
 910         if (priv->vddio)
 911                 regulator_disable(priv->vddio);
 912 }
 913
 914 static int at803x_get_features(struct phy_device *phydev)
 915 {
 916         struct at803x_priv *priv = phydev->priv;
 917         int err;
 918
 919         err = genphy_read_abilities(phydev);
 920         if (err)
 921                 return err;
 922
 923         if (phydev->drv->phy_id == QCA8081_PHY_ID) {
 924                 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
 925                 if (err < 0)
 926                         return err;
 927
 928                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
 929                                 err & MDIO_PMA_NG_EXTABLE_2_5GBT);
 930         }
 931
 932         if (phydev->drv->phy_id != ATH8031_PHY_ID)
 933                 return 0;
 934
 935         /* AR8031/AR8033 have different status registers
 936          * for copper and fiber operation. However, the
 937          * extended status register is the same for both
 938          * operation modes.
 939          *
 940          * As a result of that, ESTATUS_1000_XFULL is set
 941          * to 1 even when operating in copper TP mode.
 942          *
 943          * Remove this mode from the supported link modes
 944          * when not operating in 1000BaseX mode.
 945          */
 946         if (!priv->is_1000basex)
 947                 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 948                                    phydev->supported);
 949
 950         return 0;
 951 }
 952
 953 static int at803x_smarteee_config(struct phy_device *phydev)
 954 {
 955         struct at803x_priv *priv = phydev->priv;
 956         u16 mask = 0, val = 0;
 957         int ret;
 958
 959         if (priv->flags & AT803X_DISABLE_SMARTEEE)
 960                 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
 961                                       AT803X_MMD3_SMARTEEE_CTL3,
 962                                       AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
 963
 964         if (priv->smarteee_lpi_tw_1g) {
 965                 mask |= 0xff00;
 966                 val |= priv->smarteee_lpi_tw_1g << 8;
 967         }
 968         if (priv->smarteee_lpi_tw_100m) {
 969                 mask |= 0x00ff;
 970                 val |= priv->smarteee_lpi_tw_100m;
 971         }
 972         if (!mask)
 973                 return 0;
 974
 975         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
 976                              mask, val);
 977         if (ret)
 978                 return ret;
 979
 980         return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
 981                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
 982                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
 983 }
 984
 985 static int at803x_clk_out_config(struct phy_device *phydev)
 986 {
 987         struct at803x_priv *priv = phydev->priv;
 988
 989         if (!priv->clk_25m_mask)
 990                 return 0;
 991
 992         return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
 993                               priv->clk_25m_mask, priv->clk_25m_reg);
 994 }
 995
 996 static int at8031_pll_config(struct phy_device *phydev)
 997 {
 998         struct at803x_priv *priv = phydev->priv;
 999
1000         /* The default after hardware reset is PLL OFF. After a soft reset, the
1001          * values are retained.
1002          */
1003         if (priv->flags & AT803X_KEEP_PLL_ENABLED)
1004                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1005                                              0, AT803X_DEBUG_PLL_ON);
1006         else
1007                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1008                                              AT803X_DEBUG_PLL_ON, 0);
1009 }
1010
1011 static int at803x_hibernation_mode_config(struct phy_device *phydev)
1012 {
1013         struct at803x_priv *priv = phydev->priv;
1014
1015         /* The default after hardware reset is hibernation mode enabled. After
1016          * software reset, the value is retained.
1017          */
1018         if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
1019                 return 0;
1020
1021         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1022                                          AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
1023 }
1024
1025 static int at803x_config_init(struct phy_device *phydev)
1026 {
1027         struct at803x_priv *priv = phydev->priv;
1028         int ret;
1029
1030         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
1031                 /* Some bootloaders leave the fiber page selected.
1032                  * Switch to the appropriate page (fiber or copper), as otherwise we
1033                  * read the PHY capabilities from the wrong page.
1034                  */
1035                 phy_lock_mdio_bus(phydev);
1036                 ret = at803x_write_page(phydev,
1037                                         priv->is_fiber ? AT803X_PAGE_FIBER :
1038                                                          AT803X_PAGE_COPPER);
1039                 phy_unlock_mdio_bus(phydev);
1040                 if (ret)
1041                         return ret;
1042
1043                 ret = at8031_pll_config(phydev);
1044                 if (ret < 0)
1045                         return ret;
1046         }
1047
1048         /* The RX and TX delay default is:
1049          *   after HW reset: RX delay enabled and TX delay disabled
1050          *   after SW reset: RX delay enabled, while TX delay retains the
1051          *   value before reset.
1052          */
1053         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1054             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1055                 ret = at803x_enable_rx_delay(phydev);
1056         else
1057                 ret = at803x_disable_rx_delay(phydev);
1058         if (ret < 0)
1059                 return ret;
1060
1061         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1062             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1063                 ret = at803x_enable_tx_delay(phydev);
1064         else
1065                 ret = at803x_disable_tx_delay(phydev);
1066         if (ret < 0)
1067                 return ret;
1068
1069         ret = at803x_smarteee_config(phydev);
1070         if (ret < 0)
1071                 return ret;
1072
1073         ret = at803x_clk_out_config(phydev);
1074         if (ret < 0)
1075                 return ret;
1076
1077         ret = at803x_hibernation_mode_config(phydev);
1078         if (ret < 0)
1079                 return ret;
1080
1081         /* Ar803x extended next page bit is enabled by default. Cisco
1082          * multigig switches read this bit and attempt to negotiate 10Gbps
1083          * rates even if the next page bit is disabled. This is incorrect
1084          * behaviour but we still need to accommodate it. XNP is only needed
1085          * for 10Gbps support, so disable XNP.
1086          */
1087         return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
1088 }
1089
1090 static int at803x_ack_interrupt(struct phy_device *phydev)
1091 {
1092         int err;
1093
1094         err = phy_read(phydev, AT803X_INTR_STATUS);
1095
1096         return (err < 0) ? err : 0;
1097 }
1098
1099 static int at803x_config_intr(struct phy_device *phydev)
1100 {
1101         struct at803x_priv *priv = phydev->priv;
1102         int err;
1103         int value;
1104
1105         value = phy_read(phydev, AT803X_INTR_ENABLE);
1106
1107         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1108                 /* Clear any pending interrupts */
1109                 err = at803x_ack_interrupt(phydev);
1110                 if (err)
1111                         return err;
1112
1113                 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
1114                 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
1115                 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
1116                 value |= AT803X_INTR_ENABLE_LINK_FAIL;
1117                 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
1118                 if (priv->is_fiber) {
1119                         value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1120                         value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1121                 }
1122
1123                 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
1124         } else {
1125                 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
1126                 if (err)
1127                         return err;
1128
1129                 /* Clear any pending interrupts */
1130                 err = at803x_ack_interrupt(phydev);
1131         }
1132
1133         return err;
1134 }
1135
1136 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
1137 {
1138         int irq_status, int_enabled;
1139
1140         irq_status = phy_read(phydev, AT803X_INTR_STATUS);
1141         if (irq_status < 0) {
1142                 phy_error(phydev);
1143                 return IRQ_NONE;
1144         }
1145
1146         /* Read the current enabled interrupts */
1147         int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
1148         if (int_enabled < 0) {
1149                 phy_error(phydev);
1150                 return IRQ_NONE;
1151         }
1152
1153         /* See if this was one of our enabled interrupts */
1154         if (!(irq_status & int_enabled))
1155                 return IRQ_NONE;
1156
1157         phy_trigger_machine(phydev);
1158
1159         return IRQ_HANDLED;
1160 }
1161
1162 static void at803x_link_change_notify(struct phy_device *phydev)
1163 {
1164         /*
1165          * Conduct a hardware reset for AT8030 every time a link loss is
1166          * signalled. This is necessary to circumvent a hardware bug that
1167          * occurs when the cable is unplugged while TX packets are pending
1168          * in the FIFO. In such cases, the FIFO enters an error mode it
1169          * cannot recover from by software.
1170          */
1171         if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
1172                 struct at803x_context context;
1173
1174                 at803x_context_save(phydev, &context);
1175
1176                 phy_device_reset(phydev, 1);
1177                 msleep(1);
1178                 phy_device_reset(phydev, 0);
1179                 msleep(1);
1180
1181                 at803x_context_restore(phydev, &context);
1182
1183                 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
1184         }
1185 }
1186
1187 static int at803x_read_specific_status(struct phy_device *phydev)
1188 {
1189         int ss;
1190
1191         /* Read the AT8035 PHY-Specific Status register, which indicates the
1192          * speed and duplex that the PHY is actually using, irrespective of
1193          * whether we are in autoneg mode or not.
1194          */
1195         ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
1196         if (ss < 0)
1197                 return ss;
1198
1199         if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
1200                 int sfc, speed;
1201
1202                 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
1203                 if (sfc < 0)
1204                         return sfc;
1205
1206                 /* qca8081 takes the different bits for speed value from at803x */
1207                 if (phydev->drv->phy_id == QCA8081_PHY_ID)
1208                         speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);
1209                 else
1210                         speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);
1211
1212                 switch (speed) {
1213                 case AT803X_SS_SPEED_10:
1214                         phydev->speed = SPEED_10;
1215                         break;
1216                 case AT803X_SS_SPEED_100:
1217                         phydev->speed = SPEED_100;
1218                         break;
1219                 case AT803X_SS_SPEED_1000:
1220                         phydev->speed = SPEED_1000;
1221                         break;
1222                 case QCA808X_SS_SPEED_2500:
1223                         phydev->speed = SPEED_2500;
1224                         break;
1225                 }
1226                 if (ss & AT803X_SS_DUPLEX)
1227                         phydev->duplex = DUPLEX_FULL;
1228                 else
1229                         phydev->duplex = DUPLEX_HALF;
1230
1231                 if (ss & AT803X_SS_MDIX)
1232                         phydev->mdix = ETH_TP_MDI_X;
1233                 else
1234                         phydev->mdix = ETH_TP_MDI;
1235
1236                 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1237                 case AT803X_SFC_MANUAL_MDI:
1238                         phydev->mdix_ctrl = ETH_TP_MDI;
1239                         break;
1240                 case AT803X_SFC_MANUAL_MDIX:
1241                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1242                         break;
1243                 case AT803X_SFC_AUTOMATIC_CROSSOVER:
1244                         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1245                         break;
1246                 }
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int at803x_read_status(struct phy_device *phydev)
1253 {
1254         struct at803x_priv *priv = phydev->priv;
1255         int err, old_link = phydev->link;
1256
1257         if (priv->is_1000basex)
1258                 return genphy_c37_read_status(phydev);
1259
1260         /* Update the link, but return if there was an error */
1261         err = genphy_update_link(phydev);
1262         if (err)
1263                 return err;
1264
1265         /* why bother the PHY if nothing can have changed */
1266         if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1267                 return 0;
1268
1269         phydev->speed = SPEED_UNKNOWN;
1270         phydev->duplex = DUPLEX_UNKNOWN;
1271         phydev->pause = 0;
1272         phydev->asym_pause = 0;
1273
1274         err = genphy_read_lpa(phydev);
1275         if (err < 0)
1276                 return err;
1277
1278         err = at803x_read_specific_status(phydev);
1279         if (err < 0)
1280                 return err;
1281
1282         if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1283                 phy_resolve_aneg_pause(phydev);
1284
1285         return 0;
1286 }
1287
1288 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1289 {
1290         u16 val;
1291
1292         switch (ctrl) {
1293         case ETH_TP_MDI:
1294                 val = AT803X_SFC_MANUAL_MDI;
1295                 break;
1296         case ETH_TP_MDI_X:
1297                 val = AT803X_SFC_MANUAL_MDIX;
1298                 break;
1299         case ETH_TP_MDI_AUTO:
1300                 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1301                 break;
1302         default:
1303                 return 0;
1304         }
1305
1306         return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1307                           AT803X_SFC_MDI_CROSSOVER_MODE_M,
1308                           FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1309 }
1310
1311 static int at803x_config_aneg(struct phy_device *phydev)
1312 {
1313         struct at803x_priv *priv = phydev->priv;
1314         int ret;
1315
1316         ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1317         if (ret < 0)
1318                 return ret;
1319
1320         /* Changes of the midx bits are disruptive to the normal operation;
1321          * therefore any changes to these registers must be followed by a
1322          * software reset to take effect.
1323          */
1324         if (ret == 1) {
1325                 ret = genphy_soft_reset(phydev);
1326                 if (ret < 0)
1327                         return ret;
1328         }
1329
1330         if (priv->is_1000basex)
1331                 return genphy_c37_config_aneg(phydev);
1332
1333         /* Do not restart auto-negotiation by setting ret to 0 defautly,
1334          * when calling __genphy_config_aneg later.
1335          */
1336         ret = 0;
1337
1338         if (phydev->drv->phy_id == QCA8081_PHY_ID) {
1339                 int phy_ctrl = 0;
1340
1341                 /* The reg MII_BMCR also needs to be configured for force mode, the
1342                  * genphy_config_aneg is also needed.
1343                  */
1344                 if (phydev->autoneg == AUTONEG_DISABLE)
1345                         genphy_c45_pma_setup_forced(phydev);
1346
1347                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
1348                         phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
1349
1350                 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1351                                 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
1352                 if (ret < 0)
1353                         return ret;
1354         }
1355
1356         return __genphy_config_aneg(phydev, ret);
1357 }
1358
1359 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1360 {
1361         int val;
1362
1363         val = phy_read(phydev, AT803X_SMART_SPEED);
1364         if (val < 0)
1365                 return val;
1366
1367         if (val & AT803X_SMART_SPEED_ENABLE)
1368                 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1369         else
1370                 *d = DOWNSHIFT_DEV_DISABLE;
1371
1372         return 0;
1373 }
1374
1375 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1376 {
1377         u16 mask, set;
1378         int ret;
1379
1380         switch (cnt) {
1381         case DOWNSHIFT_DEV_DEFAULT_COUNT:
1382                 cnt = AT803X_DEFAULT_DOWNSHIFT;
1383                 fallthrough;
1384         case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1385                 set = AT803X_SMART_SPEED_ENABLE |
1386                       AT803X_SMART_SPEED_BYPASS_TIMER |
1387                       FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1388                 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1389                 break;
1390         case DOWNSHIFT_DEV_DISABLE:
1391                 set = 0;
1392                 mask = AT803X_SMART_SPEED_ENABLE |
1393                        AT803X_SMART_SPEED_BYPASS_TIMER;
1394                 break;
1395         default:
1396                 return -EINVAL;
1397         }
1398
1399         ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1400
1401         /* After changing the smart speed settings, we need to perform a
1402          * software reset, use phy_init_hw() to make sure we set the
1403          * reapply any values which might got lost during software reset.
1404          */
1405         if (ret == 1)
1406                 ret = phy_init_hw(phydev);
1407
1408         return ret;
1409 }
1410
1411 static int at803x_get_tunable(struct phy_device *phydev,
1412                               struct ethtool_tunable *tuna, void *data)
1413 {
1414         switch (tuna->id) {
1415         case ETHTOOL_PHY_DOWNSHIFT:
1416                 return at803x_get_downshift(phydev, data);
1417         default:
1418                 return -EOPNOTSUPP;
1419         }
1420 }
1421
1422 static int at803x_set_tunable(struct phy_device *phydev,
1423                               struct ethtool_tunable *tuna, const void *data)
1424 {
1425         switch (tuna->id) {
1426         case ETHTOOL_PHY_DOWNSHIFT:
1427                 return at803x_set_downshift(phydev, *(const u8 *)data);
1428         default:
1429                 return -EOPNOTSUPP;
1430         }
1431 }
1432
1433 static int at803x_cable_test_result_trans(u16 status)
1434 {
1435         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1436         case AT803X_CDT_STATUS_STAT_NORMAL:
1437                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1438         case AT803X_CDT_STATUS_STAT_SHORT:
1439                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1440         case AT803X_CDT_STATUS_STAT_OPEN:
1441                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1442         case AT803X_CDT_STATUS_STAT_FAIL:
1443         default:
1444                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1445         }
1446 }
1447
1448 static bool at803x_cdt_test_failed(u16 status)
1449 {
1450         return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1451                 AT803X_CDT_STATUS_STAT_FAIL;
1452 }
1453
1454 static bool at803x_cdt_fault_length_valid(u16 status)
1455 {
1456         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1457         case AT803X_CDT_STATUS_STAT_OPEN:
1458         case AT803X_CDT_STATUS_STAT_SHORT:
1459                 return true;
1460         }
1461         return false;
1462 }
1463
1464 static int at803x_cdt_fault_length(u16 status)
1465 {
1466         int dt;
1467
1468         /* According to the datasheet the distance to the fault is
1469          * DELTA_TIME * 0.824 meters.
1470          *
1471          * The author suspect the correct formula is:
1472          *
1473          *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1474          *
1475          * where c is the speed of light, VF is the velocity factor of
1476          * the twisted pair cable, 125MHz the counter frequency and
1477          * we need to divide by 2 because the hardware will measure the
1478          * round trip time to the fault and back to the PHY.
1479          *
1480          * With a VF of 0.69 we get the factor 0.824 mentioned in the
1481          * datasheet.
1482          */
1483         dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1484
1485         return (dt * 824) / 10;
1486 }
1487
1488 static int at803x_cdt_start(struct phy_device *phydev, int pair)
1489 {
1490         u16 cdt;
1491
1492         /* qca8081 takes the different bit 15 to enable CDT test */
1493         if (phydev->drv->phy_id == QCA8081_PHY_ID)
1494                 cdt = QCA808X_CDT_ENABLE_TEST |
1495                         QCA808X_CDT_LENGTH_UNIT |
1496                         QCA808X_CDT_INTER_CHECK_DIS;
1497         else
1498                 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1499                         AT803X_CDT_ENABLE_TEST;
1500
1501         return phy_write(phydev, AT803X_CDT, cdt);
1502 }
1503
1504 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1505 {
1506         int val, ret;
1507         u16 cdt_en;
1508
1509         if (phydev->drv->phy_id == QCA8081_PHY_ID)
1510                 cdt_en = QCA808X_CDT_ENABLE_TEST;
1511         else
1512                 cdt_en = AT803X_CDT_ENABLE_TEST;
1513
1514         /* One test run takes about 25ms */
1515         ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1516                                     !(val & cdt_en),
1517                                     30000, 100000, true);
1518
1519         return ret < 0 ? ret : 0;
1520 }
1521
1522 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1523 {
1524         static const int ethtool_pair[] = {
1525                 ETHTOOL_A_CABLE_PAIR_A,
1526                 ETHTOOL_A_CABLE_PAIR_B,
1527                 ETHTOOL_A_CABLE_PAIR_C,
1528                 ETHTOOL_A_CABLE_PAIR_D,
1529         };
1530         int ret, val;
1531
1532         ret = at803x_cdt_start(phydev, pair);
1533         if (ret)
1534                 return ret;
1535
1536         ret = at803x_cdt_wait_for_completion(phydev);
1537         if (ret)
1538                 return ret;
1539
1540         val = phy_read(phydev, AT803X_CDT_STATUS);
1541         if (val < 0)
1542                 return val;
1543
1544         if (at803x_cdt_test_failed(val))
1545                 return 0;
1546
1547         ethnl_cable_test_result(phydev, ethtool_pair[pair],
1548                                 at803x_cable_test_result_trans(val));
1549
1550         if (at803x_cdt_fault_length_valid(val))
1551                 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1552                                               at803x_cdt_fault_length(val));
1553
1554         return 1;
1555 }
1556
1557 static int at803x_cable_test_get_status(struct phy_device *phydev,
1558                                         bool *finished)
1559 {
1560         unsigned long pair_mask;
1561         int retries = 20;
1562         int pair, ret;
1563
1564         if (phydev->phy_id == ATH9331_PHY_ID ||
1565             phydev->phy_id == ATH8032_PHY_ID ||
1566             phydev->phy_id == QCA9561_PHY_ID)
1567                 pair_mask = 0x3;
1568         else
1569                 pair_mask = 0xf;
1570
1571         *finished = false;
1572
1573         /* According to the datasheet the CDT can be performed when
1574          * there is no link partner or when the link partner is
1575          * auto-negotiating. Starting the test will restart the AN
1576          * automatically. It seems that doing this repeatedly we will
1577          * get a slot where our link partner won't disturb our
1578          * measurement.
1579          */
1580         while (pair_mask && retries--) {
1581                 for_each_set_bit(pair, &pair_mask, 4) {
1582                         ret = at803x_cable_test_one_pair(phydev, pair);
1583                         if (ret < 0)
1584                                 return ret;
1585                         if (ret)
1586                                 clear_bit(pair, &pair_mask);
1587                 }
1588                 if (pair_mask)
1589                         msleep(250);
1590         }
1591
1592         *finished = true;
1593
1594         return 0;
1595 }
1596
1597 static int at803x_cable_test_start(struct phy_device *phydev)
1598 {
1599         /* Enable auto-negotiation, but advertise no capabilities, no link
1600          * will be established. A restart of the auto-negotiation is not
1601          * required, because the cable test will automatically break the link.
1602          */
1603         phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1604         phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1605         if (phydev->phy_id != ATH9331_PHY_ID &&
1606             phydev->phy_id != ATH8032_PHY_ID &&
1607             phydev->phy_id != QCA9561_PHY_ID)
1608                 phy_write(phydev, MII_CTRL1000, 0);
1609
1610         /* we do all the (time consuming) work later */
1611         return 0;
1612 }
1613
1614 static int qca83xx_config_init(struct phy_device *phydev)
1615 {
1616         u8 switch_revision;
1617
1618         switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1619
1620         switch (switch_revision) {
1621         case 1:
1622                 /* For 100M waveform */
1623                 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1624                 /* Turn on Gigabit clock */
1625                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1626                 break;
1627
1628         case 2:
1629                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1630                 fallthrough;
1631         case 4:
1632                 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1633                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1634                 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1635                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1636                 break;
1637         }
1638
1639         /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1640          * Disable on init and enable only with 100m speed following
1641          * qca original source code.
1642          */
1643         if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
1644             phydev->drv->phy_id == QCA8327_B_PHY_ID)
1645                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1646                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1647
1648         /* Following original QCA sourcecode set port to prefer master */
1649         phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1650
1651         return 0;
1652 }
1653
1654 static void qca83xx_link_change_notify(struct phy_device *phydev)
1655 {
1656         /* QCA8337 doesn't require DAC Amplitude adjustement */
1657         if (phydev->drv->phy_id == QCA8337_PHY_ID)
1658                 return;
1659
1660         /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1661         if (phydev->state == PHY_RUNNING) {
1662                 if (phydev->speed == SPEED_100)
1663                         at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1664                                               QCA8327_DEBUG_MANU_CTRL_EN,
1665                                               QCA8327_DEBUG_MANU_CTRL_EN);
1666         } else {
1667                 /* Reset DAC Amplitude adjustment */
1668                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1669                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1670         }
1671 }
1672
1673 static int qca83xx_resume(struct phy_device *phydev)
1674 {
1675         int ret, val;
1676
1677         /* Skip reset if not suspended */
1678         if (!phydev->suspended)
1679                 return 0;
1680
1681         /* Reinit the port, reset values set by suspend */
1682         qca83xx_config_init(phydev);
1683
1684         /* Reset the port on port resume */
1685         phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1686
1687         /* On resume from suspend the switch execute a reset and
1688          * restart auto-negotiation. Wait for reset to complete.
1689          */
1690         ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1691                                     50000, 600000, true);
1692         if (ret)
1693                 return ret;
1694
1695         msleep(1);
1696
1697         return 0;
1698 }
1699
1700 static int qca83xx_suspend(struct phy_device *phydev)
1701 {
1702         u16 mask = 0;
1703
1704         /* Only QCA8337 support actual suspend.
1705          * QCA8327 cause port unreliability when phy suspend
1706          * is set.
1707          */
1708         if (phydev->drv->phy_id == QCA8337_PHY_ID) {
1709                 genphy_suspend(phydev);
1710         } else {
1711                 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1712                 phy_modify(phydev, MII_BMCR, mask, 0);
1713         }
1714
1715         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1716                               AT803X_DEBUG_GATE_CLK_IN1000, 0);
1717
1718         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1719                               AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1720                               AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1721
1722         return 0;
1723 }
1724
1725 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1726 {
1727         int ret;
1728
1729         /* Enable fast retrain */
1730         ret = genphy_c45_fast_retrain(phydev, true);
1731         if (ret)
1732                 return ret;
1733
1734         phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1735                         QCA808X_TOP_OPTION1_DATA);
1736         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1737                         QCA808X_MSE_THRESHOLD_20DB_VALUE);
1738         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1739                         QCA808X_MSE_THRESHOLD_17DB_VALUE);
1740         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1741                         QCA808X_MSE_THRESHOLD_27DB_VALUE);
1742         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1743                         QCA808X_MSE_THRESHOLD_28DB_VALUE);
1744         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1745                         QCA808X_MMD3_DEBUG_1_VALUE);
1746         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1747                         QCA808X_MMD3_DEBUG_4_VALUE);
1748         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1749                         QCA808X_MMD3_DEBUG_5_VALUE);
1750         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1751                         QCA808X_MMD3_DEBUG_3_VALUE);
1752         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1753                         QCA808X_MMD3_DEBUG_6_VALUE);
1754         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1755                         QCA808X_MMD3_DEBUG_2_VALUE);
1756
1757         return 0;
1758 }
1759
1760 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev)
1761 {
1762         u16 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE);
1763
1764         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1765                         QCA808X_MASTER_SLAVE_SEED_CFG,
1766                         FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value));
1767 }
1768
1769 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1770 {
1771         u16 seed_enable = 0;
1772
1773         if (enable)
1774                 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE;
1775
1776         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1777                         QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable);
1778 }
1779
1780 static int qca808x_config_init(struct phy_device *phydev)
1781 {
1782         int ret;
1783
1784         /* Active adc&vga on 802.3az for the link 1000M and 100M */
1785         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1786                         QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1787         if (ret)
1788                 return ret;
1789
1790         /* Adjust the threshold on 802.3az for the link 1000M */
1791         ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1792                         QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
1793         if (ret)
1794                 return ret;
1795
1796         /* Config the fast retrain for the link 2500M */
1797         ret = qca808x_phy_fast_retrain_config(phydev);
1798         if (ret)
1799                 return ret;
1800
1801         /* Configure lower ramdom seed to make phy linked as slave mode */
1802         ret = qca808x_phy_ms_random_seed_set(phydev);
1803         if (ret)
1804                 return ret;
1805
1806         /* Enable seed */
1807         ret = qca808x_phy_ms_seed_enable(phydev, true);
1808         if (ret)
1809                 return ret;
1810
1811         /* Configure adc threshold as 100mv for the link 10M */
1812         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1813                         QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
1814 }
1815
1816 static int qca808x_read_status(struct phy_device *phydev)
1817 {
1818         int ret;
1819
1820         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1821         if (ret < 0)
1822                 return ret;
1823
1824         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
1825                         ret & MDIO_AN_10GBT_STAT_LP2_5G);
1826
1827         ret = genphy_read_status(phydev);
1828         if (ret)
1829                 return ret;
1830
1831         ret = at803x_read_specific_status(phydev);
1832         if (ret < 0)
1833                 return ret;
1834
1835         if (phydev->link) {
1836                 if (phydev->speed == SPEED_2500)
1837                         phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1838                 else
1839                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
1840         } else {
1841                 /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1842                  * except for master/slave configuration fault detected.
1843                  * the reason for not putting this code into the function link_change_notify is
1844                  * the corner case where the link partner is also the qca8081 PHY and the seed
1845                  * value is configured as the same value, the link can't be up and no link change
1846                  * occurs.
1847                  */
1848                 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
1849                         qca808x_phy_ms_seed_enable(phydev, false);
1850                 } else {
1851                         qca808x_phy_ms_random_seed_set(phydev);
1852                         qca808x_phy_ms_seed_enable(phydev, true);
1853                 }
1854         }
1855
1856         return 0;
1857 }
1858
1859 static int qca808x_soft_reset(struct phy_device *phydev)
1860 {
1861         int ret;
1862
1863         ret = genphy_soft_reset(phydev);
1864         if (ret < 0)
1865                 return ret;
1866
1867         return qca808x_phy_ms_seed_enable(phydev, true);
1868 }
1869
1870 static bool qca808x_cdt_fault_length_valid(int cdt_code)
1871 {
1872         switch (cdt_code) {
1873         case QCA808X_CDT_STATUS_STAT_SHORT:
1874         case QCA808X_CDT_STATUS_STAT_OPEN:
1875                 return true;
1876         default:
1877                 return false;
1878         }
1879 }
1880
1881 static int qca808x_cable_test_result_trans(int cdt_code)
1882 {
1883         switch (cdt_code) {
1884         case QCA808X_CDT_STATUS_STAT_NORMAL:
1885                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1886         case QCA808X_CDT_STATUS_STAT_SHORT:
1887                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1888         case QCA808X_CDT_STATUS_STAT_OPEN:
1889                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1890         case QCA808X_CDT_STATUS_STAT_FAIL:
1891         default:
1892                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1893         }
1894 }
1895
1896 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)
1897 {
1898         int val;
1899         u32 cdt_length_reg = 0;
1900
1901         switch (pair) {
1902         case ETHTOOL_A_CABLE_PAIR_A:
1903                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
1904                 break;
1905         case ETHTOOL_A_CABLE_PAIR_B:
1906                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
1907                 break;
1908         case ETHTOOL_A_CABLE_PAIR_C:
1909                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
1910                 break;
1911         case ETHTOOL_A_CABLE_PAIR_D:
1912                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
1913                 break;
1914         default:
1915                 return -EINVAL;
1916         }
1917
1918         val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
1919         if (val < 0)
1920                 return val;
1921
1922         return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;
1923 }
1924
1925 static int qca808x_cable_test_start(struct phy_device *phydev)
1926 {
1927         int ret;
1928
1929         /* perform CDT with the following configs:
1930          * 1. disable hibernation.
1931          * 2. force PHY working in MDI mode.
1932          * 3. for PHY working in 1000BaseT.
1933          * 4. configure the threshold.
1934          */
1935
1936         ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
1937         if (ret < 0)
1938                 return ret;
1939
1940         ret = at803x_config_mdix(phydev, ETH_TP_MDI);
1941         if (ret < 0)
1942                 return ret;
1943
1944         /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
1945         phydev->duplex = DUPLEX_FULL;
1946         phydev->speed = SPEED_1000;
1947         ret = genphy_c45_pma_setup_forced(phydev);
1948         if (ret < 0)
1949                 return ret;
1950
1951         ret = genphy_setup_forced(phydev);
1952         if (ret < 0)
1953                 return ret;
1954
1955         /* configure the thresholds for open, short, pair ok test */
1956         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
1957         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
1958         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
1959         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
1960         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
1961         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
1962
1963         return 0;
1964 }
1965
1966 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
1967 {
1968         int ret, val;
1969         int pair_a, pair_b, pair_c, pair_d;
1970
1971         *finished = false;
1972
1973         ret = at803x_cdt_start(phydev, 0);
1974         if (ret)
1975                 return ret;
1976
1977         ret = at803x_cdt_wait_for_completion(phydev);
1978         if (ret)
1979                 return ret;
1980
1981         val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
1982         if (val < 0)
1983                 return val;
1984
1985         pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);
1986         pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);
1987         pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);
1988         pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);
1989
1990         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1991                                 qca808x_cable_test_result_trans(pair_a));
1992         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
1993                                 qca808x_cable_test_result_trans(pair_b));
1994         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
1995                                 qca808x_cable_test_result_trans(pair_c));
1996         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
1997                                 qca808x_cable_test_result_trans(pair_d));
1998
1999         if (qca808x_cdt_fault_length_valid(pair_a))
2000                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
2001                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));
2002         if (qca808x_cdt_fault_length_valid(pair_b))
2003                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,
2004                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));
2005         if (qca808x_cdt_fault_length_valid(pair_c))
2006                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,
2007                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));
2008         if (qca808x_cdt_fault_length_valid(pair_d))
2009                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,
2010                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));
2011
2012         *finished = true;
2013
2014         return 0;
2015 }
2016
2017 static struct phy_driver at803x_driver[] = {
2018 {
2019         /* Qualcomm Atheros AR8035 */
2020         PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
2021         .name                   = "Qualcomm Atheros AR8035",
2022         .flags                  = PHY_POLL_CABLE_TEST,
2023         .probe                  = at803x_probe,
2024         .remove                 = at803x_remove,
2025         .config_aneg            = at803x_config_aneg,
2026         .config_init            = at803x_config_init,
2027         .soft_reset             = genphy_soft_reset,
2028         .set_wol                = at803x_set_wol,
2029         .get_wol                = at803x_get_wol,
2030         .suspend                = at803x_suspend,
2031         .resume                 = at803x_resume,
2032         /* PHY_GBIT_FEATURES */
2033         .read_status            = at803x_read_status,
2034         .config_intr            = at803x_config_intr,
2035         .handle_interrupt       = at803x_handle_interrupt,
2036         .get_tunable            = at803x_get_tunable,
2037         .set_tunable            = at803x_set_tunable,
2038         .cable_test_start       = at803x_cable_test_start,
2039         .cable_test_get_status  = at803x_cable_test_get_status,
2040 }, {
2041         /* Qualcomm Atheros AR8030 */
2042         .phy_id                 = ATH8030_PHY_ID,
2043         .name                   = "Qualcomm Atheros AR8030",
2044         .phy_id_mask            = AT8030_PHY_ID_MASK,
2045         .probe                  = at803x_probe,
2046         .remove                 = at803x_remove,
2047         .config_init            = at803x_config_init,
2048         .link_change_notify     = at803x_link_change_notify,
2049         .set_wol                = at803x_set_wol,
2050         .get_wol                = at803x_get_wol,
2051         .suspend                = at803x_suspend,
2052         .resume                 = at803x_resume,
2053         /* PHY_BASIC_FEATURES */
2054         .config_intr            = at803x_config_intr,
2055         .handle_interrupt       = at803x_handle_interrupt,
2056 }, {
2057         /* Qualcomm Atheros AR8031/AR8033 */
2058         PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2059         .name                   = "Qualcomm Atheros AR8031/AR8033",
2060         .flags                  = PHY_POLL_CABLE_TEST,
2061         .probe                  = at803x_probe,
2062         .remove                 = at803x_remove,
2063         .config_init            = at803x_config_init,
2064         .config_aneg            = at803x_config_aneg,
2065         .soft_reset             = genphy_soft_reset,
2066         .set_wol                = at803x_set_wol,
2067         .get_wol                = at803x_get_wol,
2068         .suspend                = at803x_suspend,
2069         .resume                 = at803x_resume,
2070         .read_page              = at803x_read_page,
2071         .write_page             = at803x_write_page,
2072         .get_features           = at803x_get_features,
2073         .read_status            = at803x_read_status,
2074         .config_intr            = &at803x_config_intr,
2075         .handle_interrupt       = at803x_handle_interrupt,
2076         .get_tunable            = at803x_get_tunable,
2077         .set_tunable            = at803x_set_tunable,
2078         .cable_test_start       = at803x_cable_test_start,
2079         .cable_test_get_status  = at803x_cable_test_get_status,
2080 }, {
2081         /* Qualcomm Atheros AR8032 */
2082         PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2083         .name                   = "Qualcomm Atheros AR8032",
2084         .probe                  = at803x_probe,
2085         .remove                 = at803x_remove,
2086         .flags                  = PHY_POLL_CABLE_TEST,
2087         .config_init            = at803x_config_init,
2088         .link_change_notify     = at803x_link_change_notify,
2089         .set_wol                = at803x_set_wol,
2090         .get_wol                = at803x_get_wol,
2091         .suspend                = at803x_suspend,
2092         .resume                 = at803x_resume,
2093         /* PHY_BASIC_FEATURES */
2094         .config_intr            = at803x_config_intr,
2095         .handle_interrupt       = at803x_handle_interrupt,
2096         .cable_test_start       = at803x_cable_test_start,
2097         .cable_test_get_status  = at803x_cable_test_get_status,
2098 }, {
2099         /* ATHEROS AR9331 */
2100         PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2101         .name                   = "Qualcomm Atheros AR9331 built-in PHY",
2102         .probe                  = at803x_probe,
2103         .remove                 = at803x_remove,
2104         .suspend                = at803x_suspend,
2105         .resume                 = at803x_resume,
2106         .flags                  = PHY_POLL_CABLE_TEST,
2107         /* PHY_BASIC_FEATURES */
2108         .config_intr            = &at803x_config_intr,
2109         .handle_interrupt       = at803x_handle_interrupt,
2110         .cable_test_start       = at803x_cable_test_start,
2111         .cable_test_get_status  = at803x_cable_test_get_status,
2112         .read_status            = at803x_read_status,
2113         .soft_reset             = genphy_soft_reset,
2114         .config_aneg            = at803x_config_aneg,
2115 }, {
2116         /* Qualcomm Atheros QCA9561 */
2117         PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2118         .name                   = "Qualcomm Atheros QCA9561 built-in PHY",
2119         .probe                  = at803x_probe,
2120         .remove                 = at803x_remove,
2121         .suspend                = at803x_suspend,
2122         .resume                 = at803x_resume,
2123         .flags                  = PHY_POLL_CABLE_TEST,
2124         /* PHY_BASIC_FEATURES */
2125         .config_intr            = &at803x_config_intr,
2126         .handle_interrupt       = at803x_handle_interrupt,
2127         .cable_test_start       = at803x_cable_test_start,
2128         .cable_test_get_status  = at803x_cable_test_get_status,
2129         .read_status            = at803x_read_status,
2130         .soft_reset             = genphy_soft_reset,
2131         .config_aneg            = at803x_config_aneg,
2132 }, {
2133         /* QCA8337 */
2134         .phy_id                 = QCA8337_PHY_ID,
2135         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2136         .name                   = "Qualcomm Atheros 8337 internal PHY",
2137         /* PHY_GBIT_FEATURES */
2138         .link_change_notify     = qca83xx_link_change_notify,
2139         .probe                  = at803x_probe,
2140         .flags                  = PHY_IS_INTERNAL,
2141         .config_init            = qca83xx_config_init,
2142         .soft_reset             = genphy_soft_reset,
2143         .get_sset_count         = at803x_get_sset_count,
2144         .get_strings            = at803x_get_strings,
2145         .get_stats              = at803x_get_stats,
2146         .suspend                = qca83xx_suspend,
2147         .resume                 = qca83xx_resume,
2148 }, {
2149         /* QCA8327-A from switch QCA8327-AL1A */
2150         .phy_id                 = QCA8327_A_PHY_ID,
2151         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2152         .name                   = "Qualcomm Atheros 8327-A internal PHY",
2153         /* PHY_GBIT_FEATURES */
2154         .link_change_notify     = qca83xx_link_change_notify,
2155         .probe                  = at803x_probe,
2156         .flags                  = PHY_IS_INTERNAL,
2157         .config_init            = qca83xx_config_init,
2158         .soft_reset             = genphy_soft_reset,
2159         .get_sset_count         = at803x_get_sset_count,
2160         .get_strings            = at803x_get_strings,
2161         .get_stats              = at803x_get_stats,
2162         .suspend                = qca83xx_suspend,
2163         .resume                 = qca83xx_resume,
2164 }, {
2165         /* QCA8327-B from switch QCA8327-BL1A */
2166         .phy_id                 = QCA8327_B_PHY_ID,
2167         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2168         .name                   = "Qualcomm Atheros 8327-B internal PHY",
2169         /* PHY_GBIT_FEATURES */
2170         .link_change_notify     = qca83xx_link_change_notify,
2171         .probe                  = at803x_probe,
2172         .flags                  = PHY_IS_INTERNAL,
2173         .config_init            = qca83xx_config_init,
2174         .soft_reset             = genphy_soft_reset,
2175         .get_sset_count         = at803x_get_sset_count,
2176         .get_strings            = at803x_get_strings,
2177         .get_stats              = at803x_get_stats,
2178         .suspend                = qca83xx_suspend,
2179         .resume                 = qca83xx_resume,
2180 }, {
2181         /* Qualcomm QCA8081 */
2182         PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2183         .name                   = "Qualcomm QCA8081",
2184         .flags                  = PHY_POLL_CABLE_TEST,
2185         .probe                  = at803x_probe,
2186         .remove                 = at803x_remove,
2187         .config_intr            = at803x_config_intr,
2188         .handle_interrupt       = at803x_handle_interrupt,
2189         .get_tunable            = at803x_get_tunable,
2190         .set_tunable            = at803x_set_tunable,
2191         .set_wol                = at803x_set_wol,
2192         .get_wol                = at803x_get_wol,
2193         .get_features           = at803x_get_features,
2194         .config_aneg            = at803x_config_aneg,
2195         .suspend                = genphy_suspend,
2196         .resume                 = genphy_resume,
2197         .read_status            = qca808x_read_status,
2198         .config_init            = qca808x_config_init,
2199         .soft_reset             = qca808x_soft_reset,
2200         .cable_test_start       = qca808x_cable_test_start,
2201         .cable_test_get_status  = qca808x_cable_test_get_status,
2202 }, };
2203
2204 module_phy_driver(at803x_driver);
2205
2206 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2207         { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2208         { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2209         { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2210         { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2211         { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2212         { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2213         { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2214         { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2215         { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2216         { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2217         { }
2218 };
2219
2220 MODULE_DEVICE_TABLE(mdio, atheros_tbl);