drivers/net/ethernet/ni/nixge.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016-2017, National Instruments Corp.
   3  *
   4  * Author: Moritz Fischer <[email protected]>
   5  */
   6
   7 #include <linux/etherdevice.h>
   8 #include <linux/module.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_mdio.h>
  12 #include <linux/of_net.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/phy.h>
  17 #include <linux/mii.h>
  18 #include <linux/nvmem-consumer.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/iopoll.h>
  21
  22 #define TX_BD_NUM               64
  23 #define RX_BD_NUM               128
  24
  25 /* Axi DMA Register definitions */
  26 #define XAXIDMA_TX_CR_OFFSET    0x00 /* Channel control */
  27 #define XAXIDMA_TX_SR_OFFSET    0x04 /* Status */
  28 #define XAXIDMA_TX_CDESC_OFFSET 0x08 /* Current descriptor pointer */
  29 #define XAXIDMA_TX_TDESC_OFFSET 0x10 /* Tail descriptor pointer */
  30
  31 #define XAXIDMA_RX_CR_OFFSET    0x30 /* Channel control */
  32 #define XAXIDMA_RX_SR_OFFSET    0x34 /* Status */
  33 #define XAXIDMA_RX_CDESC_OFFSET 0x38 /* Current descriptor pointer */
  34 #define XAXIDMA_RX_TDESC_OFFSET 0x40 /* Tail descriptor pointer */
  35
  36 #define XAXIDMA_CR_RUNSTOP_MASK 0x1 /* Start/stop DMA channel */
  37 #define XAXIDMA_CR_RESET_MASK   0x4 /* Reset DMA engine */
  38
  39 #define XAXIDMA_BD_CTRL_LENGTH_MASK     0x007FFFFF /* Requested len */
  40 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  41 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  42 #define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
  43
  44 #define XAXIDMA_DELAY_MASK              0xFF000000 /* Delay timeout counter */
  45 #define XAXIDMA_COALESCE_MASK           0x00FF0000 /* Coalesce counter */
  46
  47 #define XAXIDMA_DELAY_SHIFT             24
  48 #define XAXIDMA_COALESCE_SHIFT          16
  49
  50 #define XAXIDMA_IRQ_IOC_MASK            0x00001000 /* Completion intr */
  51 #define XAXIDMA_IRQ_DELAY_MASK          0x00002000 /* Delay interrupt */
  52 #define XAXIDMA_IRQ_ERROR_MASK          0x00004000 /* Error interrupt */
  53 #define XAXIDMA_IRQ_ALL_MASK            0x00007000 /* All interrupts */
  54
  55 /* Default TX/RX Threshold and waitbound values for SGDMA mode */
  56 #define XAXIDMA_DFT_TX_THRESHOLD        24
  57 #define XAXIDMA_DFT_TX_WAITBOUND        254
  58 #define XAXIDMA_DFT_RX_THRESHOLD        24
  59 #define XAXIDMA_DFT_RX_WAITBOUND        254
  60
  61 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */
  62 #define XAXIDMA_BD_STS_COMPLETE_MASK    0x80000000 /* Completed */
  63 #define XAXIDMA_BD_STS_DEC_ERR_MASK     0x40000000 /* Decode error */
  64 #define XAXIDMA_BD_STS_SLV_ERR_MASK     0x20000000 /* Slave error */
  65 #define XAXIDMA_BD_STS_INT_ERR_MASK     0x10000000 /* Internal err */
  66 #define XAXIDMA_BD_STS_ALL_ERR_MASK     0x70000000 /* All errors */
  67 #define XAXIDMA_BD_STS_RXSOF_MASK       0x08000000 /* First rx pkt */
  68 #define XAXIDMA_BD_STS_RXEOF_MASK       0x04000000 /* Last rx pkt */
  69 #define XAXIDMA_BD_STS_ALL_MASK         0xFC000000 /* All status bits */
  70
  71 #define NIXGE_REG_CTRL_OFFSET   0x4000
  72 #define NIXGE_REG_INFO          0x00
  73 #define NIXGE_REG_MAC_CTL       0x04
  74 #define NIXGE_REG_PHY_CTL       0x08
  75 #define NIXGE_REG_LED_CTL       0x0c
  76 #define NIXGE_REG_MDIO_DATA     0x10
  77 #define NIXGE_REG_MDIO_ADDR     0x14
  78 #define NIXGE_REG_MDIO_OP       0x18
  79 #define NIXGE_REG_MDIO_CTRL     0x1c
  80
  81 #define NIXGE_ID_LED_CTL_EN     BIT(0)
  82 #define NIXGE_ID_LED_CTL_VAL    BIT(1)
  83
  84 #define NIXGE_MDIO_CLAUSE45     BIT(12)
  85 #define NIXGE_MDIO_CLAUSE22     0
  86 #define NIXGE_MDIO_OP(n)     (((n) & 0x3) << 10)
  87 #define NIXGE_MDIO_OP_ADDRESS   0
  88 #define NIXGE_MDIO_C45_WRITE    BIT(0)
  89 #define NIXGE_MDIO_C45_READ     (BIT(1) | BIT(0))
  90 #define NIXGE_MDIO_C22_WRITE    BIT(0)
  91 #define NIXGE_MDIO_C22_READ     BIT(1)
  92 #define NIXGE_MDIO_ADDR(n)   (((n) & 0x1f) << 5)
  93 #define NIXGE_MDIO_MMD(n)    (((n) & 0x1f) << 0)
  94
  95 #define NIXGE_REG_MAC_LSB       0x1000
  96 #define NIXGE_REG_MAC_MSB       0x1004
  97
  98 /* Packet size info */
  99 #define NIXGE_HDR_SIZE          14 /* Size of Ethernet header */
 100 #define NIXGE_TRL_SIZE          4 /* Size of Ethernet trailer (FCS) */
 101 #define NIXGE_MTU               1500 /* Max MTU of an Ethernet frame */
 102 #define NIXGE_JUMBO_MTU         9000 /* Max MTU of a jumbo Eth. frame */
 103
 104 #define NIXGE_MAX_FRAME_SIZE     (NIXGE_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
 105 #define NIXGE_MAX_JUMBO_FRAME_SIZE \
 106         (NIXGE_JUMBO_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
 107
 108 enum nixge_version {
 109         NIXGE_V2,
 110         NIXGE_V3,
 111         NIXGE_VERSION_COUNT
 112 };
 113
 114 struct nixge_hw_dma_bd {
 115         u32 next_lo;
 116         u32 next_hi;
 117         u32 phys_lo;
 118         u32 phys_hi;
 119         u32 reserved3;
 120         u32 reserved4;
 121         u32 cntrl;
 122         u32 status;
 123         u32 app0;
 124         u32 app1;
 125         u32 app2;
 126         u32 app3;
 127         u32 app4;
 128         u32 sw_id_offset_lo;
 129         u32 sw_id_offset_hi;
 130         u32 reserved6;
 131 };
 132
 133 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 134 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
 135         do { \
 136                 (bd)->field##_lo = lower_32_bits((addr)); \
 137                 (bd)->field##_hi = upper_32_bits((addr)); \
 138         } while (0)
 139 #else
 140 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
 141         ((bd)->field##_lo = lower_32_bits((addr)))
 142 #endif
 143
 144 #define nixge_hw_dma_bd_set_phys(bd, addr) \
 145         nixge_hw_dma_bd_set_addr((bd), phys, (addr))
 146
 147 #define nixge_hw_dma_bd_set_next(bd, addr) \
 148         nixge_hw_dma_bd_set_addr((bd), next, (addr))
 149
 150 #define nixge_hw_dma_bd_set_offset(bd, addr) \
 151         nixge_hw_dma_bd_set_addr((bd), sw_id_offset, (addr))
 152
 153 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 154 #define nixge_hw_dma_bd_get_addr(bd, field) \
 155         (dma_addr_t)((((u64)(bd)->field##_hi) << 32) | ((bd)->field##_lo))
 156 #else
 157 #define nixge_hw_dma_bd_get_addr(bd, field) \
 158         (dma_addr_t)((bd)->field##_lo)
 159 #endif
 160
 161 struct nixge_tx_skb {
 162         struct sk_buff *skb;
 163         dma_addr_t mapping;
 164         size_t size;
 165         bool mapped_as_page;
 166 };
 167
 168 struct nixge_priv {
 169         struct net_device *ndev;
 170         struct napi_struct napi;
 171         struct device *dev;
 172
 173         /* Connection to PHY device */
 174         struct device_node *phy_node;
 175         phy_interface_t         phy_mode;
 176
 177         int link;
 178         unsigned int speed;
 179         unsigned int duplex;
 180
 181         /* MDIO bus data */
 182         struct mii_bus *mii_bus;        /* MII bus reference */
 183
 184         /* IO registers, dma functions and IRQs */
 185         void __iomem *ctrl_regs;
 186         void __iomem *dma_regs;
 187
 188         struct tasklet_struct dma_err_tasklet;
 189
 190         int tx_irq;
 191         int rx_irq;
 192
 193         /* Buffer descriptors */
 194         struct nixge_hw_dma_bd *tx_bd_v;
 195         struct nixge_tx_skb *tx_skb;
 196         dma_addr_t tx_bd_p;
 197
 198         struct nixge_hw_dma_bd *rx_bd_v;
 199         dma_addr_t rx_bd_p;
 200         u32 tx_bd_ci;
 201         u32 tx_bd_tail;
 202         u32 rx_bd_ci;
 203
 204         u32 coalesce_count_rx;
 205         u32 coalesce_count_tx;
 206 };
 207
 208 static void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
 209 {
 210         writel(val, priv->dma_regs + offset);
 211 }
 212
 213 static void nixge_dma_write_desc_reg(struct nixge_priv *priv, off_t offset,
 214                                      dma_addr_t addr)
 215 {
 216         writel(lower_32_bits(addr), priv->dma_regs + offset);
 217 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 218         writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
 219 #endif
 220 }
 221
 222 static u32 nixge_dma_read_reg(const struct nixge_priv *priv, off_t offset)
 223 {
 224         return readl(priv->dma_regs + offset);
 225 }
 226
 227 static void nixge_ctrl_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
 228 {
 229         writel(val, priv->ctrl_regs + offset);
 230 }
 231
 232 static u32 nixge_ctrl_read_reg(struct nixge_priv *priv, off_t offset)
 233 {
 234         return readl(priv->ctrl_regs + offset);
 235 }
 236
 237 #define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 238         readl_poll_timeout((priv)->ctrl_regs + (addr), (val), (cond), \
 239                            (sleep_us), (timeout_us))
 240
 241 #define nixge_dma_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 242         readl_poll_timeout((priv)->dma_regs + (addr), (val), (cond), \
 243                            (sleep_us), (timeout_us))
 244
 245 static void nixge_hw_dma_bd_release(struct net_device *ndev)
 246 {
 247         struct nixge_priv *priv = netdev_priv(ndev);
 248         dma_addr_t phys_addr;
 249         struct sk_buff *skb;
 250         int i;
 251
 252         if (priv->rx_bd_v) {
 253                 for (i = 0; i < RX_BD_NUM; i++) {
 254                         phys_addr = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
 255                                                              phys);
 256
 257                         dma_unmap_single(ndev->dev.parent, phys_addr,
 258                                          NIXGE_MAX_JUMBO_FRAME_SIZE,
 259                                          DMA_FROM_DEVICE);
 260
 261                         skb = (struct sk_buff *)(uintptr_t)
 262                                 nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
 263                                                          sw_id_offset);
 264                         dev_kfree_skb(skb);
 265                 }
 266
 267                 dma_free_coherent(ndev->dev.parent,
 268                                   sizeof(*priv->rx_bd_v) * RX_BD_NUM,
 269                                   priv->rx_bd_v,
 270                                   priv->rx_bd_p);
 271         }
 272
 273         if (priv->tx_skb)
 274                 devm_kfree(ndev->dev.parent, priv->tx_skb);
 275
 276         if (priv->tx_bd_v)
 277                 dma_free_coherent(ndev->dev.parent,
 278                                   sizeof(*priv->tx_bd_v) * TX_BD_NUM,
 279                                   priv->tx_bd_v,
 280                                   priv->tx_bd_p);
 281 }
 282
 283 static int nixge_hw_dma_bd_init(struct net_device *ndev)
 284 {
 285         struct nixge_priv *priv = netdev_priv(ndev);
 286         struct sk_buff *skb;
 287         dma_addr_t phys;
 288         u32 cr;
 289         int i;
 290
 291         /* Reset the indexes which are used for accessing the BDs */
 292         priv->tx_bd_ci = 0;
 293         priv->tx_bd_tail = 0;
 294         priv->rx_bd_ci = 0;
 295
 296         /* Allocate the Tx and Rx buffer descriptors. */
 297         priv->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 298                                            sizeof(*priv->tx_bd_v) * TX_BD_NUM,
 299                                            &priv->tx_bd_p, GFP_KERNEL);
 300         if (!priv->tx_bd_v)
 301                 goto out;
 302
 303         priv->tx_skb = devm_kcalloc(ndev->dev.parent,
 304                                     TX_BD_NUM, sizeof(*priv->tx_skb),
 305                                     GFP_KERNEL);
 306         if (!priv->tx_skb)
 307                 goto out;
 308
 309         priv->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 310                                            sizeof(*priv->rx_bd_v) * RX_BD_NUM,
 311                                            &priv->rx_bd_p, GFP_KERNEL);
 312         if (!priv->rx_bd_v)
 313                 goto out;
 314
 315         for (i = 0; i < TX_BD_NUM; i++) {
 316                 nixge_hw_dma_bd_set_next(&priv->tx_bd_v[i],
 317                                          priv->tx_bd_p +
 318                                          sizeof(*priv->tx_bd_v) *
 319                                          ((i + 1) % TX_BD_NUM));
 320         }
 321
 322         for (i = 0; i < RX_BD_NUM; i++) {
 323                 nixge_hw_dma_bd_set_next(&priv->rx_bd_v[i],
 324                                          priv->rx_bd_p
 325                                          + sizeof(*priv->rx_bd_v) *
 326                                          ((i + 1) % RX_BD_NUM));
 327
 328                 skb = __netdev_alloc_skb_ip_align(ndev,
 329                                                   NIXGE_MAX_JUMBO_FRAME_SIZE,
 330                                                   GFP_KERNEL);
 331                 if (!skb)
 332                         goto out;
 333
 334                 nixge_hw_dma_bd_set_offset(&priv->rx_bd_v[i], (uintptr_t)skb);
 335                 phys = dma_map_single(ndev->dev.parent, skb->data,
 336                                       NIXGE_MAX_JUMBO_FRAME_SIZE,
 337                                       DMA_FROM_DEVICE);
 338
 339                 nixge_hw_dma_bd_set_phys(&priv->rx_bd_v[i], phys);
 340
 341                 priv->rx_bd_v[i].cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
 342         }
 343
 344         /* Start updating the Rx channel control register */
 345         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 346         /* Update the interrupt coalesce count */
 347         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
 348               ((priv->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
 349         /* Update the delay timer count */
 350         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
 351               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 352         /* Enable coalesce, delay timer and error interrupts */
 353         cr |= XAXIDMA_IRQ_ALL_MASK;
 354         /* Write to the Rx channel control register */
 355         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 356
 357         /* Start updating the Tx channel control register */
 358         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 359         /* Update the interrupt coalesce count */
 360         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
 361               ((priv->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
 362         /* Update the delay timer count */
 363         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
 364               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 365         /* Enable coalesce, delay timer and error interrupts */
 366         cr |= XAXIDMA_IRQ_ALL_MASK;
 367         /* Write to the Tx channel control register */
 368         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 369
 370         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
 371          * halted state. This will make the Rx side ready for reception.
 372          */
 373         nixge_dma_write_desc_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
 374         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 375         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
 376                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 377         nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
 378                             (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
 379
 380         /* Write to the RS (Run-stop) bit in the Tx channel control register.
 381          * Tx channel is now ready to run. But only after we write to the
 382          * tail pointer register that the Tx channel will start transmitting.
 383          */
 384         nixge_dma_write_desc_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
 385         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 386         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
 387                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 388
 389         return 0;
 390 out:
 391         nixge_hw_dma_bd_release(ndev);
 392         return -ENOMEM;
 393 }
 394
 395 static void __nixge_device_reset(struct nixge_priv *priv, off_t offset)
 396 {
 397         u32 status;
 398         int err;
 399
 400         /* Reset Axi DMA. This would reset NIXGE Ethernet core as well.
 401          * The reset process of Axi DMA takes a while to complete as all
 402          * pending commands/transfers will be flushed or completed during
 403          * this reset process.
 404          */
 405         nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
 406         err = nixge_dma_poll_timeout(priv, offset, status,
 407                                      !(status & XAXIDMA_CR_RESET_MASK), 10,
 408                                      1000);
 409         if (err)
 410                 netdev_err(priv->ndev, "%s: DMA reset timeout!\n", __func__);
 411 }
 412
 413 static void nixge_device_reset(struct net_device *ndev)
 414 {
 415         struct nixge_priv *priv = netdev_priv(ndev);
 416
 417         __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET);
 418         __nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET);
 419
 420         if (nixge_hw_dma_bd_init(ndev))
 421                 netdev_err(ndev, "%s: descriptor allocation failed\n",
 422                            __func__);
 423
 424         netif_trans_update(ndev);
 425 }
 426
 427 static void nixge_handle_link_change(struct net_device *ndev)
 428 {
 429         struct nixge_priv *priv = netdev_priv(ndev);
 430         struct phy_device *phydev = ndev->phydev;
 431
 432         if (phydev->link != priv->link || phydev->speed != priv->speed ||
 433             phydev->duplex != priv->duplex) {
 434                 priv->link = phydev->link;
 435                 priv->speed = phydev->speed;
 436                 priv->duplex = phydev->duplex;
 437                 phy_print_status(phydev);
 438         }
 439 }
 440
 441 static void nixge_tx_skb_unmap(struct nixge_priv *priv,
 442                                struct nixge_tx_skb *tx_skb)
 443 {
 444         if (tx_skb->mapping) {
 445                 if (tx_skb->mapped_as_page)
 446                         dma_unmap_page(priv->ndev->dev.parent, tx_skb->mapping,
 447                                        tx_skb->size, DMA_TO_DEVICE);
 448                 else
 449                         dma_unmap_single(priv->ndev->dev.parent,
 450                                          tx_skb->mapping,
 451                                          tx_skb->size, DMA_TO_DEVICE);
 452                 tx_skb->mapping = 0;
 453         }
 454
 455         if (tx_skb->skb) {
 456                 dev_kfree_skb_any(tx_skb->skb);
 457                 tx_skb->skb = NULL;
 458         }
 459 }
 460
 461 static void nixge_start_xmit_done(struct net_device *ndev)
 462 {
 463         struct nixge_priv *priv = netdev_priv(ndev);
 464         struct nixge_hw_dma_bd *cur_p;
 465         struct nixge_tx_skb *tx_skb;
 466         unsigned int status = 0;
 467         u32 packets = 0;
 468         u32 size = 0;
 469
 470         cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
 471         tx_skb = &priv->tx_skb[priv->tx_bd_ci];
 472
 473         status = cur_p->status;
 474
 475         while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
 476                 nixge_tx_skb_unmap(priv, tx_skb);
 477                 cur_p->status = 0;
 478
 479                 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 480                 packets++;
 481
 482                 ++priv->tx_bd_ci;
 483                 priv->tx_bd_ci %= TX_BD_NUM;
 484                 cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
 485                 tx_skb = &priv->tx_skb[priv->tx_bd_ci];
 486                 status = cur_p->status;
 487         }
 488
 489         ndev->stats.tx_packets += packets;
 490         ndev->stats.tx_bytes += size;
 491
 492         if (packets)
 493                 netif_wake_queue(ndev);
 494 }
 495
 496 static int nixge_check_tx_bd_space(struct nixge_priv *priv,
 497                                    int num_frag)
 498 {
 499         struct nixge_hw_dma_bd *cur_p;
 500
 501         cur_p = &priv->tx_bd_v[(priv->tx_bd_tail + num_frag) % TX_BD_NUM];
 502         if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
 503                 return NETDEV_TX_BUSY;
 504         return 0;
 505 }
 506
 507 static netdev_tx_t nixge_start_xmit(struct sk_buff *skb,
 508                                     struct net_device *ndev)
 509 {
 510         struct nixge_priv *priv = netdev_priv(ndev);
 511         struct nixge_hw_dma_bd *cur_p;
 512         struct nixge_tx_skb *tx_skb;
 513         dma_addr_t tail_p, cur_phys;
 514         skb_frag_t *frag;
 515         u32 num_frag;
 516         u32 ii;
 517
 518         num_frag = skb_shinfo(skb)->nr_frags;
 519         cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 520         tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 521
 522         if (nixge_check_tx_bd_space(priv, num_frag)) {
 523                 if (!netif_queue_stopped(ndev))
 524                         netif_stop_queue(ndev);
 525                 return NETDEV_TX_OK;
 526         }
 527
 528         cur_phys = dma_map_single(ndev->dev.parent, skb->data,
 529                                   skb_headlen(skb), DMA_TO_DEVICE);
 530         if (dma_mapping_error(ndev->dev.parent, cur_phys))
 531                 goto drop;
 532         nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 533
 534         cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
 535
 536         tx_skb->skb = NULL;
 537         tx_skb->mapping = cur_phys;
 538         tx_skb->size = skb_headlen(skb);
 539         tx_skb->mapped_as_page = false;
 540
 541         for (ii = 0; ii < num_frag; ii++) {
 542                 ++priv->tx_bd_tail;
 543                 priv->tx_bd_tail %= TX_BD_NUM;
 544                 cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 545                 tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 546                 frag = &skb_shinfo(skb)->frags[ii];
 547
 548                 cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
 549                                             skb_frag_size(frag),
 550                                             DMA_TO_DEVICE);
 551                 if (dma_mapping_error(ndev->dev.parent, cur_phys))
 552                         goto frag_err;
 553                 nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 554
 555                 cur_p->cntrl = skb_frag_size(frag);
 556
 557                 tx_skb->skb = NULL;
 558                 tx_skb->mapping = cur_phys;
 559                 tx_skb->size = skb_frag_size(frag);
 560                 tx_skb->mapped_as_page = true;
 561         }
 562
 563         /* last buffer of the frame */
 564         tx_skb->skb = skb;
 565
 566         cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
 567
 568         tail_p = priv->tx_bd_p + sizeof(*priv->tx_bd_v) * priv->tx_bd_tail;
 569         /* Start the transfer */
 570         nixge_dma_write_desc_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
 571         ++priv->tx_bd_tail;
 572         priv->tx_bd_tail %= TX_BD_NUM;
 573
 574         return NETDEV_TX_OK;
 575 frag_err:
 576         for (; ii > 0; ii--) {
 577                 if (priv->tx_bd_tail)
 578                         priv->tx_bd_tail--;
 579                 else
 580                         priv->tx_bd_tail = TX_BD_NUM - 1;
 581
 582                 tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 583                 nixge_tx_skb_unmap(priv, tx_skb);
 584
 585                 cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 586                 cur_p->status = 0;
 587         }
 588         dma_unmap_single(priv->ndev->dev.parent,
 589                          tx_skb->mapping,
 590                          tx_skb->size, DMA_TO_DEVICE);
 591 drop:
 592         ndev->stats.tx_dropped++;
 593         return NETDEV_TX_OK;
 594 }
 595
 596 static int nixge_recv(struct net_device *ndev, int budget)
 597 {
 598         struct nixge_priv *priv = netdev_priv(ndev);
 599         struct sk_buff *skb, *new_skb;
 600         struct nixge_hw_dma_bd *cur_p;
 601         dma_addr_t tail_p = 0, cur_phys = 0;
 602         u32 packets = 0;
 603         u32 length = 0;
 604         u32 size = 0;
 605
 606         cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
 607
 608         while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK &&
 609                 budget > packets)) {
 610                 tail_p = priv->rx_bd_p + sizeof(*priv->rx_bd_v) *
 611                          priv->rx_bd_ci;
 612
 613                 skb = (struct sk_buff *)(uintptr_t)
 614                         nixge_hw_dma_bd_get_addr(cur_p, sw_id_offset);
 615
 616                 length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 617                 if (length > NIXGE_MAX_JUMBO_FRAME_SIZE)
 618                         length = NIXGE_MAX_JUMBO_FRAME_SIZE;
 619
 620                 dma_unmap_single(ndev->dev.parent,
 621                                  nixge_hw_dma_bd_get_addr(cur_p, phys),
 622                                  NIXGE_MAX_JUMBO_FRAME_SIZE,
 623                                  DMA_FROM_DEVICE);
 624
 625                 skb_put(skb, length);
 626
 627                 skb->protocol = eth_type_trans(skb, ndev);
 628                 skb_checksum_none_assert(skb);
 629
 630                 /* For now mark them as CHECKSUM_NONE since
 631                  * we don't have offload capabilities
 632                  */
 633                 skb->ip_summed = CHECKSUM_NONE;
 634
 635                 napi_gro_receive(&priv->napi, skb);
 636
 637                 size += length;
 638                 packets++;
 639
 640                 new_skb = netdev_alloc_skb_ip_align(ndev,
 641                                                     NIXGE_MAX_JUMBO_FRAME_SIZE);
 642                 if (!new_skb)
 643                         return packets;
 644
 645                 cur_phys = dma_map_single(ndev->dev.parent, new_skb->data,
 646                                           NIXGE_MAX_JUMBO_FRAME_SIZE,
 647                                           DMA_FROM_DEVICE);
 648                 if (dma_mapping_error(ndev->dev.parent, cur_phys)) {
 649                         /* FIXME: bail out and clean up */
 650                         netdev_err(ndev, "Failed to map ...\n");
 651                 }
 652                 nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 653                 cur_p->cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
 654                 cur_p->status = 0;
 655                 nixge_hw_dma_bd_set_offset(cur_p, (uintptr_t)new_skb);
 656
 657                 ++priv->rx_bd_ci;
 658                 priv->rx_bd_ci %= RX_BD_NUM;
 659                 cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
 660         }
 661
 662         ndev->stats.rx_packets += packets;
 663         ndev->stats.rx_bytes += size;
 664
 665         if (tail_p)
 666                 nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
 667
 668         return packets;
 669 }
 670
 671 static int nixge_poll(struct napi_struct *napi, int budget)
 672 {
 673         struct nixge_priv *priv = container_of(napi, struct nixge_priv, napi);
 674         int work_done;
 675         u32 status, cr;
 676
 677         work_done = 0;
 678
 679         work_done = nixge_recv(priv->ndev, budget);
 680         if (work_done < budget) {
 681                 napi_complete_done(napi, work_done);
 682                 status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
 683
 684                 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 685                         /* If there's more, reschedule, but clear */
 686                         nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 687                         napi_reschedule(napi);
 688                 } else {
 689                         /* if not, turn on RX IRQs again ... */
 690                         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 691                         cr |= (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
 692                         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 693                 }
 694         }
 695
 696         return work_done;
 697 }
 698
 699 static irqreturn_t nixge_tx_irq(int irq, void *_ndev)
 700 {
 701         struct nixge_priv *priv = netdev_priv(_ndev);
 702         struct net_device *ndev = _ndev;
 703         unsigned int status;
 704         dma_addr_t phys;
 705         u32 cr;
 706
 707         status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
 708         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 709                 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
 710                 nixge_start_xmit_done(priv->ndev);
 711                 goto out;
 712         }
 713         if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
 714                 netdev_err(ndev, "No interrupts asserted in Tx path\n");
 715                 return IRQ_NONE;
 716         }
 717         if (status & XAXIDMA_IRQ_ERROR_MASK) {
 718                 phys = nixge_hw_dma_bd_get_addr(&priv->tx_bd_v[priv->tx_bd_ci],
 719                                                 phys);
 720
 721                 netdev_err(ndev, "DMA Tx error 0x%x\n", status);
 722                 netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
 723
 724                 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 725                 /* Disable coalesce, delay timer and error interrupts */
 726                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 727                 /* Write to the Tx channel control register */
 728                 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 729
 730                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 731                 /* Disable coalesce, delay timer and error interrupts */
 732                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 733                 /* Write to the Rx channel control register */
 734                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 735
 736                 tasklet_schedule(&priv->dma_err_tasklet);
 737                 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
 738         }
 739 out:
 740         return IRQ_HANDLED;
 741 }
 742
 743 static irqreturn_t nixge_rx_irq(int irq, void *_ndev)
 744 {
 745         struct nixge_priv *priv = netdev_priv(_ndev);
 746         struct net_device *ndev = _ndev;
 747         unsigned int status;
 748         dma_addr_t phys;
 749         u32 cr;
 750
 751         status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
 752         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 753                 /* Turn of IRQs because NAPI */
 754                 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 755                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 756                 cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
 757                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 758
 759                 if (napi_schedule_prep(&priv->napi))
 760                         __napi_schedule(&priv->napi);
 761                 goto out;
 762         }
 763         if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
 764                 netdev_err(ndev, "No interrupts asserted in Rx path\n");
 765                 return IRQ_NONE;
 766         }
 767         if (status & XAXIDMA_IRQ_ERROR_MASK) {
 768                 phys = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[priv->rx_bd_ci],
 769                                                 phys);
 770                 netdev_err(ndev, "DMA Rx error 0x%x\n", status);
 771                 netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
 772
 773                 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 774                 /* Disable coalesce, delay timer and error interrupts */
 775                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 776                 /* Finally write to the Tx channel control register */
 777                 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 778
 779                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 780                 /* Disable coalesce, delay timer and error interrupts */
 781                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 782                 /* write to the Rx channel control register */
 783                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 784
 785                 tasklet_schedule(&priv->dma_err_tasklet);
 786                 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 787         }
 788 out:
 789         return IRQ_HANDLED;
 790 }
 791
 792 static void nixge_dma_err_handler(struct tasklet_struct *t)
 793 {
 794         struct nixge_priv *lp = from_tasklet(lp, t, dma_err_tasklet);
 795         struct nixge_hw_dma_bd *cur_p;
 796         struct nixge_tx_skb *tx_skb;
 797         u32 cr, i;
 798
 799         __nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
 800         __nixge_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
 801
 802         for (i = 0; i < TX_BD_NUM; i++) {
 803                 cur_p = &lp->tx_bd_v[i];
 804                 tx_skb = &lp->tx_skb[i];
 805                 nixge_tx_skb_unmap(lp, tx_skb);
 806
 807                 nixge_hw_dma_bd_set_phys(cur_p, 0);
 808                 cur_p->cntrl = 0;
 809                 cur_p->status = 0;
 810                 nixge_hw_dma_bd_set_offset(cur_p, 0);
 811         }
 812
 813         for (i = 0; i < RX_BD_NUM; i++) {
 814                 cur_p = &lp->rx_bd_v[i];
 815                 cur_p->status = 0;
 816         }
 817
 818         lp->tx_bd_ci = 0;
 819         lp->tx_bd_tail = 0;
 820         lp->rx_bd_ci = 0;
 821
 822         /* Start updating the Rx channel control register */
 823         cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
 824         /* Update the interrupt coalesce count */
 825         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
 826               (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
 827         /* Update the delay timer count */
 828         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
 829               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 830         /* Enable coalesce, delay timer and error interrupts */
 831         cr |= XAXIDMA_IRQ_ALL_MASK;
 832         /* Finally write to the Rx channel control register */
 833         nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr);
 834
 835         /* Start updating the Tx channel control register */
 836         cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
 837         /* Update the interrupt coalesce count */
 838         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
 839               (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
 840         /* Update the delay timer count */
 841         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
 842               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 843         /* Enable coalesce, delay timer and error interrupts */
 844         cr |= XAXIDMA_IRQ_ALL_MASK;
 845         /* Finally write to the Tx channel control register */
 846         nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr);
 847
 848         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
 849          * halted state. This will make the Rx side ready for reception.
 850          */
 851         nixge_dma_write_desc_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
 852         cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
 853         nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
 854                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 855         nixge_dma_write_desc_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
 856                             (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
 857
 858         /* Write to the RS (Run-stop) bit in the Tx channel control register.
 859          * Tx channel is now ready to run. But only after we write to the
 860          * tail pointer register that the Tx channel will start transmitting
 861          */
 862         nixge_dma_write_desc_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
 863         cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
 864         nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
 865                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 866 }
 867
 868 static int nixge_open(struct net_device *ndev)
 869 {
 870         struct nixge_priv *priv = netdev_priv(ndev);
 871         struct phy_device *phy;
 872         int ret;
 873
 874         nixge_device_reset(ndev);
 875
 876         phy = of_phy_connect(ndev, priv->phy_node,
 877                              &nixge_handle_link_change, 0, priv->phy_mode);
 878         if (!phy)
 879                 return -ENODEV;
 880
 881         phy_start(phy);
 882
 883         /* Enable tasklets for Axi DMA error handling */
 884         tasklet_setup(&priv->dma_err_tasklet, nixge_dma_err_handler);
 885
 886         napi_enable(&priv->napi);
 887
 888         /* Enable interrupts for Axi DMA Tx */
 889         ret = request_irq(priv->tx_irq, nixge_tx_irq, 0, ndev->name, ndev);
 890         if (ret)
 891                 goto err_tx_irq;
 892         /* Enable interrupts for Axi DMA Rx */
 893         ret = request_irq(priv->rx_irq, nixge_rx_irq, 0, ndev->name, ndev);
 894         if (ret)
 895                 goto err_rx_irq;
 896
 897         netif_start_queue(ndev);
 898
 899         return 0;
 900
 901 err_rx_irq:
 902         free_irq(priv->tx_irq, ndev);
 903 err_tx_irq:
 904         napi_disable(&priv->napi);
 905         phy_stop(phy);
 906         phy_disconnect(phy);
 907         tasklet_kill(&priv->dma_err_tasklet);
 908         netdev_err(ndev, "request_irq() failed\n");
 909         return ret;
 910 }
 911
 912 static int nixge_stop(struct net_device *ndev)
 913 {
 914         struct nixge_priv *priv = netdev_priv(ndev);
 915         u32 cr;
 916
 917         netif_stop_queue(ndev);
 918         napi_disable(&priv->napi);
 919
 920         if (ndev->phydev) {
 921                 phy_stop(ndev->phydev);
 922                 phy_disconnect(ndev->phydev);
 923         }
 924
 925         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 926         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
 927                             cr & (~XAXIDMA_CR_RUNSTOP_MASK));
 928         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 929         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
 930                             cr & (~XAXIDMA_CR_RUNSTOP_MASK));
 931
 932         tasklet_kill(&priv->dma_err_tasklet);
 933
 934         free_irq(priv->tx_irq, ndev);
 935         free_irq(priv->rx_irq, ndev);
 936
 937         nixge_hw_dma_bd_release(ndev);
 938
 939         return 0;
 940 }
 941
 942 static int nixge_change_mtu(struct net_device *ndev, int new_mtu)
 943 {
 944         if (netif_running(ndev))
 945                 return -EBUSY;
 946
 947         if ((new_mtu + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE) >
 948              NIXGE_MAX_JUMBO_FRAME_SIZE)
 949                 return -EINVAL;
 950
 951         ndev->mtu = new_mtu;
 952
 953         return 0;
 954 }
 955
 956 static s32 __nixge_hw_set_mac_address(struct net_device *ndev)
 957 {
 958         struct nixge_priv *priv = netdev_priv(ndev);
 959
 960         nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
 961                              (ndev->dev_addr[2]) << 24 |
 962                              (ndev->dev_addr[3] << 16) |
 963                              (ndev->dev_addr[4] << 8) |
 964                              (ndev->dev_addr[5] << 0));
 965
 966         nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,
 967                              (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));
 968
 969         return 0;
 970 }
 971
 972 static int nixge_net_set_mac_address(struct net_device *ndev, void *p)
 973 {
 974         int err;
 975
 976         err = eth_mac_addr(ndev, p);
 977         if (!err)
 978                 __nixge_hw_set_mac_address(ndev);
 979
 980         return err;
 981 }
 982
 983 static const struct net_device_ops nixge_netdev_ops = {
 984         .ndo_open = nixge_open,
 985         .ndo_stop = nixge_stop,
 986         .ndo_start_xmit = nixge_start_xmit,
 987         .ndo_change_mtu = nixge_change_mtu,
 988         .ndo_set_mac_address = nixge_net_set_mac_address,
 989         .ndo_validate_addr = eth_validate_addr,
 990 };
 991
 992 static void nixge_ethtools_get_drvinfo(struct net_device *ndev,
 993                                        struct ethtool_drvinfo *ed)
 994 {
 995         strscpy(ed->driver, "nixge", sizeof(ed->driver));
 996         strscpy(ed->bus_info, "platform", sizeof(ed->bus_info));
 997 }
 998
 999 static int
1000 nixge_ethtools_get_coalesce(struct net_device *ndev,
1001                             struct ethtool_coalesce *ecoalesce,
1002                             struct kernel_ethtool_coalesce *kernel_coal,
1003                             struct netlink_ext_ack *extack)
1004 {
1005         struct nixge_priv *priv = netdev_priv(ndev);
1006         u32 regval = 0;
1007
1008         regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
1009         ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1010                                              >> XAXIDMA_COALESCE_SHIFT;
1011         regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
1012         ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1013                                              >> XAXIDMA_COALESCE_SHIFT;
1014         return 0;
1015 }
1016
1017 static int
1018 nixge_ethtools_set_coalesce(struct net_device *ndev,
1019                             struct ethtool_coalesce *ecoalesce,
1020                             struct kernel_ethtool_coalesce *kernel_coal,
1021                             struct netlink_ext_ack *extack)
1022 {
1023         struct nixge_priv *priv = netdev_priv(ndev);
1024
1025         if (netif_running(ndev)) {
1026                 netdev_err(ndev,
1027                            "Please stop netif before applying configuration\n");
1028                 return -EBUSY;
1029         }
1030
1031         if (ecoalesce->rx_max_coalesced_frames)
1032                 priv->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1033         if (ecoalesce->tx_max_coalesced_frames)
1034                 priv->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1035
1036         return 0;
1037 }
1038
1039 static int nixge_ethtools_set_phys_id(struct net_device *ndev,
1040                                       enum ethtool_phys_id_state state)
1041 {
1042         struct nixge_priv *priv = netdev_priv(ndev);
1043         u32 ctrl;
1044
1045         ctrl = nixge_ctrl_read_reg(priv, NIXGE_REG_LED_CTL);
1046         switch (state) {
1047         case ETHTOOL_ID_ACTIVE:
1048                 ctrl |= NIXGE_ID_LED_CTL_EN;
1049                 /* Enable identification LED override*/
1050                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1051                 return 2;
1052
1053         case ETHTOOL_ID_ON:
1054                 ctrl |= NIXGE_ID_LED_CTL_VAL;
1055                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1056                 break;
1057
1058         case ETHTOOL_ID_OFF:
1059                 ctrl &= ~NIXGE_ID_LED_CTL_VAL;
1060                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1061                 break;
1062
1063         case ETHTOOL_ID_INACTIVE:
1064                 /* Restore LED settings */
1065                 ctrl &= ~NIXGE_ID_LED_CTL_EN;
1066                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1067                 break;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static const struct ethtool_ops nixge_ethtool_ops = {
1074         .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES,
1075         .get_drvinfo    = nixge_ethtools_get_drvinfo,
1076         .get_coalesce   = nixge_ethtools_get_coalesce,
1077         .set_coalesce   = nixge_ethtools_set_coalesce,
1078         .set_phys_id    = nixge_ethtools_set_phys_id,
1079         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1080         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1081         .get_link               = ethtool_op_get_link,
1082 };
1083
1084 static int nixge_mdio_read_c22(struct mii_bus *bus, int phy_id, int reg)
1085 {
1086         struct nixge_priv *priv = bus->priv;
1087         u32 status, tmp;
1088         int err;
1089         u16 device;
1090
1091         device = reg & 0x1f;
1092
1093         tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
1094               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1095
1096         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1097         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1098
1099         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1100                                       !status, 10, 1000);
1101         if (err) {
1102                 dev_err(priv->dev, "timeout setting read command");
1103                 return err;
1104         }
1105
1106         status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1107
1108         return status;
1109 }
1110
1111 static int nixge_mdio_read_c45(struct mii_bus *bus, int phy_id, int device,
1112                                int reg)
1113 {
1114         struct nixge_priv *priv = bus->priv;
1115         u32 status, tmp;
1116         int err;
1117
1118         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1119
1120         tmp = NIXGE_MDIO_CLAUSE45 |
1121               NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
1122               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1123
1124         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1125         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1126
1127         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1128                                       !status, 10, 1000);
1129         if (err) {
1130                 dev_err(priv->dev, "timeout setting address");
1131                 return err;
1132         }
1133
1134         tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
1135               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1136
1137         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1138         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1139
1140         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1141                                       !status, 10, 1000);
1142         if (err) {
1143                 dev_err(priv->dev, "timeout setting read command");
1144                 return err;
1145         }
1146
1147         status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1148
1149         return status;
1150 }
1151
1152 static int nixge_mdio_write_c22(struct mii_bus *bus, int phy_id, int reg,
1153                                 u16 val)
1154 {
1155         struct nixge_priv *priv = bus->priv;
1156         u32 status, tmp;
1157         u16 device;
1158         int err;
1159
1160         device = reg & 0x1f;
1161
1162         tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
1163               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1164
1165         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1166         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1167         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1168
1169         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1170                                       !status, 10, 1000);
1171         if (err)
1172                 dev_err(priv->dev, "timeout setting write command");
1173
1174         return err;
1175 }
1176
1177 static int nixge_mdio_write_c45(struct mii_bus *bus, int phy_id,
1178                                 int device, int reg, u16 val)
1179 {
1180         struct nixge_priv *priv = bus->priv;
1181         u32 status, tmp;
1182         int err;
1183
1184         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1185
1186         tmp = NIXGE_MDIO_CLAUSE45 |
1187               NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
1188               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1189
1190         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1191         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1192
1193         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1194                                       !status, 10, 1000);
1195         if (err) {
1196                 dev_err(priv->dev, "timeout setting address");
1197                 return err;
1198         }
1199
1200         tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) |
1201               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1202
1203         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1204         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1205
1206         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1207                                       !status, 10, 1000);
1208         if (err)
1209                 dev_err(priv->dev, "timeout setting write command");
1210
1211         return err;
1212 }
1213
1214 static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
1215 {
1216         struct mii_bus *bus;
1217
1218         bus = devm_mdiobus_alloc(priv->dev);
1219         if (!bus)
1220                 return -ENOMEM;
1221
1222         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
1223         bus->priv = priv;
1224         bus->name = "nixge_mii_bus";
1225         bus->read = nixge_mdio_read_c22;
1226         bus->write = nixge_mdio_write_c22;
1227         bus->read_c45 = nixge_mdio_read_c45;
1228         bus->write_c45 = nixge_mdio_write_c45;
1229         bus->parent = priv->dev;
1230
1231         priv->mii_bus = bus;
1232
1233         return of_mdiobus_register(bus, np);
1234 }
1235
1236 static void *nixge_get_nvmem_address(struct device *dev)
1237 {
1238         struct nvmem_cell *cell;
1239         size_t cell_size;
1240         char *mac;
1241
1242         cell = nvmem_cell_get(dev, "address");
1243         if (IS_ERR(cell))
1244                 return cell;
1245
1246         mac = nvmem_cell_read(cell, &cell_size);
1247         nvmem_cell_put(cell);
1248
1249         return mac;
1250 }
1251
1252 /* Match table for of_platform binding */
1253 static const struct of_device_id nixge_dt_ids[] = {
1254         { .compatible = "ni,xge-enet-2.00", .data = (void *)NIXGE_V2 },
1255         { .compatible = "ni,xge-enet-3.00", .data = (void *)NIXGE_V3 },
1256         {},
1257 };
1258 MODULE_DEVICE_TABLE(of, nixge_dt_ids);
1259
1260 static int nixge_of_get_resources(struct platform_device *pdev)
1261 {
1262         const struct of_device_id *of_id;
1263         enum nixge_version version;
1264         struct net_device *ndev;
1265         struct nixge_priv *priv;
1266
1267         ndev = platform_get_drvdata(pdev);
1268         priv = netdev_priv(ndev);
1269         of_id = of_match_node(nixge_dt_ids, pdev->dev.of_node);
1270         if (!of_id)
1271                 return -ENODEV;
1272
1273         version = (enum nixge_version)of_id->data;
1274         if (version <= NIXGE_V2)
1275                 priv->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1276         else
1277                 priv->dma_regs = devm_platform_ioremap_resource_byname(pdev, "dma");
1278         if (IS_ERR(priv->dma_regs)) {
1279                 netdev_err(ndev, "failed to map dma regs\n");
1280                 return PTR_ERR(priv->dma_regs);
1281         }
1282         if (version <= NIXGE_V2)
1283                 priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
1284         else
1285                 priv->ctrl_regs = devm_platform_ioremap_resource_byname(pdev, "ctrl");
1286         if (IS_ERR(priv->ctrl_regs)) {
1287                 netdev_err(ndev, "failed to map ctrl regs\n");
1288                 return PTR_ERR(priv->ctrl_regs);
1289         }
1290         return 0;
1291 }
1292
1293 static int nixge_probe(struct platform_device *pdev)
1294 {
1295         struct device_node *mn, *phy_node;
1296         struct nixge_priv *priv;
1297         struct net_device *ndev;
1298         const u8 *mac_addr;
1299         int err;
1300
1301         ndev = alloc_etherdev(sizeof(*priv));
1302         if (!ndev)
1303                 return -ENOMEM;
1304
1305         platform_set_drvdata(pdev, ndev);
1306         SET_NETDEV_DEV(ndev, &pdev->dev);
1307
1308         ndev->features = NETIF_F_SG;
1309         ndev->netdev_ops = &nixge_netdev_ops;
1310         ndev->ethtool_ops = &nixge_ethtool_ops;
1311
1312         /* MTU range: 64 - 9000 */
1313         ndev->min_mtu = 64;
1314         ndev->max_mtu = NIXGE_JUMBO_MTU;
1315
1316         mac_addr = nixge_get_nvmem_address(&pdev->dev);
1317         if (!IS_ERR(mac_addr) && is_valid_ether_addr(mac_addr)) {
1318                 eth_hw_addr_set(ndev, mac_addr);
1319                 kfree(mac_addr);
1320         } else {
1321                 eth_hw_addr_random(ndev);
1322         }
1323
1324         priv = netdev_priv(ndev);
1325         priv->ndev = ndev;
1326         priv->dev = &pdev->dev;
1327
1328         netif_napi_add(ndev, &priv->napi, nixge_poll);
1329         err = nixge_of_get_resources(pdev);
1330         if (err)
1331                 goto free_netdev;
1332         __nixge_hw_set_mac_address(ndev);
1333
1334         priv->tx_irq = platform_get_irq_byname(pdev, "tx");
1335         if (priv->tx_irq < 0) {
1336                 netdev_err(ndev, "could not find 'tx' irq");
1337                 err = priv->tx_irq;
1338                 goto free_netdev;
1339         }
1340
1341         priv->rx_irq = platform_get_irq_byname(pdev, "rx");
1342         if (priv->rx_irq < 0) {
1343                 netdev_err(ndev, "could not find 'rx' irq");
1344                 err = priv->rx_irq;
1345                 goto free_netdev;
1346         }
1347
1348         priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1349         priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1350
1351         mn = of_get_child_by_name(pdev->dev.of_node, "mdio");
1352         if (mn) {
1353                 err = nixge_mdio_setup(priv, mn);
1354                 of_node_put(mn);
1355                 if (err) {
1356                         netdev_err(ndev, "error registering mdio bus");
1357                         goto free_netdev;
1358                 }
1359         }
1360
1361         err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode);
1362         if (err) {
1363                 netdev_err(ndev, "not find \"phy-mode\" property\n");
1364                 goto unregister_mdio;
1365         }
1366
1367         phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1368         if (!phy_node && of_phy_is_fixed_link(pdev->dev.of_node)) {
1369                 err = of_phy_register_fixed_link(pdev->dev.of_node);
1370                 if (err < 0) {
1371                         netdev_err(ndev, "broken fixed-link specification\n");
1372                         goto unregister_mdio;
1373                 }
1374                 phy_node = of_node_get(pdev->dev.of_node);
1375         }
1376         priv->phy_node = phy_node;
1377
1378         err = register_netdev(priv->ndev);
1379         if (err) {
1380                 netdev_err(ndev, "register_netdev() error (%i)\n", err);
1381                 goto free_phy;
1382         }
1383
1384         return 0;
1385
1386 free_phy:
1387         if (of_phy_is_fixed_link(pdev->dev.of_node))
1388                 of_phy_deregister_fixed_link(pdev->dev.of_node);
1389         of_node_put(phy_node);
1390
1391 unregister_mdio:
1392         if (priv->mii_bus)
1393                 mdiobus_unregister(priv->mii_bus);
1394
1395 free_netdev:
1396         free_netdev(ndev);
1397
1398         return err;
1399 }
1400
1401 static int nixge_remove(struct platform_device *pdev)
1402 {
1403         struct net_device *ndev = platform_get_drvdata(pdev);
1404         struct nixge_priv *priv = netdev_priv(ndev);
1405
1406         unregister_netdev(ndev);
1407
1408         if (of_phy_is_fixed_link(pdev->dev.of_node))
1409                 of_phy_deregister_fixed_link(pdev->dev.of_node);
1410         of_node_put(priv->phy_node);
1411
1412         if (priv->mii_bus)
1413                 mdiobus_unregister(priv->mii_bus);
1414
1415         free_netdev(ndev);
1416
1417         return 0;
1418 }
1419
1420 static struct platform_driver nixge_driver = {
1421         .probe          = nixge_probe,
1422         .remove         = nixge_remove,
1423         .driver         = {
1424                 .name           = "nixge",
1425                 .of_match_table = nixge_dt_ids,
1426         },
1427 };
1428 module_platform_driver(nixge_driver);
1429
1430 MODULE_LICENSE("GPL v2");
1431 MODULE_DESCRIPTION("National Instruments XGE Management MAC");
1432 MODULE_AUTHOR("Moritz Fischer <[email protected]>");