drivers/irqchip/irq-stm32-exti.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics 2017
   5  * Author:  Maxime Coquelin <[email protected]>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/delay.h>
  10 #include <linux/hwspinlock.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/irqchip/chained_irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/syscore_ops.h>
  22
  23 #include <dt-bindings/interrupt-controller/arm-gic.h>
  24
  25 #define IRQS_PER_BANK 32
  26
  27 #define HWSPNLCK_TIMEOUT        1000 /* usec */
  28
  29 struct stm32_exti_bank {
  30         u32 imr_ofst;
  31         u32 emr_ofst;
  32         u32 rtsr_ofst;
  33         u32 ftsr_ofst;
  34         u32 swier_ofst;
  35         u32 rpr_ofst;
  36         u32 fpr_ofst;
  37         u32 trg_ofst;
  38 };
  39
  40 #define UNDEF_REG ~0
  41
  42 struct stm32_exti_drv_data {
  43         const struct stm32_exti_bank **exti_banks;
  44         const u8 *desc_irqs;
  45         u32 bank_nr;
  46 };
  47
  48 struct stm32_exti_chip_data {
  49         struct stm32_exti_host_data *host_data;
  50         const struct stm32_exti_bank *reg_bank;
  51         struct raw_spinlock rlock;
  52         u32 wake_active;
  53         u32 mask_cache;
  54         u32 rtsr_cache;
  55         u32 ftsr_cache;
  56 };
  57
  58 struct stm32_exti_host_data {
  59         void __iomem *base;
  60         struct stm32_exti_chip_data *chips_data;
  61         const struct stm32_exti_drv_data *drv_data;
  62         struct hwspinlock *hwlock;
  63 };
  64
  65 static struct stm32_exti_host_data *stm32_host_data;
  66
  67 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
  68         .imr_ofst       = 0x00,
  69         .emr_ofst       = 0x04,
  70         .rtsr_ofst      = 0x08,
  71         .ftsr_ofst      = 0x0C,
  72         .swier_ofst     = 0x10,
  73         .rpr_ofst       = 0x14,
  74         .fpr_ofst       = UNDEF_REG,
  75         .trg_ofst       = UNDEF_REG,
  76 };
  77
  78 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
  79         &stm32f4xx_exti_b1,
  80 };
  81
  82 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
  83         .exti_banks = stm32f4xx_exti_banks,
  84         .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
  85 };
  86
  87 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
  88         .imr_ofst       = 0x80,
  89         .emr_ofst       = 0x84,
  90         .rtsr_ofst      = 0x00,
  91         .ftsr_ofst      = 0x04,
  92         .swier_ofst     = 0x08,
  93         .rpr_ofst       = 0x88,
  94         .fpr_ofst       = UNDEF_REG,
  95         .trg_ofst       = UNDEF_REG,
  96 };
  97
  98 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
  99         .imr_ofst       = 0x90,
 100         .emr_ofst       = 0x94,
 101         .rtsr_ofst      = 0x20,
 102         .ftsr_ofst      = 0x24,
 103         .swier_ofst     = 0x28,
 104         .rpr_ofst       = 0x98,
 105         .fpr_ofst       = UNDEF_REG,
 106         .trg_ofst       = UNDEF_REG,
 107 };
 108
 109 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
 110         .imr_ofst       = 0xA0,
 111         .emr_ofst       = 0xA4,
 112         .rtsr_ofst      = 0x40,
 113         .ftsr_ofst      = 0x44,
 114         .swier_ofst     = 0x48,
 115         .rpr_ofst       = 0xA8,
 116         .fpr_ofst       = UNDEF_REG,
 117         .trg_ofst       = UNDEF_REG,
 118 };
 119
 120 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
 121         &stm32h7xx_exti_b1,
 122         &stm32h7xx_exti_b2,
 123         &stm32h7xx_exti_b3,
 124 };
 125
 126 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
 127         .exti_banks = stm32h7xx_exti_banks,
 128         .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
 129 };
 130
 131 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
 132         .imr_ofst       = 0x80,
 133         .emr_ofst       = UNDEF_REG,
 134         .rtsr_ofst      = 0x00,
 135         .ftsr_ofst      = 0x04,
 136         .swier_ofst     = 0x08,
 137         .rpr_ofst       = 0x0C,
 138         .fpr_ofst       = 0x10,
 139         .trg_ofst       = 0x3EC,
 140 };
 141
 142 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
 143         .imr_ofst       = 0x90,
 144         .emr_ofst       = UNDEF_REG,
 145         .rtsr_ofst      = 0x20,
 146         .ftsr_ofst      = 0x24,
 147         .swier_ofst     = 0x28,
 148         .rpr_ofst       = 0x2C,
 149         .fpr_ofst       = 0x30,
 150         .trg_ofst       = 0x3E8,
 151 };
 152
 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
 154         .imr_ofst       = 0xA0,
 155         .emr_ofst       = UNDEF_REG,
 156         .rtsr_ofst      = 0x40,
 157         .ftsr_ofst      = 0x44,
 158         .swier_ofst     = 0x48,
 159         .rpr_ofst       = 0x4C,
 160         .fpr_ofst       = 0x50,
 161         .trg_ofst       = 0x3E4,
 162 };
 163
 164 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
 165         &stm32mp1_exti_b1,
 166         &stm32mp1_exti_b2,
 167         &stm32mp1_exti_b3,
 168 };
 169
 170 static struct irq_chip stm32_exti_h_chip;
 171 static struct irq_chip stm32_exti_h_chip_direct;
 172
 173 #define EXTI_INVALID_IRQ       U8_MAX
 174 #define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
 175
 176 static const u8 stm32mp1_desc_irq[] = {
 177         /* default value */
 178         [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
 179
 180         [0] = 6,
 181         [1] = 7,
 182         [2] = 8,
 183         [3] = 9,
 184         [4] = 10,
 185         [5] = 23,
 186         [6] = 64,
 187         [7] = 65,
 188         [8] = 66,
 189         [9] = 67,
 190         [10] = 40,
 191         [11] = 42,
 192         [12] = 76,
 193         [13] = 77,
 194         [14] = 121,
 195         [15] = 127,
 196         [16] = 1,
 197         [19] = 3,
 198         [21] = 31,
 199         [22] = 33,
 200         [23] = 72,
 201         [24] = 95,
 202         [25] = 107,
 203         [26] = 37,
 204         [27] = 38,
 205         [28] = 39,
 206         [29] = 71,
 207         [30] = 52,
 208         [31] = 53,
 209         [32] = 82,
 210         [33] = 83,
 211         [47] = 93,
 212         [48] = 138,
 213         [50] = 139,
 214         [52] = 140,
 215         [53] = 141,
 216         [54] = 135,
 217         [61] = 100,
 218         [65] = 144,
 219         [68] = 143,
 220         [70] = 62,
 221         [73] = 129,
 222 };
 223
 224 static const u8 stm32mp13_desc_irq[] = {
 225         /* default value */
 226         [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
 227
 228         [0] = 6,
 229         [1] = 7,
 230         [2] = 8,
 231         [3] = 9,
 232         [4] = 10,
 233         [5] = 24,
 234         [6] = 65,
 235         [7] = 66,
 236         [8] = 67,
 237         [9] = 68,
 238         [10] = 41,
 239         [11] = 43,
 240         [12] = 77,
 241         [13] = 78,
 242         [14] = 106,
 243         [15] = 109,
 244         [16] = 1,
 245         [19] = 3,
 246         [21] = 32,
 247         [22] = 34,
 248         [23] = 73,
 249         [24] = 93,
 250         [25] = 114,
 251         [26] = 38,
 252         [27] = 39,
 253         [28] = 40,
 254         [29] = 72,
 255         [30] = 53,
 256         [31] = 54,
 257         [32] = 83,
 258         [33] = 84,
 259         [44] = 96,
 260         [47] = 92,
 261         [48] = 116,
 262         [50] = 117,
 263         [52] = 118,
 264         [53] = 119,
 265         [68] = 63,
 266         [70] = 98,
 267 };
 268
 269 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
 270         .exti_banks = stm32mp1_exti_banks,
 271         .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
 272         .desc_irqs = stm32mp1_desc_irq,
 273 };
 274
 275 static const struct stm32_exti_drv_data stm32mp13_drv_data = {
 276         .exti_banks = stm32mp1_exti_banks,
 277         .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
 278         .desc_irqs = stm32mp13_desc_irq,
 279 };
 280
 281 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
 282 {
 283         struct stm32_exti_chip_data *chip_data = gc->private;
 284         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 285         unsigned long pending;
 286
 287         pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
 288         if (stm32_bank->fpr_ofst != UNDEF_REG)
 289                 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
 290
 291         return pending;
 292 }
 293
 294 static void stm32_irq_handler(struct irq_desc *desc)
 295 {
 296         struct irq_domain *domain = irq_desc_get_handler_data(desc);
 297         struct irq_chip *chip = irq_desc_get_chip(desc);
 298         unsigned int nbanks = domain->gc->num_chips;
 299         struct irq_chip_generic *gc;
 300         unsigned long pending;
 301         int n, i, irq_base = 0;
 302
 303         chained_irq_enter(chip, desc);
 304
 305         for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
 306                 gc = irq_get_domain_generic_chip(domain, irq_base);
 307
 308                 while ((pending = stm32_exti_pending(gc))) {
 309                         for_each_set_bit(n, &pending, IRQS_PER_BANK)
 310                                 generic_handle_domain_irq(domain, irq_base + n);
 311                 }
 312         }
 313
 314         chained_irq_exit(chip, desc);
 315 }
 316
 317 static int stm32_exti_set_type(struct irq_data *d,
 318                                unsigned int type, u32 *rtsr, u32 *ftsr)
 319 {
 320         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 321
 322         switch (type) {
 323         case IRQ_TYPE_EDGE_RISING:
 324                 *rtsr |= mask;
 325                 *ftsr &= ~mask;
 326                 break;
 327         case IRQ_TYPE_EDGE_FALLING:
 328                 *rtsr &= ~mask;
 329                 *ftsr |= mask;
 330                 break;
 331         case IRQ_TYPE_EDGE_BOTH:
 332                 *rtsr |= mask;
 333                 *ftsr |= mask;
 334                 break;
 335         default:
 336                 return -EINVAL;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
 343 {
 344         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 345         struct stm32_exti_chip_data *chip_data = gc->private;
 346         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 347         struct hwspinlock *hwlock = chip_data->host_data->hwlock;
 348         u32 rtsr, ftsr;
 349         int err;
 350
 351         irq_gc_lock(gc);
 352
 353         if (hwlock) {
 354                 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
 355                 if (err) {
 356                         pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
 357                         goto unlock;
 358                 }
 359         }
 360
 361         rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
 362         ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
 363
 364         err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
 365         if (err)
 366                 goto unspinlock;
 367
 368         irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
 369         irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
 370
 371 unspinlock:
 372         if (hwlock)
 373                 hwspin_unlock_in_atomic(hwlock);
 374 unlock:
 375         irq_gc_unlock(gc);
 376
 377         return err;
 378 }
 379
 380 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
 381                                u32 wake_active)
 382 {
 383         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 384         void __iomem *base = chip_data->host_data->base;
 385
 386         /* save rtsr, ftsr registers */
 387         chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
 388         chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
 389
 390         writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
 391 }
 392
 393 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
 394                               u32 mask_cache)
 395 {
 396         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 397         void __iomem *base = chip_data->host_data->base;
 398
 399         /* restore rtsr, ftsr, registers */
 400         writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
 401         writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
 402
 403         writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
 404 }
 405
 406 static void stm32_irq_suspend(struct irq_chip_generic *gc)
 407 {
 408         struct stm32_exti_chip_data *chip_data = gc->private;
 409
 410         irq_gc_lock(gc);
 411         stm32_chip_suspend(chip_data, gc->wake_active);
 412         irq_gc_unlock(gc);
 413 }
 414
 415 static void stm32_irq_resume(struct irq_chip_generic *gc)
 416 {
 417         struct stm32_exti_chip_data *chip_data = gc->private;
 418
 419         irq_gc_lock(gc);
 420         stm32_chip_resume(chip_data, gc->mask_cache);
 421         irq_gc_unlock(gc);
 422 }
 423
 424 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
 425                             unsigned int nr_irqs, void *data)
 426 {
 427         struct irq_fwspec *fwspec = data;
 428         irq_hw_number_t hwirq;
 429
 430         hwirq = fwspec->param[0];
 431
 432         irq_map_generic_chip(d, virq, hwirq);
 433
 434         return 0;
 435 }
 436
 437 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
 438                             unsigned int nr_irqs)
 439 {
 440         struct irq_data *data = irq_domain_get_irq_data(d, virq);
 441
 442         irq_domain_reset_irq_data(data);
 443 }
 444
 445 static const struct irq_domain_ops irq_exti_domain_ops = {
 446         .map    = irq_map_generic_chip,
 447         .alloc  = stm32_exti_alloc,
 448         .free   = stm32_exti_free,
 449 };
 450
 451 static void stm32_irq_ack(struct irq_data *d)
 452 {
 453         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 454         struct stm32_exti_chip_data *chip_data = gc->private;
 455         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 456
 457         irq_gc_lock(gc);
 458
 459         irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
 460         if (stm32_bank->fpr_ofst != UNDEF_REG)
 461                 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
 462
 463         irq_gc_unlock(gc);
 464 }
 465
 466 /* directly set the target bit without reading first. */
 467 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
 468 {
 469         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 470         void __iomem *base = chip_data->host_data->base;
 471         u32 val = BIT(d->hwirq % IRQS_PER_BANK);
 472
 473         writel_relaxed(val, base + reg);
 474 }
 475
 476 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
 477 {
 478         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 479         void __iomem *base = chip_data->host_data->base;
 480         u32 val;
 481
 482         val = readl_relaxed(base + reg);
 483         val |= BIT(d->hwirq % IRQS_PER_BANK);
 484         writel_relaxed(val, base + reg);
 485
 486         return val;
 487 }
 488
 489 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
 490 {
 491         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 492         void __iomem *base = chip_data->host_data->base;
 493         u32 val;
 494
 495         val = readl_relaxed(base + reg);
 496         val &= ~BIT(d->hwirq % IRQS_PER_BANK);
 497         writel_relaxed(val, base + reg);
 498
 499         return val;
 500 }
 501
 502 static void stm32_exti_h_eoi(struct irq_data *d)
 503 {
 504         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 505         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 506
 507         raw_spin_lock(&chip_data->rlock);
 508
 509         stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
 510         if (stm32_bank->fpr_ofst != UNDEF_REG)
 511                 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
 512
 513         raw_spin_unlock(&chip_data->rlock);
 514
 515         if (d->parent_data->chip)
 516                 irq_chip_eoi_parent(d);
 517 }
 518
 519 static void stm32_exti_h_mask(struct irq_data *d)
 520 {
 521         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 522         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 523
 524         raw_spin_lock(&chip_data->rlock);
 525         chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
 526         raw_spin_unlock(&chip_data->rlock);
 527
 528         if (d->parent_data->chip)
 529                 irq_chip_mask_parent(d);
 530 }
 531
 532 static void stm32_exti_h_unmask(struct irq_data *d)
 533 {
 534         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 535         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 536
 537         raw_spin_lock(&chip_data->rlock);
 538         chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
 539         raw_spin_unlock(&chip_data->rlock);
 540
 541         if (d->parent_data->chip)
 542                 irq_chip_unmask_parent(d);
 543 }
 544
 545 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
 546 {
 547         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 548         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 549         struct hwspinlock *hwlock = chip_data->host_data->hwlock;
 550         void __iomem *base = chip_data->host_data->base;
 551         u32 rtsr, ftsr;
 552         int err;
 553
 554         raw_spin_lock(&chip_data->rlock);
 555
 556         if (hwlock) {
 557                 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
 558                 if (err) {
 559                         pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
 560                         goto unlock;
 561                 }
 562         }
 563
 564         rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
 565         ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
 566
 567         err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
 568         if (err)
 569                 goto unspinlock;
 570
 571         writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
 572         writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
 573
 574 unspinlock:
 575         if (hwlock)
 576                 hwspin_unlock_in_atomic(hwlock);
 577 unlock:
 578         raw_spin_unlock(&chip_data->rlock);
 579
 580         return err;
 581 }
 582
 583 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
 584 {
 585         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 586         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 587
 588         raw_spin_lock(&chip_data->rlock);
 589
 590         if (on)
 591                 chip_data->wake_active |= mask;
 592         else
 593                 chip_data->wake_active &= ~mask;
 594
 595         raw_spin_unlock(&chip_data->rlock);
 596
 597         return 0;
 598 }
 599
 600 static int stm32_exti_h_set_affinity(struct irq_data *d,
 601                                      const struct cpumask *dest, bool force)
 602 {
 603         if (d->parent_data->chip)
 604                 return irq_chip_set_affinity_parent(d, dest, force);
 605
 606         return IRQ_SET_MASK_OK_DONE;
 607 }
 608
 609 static int __maybe_unused stm32_exti_h_suspend(void)
 610 {
 611         struct stm32_exti_chip_data *chip_data;
 612         int i;
 613
 614         for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
 615                 chip_data = &stm32_host_data->chips_data[i];
 616                 raw_spin_lock(&chip_data->rlock);
 617                 stm32_chip_suspend(chip_data, chip_data->wake_active);
 618                 raw_spin_unlock(&chip_data->rlock);
 619         }
 620
 621         return 0;
 622 }
 623
 624 static void __maybe_unused stm32_exti_h_resume(void)
 625 {
 626         struct stm32_exti_chip_data *chip_data;
 627         int i;
 628
 629         for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
 630                 chip_data = &stm32_host_data->chips_data[i];
 631                 raw_spin_lock(&chip_data->rlock);
 632                 stm32_chip_resume(chip_data, chip_data->mask_cache);
 633                 raw_spin_unlock(&chip_data->rlock);
 634         }
 635 }
 636
 637 static struct syscore_ops stm32_exti_h_syscore_ops = {
 638 #ifdef CONFIG_PM_SLEEP
 639         .suspend        = stm32_exti_h_suspend,
 640         .resume         = stm32_exti_h_resume,
 641 #endif
 642 };
 643
 644 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
 645 {
 646         stm32_host_data = host_data;
 647         register_syscore_ops(&stm32_exti_h_syscore_ops);
 648 }
 649
 650 static void stm32_exti_h_syscore_deinit(void)
 651 {
 652         unregister_syscore_ops(&stm32_exti_h_syscore_ops);
 653 }
 654
 655 static int stm32_exti_h_retrigger(struct irq_data *d)
 656 {
 657         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 658         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 659         void __iomem *base = chip_data->host_data->base;
 660         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 661
 662         writel_relaxed(mask, base + stm32_bank->swier_ofst);
 663
 664         return 0;
 665 }
 666
 667 static struct irq_chip stm32_exti_h_chip = {
 668         .name                   = "stm32-exti-h",
 669         .irq_eoi                = stm32_exti_h_eoi,
 670         .irq_mask               = stm32_exti_h_mask,
 671         .irq_unmask             = stm32_exti_h_unmask,
 672         .irq_retrigger          = stm32_exti_h_retrigger,
 673         .irq_set_type           = stm32_exti_h_set_type,
 674         .irq_set_wake           = stm32_exti_h_set_wake,
 675         .flags                  = IRQCHIP_MASK_ON_SUSPEND,
 676         .irq_set_affinity       = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
 677 };
 678
 679 static struct irq_chip stm32_exti_h_chip_direct = {
 680         .name                   = "stm32-exti-h-direct",
 681         .irq_eoi                = irq_chip_eoi_parent,
 682         .irq_ack                = irq_chip_ack_parent,
 683         .irq_mask               = stm32_exti_h_mask,
 684         .irq_unmask             = stm32_exti_h_unmask,
 685         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 686         .irq_set_type           = irq_chip_set_type_parent,
 687         .irq_set_wake           = stm32_exti_h_set_wake,
 688         .flags                  = IRQCHIP_MASK_ON_SUSPEND,
 689         .irq_set_affinity       = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
 690 };
 691
 692 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
 693                                      unsigned int virq,
 694                                      unsigned int nr_irqs, void *data)
 695 {
 696         struct stm32_exti_host_data *host_data = dm->host_data;
 697         struct stm32_exti_chip_data *chip_data;
 698         u8 desc_irq;
 699         struct irq_fwspec *fwspec = data;
 700         struct irq_fwspec p_fwspec;
 701         irq_hw_number_t hwirq;
 702         int bank;
 703         u32 event_trg;
 704         struct irq_chip *chip;
 705
 706         hwirq = fwspec->param[0];
 707         if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
 708                 return -EINVAL;
 709
 710         bank  = hwirq / IRQS_PER_BANK;
 711         chip_data = &host_data->chips_data[bank];
 712
 713         event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
 714         chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
 715                &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
 716
 717         irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
 718
 719         if (!host_data->drv_data->desc_irqs)
 720                 return -EINVAL;
 721
 722         desc_irq = host_data->drv_data->desc_irqs[hwirq];
 723         if (desc_irq != EXTI_INVALID_IRQ) {
 724                 p_fwspec.fwnode = dm->parent->fwnode;
 725                 p_fwspec.param_count = 3;
 726                 p_fwspec.param[0] = GIC_SPI;
 727                 p_fwspec.param[1] = desc_irq;
 728                 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
 729
 730                 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
 731         }
 732
 733         return 0;
 734 }
 735
 736 static struct
 737 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
 738                                            struct device_node *node)
 739 {
 740         struct stm32_exti_host_data *host_data;
 741
 742         host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
 743         if (!host_data)
 744                 return NULL;
 745
 746         host_data->drv_data = dd;
 747         host_data->chips_data = kcalloc(dd->bank_nr,
 748                                         sizeof(struct stm32_exti_chip_data),
 749                                         GFP_KERNEL);
 750         if (!host_data->chips_data)
 751                 goto free_host_data;
 752
 753         host_data->base = of_iomap(node, 0);
 754         if (!host_data->base) {
 755                 pr_err("%pOF: Unable to map registers\n", node);
 756                 goto free_chips_data;
 757         }
 758
 759         stm32_host_data = host_data;
 760
 761         return host_data;
 762
 763 free_chips_data:
 764         kfree(host_data->chips_data);
 765 free_host_data:
 766         kfree(host_data);
 767
 768         return NULL;
 769 }
 770
 771 static struct
 772 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
 773                                            u32 bank_idx,
 774                                            struct device_node *node)
 775 {
 776         const struct stm32_exti_bank *stm32_bank;
 777         struct stm32_exti_chip_data *chip_data;
 778         void __iomem *base = h_data->base;
 779
 780         stm32_bank = h_data->drv_data->exti_banks[bank_idx];
 781         chip_data = &h_data->chips_data[bank_idx];
 782         chip_data->host_data = h_data;
 783         chip_data->reg_bank = stm32_bank;
 784
 785         raw_spin_lock_init(&chip_data->rlock);
 786
 787         /*
 788          * This IP has no reset, so after hot reboot we should
 789          * clear registers to avoid residue
 790          */
 791         writel_relaxed(0, base + stm32_bank->imr_ofst);
 792         if (stm32_bank->emr_ofst != UNDEF_REG)
 793                 writel_relaxed(0, base + stm32_bank->emr_ofst);
 794
 795         pr_info("%pOF: bank%d\n", node, bank_idx);
 796
 797         return chip_data;
 798 }
 799
 800 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 801                                   struct device_node *node)
 802 {
 803         struct stm32_exti_host_data *host_data;
 804         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 805         int nr_irqs, ret, i;
 806         struct irq_chip_generic *gc;
 807         struct irq_domain *domain;
 808
 809         host_data = stm32_exti_host_init(drv_data, node);
 810         if (!host_data)
 811                 return -ENOMEM;
 812
 813         domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
 814                                        &irq_exti_domain_ops, NULL);
 815         if (!domain) {
 816                 pr_err("%pOFn: Could not register interrupt domain.\n",
 817                        node);
 818                 ret = -ENOMEM;
 819                 goto out_unmap;
 820         }
 821
 822         ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
 823                                              handle_edge_irq, clr, 0, 0);
 824         if (ret) {
 825                 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
 826                        node);
 827                 goto out_free_domain;
 828         }
 829
 830         for (i = 0; i < drv_data->bank_nr; i++) {
 831                 const struct stm32_exti_bank *stm32_bank;
 832                 struct stm32_exti_chip_data *chip_data;
 833
 834                 stm32_bank = drv_data->exti_banks[i];
 835                 chip_data = stm32_exti_chip_init(host_data, i, node);
 836
 837                 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
 838
 839                 gc->reg_base = host_data->base;
 840                 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
 841                 gc->chip_types->chip.irq_ack = stm32_irq_ack;
 842                 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
 843                 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
 844                 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
 845                 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
 846                 gc->suspend = stm32_irq_suspend;
 847                 gc->resume = stm32_irq_resume;
 848                 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
 849
 850                 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
 851                 gc->private = (void *)chip_data;
 852         }
 853
 854         nr_irqs = of_irq_count(node);
 855         for (i = 0; i < nr_irqs; i++) {
 856                 unsigned int irq = irq_of_parse_and_map(node, i);
 857
 858                 irq_set_handler_data(irq, domain);
 859                 irq_set_chained_handler(irq, stm32_irq_handler);
 860         }
 861
 862         return 0;
 863
 864 out_free_domain:
 865         irq_domain_remove(domain);
 866 out_unmap:
 867         iounmap(host_data->base);
 868         kfree(host_data->chips_data);
 869         kfree(host_data);
 870         return ret;
 871 }
 872
 873 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
 874         .alloc  = stm32_exti_h_domain_alloc,
 875         .free   = irq_domain_free_irqs_common,
 876         .xlate = irq_domain_xlate_twocell,
 877 };
 878
 879 static void stm32_exti_remove_irq(void *data)
 880 {
 881         struct irq_domain *domain = data;
 882
 883         irq_domain_remove(domain);
 884 }
 885
 886 static int stm32_exti_remove(struct platform_device *pdev)
 887 {
 888         stm32_exti_h_syscore_deinit();
 889         return 0;
 890 }
 891
 892 static int stm32_exti_probe(struct platform_device *pdev)
 893 {
 894         int ret, i;
 895         struct device *dev = &pdev->dev;
 896         struct device_node *np = dev->of_node;
 897         struct irq_domain *parent_domain, *domain;
 898         struct stm32_exti_host_data *host_data;
 899         const struct stm32_exti_drv_data *drv_data;
 900
 901         host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
 902         if (!host_data)
 903                 return -ENOMEM;
 904
 905         /* check for optional hwspinlock which may be not available yet */
 906         ret = of_hwspin_lock_get_id(np, 0);
 907         if (ret == -EPROBE_DEFER)
 908                 /* hwspinlock framework not yet ready */
 909                 return ret;
 910
 911         if (ret >= 0) {
 912                 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
 913                 if (!host_data->hwlock) {
 914                         dev_err(dev, "Failed to request hwspinlock\n");
 915                         return -EINVAL;
 916                 }
 917         } else if (ret != -ENOENT) {
 918                 /* note: ENOENT is a valid case (means 'no hwspinlock') */
 919                 dev_err(dev, "Failed to get hwspinlock\n");
 920                 return ret;
 921         }
 922
 923         /* initialize host_data */
 924         drv_data = of_device_get_match_data(dev);
 925         if (!drv_data) {
 926                 dev_err(dev, "no of match data\n");
 927                 return -ENODEV;
 928         }
 929         host_data->drv_data = drv_data;
 930
 931         host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
 932                                              sizeof(*host_data->chips_data),
 933                                              GFP_KERNEL);
 934         if (!host_data->chips_data)
 935                 return -ENOMEM;
 936
 937         host_data->base = devm_platform_ioremap_resource(pdev, 0);
 938         if (IS_ERR(host_data->base))
 939                 return PTR_ERR(host_data->base);
 940
 941         for (i = 0; i < drv_data->bank_nr; i++)
 942                 stm32_exti_chip_init(host_data, i, np);
 943
 944         parent_domain = irq_find_host(of_irq_find_parent(np));
 945         if (!parent_domain) {
 946                 dev_err(dev, "GIC interrupt-parent not found\n");
 947                 return -EINVAL;
 948         }
 949
 950         domain = irq_domain_add_hierarchy(parent_domain, 0,
 951                                           drv_data->bank_nr * IRQS_PER_BANK,
 952                                           np, &stm32_exti_h_domain_ops,
 953                                           host_data);
 954
 955         if (!domain) {
 956                 dev_err(dev, "Could not register exti domain\n");
 957                 return -ENOMEM;
 958         }
 959
 960         ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
 961         if (ret)
 962                 return ret;
 963
 964         stm32_exti_h_syscore_init(host_data);
 965
 966         return 0;
 967 }
 968
 969 /* platform driver only for MP1 */
 970 static const struct of_device_id stm32_exti_ids[] = {
 971         { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
 972         { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
 973         {},
 974 };
 975 MODULE_DEVICE_TABLE(of, stm32_exti_ids);
 976
 977 static struct platform_driver stm32_exti_driver = {
 978         .probe          = stm32_exti_probe,
 979         .remove         = stm32_exti_remove,
 980         .driver         = {
 981                 .name   = "stm32_exti",
 982                 .of_match_table = stm32_exti_ids,
 983         },
 984 };
 985
 986 static int __init stm32_exti_arch_init(void)
 987 {
 988         return platform_driver_register(&stm32_exti_driver);
 989 }
 990
 991 static void __exit stm32_exti_arch_exit(void)
 992 {
 993         return platform_driver_unregister(&stm32_exti_driver);
 994 }
 995
 996 arch_initcall(stm32_exti_arch_init);
 997 module_exit(stm32_exti_arch_exit);
 998
 999 /* no platform driver for F4 and H7 */
1000 static int __init stm32f4_exti_of_init(struct device_node *np,
1001                                        struct device_node *parent)
1002 {
1003         return stm32_exti_init(&stm32f4xx_drv_data, np);
1004 }
1005
1006 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
1007
1008 static int __init stm32h7_exti_of_init(struct device_node *np,
1009                                        struct device_node *parent)
1010 {
1011         return stm32_exti_init(&stm32h7xx_drv_data, np);
1012 }
1013
1014 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);