drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
  42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
  43
  44 static int mes_v11_0_hw_fini(void *handle);
  45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  47
  48 #define MES_EOP_SIZE   2048
  49
  50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  51 {
  52         struct amdgpu_device *adev = ring->adev;
  53
  54         if (ring->use_doorbell) {
  55                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  56                              ring->wptr);
  57                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  58         } else {
  59                 BUG();
  60         }
  61 }
  62
  63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  64 {
  65         return *ring->rptr_cpu_addr;
  66 }
  67
  68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  69 {
  70         u64 wptr;
  71
  72         if (ring->use_doorbell)
  73                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  74         else
  75                 BUG();
  76         return wptr;
  77 }
  78
  79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  80         .type = AMDGPU_RING_TYPE_MES,
  81         .align_mask = 1,
  82         .nop = 0,
  83         .support_64bit_ptrs = true,
  84         .get_rptr = mes_v11_0_ring_get_rptr,
  85         .get_wptr = mes_v11_0_ring_get_wptr,
  86         .set_wptr = mes_v11_0_ring_set_wptr,
  87         .insert_nop = amdgpu_ring_insert_nop,
  88 };
  89
  90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
  91                                                     void *pkt, int size,
  92                                                     int api_status_off)
  93 {
  94         int ndw = size / 4;
  95         signed long r;
  96         union MESAPI__ADD_QUEUE *x_pkt = pkt;
  97         struct MES_API_STATUS *api_status;
  98         struct amdgpu_device *adev = mes->adev;
  99         struct amdgpu_ring *ring = &mes->ring;
 100         unsigned long flags;
 101         signed long timeout = adev->usec_timeout;
 102
 103         if (amdgpu_emu_mode) {
 104                 timeout *= 100;
 105         } else if (amdgpu_sriov_vf(adev)) {
 106                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 107                 timeout = 15 * 600 * 1000;
 108         }
 109         BUG_ON(size % 4 != 0);
 110
 111         spin_lock_irqsave(&mes->ring_lock, flags);
 112         if (amdgpu_ring_alloc(ring, ndw)) {
 113                 spin_unlock_irqrestore(&mes->ring_lock, flags);
 114                 return -ENOMEM;
 115         }
 116
 117         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 118         api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr;
 119         api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq;
 120
 121         amdgpu_ring_write_multiple(ring, pkt, ndw);
 122         amdgpu_ring_commit(ring);
 123         spin_unlock_irqrestore(&mes->ring_lock, flags);
 124
 125         DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
 126
 127         r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
 128                       timeout);
 129         if (r < 1) {
 130                 DRM_ERROR("MES failed to response msg=%d\n",
 131                           x_pkt->header.opcode);
 132
 133                 while (halt_if_hws_hang)
 134                         schedule();
 135
 136                 return -ETIMEDOUT;
 137         }
 138
 139         return 0;
 140 }
 141
 142 static int convert_to_mes_queue_type(int queue_type)
 143 {
 144         if (queue_type == AMDGPU_RING_TYPE_GFX)
 145                 return MES_QUEUE_TYPE_GFX;
 146         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 147                 return MES_QUEUE_TYPE_COMPUTE;
 148         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 149                 return MES_QUEUE_TYPE_SDMA;
 150         else
 151                 BUG();
 152         return -1;
 153 }
 154
 155 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 156                                   struct mes_add_queue_input *input)
 157 {
 158         struct amdgpu_device *adev = mes->adev;
 159         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 160         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 161         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 162
 163         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 164
 165         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 166         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 167         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 168
 169         mes_add_queue_pkt.process_id = input->process_id;
 170         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 171         mes_add_queue_pkt.process_va_start = input->process_va_start;
 172         mes_add_queue_pkt.process_va_end = input->process_va_end;
 173         mes_add_queue_pkt.process_quantum = input->process_quantum;
 174         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 175         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 176         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 177         mes_add_queue_pkt.inprocess_gang_priority =
 178                 input->inprocess_gang_priority;
 179         mes_add_queue_pkt.gang_global_priority_level =
 180                 input->gang_global_priority_level;
 181         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 182         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 183
 184         if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
 185                         AMDGPU_MES_API_VERSION_SHIFT) >= 2)
 186                 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 187         else
 188                 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 189
 190         mes_add_queue_pkt.queue_type =
 191                 convert_to_mes_queue_type(input->queue_type);
 192         mes_add_queue_pkt.paging = input->paging;
 193         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 194         mes_add_queue_pkt.gws_base = input->gws_base;
 195         mes_add_queue_pkt.gws_size = input->gws_size;
 196         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 197         mes_add_queue_pkt.tma_addr = input->tma_addr;
 198         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 199         mes_add_queue_pkt.trap_en = 1;
 200
 201         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 202         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 203         mes_add_queue_pkt.gds_size = input->queue_size;
 204
 205         if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) &&
 206                   (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) &&
 207                   (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3))))
 208                 mes_add_queue_pkt.trap_en = 1;
 209
 210         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 211         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 212         mes_add_queue_pkt.gds_size = input->queue_size;
 213
 214         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 215                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 216                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 217 }
 218
 219 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 220                                      struct mes_remove_queue_input *input)
 221 {
 222         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 223
 224         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 225
 226         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 227         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 228         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 229
 230         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 231         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 232
 233         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 234                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 235                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 236 }
 237
 238 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 239                         struct mes_unmap_legacy_queue_input *input)
 240 {
 241         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 242
 243         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 244
 245         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 246         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 247         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 248
 249         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 250         mes_remove_queue_pkt.gang_context_addr = 0;
 251
 252         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 253         mes_remove_queue_pkt.queue_id = input->queue_id;
 254
 255         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 256                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 257                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 258                 mes_remove_queue_pkt.tf_data =
 259                         lower_32_bits(input->trail_fence_data);
 260         } else {
 261                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 262                 mes_remove_queue_pkt.queue_type =
 263                         convert_to_mes_queue_type(input->queue_type);
 264         }
 265
 266         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 267                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 268                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 269 }
 270
 271 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 272                                   struct mes_suspend_gang_input *input)
 273 {
 274         return 0;
 275 }
 276
 277 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 278                                  struct mes_resume_gang_input *input)
 279 {
 280         return 0;
 281 }
 282
 283 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 284 {
 285         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 286
 287         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 288
 289         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 290         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 291         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 292
 293         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 294                         &mes_status_pkt, sizeof(mes_status_pkt),
 295                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 296 }
 297
 298 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
 299                              struct mes_misc_op_input *input)
 300 {
 301         union MESAPI__MISC misc_pkt;
 302
 303         memset(&misc_pkt, 0, sizeof(misc_pkt));
 304
 305         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 306         misc_pkt.header.opcode = MES_SCH_API_MISC;
 307         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 308
 309         switch (input->op) {
 310         case MES_MISC_OP_READ_REG:
 311                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 312                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 313                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 314                 break;
 315         case MES_MISC_OP_WRITE_REG:
 316                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 317                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 318                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 319                 break;
 320         case MES_MISC_OP_WRM_REG_WAIT:
 321                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 322                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 323                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 324                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 325                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 326                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 327                 break;
 328         case MES_MISC_OP_WRM_REG_WR_WAIT:
 329                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 330                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 331                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 332                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 333                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 334                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 335                 break;
 336         default:
 337                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 338                 return -EINVAL;
 339         }
 340
 341         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 342                         &misc_pkt, sizeof(misc_pkt),
 343                         offsetof(union MESAPI__MISC, api_status));
 344 }
 345
 346 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 347 {
 348         int i;
 349         struct amdgpu_device *adev = mes->adev;
 350         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 351
 352         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 353
 354         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 355         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 356         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 357
 358         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 359         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 360         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 361         mes_set_hw_res_pkt.paging_vmid = 0;
 362         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 363         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 364                 mes->query_status_fence_gpu_addr;
 365
 366         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 367                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 368                         mes->compute_hqd_mask[i];
 369
 370         for (i = 0; i < MAX_GFX_PIPES; i++)
 371                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 372
 373         for (i = 0; i < MAX_SDMA_PIPES; i++)
 374                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 375
 376         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 377                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 378                         mes->aggregated_doorbells[i];
 379
 380         for (i = 0; i < 5; i++) {
 381                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 382                 mes_set_hw_res_pkt.mmhub_base[i] =
 383                                 adev->reg_offset[MMHUB_HWIP][0][i];
 384                 mes_set_hw_res_pkt.osssys_base[i] =
 385                 adev->reg_offset[OSSSYS_HWIP][0][i];
 386         }
 387
 388         mes_set_hw_res_pkt.disable_reset = 1;
 389         mes_set_hw_res_pkt.disable_mes_log = 1;
 390         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 391         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 392         mes_set_hw_res_pkt.oversubscription_timer = 50;
 393
 394         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 395                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 396                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 397 }
 398
 399 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
 400 {
 401         struct amdgpu_device *adev = mes->adev;
 402         uint32_t data;
 403
 404         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
 405         data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
 406                   CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
 407                   CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
 408         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
 409                 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
 410         data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
 411         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
 412
 413         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
 414         data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
 415                   CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
 416                   CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
 417         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
 418                 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
 419         data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
 420         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
 421
 422         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
 423         data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
 424                   CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
 425                   CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
 426         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
 427                 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
 428         data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
 429         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
 430
 431         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
 432         data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
 433                   CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
 434                   CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
 435         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
 436                 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
 437         data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
 438         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
 439
 440         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
 441         data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
 442                   CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
 443                   CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
 444         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
 445                 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
 446         data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
 447         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
 448
 449         data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
 450         WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
 451 }
 452
 453 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 454         .add_hw_queue = mes_v11_0_add_hw_queue,
 455         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 456         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 457         .suspend_gang = mes_v11_0_suspend_gang,
 458         .resume_gang = mes_v11_0_resume_gang,
 459         .misc_op = mes_v11_0_misc_op,
 460 };
 461
 462 static int mes_v11_0_init_microcode(struct amdgpu_device *adev,
 463                                     enum admgpu_mes_pipe pipe)
 464 {
 465         char fw_name[30];
 466         char ucode_prefix[30];
 467         int err;
 468         const struct mes_firmware_header_v1_0 *mes_hdr;
 469         struct amdgpu_firmware_info *info;
 470
 471         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 472
 473         if (pipe == AMDGPU_MES_SCHED_PIPE)
 474                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
 475                          ucode_prefix);
 476         else
 477                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin",
 478                          ucode_prefix);
 479
 480         err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
 481         if (err)
 482                 return err;
 483
 484         err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
 485         if (err) {
 486                 release_firmware(adev->mes.fw[pipe]);
 487                 adev->mes.fw[pipe] = NULL;
 488                 return err;
 489         }
 490
 491         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 492                 adev->mes.fw[pipe]->data;
 493         adev->mes.uc_start_addr[pipe] =
 494                 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
 495                 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
 496         adev->mes.data_start_addr[pipe] =
 497                 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
 498                 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
 499
 500         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 501                 int ucode, ucode_data;
 502
 503                 if (pipe == AMDGPU_MES_SCHED_PIPE) {
 504                         ucode = AMDGPU_UCODE_ID_CP_MES;
 505                         ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
 506                 } else {
 507                         ucode = AMDGPU_UCODE_ID_CP_MES1;
 508                         ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
 509                 }
 510
 511                 info = &adev->firmware.ucode[ucode];
 512                 info->ucode_id = ucode;
 513                 info->fw = adev->mes.fw[pipe];
 514                 adev->firmware.fw_size +=
 515                         ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
 516                               PAGE_SIZE);
 517
 518                 info = &adev->firmware.ucode[ucode_data];
 519                 info->ucode_id = ucode_data;
 520                 info->fw = adev->mes.fw[pipe];
 521                 adev->firmware.fw_size +=
 522                         ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
 523                               PAGE_SIZE);
 524         }
 525
 526         return 0;
 527 }
 528
 529 static void mes_v11_0_free_microcode(struct amdgpu_device *adev,
 530                                      enum admgpu_mes_pipe pipe)
 531 {
 532         release_firmware(adev->mes.fw[pipe]);
 533         adev->mes.fw[pipe] = NULL;
 534 }
 535
 536 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 537                                            enum admgpu_mes_pipe pipe)
 538 {
 539         int r;
 540         const struct mes_firmware_header_v1_0 *mes_hdr;
 541         const __le32 *fw_data;
 542         unsigned fw_size;
 543
 544         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 545                 adev->mes.fw[pipe]->data;
 546
 547         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 548                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 549         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 550
 551         r = amdgpu_bo_create_reserved(adev, fw_size,
 552                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 553                                       &adev->mes.ucode_fw_obj[pipe],
 554                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 555                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 556         if (r) {
 557                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 558                 return r;
 559         }
 560
 561         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 562
 563         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 564         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 565
 566         return 0;
 567 }
 568
 569 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 570                                                 enum admgpu_mes_pipe pipe)
 571 {
 572         int r;
 573         const struct mes_firmware_header_v1_0 *mes_hdr;
 574         const __le32 *fw_data;
 575         unsigned fw_size;
 576
 577         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 578                 adev->mes.fw[pipe]->data;
 579
 580         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 581                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 582         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 583
 584         r = amdgpu_bo_create_reserved(adev, fw_size,
 585                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
 586                                       &adev->mes.data_fw_obj[pipe],
 587                                       &adev->mes.data_fw_gpu_addr[pipe],
 588                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 589         if (r) {
 590                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 591                 return r;
 592         }
 593
 594         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 595
 596         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 597         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 598
 599         return 0;
 600 }
 601
 602 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 603                                          enum admgpu_mes_pipe pipe)
 604 {
 605         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 606                               &adev->mes.data_fw_gpu_addr[pipe],
 607                               (void **)&adev->mes.data_fw_ptr[pipe]);
 608
 609         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 610                               &adev->mes.ucode_fw_gpu_addr[pipe],
 611                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 612 }
 613
 614 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 615 {
 616         uint64_t ucode_addr;
 617         uint32_t pipe, data = 0;
 618
 619         if (enable) {
 620                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 621                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 622                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 623                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 624                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 625
 626                 mutex_lock(&adev->srbm_mutex);
 627                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 628                         if (!adev->enable_mes_kiq &&
 629                             pipe == AMDGPU_MES_KIQ_PIPE)
 630                                 continue;
 631
 632                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 633
 634                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 635                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 636                                      lower_32_bits(ucode_addr));
 637                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 638                                      upper_32_bits(ucode_addr));
 639                 }
 640                 soc21_grbm_select(adev, 0, 0, 0, 0);
 641                 mutex_unlock(&adev->srbm_mutex);
 642
 643                 /* unhalt MES and activate pipe0 */
 644                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 645                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 646                                      adev->enable_mes_kiq ? 1 : 0);
 647                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 648
 649                 if (amdgpu_emu_mode)
 650                         msleep(100);
 651                 else
 652                         udelay(50);
 653         } else {
 654                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 655                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 656                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 657                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 658                                      MES_INVALIDATE_ICACHE, 1);
 659                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 660                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 661                                      adev->enable_mes_kiq ? 1 : 0);
 662                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 663                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 664         }
 665 }
 666
 667 /* This function is for backdoor MES firmware */
 668 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 669                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 670 {
 671         int r;
 672         uint32_t data;
 673         uint64_t ucode_addr;
 674
 675         mes_v11_0_enable(adev, false);
 676
 677         if (!adev->mes.fw[pipe])
 678                 return -EINVAL;
 679
 680         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 681         if (r)
 682                 return r;
 683
 684         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 685         if (r) {
 686                 mes_v11_0_free_ucode_buffers(adev, pipe);
 687                 return r;
 688         }
 689
 690         mutex_lock(&adev->srbm_mutex);
 691         /* me=3, pipe=0, queue=0 */
 692         soc21_grbm_select(adev, 3, pipe, 0, 0);
 693
 694         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 695
 696         /* set ucode start address */
 697         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 698         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 699                      lower_32_bits(ucode_addr));
 700         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 701                      upper_32_bits(ucode_addr));
 702
 703         /* set ucode fimrware address */
 704         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 705                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 706         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 707                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 708
 709         /* set ucode instruction cache boundary to 2M-1 */
 710         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 711
 712         /* set ucode data firmware address */
 713         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 714                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 715         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 716                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 717
 718         /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
 719         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 720
 721         if (prime_icache) {
 722                 /* invalidate ICACHE */
 723                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 724                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 725                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 726                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 727
 728                 /* prime the ICACHE. */
 729                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 730                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 731                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 732         }
 733
 734         soc21_grbm_select(adev, 0, 0, 0, 0);
 735         mutex_unlock(&adev->srbm_mutex);
 736
 737         return 0;
 738 }
 739
 740 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 741                                       enum admgpu_mes_pipe pipe)
 742 {
 743         int r;
 744         u32 *eop;
 745
 746         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 747                               AMDGPU_GEM_DOMAIN_GTT,
 748                               &adev->mes.eop_gpu_obj[pipe],
 749                               &adev->mes.eop_gpu_addr[pipe],
 750                               (void **)&eop);
 751         if (r) {
 752                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 753                 return r;
 754         }
 755
 756         memset(eop, 0,
 757                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 758
 759         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 760         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 761
 762         return 0;
 763 }
 764
 765 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 766 {
 767         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 768         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 769         uint32_t tmp;
 770
 771         mqd->header = 0xC0310800;
 772         mqd->compute_pipelinestat_enable = 0x00000001;
 773         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 774         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 775         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 776         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 777         mqd->compute_misc_reserved = 0x00000007;
 778
 779         eop_base_addr = ring->eop_gpu_addr >> 8;
 780
 781         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 782         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 783         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 784                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 785
 786         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 787         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 788         mqd->cp_hqd_eop_control = tmp;
 789
 790         /* disable the queue if it's active */
 791         ring->wptr = 0;
 792         mqd->cp_hqd_pq_rptr = 0;
 793         mqd->cp_hqd_pq_wptr_lo = 0;
 794         mqd->cp_hqd_pq_wptr_hi = 0;
 795
 796         /* set the pointer to the MQD */
 797         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 798         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 799
 800         /* set MQD vmid to 0 */
 801         tmp = regCP_MQD_CONTROL_DEFAULT;
 802         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 803         mqd->cp_mqd_control = tmp;
 804
 805         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 806         hqd_gpu_addr = ring->gpu_addr >> 8;
 807         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 808         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 809
 810         /* set the wb address whether it's enabled or not */
 811         wb_gpu_addr = ring->rptr_gpu_addr;
 812         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 813         mqd->cp_hqd_pq_rptr_report_addr_hi =
 814                 upper_32_bits(wb_gpu_addr) & 0xffff;
 815
 816         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 817         wb_gpu_addr = ring->wptr_gpu_addr;
 818         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 819         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 820
 821         /* set up the HQD, this is similar to CP_RB0_CNTL */
 822         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 823         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 824                             (order_base_2(ring->ring_size / 4) - 1));
 825         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 826                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 827         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 828         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 829         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 830         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 831         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 832         mqd->cp_hqd_pq_control = tmp;
 833
 834         /* enable doorbell */
 835         tmp = 0;
 836         if (ring->use_doorbell) {
 837                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 838                                     DOORBELL_OFFSET, ring->doorbell_index);
 839                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 840                                     DOORBELL_EN, 1);
 841                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 842                                     DOORBELL_SOURCE, 0);
 843                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 844                                     DOORBELL_HIT, 0);
 845         }
 846         else
 847                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 848                                     DOORBELL_EN, 0);
 849         mqd->cp_hqd_pq_doorbell_control = tmp;
 850
 851         mqd->cp_hqd_vmid = 0;
 852         /* activate the queue */
 853         mqd->cp_hqd_active = 1;
 854
 855         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 856         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 857                             PRELOAD_SIZE, 0x55);
 858         mqd->cp_hqd_persistent_state = tmp;
 859
 860         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 861         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 862         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 863
 864         return 0;
 865 }
 866
 867 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 868 {
 869         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 870         struct amdgpu_device *adev = ring->adev;
 871         uint32_t data = 0;
 872
 873         mutex_lock(&adev->srbm_mutex);
 874         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 875
 876         /* set CP_HQD_VMID.VMID = 0. */
 877         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 878         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 879         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 880
 881         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 882         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 883         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 884                              DOORBELL_EN, 0);
 885         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 886
 887         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 888         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 889         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 890
 891         /* set CP_MQD_CONTROL.VMID=0 */
 892         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 893         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 894         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 895
 896         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 897         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 898         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 899
 900         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 901         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 902                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 903         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 904                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 905
 906         /* set CP_HQD_PQ_CONTROL */
 907         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 908
 909         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 910         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 911                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 912         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 913                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 914
 915         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 916         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 917                      mqd->cp_hqd_pq_doorbell_control);
 918
 919         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 920         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 921
 922         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 923         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 924
 925         soc21_grbm_select(adev, 0, 0, 0, 0);
 926         mutex_unlock(&adev->srbm_mutex);
 927 }
 928
 929 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
 930 {
 931         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 932         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 933         int r;
 934
 935         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 936                 return -EINVAL;
 937
 938         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
 939         if (r) {
 940                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 941                 return r;
 942         }
 943
 944         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
 945
 946         r = amdgpu_ring_test_ring(kiq_ring);
 947         if (r) {
 948                 DRM_ERROR("kfq enable failed\n");
 949                 kiq_ring->sched.ready = false;
 950         }
 951         return r;
 952 }
 953
 954 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 955                                 enum admgpu_mes_pipe pipe)
 956 {
 957         struct amdgpu_ring *ring;
 958         int r;
 959
 960         if (pipe == AMDGPU_MES_KIQ_PIPE)
 961                 ring = &adev->gfx.kiq.ring;
 962         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 963                 ring = &adev->mes.ring;
 964         else
 965                 BUG();
 966
 967         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
 968             (amdgpu_in_reset(adev) || adev->in_suspend)) {
 969                 *(ring->wptr_cpu_addr) = 0;
 970                 *(ring->rptr_cpu_addr) = 0;
 971                 amdgpu_ring_clear_ring(ring);
 972         }
 973
 974         r = mes_v11_0_mqd_init(ring);
 975         if (r)
 976                 return r;
 977
 978         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 979                 r = mes_v11_0_kiq_enable_queue(adev);
 980                 if (r)
 981                         return r;
 982         } else {
 983                 mes_v11_0_queue_init_register(ring);
 984         }
 985
 986         /* get MES scheduler/KIQ versions */
 987         mutex_lock(&adev->srbm_mutex);
 988         soc21_grbm_select(adev, 3, pipe, 0, 0);
 989
 990         if (pipe == AMDGPU_MES_SCHED_PIPE)
 991                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 992         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
 993                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 994
 995         soc21_grbm_select(adev, 0, 0, 0, 0);
 996         mutex_unlock(&adev->srbm_mutex);
 997
 998         return 0;
 999 }
1000
1001 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1002 {
1003         struct amdgpu_ring *ring;
1004
1005         ring = &adev->mes.ring;
1006
1007         ring->funcs = &mes_v11_0_ring_funcs;
1008
1009         ring->me = 3;
1010         ring->pipe = 0;
1011         ring->queue = 0;
1012
1013         ring->ring_obj = NULL;
1014         ring->use_doorbell = true;
1015         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1016         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1017         ring->no_scheduler = true;
1018         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1019
1020         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1021                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1022 }
1023
1024 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1025 {
1026         struct amdgpu_ring *ring;
1027
1028         spin_lock_init(&adev->gfx.kiq.ring_lock);
1029
1030         ring = &adev->gfx.kiq.ring;
1031
1032         ring->me = 3;
1033         ring->pipe = 1;
1034         ring->queue = 0;
1035
1036         ring->adev = NULL;
1037         ring->ring_obj = NULL;
1038         ring->use_doorbell = true;
1039         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1040         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1041         ring->no_scheduler = true;
1042         sprintf(ring->name, "mes_kiq_%d.%d.%d",
1043                 ring->me, ring->pipe, ring->queue);
1044
1045         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1046                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1047 }
1048
1049 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1050                                  enum admgpu_mes_pipe pipe)
1051 {
1052         int r, mqd_size = sizeof(struct v11_compute_mqd);
1053         struct amdgpu_ring *ring;
1054
1055         if (pipe == AMDGPU_MES_KIQ_PIPE)
1056                 ring = &adev->gfx.kiq.ring;
1057         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1058                 ring = &adev->mes.ring;
1059         else
1060                 BUG();
1061
1062         if (ring->mqd_obj)
1063                 return 0;
1064
1065         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1066                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1067                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1068         if (r) {
1069                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1070                 return r;
1071         }
1072
1073         memset(ring->mqd_ptr, 0, mqd_size);
1074
1075         /* prepare MQD backup */
1076         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1077         if (!adev->mes.mqd_backup[pipe])
1078                 dev_warn(adev->dev,
1079                          "no memory to create MQD backup for ring %s\n",
1080                          ring->name);
1081
1082         return 0;
1083 }
1084
1085 static int mes_v11_0_sw_init(void *handle)
1086 {
1087         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1088         int pipe, r;
1089
1090         adev->mes.adev = adev;
1091         adev->mes.funcs = &mes_v11_0_funcs;
1092         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1093         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1094
1095         r = amdgpu_mes_init(adev);
1096         if (r)
1097                 return r;
1098
1099         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1100                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1101                         continue;
1102
1103                 r = mes_v11_0_init_microcode(adev, pipe);
1104                 if (r)
1105                         return r;
1106
1107                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1108                 if (r)
1109                         return r;
1110
1111                 r = mes_v11_0_mqd_sw_init(adev, pipe);
1112                 if (r)
1113                         return r;
1114         }
1115
1116         if (adev->enable_mes_kiq) {
1117                 r = mes_v11_0_kiq_ring_init(adev);
1118                 if (r)
1119                         return r;
1120         }
1121
1122         r = mes_v11_0_ring_init(adev);
1123         if (r)
1124                 return r;
1125
1126         return 0;
1127 }
1128
1129 static int mes_v11_0_sw_fini(void *handle)
1130 {
1131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132         int pipe;
1133
1134         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1135         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1136
1137         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1138                 kfree(adev->mes.mqd_backup[pipe]);
1139
1140                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1141                                       &adev->mes.eop_gpu_addr[pipe],
1142                                       NULL);
1143
1144                 mes_v11_0_free_microcode(adev, pipe);
1145         }
1146
1147         amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj,
1148                               &adev->gfx.kiq.ring.mqd_gpu_addr,
1149                               &adev->gfx.kiq.ring.mqd_ptr);
1150
1151         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1152                               &adev->mes.ring.mqd_gpu_addr,
1153                               &adev->mes.ring.mqd_ptr);
1154
1155         amdgpu_ring_fini(&adev->gfx.kiq.ring);
1156         amdgpu_ring_fini(&adev->mes.ring);
1157
1158         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1159                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1160                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1161         }
1162
1163         amdgpu_mes_fini(adev);
1164         return 0;
1165 }
1166
1167 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1168 {
1169         uint32_t data;
1170         int i;
1171
1172         mutex_lock(&adev->srbm_mutex);
1173         soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1174
1175         /* disable the queue if it's active */
1176         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1177                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1178                 for (i = 0; i < adev->usec_timeout; i++) {
1179                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1180                                 break;
1181                         udelay(1);
1182                 }
1183         }
1184         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1185         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1186                                 DOORBELL_EN, 0);
1187         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1188                                 DOORBELL_HIT, 1);
1189         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1190
1191         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1192
1193         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1194         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1195         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1196
1197         soc21_grbm_select(adev, 0, 0, 0, 0);
1198         mutex_unlock(&adev->srbm_mutex);
1199
1200         adev->mes.ring.sched.ready = false;
1201 }
1202
1203 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1204 {
1205         uint32_t tmp;
1206         struct amdgpu_device *adev = ring->adev;
1207
1208         /* tell RLC which is KIQ queue */
1209         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1210         tmp &= 0xffffff00;
1211         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1212         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1213         tmp |= 0x80;
1214         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1215 }
1216
1217 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1218 {
1219         int r = 0;
1220
1221         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1222
1223                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1224                 if (r) {
1225                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1226                         return r;
1227                 }
1228
1229                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1230                 if (r) {
1231                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1232                         return r;
1233                 }
1234
1235         }
1236
1237         mes_v11_0_enable(adev, true);
1238
1239         mes_v11_0_kiq_setting(&adev->gfx.kiq.ring);
1240
1241         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1242         if (r)
1243                 goto failure;
1244
1245         return r;
1246
1247 failure:
1248         mes_v11_0_hw_fini(adev);
1249         return r;
1250 }
1251
1252 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1253 {
1254         if (adev->mes.ring.sched.ready)
1255                 mes_v11_0_kiq_dequeue_sched(adev);
1256
1257         if (!amdgpu_sriov_vf(adev))
1258                 mes_v11_0_enable(adev, false);
1259
1260         return 0;
1261 }
1262
1263 static int mes_v11_0_hw_init(void *handle)
1264 {
1265         int r;
1266         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267
1268         if (!adev->enable_mes_kiq) {
1269                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1270                         r = mes_v11_0_load_microcode(adev,
1271                                              AMDGPU_MES_SCHED_PIPE, true);
1272                         if (r) {
1273                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1274                                 return r;
1275                         }
1276                 }
1277
1278                 mes_v11_0_enable(adev, true);
1279         }
1280
1281         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1282         if (r)
1283                 goto failure;
1284
1285         r = mes_v11_0_set_hw_resources(&adev->mes);
1286         if (r)
1287                 goto failure;
1288
1289         mes_v11_0_init_aggregated_doorbell(&adev->mes);
1290
1291         r = mes_v11_0_query_sched_status(&adev->mes);
1292         if (r) {
1293                 DRM_ERROR("MES is busy\n");
1294                 goto failure;
1295         }
1296
1297         /*
1298          * Disable KIQ ring usage from the driver once MES is enabled.
1299          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1300          * with MES enabled.
1301          */
1302         adev->gfx.kiq.ring.sched.ready = false;
1303         adev->mes.ring.sched.ready = true;
1304
1305         return 0;
1306
1307 failure:
1308         mes_v11_0_hw_fini(adev);
1309         return r;
1310 }
1311
1312 static int mes_v11_0_hw_fini(void *handle)
1313 {
1314         return 0;
1315 }
1316
1317 static int mes_v11_0_suspend(void *handle)
1318 {
1319         int r;
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322         r = amdgpu_mes_suspend(adev);
1323         if (r)
1324                 return r;
1325
1326         return mes_v11_0_hw_fini(adev);
1327 }
1328
1329 static int mes_v11_0_resume(void *handle)
1330 {
1331         int r;
1332         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333
1334         r = mes_v11_0_hw_init(adev);
1335         if (r)
1336                 return r;
1337
1338         return amdgpu_mes_resume(adev);
1339 }
1340
1341 static int mes_v11_0_late_init(void *handle)
1342 {
1343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1346         if (!amdgpu_in_reset(adev) && !adev->in_s0ix &&
1347             (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
1348                 amdgpu_mes_self_test(adev);
1349
1350         return 0;
1351 }
1352
1353 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1354         .name = "mes_v11_0",
1355         .late_init = mes_v11_0_late_init,
1356         .sw_init = mes_v11_0_sw_init,
1357         .sw_fini = mes_v11_0_sw_fini,
1358         .hw_init = mes_v11_0_hw_init,
1359         .hw_fini = mes_v11_0_hw_fini,
1360         .suspend = mes_v11_0_suspend,
1361         .resume = mes_v11_0_resume,
1362 };
1363
1364 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1365         .type = AMD_IP_BLOCK_TYPE_MES,
1366         .major = 11,
1367         .minor = 0,
1368         .rev = 0,
1369         .funcs = &mes_v11_0_ip_funcs,
1370 };