drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * This is a legacy interface and is only provided for backwards compatibility.
  84  * The amdgpu driver provides a sysfs API for adjusting certain power
  85  * related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  * - battery
  88  * - balanced
  89  * - performance
  90  *
  91  * battery
  92  *
  93  * On older GPUs, the vbios provided a special power state for battery
  94  * operation.  Selecting battery switched to this state.  This is no
  95  * longer provided on newer GPUs so the option does nothing in that case.
  96  *
  97  * balanced
  98  *
  99  * On older GPUs, the vbios provided a special power state for balanced
 100  * operation.  Selecting balanced switched to this state.  This is no
 101  * longer provided on newer GPUs so the option does nothing in that case.
 102  *
 103  * performance
 104  *
 105  * On older GPUs, the vbios provided a special power state for performance
 106  * operation.  Selecting performance switched to this state.  This is no
 107  * longer provided on newer GPUs so the option does nothing in that case.
 108  *
 109  */
 110
 111 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 112                                     struct device_attribute *attr,
 113                                     char *buf)
 114 {
 115         struct drm_device *ddev = dev_get_drvdata(dev);
 116         struct amdgpu_device *adev = ddev->dev_private;
 117         enum amd_pm_state_type pm;
 118
 119         if (adev->powerplay.pp_funcs->get_current_power_state)
 120                 pm = amdgpu_dpm_get_current_power_state(adev);
 121         else
 122                 pm = adev->pm.dpm.user_state;
 123
 124         return snprintf(buf, PAGE_SIZE, "%s\n",
 125                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 126                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 127 }
 128
 129 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 130                                     struct device_attribute *attr,
 131                                     const char *buf,
 132                                     size_t count)
 133 {
 134         struct drm_device *ddev = dev_get_drvdata(dev);
 135         struct amdgpu_device *adev = ddev->dev_private;
 136         enum amd_pm_state_type  state;
 137
 138         if (strncmp("battery", buf, strlen("battery")) == 0)
 139                 state = POWER_STATE_TYPE_BATTERY;
 140         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 141                 state = POWER_STATE_TYPE_BALANCED;
 142         else if (strncmp("performance", buf, strlen("performance")) == 0)
 143                 state = POWER_STATE_TYPE_PERFORMANCE;
 144         else {
 145                 count = -EINVAL;
 146                 goto fail;
 147         }
 148
 149         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 150                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 151         } else {
 152                 mutex_lock(&adev->pm.mutex);
 153                 adev->pm.dpm.user_state = state;
 154                 mutex_unlock(&adev->pm.mutex);
 155
 156                 /* Can't set dpm state when the card is off */
 157                 if (!(adev->flags & AMD_IS_PX) ||
 158                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 159                         amdgpu_pm_compute_clocks(adev);
 160         }
 161 fail:
 162         return count;
 163 }
 164
 165
 166 /**
 167  * DOC: power_dpm_force_performance_level
 168  *
 169  * The amdgpu driver provides a sysfs API for adjusting certain power
 170  * related parameters.  The file power_dpm_force_performance_level is
 171  * used for this.  It accepts the following arguments:
 172  * - auto
 173  * - low
 174  * - high
 175  * - manual
 176  * - GPU fan
 177  * - profile_standard
 178  * - profile_min_sclk
 179  * - profile_min_mclk
 180  * - profile_peak
 181  *
 182  * auto
 183  *
 184  * When auto is selected, the driver will attempt to dynamically select
 185  * the optimal power profile for current conditions in the driver.
 186  *
 187  * low
 188  *
 189  * When low is selected, the clocks are forced to the lowest power state.
 190  *
 191  * high
 192  *
 193  * When high is selected, the clocks are forced to the highest power state.
 194  *
 195  * manual
 196  *
 197  * When manual is selected, the user can manually adjust which power states
 198  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 199  * and pp_dpm_pcie files and adjust the power state transition heuristics
 200  * via the pp_power_profile_mode sysfs file.
 201  *
 202  * profile_standard
 203  * profile_min_sclk
 204  * profile_min_mclk
 205  * profile_peak
 206  *
 207  * When the profiling modes are selected, clock and power gating are
 208  * disabled and the clocks are set for different profiling cases. This
 209  * mode is recommended for profiling specific work loads where you do
 210  * not want clock or power gating for clock fluctuation to interfere
 211  * with your results. profile_standard sets the clocks to a fixed clock
 212  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 213  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 214  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 215  *
 216  */
 217
 218 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 219                                                 struct device_attribute *attr,
 220                                                                 char *buf)
 221 {
 222         struct drm_device *ddev = dev_get_drvdata(dev);
 223         struct amdgpu_device *adev = ddev->dev_private;
 224         enum amd_dpm_forced_level level = 0xff;
 225
 226         if  ((adev->flags & AMD_IS_PX) &&
 227              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 228                 return snprintf(buf, PAGE_SIZE, "off\n");
 229
 230         if (adev->powerplay.pp_funcs->get_performance_level)
 231                 level = amdgpu_dpm_get_performance_level(adev);
 232         else
 233                 level = adev->pm.dpm.forced_level;
 234
 235         return snprintf(buf, PAGE_SIZE, "%s\n",
 236                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 237                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 238                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 239                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 240                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 241                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 242                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 243                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 244                         "unknown");
 245 }
 246
 247 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 248                                                        struct device_attribute *attr,
 249                                                        const char *buf,
 250                                                        size_t count)
 251 {
 252         struct drm_device *ddev = dev_get_drvdata(dev);
 253         struct amdgpu_device *adev = ddev->dev_private;
 254         enum amd_dpm_forced_level level;
 255         enum amd_dpm_forced_level current_level = 0xff;
 256         int ret = 0;
 257
 258         /* Can't force performance level when the card is off */
 259         if  ((adev->flags & AMD_IS_PX) &&
 260              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 261                 return -EINVAL;
 262
 263         if (adev->powerplay.pp_funcs->get_performance_level)
 264                 current_level = amdgpu_dpm_get_performance_level(adev);
 265
 266         if (strncmp("low", buf, strlen("low")) == 0) {
 267                 level = AMD_DPM_FORCED_LEVEL_LOW;
 268         } else if (strncmp("high", buf, strlen("high")) == 0) {
 269                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 270         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 271                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 272         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 273                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 274         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 275                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 276         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 278         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 280         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 282         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 284         }  else {
 285                 count = -EINVAL;
 286                 goto fail;
 287         }
 288
 289         if (current_level == level)
 290                 return count;
 291
 292         if (adev->powerplay.pp_funcs->force_performance_level) {
 293                 mutex_lock(&adev->pm.mutex);
 294                 if (adev->pm.dpm.thermal_active) {
 295                         count = -EINVAL;
 296                         mutex_unlock(&adev->pm.mutex);
 297                         goto fail;
 298                 }
 299                 ret = amdgpu_dpm_force_performance_level(adev, level);
 300                 if (ret)
 301                         count = -EINVAL;
 302                 else
 303                         adev->pm.dpm.forced_level = level;
 304                 mutex_unlock(&adev->pm.mutex);
 305         }
 306
 307 fail:
 308         return count;
 309 }
 310
 311 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 312                 struct device_attribute *attr,
 313                 char *buf)
 314 {
 315         struct drm_device *ddev = dev_get_drvdata(dev);
 316         struct amdgpu_device *adev = ddev->dev_private;
 317         struct pp_states_info data;
 318         int i, buf_len;
 319
 320         if (adev->powerplay.pp_funcs->get_pp_num_states)
 321                 amdgpu_dpm_get_pp_num_states(adev, &data);
 322
 323         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 324         for (i = 0; i < data.nums; i++)
 325                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 326                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 327                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 328                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 329                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 330
 331         return buf_len;
 332 }
 333
 334 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 335                 struct device_attribute *attr,
 336                 char *buf)
 337 {
 338         struct drm_device *ddev = dev_get_drvdata(dev);
 339         struct amdgpu_device *adev = ddev->dev_private;
 340         struct pp_states_info data;
 341         enum amd_pm_state_type pm = 0;
 342         int i = 0;
 343
 344         if (adev->powerplay.pp_funcs->get_current_power_state
 345                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 346                 pm = amdgpu_dpm_get_current_power_state(adev);
 347                 amdgpu_dpm_get_pp_num_states(adev, &data);
 348
 349                 for (i = 0; i < data.nums; i++) {
 350                         if (pm == data.states[i])
 351                                 break;
 352                 }
 353
 354                 if (i == data.nums)
 355                         i = -EINVAL;
 356         }
 357
 358         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 359 }
 360
 361 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 362                 struct device_attribute *attr,
 363                 char *buf)
 364 {
 365         struct drm_device *ddev = dev_get_drvdata(dev);
 366         struct amdgpu_device *adev = ddev->dev_private;
 367
 368         if (adev->pp_force_state_enabled)
 369                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 370         else
 371                 return snprintf(buf, PAGE_SIZE, "\n");
 372 }
 373
 374 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 375                 struct device_attribute *attr,
 376                 const char *buf,
 377                 size_t count)
 378 {
 379         struct drm_device *ddev = dev_get_drvdata(dev);
 380         struct amdgpu_device *adev = ddev->dev_private;
 381         enum amd_pm_state_type state = 0;
 382         unsigned long idx;
 383         int ret;
 384
 385         if (strlen(buf) == 1)
 386                 adev->pp_force_state_enabled = false;
 387         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 388                         adev->powerplay.pp_funcs->get_pp_num_states) {
 389                 struct pp_states_info data;
 390
 391                 ret = kstrtoul(buf, 0, &idx);
 392                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 393                         count = -EINVAL;
 394                         goto fail;
 395                 }
 396
 397                 amdgpu_dpm_get_pp_num_states(adev, &data);
 398                 state = data.states[idx];
 399                 /* only set user selected power states */
 400                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 401                     state != POWER_STATE_TYPE_DEFAULT) {
 402                         amdgpu_dpm_dispatch_task(adev,
 403                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 404                         adev->pp_force_state_enabled = true;
 405                 }
 406         }
 407 fail:
 408         return count;
 409 }
 410
 411 /**
 412  * DOC: pp_table
 413  *
 414  * The amdgpu driver provides a sysfs API for uploading new powerplay
 415  * tables.  The file pp_table is used for this.  Reading the file
 416  * will dump the current power play table.  Writing to the file
 417  * will attempt to upload a new powerplay table and re-initialize
 418  * powerplay using that new table.
 419  *
 420  */
 421
 422 static ssize_t amdgpu_get_pp_table(struct device *dev,
 423                 struct device_attribute *attr,
 424                 char *buf)
 425 {
 426         struct drm_device *ddev = dev_get_drvdata(dev);
 427         struct amdgpu_device *adev = ddev->dev_private;
 428         char *table = NULL;
 429         int size;
 430
 431         if (adev->powerplay.pp_funcs->get_pp_table)
 432                 size = amdgpu_dpm_get_pp_table(adev, &table);
 433         else
 434                 return 0;
 435
 436         if (size >= PAGE_SIZE)
 437                 size = PAGE_SIZE - 1;
 438
 439         memcpy(buf, table, size);
 440
 441         return size;
 442 }
 443
 444 static ssize_t amdgpu_set_pp_table(struct device *dev,
 445                 struct device_attribute *attr,
 446                 const char *buf,
 447                 size_t count)
 448 {
 449         struct drm_device *ddev = dev_get_drvdata(dev);
 450         struct amdgpu_device *adev = ddev->dev_private;
 451
 452         if (adev->powerplay.pp_funcs->set_pp_table)
 453                 amdgpu_dpm_set_pp_table(adev, buf, count);
 454
 455         return count;
 456 }
 457
 458 /**
 459  * DOC: pp_od_clk_voltage
 460  *
 461  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 462  * in each power level within a power state.  The pp_od_clk_voltage is used for
 463  * this.
 464  *
 465  * Reading the file will display:
 466  * - a list of engine clock levels and voltages labeled OD_SCLK
 467  * - a list of memory clock levels and voltages labeled OD_MCLK
 468  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 469  *
 470  * To manually adjust these settings, first select manual using
 471  * power_dpm_force_performance_level. Enter a new value for each
 472  * level by writing a string that contains "s/m level clock voltage" to
 473  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 474  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 475  * 810 mV.  When you have edited all of the states as needed, write
 476  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 477  * default power levels, write "r" (reset) to the file to reset them.
 478  *
 479  */
 480
 481 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 482                 struct device_attribute *attr,
 483                 const char *buf,
 484                 size_t count)
 485 {
 486         struct drm_device *ddev = dev_get_drvdata(dev);
 487         struct amdgpu_device *adev = ddev->dev_private;
 488         int ret;
 489         uint32_t parameter_size = 0;
 490         long parameter[64];
 491         char buf_cpy[128];
 492         char *tmp_str;
 493         char *sub_str;
 494         const char delimiter[3] = {' ', '\n', '\0'};
 495         uint32_t type;
 496
 497         if (count > 127)
 498                 return -EINVAL;
 499
 500         if (*buf == 's')
 501                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 502         else if (*buf == 'm')
 503                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 504         else if(*buf == 'r')
 505                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 506         else if (*buf == 'c')
 507                 type = PP_OD_COMMIT_DPM_TABLE;
 508         else
 509                 return -EINVAL;
 510
 511         memcpy(buf_cpy, buf, count+1);
 512
 513         tmp_str = buf_cpy;
 514
 515         while (isspace(*++tmp_str));
 516
 517         while (tmp_str[0]) {
 518                 sub_str = strsep(&tmp_str, delimiter);
 519                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 520                 if (ret)
 521                         return -EINVAL;
 522                 parameter_size++;
 523
 524                 while (isspace(*tmp_str))
 525                         tmp_str++;
 526         }
 527
 528         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 529                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 530                                                 parameter, parameter_size);
 531
 532         if (ret)
 533                 return -EINVAL;
 534
 535         if (type == PP_OD_COMMIT_DPM_TABLE) {
 536                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 537                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 538                         return count;
 539                 } else {
 540                         return -EINVAL;
 541                 }
 542         }
 543
 544         return count;
 545 }
 546
 547 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 548                 struct device_attribute *attr,
 549                 char *buf)
 550 {
 551         struct drm_device *ddev = dev_get_drvdata(dev);
 552         struct amdgpu_device *adev = ddev->dev_private;
 553         uint32_t size = 0;
 554
 555         if (adev->powerplay.pp_funcs->print_clock_levels) {
 556                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 557                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 558                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 559                 return size;
 560         } else {
 561                 return snprintf(buf, PAGE_SIZE, "\n");
 562         }
 563
 564 }
 565
 566 /**
 567  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 568  *
 569  * The amdgpu driver provides a sysfs API for adjusting what power levels
 570  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 571  * and pp_dpm_pcie are used for this.
 572  *
 573  * Reading back the files will show you the available power levels within
 574  * the power state and the clock information for those levels.
 575  *
 576  * To manually adjust these states, first select manual using
 577  * power_dpm_force_performance_level.
 578  * Secondly,Enter a new value for each level by inputing a string that
 579  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 580  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 581  */
 582
 583 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 584                 struct device_attribute *attr,
 585                 char *buf)
 586 {
 587         struct drm_device *ddev = dev_get_drvdata(dev);
 588         struct amdgpu_device *adev = ddev->dev_private;
 589
 590         if (adev->powerplay.pp_funcs->print_clock_levels)
 591                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 592         else
 593                 return snprintf(buf, PAGE_SIZE, "\n");
 594 }
 595
 596 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 597                 struct device_attribute *attr,
 598                 const char *buf,
 599                 size_t count)
 600 {
 601         struct drm_device *ddev = dev_get_drvdata(dev);
 602         struct amdgpu_device *adev = ddev->dev_private;
 603         int ret;
 604         long level;
 605         uint32_t mask = 0;
 606         char *sub_str = NULL;
 607         char *tmp;
 608         char buf_cpy[count];
 609         const char delimiter[3] = {' ', '\n', '\0'};
 610
 611         memcpy(buf_cpy, buf, count+1);
 612         tmp = buf_cpy;
 613         while (tmp[0]) {
 614                 sub_str =  strsep(&tmp, delimiter);
 615                 if (strlen(sub_str)) {
 616                         ret = kstrtol(sub_str, 0, &level);
 617
 618                         if (ret) {
 619                                 count = -EINVAL;
 620                                 goto fail;
 621                         }
 622                         mask |= 1 << level;
 623                 } else
 624                         break;
 625         }
 626         if (adev->powerplay.pp_funcs->force_clock_level)
 627                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 628
 629 fail:
 630         return count;
 631 }
 632
 633 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 634                 struct device_attribute *attr,
 635                 char *buf)
 636 {
 637         struct drm_device *ddev = dev_get_drvdata(dev);
 638         struct amdgpu_device *adev = ddev->dev_private;
 639
 640         if (adev->powerplay.pp_funcs->print_clock_levels)
 641                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 642         else
 643                 return snprintf(buf, PAGE_SIZE, "\n");
 644 }
 645
 646 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 647                 struct device_attribute *attr,
 648                 const char *buf,
 649                 size_t count)
 650 {
 651         struct drm_device *ddev = dev_get_drvdata(dev);
 652         struct amdgpu_device *adev = ddev->dev_private;
 653         int ret;
 654         long level;
 655         uint32_t mask = 0;
 656         char *sub_str = NULL;
 657         char *tmp;
 658         char buf_cpy[count];
 659         const char delimiter[3] = {' ', '\n', '\0'};
 660
 661         memcpy(buf_cpy, buf, count+1);
 662         tmp = buf_cpy;
 663         while (tmp[0]) {
 664                 sub_str =  strsep(&tmp, delimiter);
 665                 if (strlen(sub_str)) {
 666                         ret = kstrtol(sub_str, 0, &level);
 667
 668                         if (ret) {
 669                                 count = -EINVAL;
 670                                 goto fail;
 671                         }
 672                         mask |= 1 << level;
 673                 } else
 674                         break;
 675         }
 676         if (adev->powerplay.pp_funcs->force_clock_level)
 677                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 678
 679 fail:
 680         return count;
 681 }
 682
 683 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 684                 struct device_attribute *attr,
 685                 char *buf)
 686 {
 687         struct drm_device *ddev = dev_get_drvdata(dev);
 688         struct amdgpu_device *adev = ddev->dev_private;
 689
 690         if (adev->powerplay.pp_funcs->print_clock_levels)
 691                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 692         else
 693                 return snprintf(buf, PAGE_SIZE, "\n");
 694 }
 695
 696 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 697                 struct device_attribute *attr,
 698                 const char *buf,
 699                 size_t count)
 700 {
 701         struct drm_device *ddev = dev_get_drvdata(dev);
 702         struct amdgpu_device *adev = ddev->dev_private;
 703         int ret;
 704         long level;
 705         uint32_t mask = 0;
 706         char *sub_str = NULL;
 707         char *tmp;
 708         char buf_cpy[count];
 709         const char delimiter[3] = {' ', '\n', '\0'};
 710
 711         memcpy(buf_cpy, buf, count+1);
 712         tmp = buf_cpy;
 713
 714         while (tmp[0]) {
 715                 sub_str =  strsep(&tmp, delimiter);
 716                 if (strlen(sub_str)) {
 717                         ret = kstrtol(sub_str, 0, &level);
 718
 719                         if (ret) {
 720                                 count = -EINVAL;
 721                                 goto fail;
 722                         }
 723                         mask |= 1 << level;
 724                 } else
 725                         break;
 726         }
 727         if (adev->powerplay.pp_funcs->force_clock_level)
 728                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 729
 730 fail:
 731         return count;
 732 }
 733
 734 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 735                 struct device_attribute *attr,
 736                 char *buf)
 737 {
 738         struct drm_device *ddev = dev_get_drvdata(dev);
 739         struct amdgpu_device *adev = ddev->dev_private;
 740         uint32_t value = 0;
 741
 742         if (adev->powerplay.pp_funcs->get_sclk_od)
 743                 value = amdgpu_dpm_get_sclk_od(adev);
 744
 745         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 746 }
 747
 748 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 749                 struct device_attribute *attr,
 750                 const char *buf,
 751                 size_t count)
 752 {
 753         struct drm_device *ddev = dev_get_drvdata(dev);
 754         struct amdgpu_device *adev = ddev->dev_private;
 755         int ret;
 756         long int value;
 757
 758         ret = kstrtol(buf, 0, &value);
 759
 760         if (ret) {
 761                 count = -EINVAL;
 762                 goto fail;
 763         }
 764         if (adev->powerplay.pp_funcs->set_sclk_od)
 765                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 766
 767         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 768                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 769         } else {
 770                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 771                 amdgpu_pm_compute_clocks(adev);
 772         }
 773
 774 fail:
 775         return count;
 776 }
 777
 778 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 779                 struct device_attribute *attr,
 780                 char *buf)
 781 {
 782         struct drm_device *ddev = dev_get_drvdata(dev);
 783         struct amdgpu_device *adev = ddev->dev_private;
 784         uint32_t value = 0;
 785
 786         if (adev->powerplay.pp_funcs->get_mclk_od)
 787                 value = amdgpu_dpm_get_mclk_od(adev);
 788
 789         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 790 }
 791
 792 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 793                 struct device_attribute *attr,
 794                 const char *buf,
 795                 size_t count)
 796 {
 797         struct drm_device *ddev = dev_get_drvdata(dev);
 798         struct amdgpu_device *adev = ddev->dev_private;
 799         int ret;
 800         long int value;
 801
 802         ret = kstrtol(buf, 0, &value);
 803
 804         if (ret) {
 805                 count = -EINVAL;
 806                 goto fail;
 807         }
 808         if (adev->powerplay.pp_funcs->set_mclk_od)
 809                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 810
 811         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 812                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 813         } else {
 814                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 815                 amdgpu_pm_compute_clocks(adev);
 816         }
 817
 818 fail:
 819         return count;
 820 }
 821
 822 /**
 823  * DOC: pp_power_profile_mode
 824  *
 825  * The amdgpu driver provides a sysfs API for adjusting the heuristics
 826  * related to switching between power levels in a power state.  The file
 827  * pp_power_profile_mode is used for this.
 828  *
 829  * Reading this file outputs a list of all of the predefined power profiles
 830  * and the relevant heuristics settings for that profile.
 831  *
 832  * To select a profile or create a custom profile, first select manual using
 833  * power_dpm_force_performance_level.  Writing the number of a predefined
 834  * profile to pp_power_profile_mode will enable those heuristics.  To
 835  * create a custom set of heuristics, write a string of numbers to the file
 836  * starting with the number of the custom profile along with a setting
 837  * for each heuristic parameter.  Due to differences across asic families
 838  * the heuristic parameters vary from family to family.
 839  *
 840  */
 841
 842 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 843                 struct device_attribute *attr,
 844                 char *buf)
 845 {
 846         struct drm_device *ddev = dev_get_drvdata(dev);
 847         struct amdgpu_device *adev = ddev->dev_private;
 848
 849         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 850                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 851
 852         return snprintf(buf, PAGE_SIZE, "\n");
 853 }
 854
 855
 856 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 857                 struct device_attribute *attr,
 858                 const char *buf,
 859                 size_t count)
 860 {
 861         int ret = 0xff;
 862         struct drm_device *ddev = dev_get_drvdata(dev);
 863         struct amdgpu_device *adev = ddev->dev_private;
 864         uint32_t parameter_size = 0;
 865         long parameter[64];
 866         char *sub_str, buf_cpy[128];
 867         char *tmp_str;
 868         uint32_t i = 0;
 869         char tmp[2];
 870         long int profile_mode = 0;
 871         const char delimiter[3] = {' ', '\n', '\0'};
 872
 873         tmp[0] = *(buf);
 874         tmp[1] = '\0';
 875         ret = kstrtol(tmp, 0, &profile_mode);
 876         if (ret)
 877                 goto fail;
 878
 879         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 880                 if (count < 2 || count > 127)
 881                         return -EINVAL;
 882                 while (isspace(*++buf))
 883                         i++;
 884                 memcpy(buf_cpy, buf, count-i);
 885                 tmp_str = buf_cpy;
 886                 while (tmp_str[0]) {
 887                         sub_str = strsep(&tmp_str, delimiter);
 888                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 889                         if (ret) {
 890                                 count = -EINVAL;
 891                                 goto fail;
 892                         }
 893                         parameter_size++;
 894                         while (isspace(*tmp_str))
 895                                 tmp_str++;
 896                 }
 897         }
 898         parameter[parameter_size] = profile_mode;
 899         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 900                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 901
 902         if (!ret)
 903                 return count;
 904 fail:
 905         return -EINVAL;
 906 }
 907
 908 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 909 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 910                    amdgpu_get_dpm_forced_performance_level,
 911                    amdgpu_set_dpm_forced_performance_level);
 912 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 913 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 914 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 915                 amdgpu_get_pp_force_state,
 916                 amdgpu_set_pp_force_state);
 917 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 918                 amdgpu_get_pp_table,
 919                 amdgpu_set_pp_table);
 920 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 921                 amdgpu_get_pp_dpm_sclk,
 922                 amdgpu_set_pp_dpm_sclk);
 923 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 924                 amdgpu_get_pp_dpm_mclk,
 925                 amdgpu_set_pp_dpm_mclk);
 926 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 927                 amdgpu_get_pp_dpm_pcie,
 928                 amdgpu_set_pp_dpm_pcie);
 929 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 930                 amdgpu_get_pp_sclk_od,
 931                 amdgpu_set_pp_sclk_od);
 932 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 933                 amdgpu_get_pp_mclk_od,
 934                 amdgpu_set_pp_mclk_od);
 935 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 936                 amdgpu_get_pp_power_profile_mode,
 937                 amdgpu_set_pp_power_profile_mode);
 938 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 939                 amdgpu_get_pp_od_clk_voltage,
 940                 amdgpu_set_pp_od_clk_voltage);
 941
 942 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 943                                       struct device_attribute *attr,
 944                                       char *buf)
 945 {
 946         struct amdgpu_device *adev = dev_get_drvdata(dev);
 947         struct drm_device *ddev = adev->ddev;
 948         int r, temp, size = sizeof(temp);
 949
 950         /* Can't get temperature when the card is off */
 951         if  ((adev->flags & AMD_IS_PX) &&
 952              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 953                 return -EINVAL;
 954
 955         /* sanity check PP is enabled */
 956         if (!(adev->powerplay.pp_funcs &&
 957               adev->powerplay.pp_funcs->read_sensor))
 958                 return -EINVAL;
 959
 960         /* get the temperature */
 961         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 962                                    (void *)&temp, &size);
 963         if (r)
 964                 return r;
 965
 966         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 967 }
 968
 969 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 970                                              struct device_attribute *attr,
 971                                              char *buf)
 972 {
 973         struct amdgpu_device *adev = dev_get_drvdata(dev);
 974         int hyst = to_sensor_dev_attr(attr)->index;
 975         int temp;
 976
 977         if (hyst)
 978                 temp = adev->pm.dpm.thermal.min_temp;
 979         else
 980                 temp = adev->pm.dpm.thermal.max_temp;
 981
 982         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 983 }
 984
 985 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 986                                             struct device_attribute *attr,
 987                                             char *buf)
 988 {
 989         struct amdgpu_device *adev = dev_get_drvdata(dev);
 990         u32 pwm_mode = 0;
 991
 992         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 993                 return -EINVAL;
 994
 995         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 996
 997         return sprintf(buf, "%i\n", pwm_mode);
 998 }
 999
1000 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1001                                             struct device_attribute *attr,
1002                                             const char *buf,
1003                                             size_t count)
1004 {
1005         struct amdgpu_device *adev = dev_get_drvdata(dev);
1006         int err;
1007         int value;
1008
1009         /* Can't adjust fan when the card is off */
1010         if  ((adev->flags & AMD_IS_PX) &&
1011              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1012                 return -EINVAL;
1013
1014         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1015                 return -EINVAL;
1016
1017         err = kstrtoint(buf, 10, &value);
1018         if (err)
1019                 return err;
1020
1021         amdgpu_dpm_set_fan_control_mode(adev, value);
1022
1023         return count;
1024 }
1025
1026 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1027                                          struct device_attribute *attr,
1028                                          char *buf)
1029 {
1030         return sprintf(buf, "%i\n", 0);
1031 }
1032
1033 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1034                                          struct device_attribute *attr,
1035                                          char *buf)
1036 {
1037         return sprintf(buf, "%i\n", 255);
1038 }
1039
1040 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1041                                      struct device_attribute *attr,
1042                                      const char *buf, size_t count)
1043 {
1044         struct amdgpu_device *adev = dev_get_drvdata(dev);
1045         int err;
1046         u32 value;
1047
1048         /* Can't adjust fan when the card is off */
1049         if  ((adev->flags & AMD_IS_PX) &&
1050              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1051                 return -EINVAL;
1052
1053         err = kstrtou32(buf, 10, &value);
1054         if (err)
1055                 return err;
1056
1057         value = (value * 100) / 255;
1058
1059         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1060                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1061                 if (err)
1062                         return err;
1063         }
1064
1065         return count;
1066 }
1067
1068 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1069                                      struct device_attribute *attr,
1070                                      char *buf)
1071 {
1072         struct amdgpu_device *adev = dev_get_drvdata(dev);
1073         int err;
1074         u32 speed = 0;
1075
1076         /* Can't adjust fan when the card is off */
1077         if  ((adev->flags & AMD_IS_PX) &&
1078              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1079                 return -EINVAL;
1080
1081         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1082                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1083                 if (err)
1084                         return err;
1085         }
1086
1087         speed = (speed * 255) / 100;
1088
1089         return sprintf(buf, "%i\n", speed);
1090 }
1091
1092 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1093                                            struct device_attribute *attr,
1094                                            char *buf)
1095 {
1096         struct amdgpu_device *adev = dev_get_drvdata(dev);
1097         int err;
1098         u32 speed = 0;
1099
1100         /* Can't adjust fan when the card is off */
1101         if  ((adev->flags & AMD_IS_PX) &&
1102              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1103                 return -EINVAL;
1104
1105         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1106                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1107                 if (err)
1108                         return err;
1109         }
1110
1111         return sprintf(buf, "%i\n", speed);
1112 }
1113
1114 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1115                                         struct device_attribute *attr,
1116                                         char *buf)
1117 {
1118         struct amdgpu_device *adev = dev_get_drvdata(dev);
1119         struct drm_device *ddev = adev->ddev;
1120         u32 vddgfx;
1121         int r, size = sizeof(vddgfx);
1122
1123         /* Can't get voltage when the card is off */
1124         if  ((adev->flags & AMD_IS_PX) &&
1125              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1126                 return -EINVAL;
1127
1128         /* sanity check PP is enabled */
1129         if (!(adev->powerplay.pp_funcs &&
1130               adev->powerplay.pp_funcs->read_sensor))
1131               return -EINVAL;
1132
1133         /* get the voltage */
1134         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1135                                    (void *)&vddgfx, &size);
1136         if (r)
1137                 return r;
1138
1139         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1140 }
1141
1142 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1143                                               struct device_attribute *attr,
1144                                               char *buf)
1145 {
1146         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1147 }
1148
1149 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1150                                        struct device_attribute *attr,
1151                                        char *buf)
1152 {
1153         struct amdgpu_device *adev = dev_get_drvdata(dev);
1154         struct drm_device *ddev = adev->ddev;
1155         u32 vddnb;
1156         int r, size = sizeof(vddnb);
1157
1158         /* only APUs have vddnb */
1159         if  (adev->flags & AMD_IS_APU)
1160                 return -EINVAL;
1161
1162         /* Can't get voltage when the card is off */
1163         if  ((adev->flags & AMD_IS_PX) &&
1164              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1165                 return -EINVAL;
1166
1167         /* sanity check PP is enabled */
1168         if (!(adev->powerplay.pp_funcs &&
1169               adev->powerplay.pp_funcs->read_sensor))
1170               return -EINVAL;
1171
1172         /* get the voltage */
1173         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1174                                    (void *)&vddnb, &size);
1175         if (r)
1176                 return r;
1177
1178         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1179 }
1180
1181 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1182                                               struct device_attribute *attr,
1183                                               char *buf)
1184 {
1185         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1186 }
1187
1188 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1189                                            struct device_attribute *attr,
1190                                            char *buf)
1191 {
1192         struct amdgpu_device *adev = dev_get_drvdata(dev);
1193         struct drm_device *ddev = adev->ddev;
1194         u32 query = 0;
1195         int r, size = sizeof(u32);
1196         unsigned uw;
1197
1198         /* Can't get power when the card is off */
1199         if  ((adev->flags & AMD_IS_PX) &&
1200              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1201                 return -EINVAL;
1202
1203         /* sanity check PP is enabled */
1204         if (!(adev->powerplay.pp_funcs &&
1205               adev->powerplay.pp_funcs->read_sensor))
1206               return -EINVAL;
1207
1208         /* get the voltage */
1209         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1210                                    (void *)&query, &size);
1211         if (r)
1212                 return r;
1213
1214         /* convert to microwatts */
1215         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1216
1217         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1218 }
1219
1220 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1221                                          struct device_attribute *attr,
1222                                          char *buf)
1223 {
1224         return sprintf(buf, "%i\n", 0);
1225 }
1226
1227 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1228                                          struct device_attribute *attr,
1229                                          char *buf)
1230 {
1231         struct amdgpu_device *adev = dev_get_drvdata(dev);
1232         uint32_t limit = 0;
1233
1234         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1235                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1236                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1237         } else {
1238                 return snprintf(buf, PAGE_SIZE, "\n");
1239         }
1240 }
1241
1242 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1243                                          struct device_attribute *attr,
1244                                          char *buf)
1245 {
1246         struct amdgpu_device *adev = dev_get_drvdata(dev);
1247         uint32_t limit = 0;
1248
1249         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1250                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1251                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1252         } else {
1253                 return snprintf(buf, PAGE_SIZE, "\n");
1254         }
1255 }
1256
1257
1258 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1259                 struct device_attribute *attr,
1260                 const char *buf,
1261                 size_t count)
1262 {
1263         struct amdgpu_device *adev = dev_get_drvdata(dev);
1264         int err;
1265         u32 value;
1266
1267         err = kstrtou32(buf, 10, &value);
1268         if (err)
1269                 return err;
1270
1271         value = value / 1000000; /* convert to Watt */
1272         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1273                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1274                 if (err)
1275                         return err;
1276         } else {
1277                 return -EINVAL;
1278         }
1279
1280         return count;
1281 }
1282
1283
1284 /**
1285  * DOC: hwmon
1286  *
1287  * The amdgpu driver exposes the following sensor interfaces:
1288  * - GPU temperature (via the on-die sensor)
1289  * - GPU voltage
1290  * - Northbridge voltage (APUs only)
1291  * - GPU power
1292  * - GPU fan
1293  *
1294  * hwmon interfaces for GPU temperature:
1295  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1296  * - temp1_crit: temperature critical max value in millidegrees Celsius
1297  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1298  *
1299  * hwmon interfaces for GPU voltage:
1300  * - in0_input: the voltage on the GPU in millivolts
1301  * - in1_input: the voltage on the Northbridge in millivolts
1302  *
1303  * hwmon interfaces for GPU power:
1304  * - power1_average: average power used by the GPU in microWatts
1305  * - power1_cap_min: minimum cap supported in microWatts
1306  * - power1_cap_max: maximum cap supported in microWatts
1307  * - power1_cap: selected power cap in microWatts
1308  *
1309  * hwmon interfaces for GPU fan:
1310  * - pwm1: pulse width modulation fan level (0-255)
1311  * - pwm1_enable: pulse width modulation fan control method
1312  *                0: no fan speed control
1313  *                1: manual fan speed control using pwm interface
1314  *                2: automatic fan speed control
1315  * - pwm1_min: pulse width modulation fan control minimum level (0)
1316  * - pwm1_max: pulse width modulation fan control maximum level (255)
1317  * - fan1_input: fan speed in RPM
1318  *
1319  * You can use hwmon tools like sensors to view this information on your system.
1320  *
1321  */
1322
1323 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1324 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1325 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1326 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1327 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1328 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1329 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1330 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1331 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1332 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1333 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1334 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1335 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1336 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1337 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1338 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1339
1340 static struct attribute *hwmon_attributes[] = {
1341         &sensor_dev_attr_temp1_input.dev_attr.attr,
1342         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1343         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1344         &sensor_dev_attr_pwm1.dev_attr.attr,
1345         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1346         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1347         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1348         &sensor_dev_attr_fan1_input.dev_attr.attr,
1349         &sensor_dev_attr_in0_input.dev_attr.attr,
1350         &sensor_dev_attr_in0_label.dev_attr.attr,
1351         &sensor_dev_attr_in1_input.dev_attr.attr,
1352         &sensor_dev_attr_in1_label.dev_attr.attr,
1353         &sensor_dev_attr_power1_average.dev_attr.attr,
1354         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1355         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1356         &sensor_dev_attr_power1_cap.dev_attr.attr,
1357         NULL
1358 };
1359
1360 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1361                                         struct attribute *attr, int index)
1362 {
1363         struct device *dev = kobj_to_dev(kobj);
1364         struct amdgpu_device *adev = dev_get_drvdata(dev);
1365         umode_t effective_mode = attr->mode;
1366
1367
1368         /* Skip fan attributes if fan is not present */
1369         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1370             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1371             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1372             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1373             attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
1374                 return 0;
1375
1376         /* Skip limit attributes if DPM is not enabled */
1377         if (!adev->pm.dpm_enabled &&
1378             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1379              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1380              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1381              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1382              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1383              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1384                 return 0;
1385
1386         /* mask fan attributes if we have no bindings for this asic to expose */
1387         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1388              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1389             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1390              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1391                 effective_mode &= ~S_IRUGO;
1392
1393         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1394              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1395             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1396              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1397                 effective_mode &= ~S_IWUSR;
1398
1399         if ((adev->flags & AMD_IS_APU) &&
1400             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1401              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1402              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1403                 return 0;
1404
1405         /* hide max/min values if we can't both query and manage the fan */
1406         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1407              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1408             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1409              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1410                 return 0;
1411
1412         /* only APUs have vddnb */
1413         if (!(adev->flags & AMD_IS_APU) &&
1414             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1415              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1416                 return 0;
1417
1418         return effective_mode;
1419 }
1420
1421 static const struct attribute_group hwmon_attrgroup = {
1422         .attrs = hwmon_attributes,
1423         .is_visible = hwmon_attributes_visible,
1424 };
1425
1426 static const struct attribute_group *hwmon_groups[] = {
1427         &hwmon_attrgroup,
1428         NULL
1429 };
1430
1431 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1432 {
1433         struct amdgpu_device *adev =
1434                 container_of(work, struct amdgpu_device,
1435                              pm.dpm.thermal.work);
1436         /* switch to the thermal state */
1437         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1438         int temp, size = sizeof(temp);
1439
1440         if (!adev->pm.dpm_enabled)
1441                 return;
1442
1443         if (adev->powerplay.pp_funcs &&
1444             adev->powerplay.pp_funcs->read_sensor &&
1445             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1446                                     (void *)&temp, &size)) {
1447                 if (temp < adev->pm.dpm.thermal.min_temp)
1448                         /* switch back the user state */
1449                         dpm_state = adev->pm.dpm.user_state;
1450         } else {
1451                 if (adev->pm.dpm.thermal.high_to_low)
1452                         /* switch back the user state */
1453                         dpm_state = adev->pm.dpm.user_state;
1454         }
1455         mutex_lock(&adev->pm.mutex);
1456         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1457                 adev->pm.dpm.thermal_active = true;
1458         else
1459                 adev->pm.dpm.thermal_active = false;
1460         adev->pm.dpm.state = dpm_state;
1461         mutex_unlock(&adev->pm.mutex);
1462
1463         amdgpu_pm_compute_clocks(adev);
1464 }
1465
1466 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1467                                                      enum amd_pm_state_type dpm_state)
1468 {
1469         int i;
1470         struct amdgpu_ps *ps;
1471         u32 ui_class;
1472         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1473                 true : false;
1474
1475         /* check if the vblank period is too short to adjust the mclk */
1476         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1477                 if (amdgpu_dpm_vblank_too_short(adev))
1478                         single_display = false;
1479         }
1480
1481         /* certain older asics have a separare 3D performance state,
1482          * so try that first if the user selected performance
1483          */
1484         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1485                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1486         /* balanced states don't exist at the moment */
1487         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1488                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1489
1490 restart_search:
1491         /* Pick the best power state based on current conditions */
1492         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1493                 ps = &adev->pm.dpm.ps[i];
1494                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1495                 switch (dpm_state) {
1496                 /* user states */
1497                 case POWER_STATE_TYPE_BATTERY:
1498                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1499                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1500                                         if (single_display)
1501                                                 return ps;
1502                                 } else
1503                                         return ps;
1504                         }
1505                         break;
1506                 case POWER_STATE_TYPE_BALANCED:
1507                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1508                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1509                                         if (single_display)
1510                                                 return ps;
1511                                 } else
1512                                         return ps;
1513                         }
1514                         break;
1515                 case POWER_STATE_TYPE_PERFORMANCE:
1516                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1517                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1518                                         if (single_display)
1519                                                 return ps;
1520                                 } else
1521                                         return ps;
1522                         }
1523                         break;
1524                 /* internal states */
1525                 case POWER_STATE_TYPE_INTERNAL_UVD:
1526                         if (adev->pm.dpm.uvd_ps)
1527                                 return adev->pm.dpm.uvd_ps;
1528                         else
1529                                 break;
1530                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1531                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1532                                 return ps;
1533                         break;
1534                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1535                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1536                                 return ps;
1537                         break;
1538                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1539                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1540                                 return ps;
1541                         break;
1542                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1543                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1544                                 return ps;
1545                         break;
1546                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1547                         return adev->pm.dpm.boot_ps;
1548                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1549                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1550                                 return ps;
1551                         break;
1552                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1553                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1554                                 return ps;
1555                         break;
1556                 case POWER_STATE_TYPE_INTERNAL_ULV:
1557                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1558                                 return ps;
1559                         break;
1560                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1561                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1562                                 return ps;
1563                         break;
1564                 default:
1565                         break;
1566                 }
1567         }
1568         /* use a fallback state if we didn't match */
1569         switch (dpm_state) {
1570         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1571                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1572                 goto restart_search;
1573         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1574         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1575         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1576                 if (adev->pm.dpm.uvd_ps) {
1577                         return adev->pm.dpm.uvd_ps;
1578                 } else {
1579                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1580                         goto restart_search;
1581                 }
1582         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1583                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1584                 goto restart_search;
1585         case POWER_STATE_TYPE_INTERNAL_ACPI:
1586                 dpm_state = POWER_STATE_TYPE_BATTERY;
1587                 goto restart_search;
1588         case POWER_STATE_TYPE_BATTERY:
1589         case POWER_STATE_TYPE_BALANCED:
1590         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1591                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1592                 goto restart_search;
1593         default:
1594                 break;
1595         }
1596
1597         return NULL;
1598 }
1599
1600 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1601 {
1602         struct amdgpu_ps *ps;
1603         enum amd_pm_state_type dpm_state;
1604         int ret;
1605         bool equal = false;
1606
1607         /* if dpm init failed */
1608         if (!adev->pm.dpm_enabled)
1609                 return;
1610
1611         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1612                 /* add other state override checks here */
1613                 if ((!adev->pm.dpm.thermal_active) &&
1614                     (!adev->pm.dpm.uvd_active))
1615                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1616         }
1617         dpm_state = adev->pm.dpm.state;
1618
1619         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1620         if (ps)
1621                 adev->pm.dpm.requested_ps = ps;
1622         else
1623                 return;
1624
1625         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1626                 printk("switching from power state:\n");
1627                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1628                 printk("switching to power state:\n");
1629                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1630         }
1631
1632         /* update whether vce is active */
1633         ps->vce_active = adev->pm.dpm.vce_active;
1634         if (adev->powerplay.pp_funcs->display_configuration_changed)
1635                 amdgpu_dpm_display_configuration_changed(adev);
1636
1637         ret = amdgpu_dpm_pre_set_power_state(adev);
1638         if (ret)
1639                 return;
1640
1641         if (adev->powerplay.pp_funcs->check_state_equal) {
1642                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1643                         equal = false;
1644         }
1645
1646         if (equal)
1647                 return;
1648
1649         amdgpu_dpm_set_power_state(adev);
1650         amdgpu_dpm_post_set_power_state(adev);
1651
1652         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1653         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1654
1655         if (adev->powerplay.pp_funcs->force_performance_level) {
1656                 if (adev->pm.dpm.thermal_active) {
1657                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1658                         /* force low perf level for thermal */
1659                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1660                         /* save the user's level */
1661                         adev->pm.dpm.forced_level = level;
1662                 } else {
1663                         /* otherwise, user selected level */
1664                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1665                 }
1666         }
1667 }
1668
1669 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1670 {
1671         if (adev->powerplay.pp_funcs->powergate_uvd) {
1672                 /* enable/disable UVD */
1673                 mutex_lock(&adev->pm.mutex);
1674                 amdgpu_dpm_powergate_uvd(adev, !enable);
1675                 mutex_unlock(&adev->pm.mutex);
1676         } else {
1677                 if (enable) {
1678                         mutex_lock(&adev->pm.mutex);
1679                         adev->pm.dpm.uvd_active = true;
1680                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1681                         mutex_unlock(&adev->pm.mutex);
1682                 } else {
1683                         mutex_lock(&adev->pm.mutex);
1684                         adev->pm.dpm.uvd_active = false;
1685                         mutex_unlock(&adev->pm.mutex);
1686                 }
1687                 amdgpu_pm_compute_clocks(adev);
1688         }
1689 }
1690
1691 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1692 {
1693         if (adev->powerplay.pp_funcs->powergate_vce) {
1694                 /* enable/disable VCE */
1695                 mutex_lock(&adev->pm.mutex);
1696                 amdgpu_dpm_powergate_vce(adev, !enable);
1697                 mutex_unlock(&adev->pm.mutex);
1698         } else {
1699                 if (enable) {
1700                         mutex_lock(&adev->pm.mutex);
1701                         adev->pm.dpm.vce_active = true;
1702                         /* XXX select vce level based on ring/task */
1703                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1704                         mutex_unlock(&adev->pm.mutex);
1705                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1706                                                                AMD_CG_STATE_UNGATE);
1707                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1708                                                                AMD_PG_STATE_UNGATE);
1709                         amdgpu_pm_compute_clocks(adev);
1710                 } else {
1711                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1712                                                                AMD_PG_STATE_GATE);
1713                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1714                                                                AMD_CG_STATE_GATE);
1715                         mutex_lock(&adev->pm.mutex);
1716                         adev->pm.dpm.vce_active = false;
1717                         mutex_unlock(&adev->pm.mutex);
1718                         amdgpu_pm_compute_clocks(adev);
1719                 }
1720
1721         }
1722 }
1723
1724 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1725 {
1726         int i;
1727
1728         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1729                 return;
1730
1731         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1732                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1733
1734 }
1735
1736 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1737 {
1738         int ret;
1739
1740         if (adev->pm.sysfs_initialized)
1741                 return 0;
1742
1743         if (adev->pm.dpm_enabled == 0)
1744                 return 0;
1745
1746         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1747                                                                    DRIVER_NAME, adev,
1748                                                                    hwmon_groups);
1749         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1750                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1751                 dev_err(adev->dev,
1752                         "Unable to register hwmon device: %d\n", ret);
1753                 return ret;
1754         }
1755
1756         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1757         if (ret) {
1758                 DRM_ERROR("failed to create device file for dpm state\n");
1759                 return ret;
1760         }
1761         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1762         if (ret) {
1763                 DRM_ERROR("failed to create device file for dpm state\n");
1764                 return ret;
1765         }
1766
1767
1768         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1769         if (ret) {
1770                 DRM_ERROR("failed to create device file pp_num_states\n");
1771                 return ret;
1772         }
1773         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1774         if (ret) {
1775                 DRM_ERROR("failed to create device file pp_cur_state\n");
1776                 return ret;
1777         }
1778         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1779         if (ret) {
1780                 DRM_ERROR("failed to create device file pp_force_state\n");
1781                 return ret;
1782         }
1783         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1784         if (ret) {
1785                 DRM_ERROR("failed to create device file pp_table\n");
1786                 return ret;
1787         }
1788
1789         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1790         if (ret) {
1791                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1792                 return ret;
1793         }
1794         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1795         if (ret) {
1796                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1797                 return ret;
1798         }
1799         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1800         if (ret) {
1801                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1802                 return ret;
1803         }
1804         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1805         if (ret) {
1806                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1807                 return ret;
1808         }
1809         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1810         if (ret) {
1811                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1812                 return ret;
1813         }
1814         ret = device_create_file(adev->dev,
1815                         &dev_attr_pp_power_profile_mode);
1816         if (ret) {
1817                 DRM_ERROR("failed to create device file "
1818                                 "pp_power_profile_mode\n");
1819                 return ret;
1820         }
1821         ret = device_create_file(adev->dev,
1822                         &dev_attr_pp_od_clk_voltage);
1823         if (ret) {
1824                 DRM_ERROR("failed to create device file "
1825                                 "pp_od_clk_voltage\n");
1826                 return ret;
1827         }
1828         ret = amdgpu_debugfs_pm_init(adev);
1829         if (ret) {
1830                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1831                 return ret;
1832         }
1833
1834         adev->pm.sysfs_initialized = true;
1835
1836         return 0;
1837 }
1838
1839 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1840 {
1841         if (adev->pm.dpm_enabled == 0)
1842                 return;
1843
1844         if (adev->pm.int_hwmon_dev)
1845                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1846         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1847         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1848
1849         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1850         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1851         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1852         device_remove_file(adev->dev, &dev_attr_pp_table);
1853
1854         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1855         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1856         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1857         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1858         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1859         device_remove_file(adev->dev,
1860                         &dev_attr_pp_power_profile_mode);
1861         device_remove_file(adev->dev,
1862                         &dev_attr_pp_od_clk_voltage);
1863 }
1864
1865 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1866 {
1867         int i = 0;
1868
1869         if (!adev->pm.dpm_enabled)
1870                 return;
1871
1872         if (adev->mode_info.num_crtc)
1873                 amdgpu_display_bandwidth_update(adev);
1874
1875         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1876                 struct amdgpu_ring *ring = adev->rings[i];
1877                 if (ring && ring->ready)
1878                         amdgpu_fence_wait_empty(ring);
1879         }
1880
1881         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1882                 if (!amdgpu_device_has_dc_support(adev)) {
1883                         mutex_lock(&adev->pm.mutex);
1884                         amdgpu_dpm_get_active_displays(adev);
1885                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
1886                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1887                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1888                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1889                         if (adev->pm.pm_display_cfg.vrefresh > 120)
1890                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
1891                         if (adev->powerplay.pp_funcs->display_configuration_change)
1892                                 adev->powerplay.pp_funcs->display_configuration_change(
1893                                                                 adev->powerplay.pp_handle,
1894                                                                 &adev->pm.pm_display_cfg);
1895                         mutex_unlock(&adev->pm.mutex);
1896                 }
1897                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1898         } else {
1899                 mutex_lock(&adev->pm.mutex);
1900                 amdgpu_dpm_get_active_displays(adev);
1901                 /* update battery/ac status */
1902                 if (power_supply_is_system_supplied() > 0)
1903                         adev->pm.dpm.ac_power = true;
1904                 else
1905                         adev->pm.dpm.ac_power = false;
1906
1907                 amdgpu_dpm_change_power_state_locked(adev);
1908
1909                 mutex_unlock(&adev->pm.mutex);
1910         }
1911 }
1912
1913 /*
1914  * Debugfs info
1915  */
1916 #if defined(CONFIG_DEBUG_FS)
1917
1918 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1919 {
1920         uint32_t value;
1921         uint32_t query = 0;
1922         int size;
1923
1924         /* sanity check PP is enabled */
1925         if (!(adev->powerplay.pp_funcs &&
1926               adev->powerplay.pp_funcs->read_sensor))
1927               return -EINVAL;
1928
1929         /* GPU Clocks */
1930         size = sizeof(value);
1931         seq_printf(m, "GFX Clocks and Power:\n");
1932         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1933                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1934         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1935                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1936         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1937                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1938         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1939                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1940         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1941                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1942         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1943                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1944         size = sizeof(uint32_t);
1945         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1946                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1947         size = sizeof(value);
1948         seq_printf(m, "\n");
1949
1950         /* GPU Temp */
1951         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1952                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1953
1954         /* GPU Load */
1955         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1956                 seq_printf(m, "GPU Load: %u %%\n", value);
1957         seq_printf(m, "\n");
1958
1959         /* UVD clocks */
1960         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1961                 if (!value) {
1962                         seq_printf(m, "UVD: Disabled\n");
1963                 } else {
1964                         seq_printf(m, "UVD: Enabled\n");
1965                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1966                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1967                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1968                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1969                 }
1970         }
1971         seq_printf(m, "\n");
1972
1973         /* VCE clocks */
1974         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1975                 if (!value) {
1976                         seq_printf(m, "VCE: Disabled\n");
1977                 } else {
1978                         seq_printf(m, "VCE: Enabled\n");
1979                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1980                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1981                 }
1982         }
1983
1984         return 0;
1985 }
1986
1987 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1988 {
1989         int i;
1990
1991         for (i = 0; clocks[i].flag; i++)
1992                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1993                            (flags & clocks[i].flag) ? "On" : "Off");
1994 }
1995
1996 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1997 {
1998         struct drm_info_node *node = (struct drm_info_node *) m->private;
1999         struct drm_device *dev = node->minor->dev;
2000         struct amdgpu_device *adev = dev->dev_private;
2001         struct drm_device *ddev = adev->ddev;
2002         u32 flags = 0;
2003
2004         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2005         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2006         amdgpu_parse_cg_state(m, flags);
2007         seq_printf(m, "\n");
2008
2009         if (!adev->pm.dpm_enabled) {
2010                 seq_printf(m, "dpm not enabled\n");
2011                 return 0;
2012         }
2013         if  ((adev->flags & AMD_IS_PX) &&
2014              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2015                 seq_printf(m, "PX asic powered off\n");
2016         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2017                 mutex_lock(&adev->pm.mutex);
2018                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2019                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2020                 else
2021                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2022                 mutex_unlock(&adev->pm.mutex);
2023         } else {
2024                 return amdgpu_debugfs_pm_info_pp(m, adev);
2025         }
2026
2027         return 0;
2028 }
2029
2030 static const struct drm_info_list amdgpu_pm_info_list[] = {
2031         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2032 };
2033 #endif
2034
2035 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2036 {
2037 #if defined(CONFIG_DEBUG_FS)
2038         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2039 #else
2040         return 0;
2041 #endif
2042 }