drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "amdgpu.h"
  25 #include "gmc_v9_0.h"
  26 #include "amdgpu_atomfirmware.h"
  27
  28 #include "vega10/soc15ip.h"
  29 #include "vega10/HDP/hdp_4_0_offset.h"
  30 #include "vega10/HDP/hdp_4_0_sh_mask.h"
  31 #include "vega10/GC/gc_9_0_sh_mask.h"
  32 #include "vega10/DC/dce_12_0_offset.h"
  33 #include "vega10/DC/dce_12_0_sh_mask.h"
  34 #include "vega10/vega10_enum.h"
  35
  36 #include "soc15_common.h"
  37
  38 #include "nbio_v6_1.h"
  39 #include "nbio_v7_0.h"
  40 #include "gfxhub_v1_0.h"
  41 #include "mmhub_v1_0.h"
  42
  43 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  44 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  45 //DF_CS_AON0_DramBaseAddress0
  46 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  47 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  48 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  49 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  50 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  51 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  52 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  53 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  54 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  55 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  56
  57 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  58 #define AMDGPU_NUM_OF_VMIDS                     8
  59
  60 static const u32 golden_settings_vega10_hdp[] =
  61 {
  62         0xf64, 0x0fffffff, 0x00000000,
  63         0xf65, 0x0fffffff, 0x00000000,
  64         0xf66, 0x0fffffff, 0x00000000,
  65         0xf67, 0x0fffffff, 0x00000000,
  66         0xf68, 0x0fffffff, 0x00000000,
  67         0xf6a, 0x0fffffff, 0x00000000,
  68         0xf6b, 0x0fffffff, 0x00000000,
  69         0xf6c, 0x0fffffff, 0x00000000,
  70         0xf6d, 0x0fffffff, 0x00000000,
  71         0xf6e, 0x0fffffff, 0x00000000,
  72 };
  73
  74 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  75                                         struct amdgpu_irq_src *src,
  76                                         unsigned type,
  77                                         enum amdgpu_interrupt_state state)
  78 {
  79         struct amdgpu_vmhub *hub;
  80         u32 tmp, reg, bits, i;
  81
  82         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  83                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  84                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  85                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  86                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  87                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  88                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
  89
  90         switch (state) {
  91         case AMDGPU_IRQ_STATE_DISABLE:
  92                 /* MM HUB */
  93                 hub = &adev->vmhub[AMDGPU_MMHUB];
  94                 for (i = 0; i< 16; i++) {
  95                         reg = hub->vm_context0_cntl + i;
  96                         tmp = RREG32(reg);
  97                         tmp &= ~bits;
  98                         WREG32(reg, tmp);
  99                 }
 100
 101                 /* GFX HUB */
 102                 hub = &adev->vmhub[AMDGPU_GFXHUB];
 103                 for (i = 0; i < 16; i++) {
 104                         reg = hub->vm_context0_cntl + i;
 105                         tmp = RREG32(reg);
 106                         tmp &= ~bits;
 107                         WREG32(reg, tmp);
 108                 }
 109                 break;
 110         case AMDGPU_IRQ_STATE_ENABLE:
 111                 /* MM HUB */
 112                 hub = &adev->vmhub[AMDGPU_MMHUB];
 113                 for (i = 0; i< 16; i++) {
 114                         reg = hub->vm_context0_cntl + i;
 115                         tmp = RREG32(reg);
 116                         tmp |= bits;
 117                         WREG32(reg, tmp);
 118                 }
 119
 120                 /* GFX HUB */
 121                 hub = &adev->vmhub[AMDGPU_GFXHUB];
 122                 for (i = 0; i < 16; i++) {
 123                         reg = hub->vm_context0_cntl + i;
 124                         tmp = RREG32(reg);
 125                         tmp |= bits;
 126                         WREG32(reg, tmp);
 127                 }
 128                 break;
 129         default:
 130                 break;
 131         }
 132
 133         return 0;
 134 }
 135
 136 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 137                                 struct amdgpu_irq_src *source,
 138                                 struct amdgpu_iv_entry *entry)
 139 {
 140         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
 141         uint32_t status = 0;
 142         u64 addr;
 143
 144         addr = (u64)entry->src_data[0] << 12;
 145         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 146
 147         if (!amdgpu_sriov_vf(adev)) {
 148                 status = RREG32(hub->vm_l2_pro_fault_status);
 149                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 150         }
 151
 152         if (printk_ratelimit()) {
 153                 dev_err(adev->dev,
 154                         "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
 155                         entry->vm_id_src ? "mmhub" : "gfxhub",
 156                         entry->src_id, entry->ring_id, entry->vm_id,
 157                         entry->pas_id);
 158                 dev_err(adev->dev, "  at page 0x%016llx from %d\n",
 159                         addr, entry->client_id);
 160                 if (!amdgpu_sriov_vf(adev))
 161                         dev_err(adev->dev,
 162                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 163                                 status);
 164         }
 165
 166         return 0;
 167 }
 168
 169 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 170         .set = gmc_v9_0_vm_fault_interrupt_state,
 171         .process = gmc_v9_0_process_interrupt,
 172 };
 173
 174 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 175 {
 176         adev->mc.vm_fault.num_types = 1;
 177         adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 178 }
 179
 180 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
 181 {
 182         u32 req = 0;
 183
 184         /* invalidate using legacy mode on vm_id*/
 185         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 186                             PER_VMID_INVALIDATE_REQ, 1 << vm_id);
 187         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
 188         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 189         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 190         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 191         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 192         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 193         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 194                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 195
 196         return req;
 197 }
 198
 199 /*
 200  * GART
 201  * VMID 0 is the physical GPU addresses as used by the kernel.
 202  * VMIDs 1-15 are used for userspace clients and are handled
 203  * by the amdgpu vm/hsa code.
 204  */
 205
 206 /**
 207  * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
 208  *
 209  * @adev: amdgpu_device pointer
 210  * @vmid: vm instance to flush
 211  *
 212  * Flush the TLB for the requested page table.
 213  */
 214 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 215                                         uint32_t vmid)
 216 {
 217         /* Use register 17 for GART */
 218         const unsigned eng = 17;
 219         unsigned i, j;
 220
 221         /* flush hdp cache */
 222         if (adev->flags & AMD_IS_APU)
 223                 nbio_v7_0_hdp_flush(adev);
 224         else
 225                 nbio_v6_1_hdp_flush(adev);
 226
 227         spin_lock(&adev->mc.invalidate_lock);
 228
 229         for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
 230                 struct amdgpu_vmhub *hub = &adev->vmhub[i];
 231                 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
 232
 233                 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 234
 235                 /* Busy wait for ACK.*/
 236                 for (j = 0; j < 100; j++) {
 237                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 238                         tmp &= 1 << vmid;
 239                         if (tmp)
 240                                 break;
 241                         cpu_relax();
 242                 }
 243                 if (j < 100)
 244                         continue;
 245
 246                 /* Wait for ACK with a delay.*/
 247                 for (j = 0; j < adev->usec_timeout; j++) {
 248                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 249                         tmp &= 1 << vmid;
 250                         if (tmp)
 251                                 break;
 252                         udelay(1);
 253                 }
 254                 if (j < adev->usec_timeout)
 255                         continue;
 256
 257                 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 258         }
 259
 260         spin_unlock(&adev->mc.invalidate_lock);
 261 }
 262
 263 /**
 264  * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
 265  *
 266  * @adev: amdgpu_device pointer
 267  * @cpu_pt_addr: cpu address of the page table
 268  * @gpu_page_idx: entry in the page table to update
 269  * @addr: dst addr to write into pte/pde
 270  * @flags: access flags
 271  *
 272  * Update the page tables using the CPU.
 273  */
 274 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
 275                                         void *cpu_pt_addr,
 276                                         uint32_t gpu_page_idx,
 277                                         uint64_t addr,
 278                                         uint64_t flags)
 279 {
 280         void __iomem *ptr = (void *)cpu_pt_addr;
 281         uint64_t value;
 282
 283         /*
 284          * PTE format on VEGA 10:
 285          * 63:59 reserved
 286          * 58:57 mtype
 287          * 56 F
 288          * 55 L
 289          * 54 P
 290          * 53 SW
 291          * 52 T
 292          * 50:48 reserved
 293          * 47:12 4k physical page base address
 294          * 11:7 fragment
 295          * 6 write
 296          * 5 read
 297          * 4 exe
 298          * 3 Z
 299          * 2 snooped
 300          * 1 system
 301          * 0 valid
 302          *
 303          * PDE format on VEGA 10:
 304          * 63:59 block fragment size
 305          * 58:55 reserved
 306          * 54 P
 307          * 53:48 reserved
 308          * 47:6 physical base address of PD or PTE
 309          * 5:3 reserved
 310          * 2 C
 311          * 1 system
 312          * 0 valid
 313          */
 314
 315         /*
 316          * The following is for PTE only. GART does not have PDEs.
 317         */
 318         value = addr & 0x0000FFFFFFFFF000ULL;
 319         value |= flags;
 320         writeq(value, ptr + (gpu_page_idx * 8));
 321         return 0;
 322 }
 323
 324 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 325                                                 uint32_t flags)
 326
 327 {
 328         uint64_t pte_flag = 0;
 329
 330         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 331                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 332         if (flags & AMDGPU_VM_PAGE_READABLE)
 333                 pte_flag |= AMDGPU_PTE_READABLE;
 334         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 335                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 336
 337         switch (flags & AMDGPU_VM_MTYPE_MASK) {
 338         case AMDGPU_VM_MTYPE_DEFAULT:
 339                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 340                 break;
 341         case AMDGPU_VM_MTYPE_NC:
 342                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 343                 break;
 344         case AMDGPU_VM_MTYPE_WC:
 345                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
 346                 break;
 347         case AMDGPU_VM_MTYPE_CC:
 348                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
 349                 break;
 350         case AMDGPU_VM_MTYPE_UC:
 351                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
 352                 break;
 353         default:
 354                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 355                 break;
 356         }
 357
 358         if (flags & AMDGPU_VM_PAGE_PRT)
 359                 pte_flag |= AMDGPU_PTE_PRT;
 360
 361         return pte_flag;
 362 }
 363
 364 static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
 365 {
 366         addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
 367         BUG_ON(addr & 0xFFFF00000000003FULL);
 368         return addr;
 369 }
 370
 371 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
 372         .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
 373         .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
 374         .get_invalidate_req = gmc_v9_0_get_invalidate_req,
 375         .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
 376         .get_vm_pde = gmc_v9_0_get_vm_pde
 377 };
 378
 379 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
 380 {
 381         if (adev->gart.gart_funcs == NULL)
 382                 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
 383 }
 384
 385 static int gmc_v9_0_early_init(void *handle)
 386 {
 387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 388
 389         gmc_v9_0_set_gart_funcs(adev);
 390         gmc_v9_0_set_irq_funcs(adev);
 391
 392         return 0;
 393 }
 394
 395 static int gmc_v9_0_late_init(void *handle)
 396 {
 397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 398         unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
 399         unsigned i;
 400
 401         for(i = 0; i < adev->num_rings; ++i) {
 402                 struct amdgpu_ring *ring = adev->rings[i];
 403                 unsigned vmhub = ring->funcs->vmhub;
 404
 405                 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
 406                 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
 407                          ring->idx, ring->name, ring->vm_inv_eng,
 408                          ring->funcs->vmhub);
 409         }
 410
 411         /* Engine 17 is used for GART flushes */
 412         for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
 413                 BUG_ON(vm_inv_eng[i] > 17);
 414
 415         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 416 }
 417
 418 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 419                                         struct amdgpu_mc *mc)
 420 {
 421         u64 base = 0;
 422         if (!amdgpu_sriov_vf(adev))
 423                 base = mmhub_v1_0_get_fb_location(adev);
 424         amdgpu_vram_location(adev, &adev->mc, base);
 425         amdgpu_gart_location(adev, mc);
 426         /* base offset of vram pages */
 427         if (adev->flags & AMD_IS_APU)
 428                 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 429         else
 430                 adev->vm_manager.vram_base_offset = 0;
 431 }
 432
 433 /**
 434  * gmc_v9_0_mc_init - initialize the memory controller driver params
 435  *
 436  * @adev: amdgpu_device pointer
 437  *
 438  * Look up the amount of vram, vram width, and decide how to place
 439  * vram and gart within the GPU's physical address space.
 440  * Returns 0 for success.
 441  */
 442 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 443 {
 444         u32 tmp;
 445         int chansize, numchan;
 446
 447         adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 448         if (!adev->mc.vram_width) {
 449                 /* hbm memory channel size */
 450                 chansize = 128;
 451
 452                 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
 453                 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
 454                 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 455                 switch (tmp) {
 456                 case 0:
 457                 default:
 458                         numchan = 1;
 459                         break;
 460                 case 1:
 461                         numchan = 2;
 462                         break;
 463                 case 2:
 464                         numchan = 0;
 465                         break;
 466                 case 3:
 467                         numchan = 4;
 468                         break;
 469                 case 4:
 470                         numchan = 0;
 471                         break;
 472                 case 5:
 473                         numchan = 8;
 474                         break;
 475                 case 6:
 476                         numchan = 0;
 477                         break;
 478                 case 7:
 479                         numchan = 16;
 480                         break;
 481                 case 8:
 482                         numchan = 2;
 483                         break;
 484                 }
 485                 adev->mc.vram_width = numchan * chansize;
 486         }
 487
 488         /* Could aper size report 0 ? */
 489         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 490         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 491         /* size in MB on si */
 492         adev->mc.mc_vram_size =
 493                 ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
 494                  nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
 495         adev->mc.real_vram_size = adev->mc.mc_vram_size;
 496         adev->mc.visible_vram_size = adev->mc.aper_size;
 497
 498         /* In case the PCI BAR is larger than the actual amount of vram */
 499         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 500                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 501
 502         amdgpu_gart_set_defaults(adev);
 503         gmc_v9_0_vram_gtt_location(adev, &adev->mc);
 504
 505         return 0;
 506 }
 507
 508 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 509 {
 510         int r;
 511
 512         if (adev->gart.robj) {
 513                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 514                 return 0;
 515         }
 516         /* Initialize common gart structure */
 517         r = amdgpu_gart_init(adev);
 518         if (r)
 519                 return r;
 520         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 521         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
 522                                  AMDGPU_PTE_EXECUTABLE;
 523         return amdgpu_gart_table_vram_alloc(adev);
 524 }
 525
 526 static int gmc_v9_0_sw_init(void *handle)
 527 {
 528         int r;
 529         int dma_bits;
 530         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 531
 532         gfxhub_v1_0_init(adev);
 533         mmhub_v1_0_init(adev);
 534
 535         spin_lock_init(&adev->mc.invalidate_lock);
 536
 537         switch (adev->asic_type) {
 538         case CHIP_RAVEN:
 539                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 540                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
 541                         adev->vm_manager.vm_size = 1U << 18;
 542                         adev->vm_manager.block_size = 9;
 543                         adev->vm_manager.num_level = 3;
 544                         amdgpu_vm_set_fragment_size(adev, 9);
 545                 } else {
 546                         /* vm_size is 64GB for legacy 2-level page support */
 547                         amdgpu_vm_adjust_size(adev, 64, 9);
 548                         adev->vm_manager.num_level = 1;
 549                 }
 550                 break;
 551         case CHIP_VEGA10:
 552                 /* XXX Don't know how to get VRAM type yet. */
 553                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
 554                 /*
 555                  * To fulfill 4-level page support,
 556                  * vm size is 256TB (48bit), maximum size of Vega10,
 557                  * block size 512 (9bit)
 558                  */
 559                 adev->vm_manager.vm_size = 1U << 18;
 560                 adev->vm_manager.block_size = 9;
 561                 adev->vm_manager.num_level = 3;
 562                 amdgpu_vm_set_fragment_size(adev, 9);
 563                 break;
 564         default:
 565                 break;
 566         }
 567
 568         DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
 569                         adev->vm_manager.vm_size,
 570                         adev->vm_manager.block_size,
 571                         adev->vm_manager.fragment_size);
 572
 573         /* This interrupt is VMC page fault.*/
 574         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
 575                                 &adev->mc.vm_fault);
 576         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
 577                                 &adev->mc.vm_fault);
 578
 579         if (r)
 580                 return r;
 581
 582         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 583
 584         /* Set the internal MC address mask
 585          * This is the max address of the GPU's
 586          * internal address space.
 587          */
 588         adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 589
 590         /*
 591          * It needs to reserve 8M stolen memory for vega10
 592          * TODO: Figure out how to avoid that...
 593          */
 594         adev->mc.stolen_size = 8 * 1024 * 1024;
 595
 596         /* set DMA mask + need_dma32 flags.
 597          * PCIE - can handle 44-bits.
 598          * IGP - can handle 44-bits
 599          * PCI - dma32 for legacy pci gart, 44 bits on vega10
 600          */
 601         adev->need_dma32 = false;
 602         dma_bits = adev->need_dma32 ? 32 : 44;
 603         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 604         if (r) {
 605                 adev->need_dma32 = true;
 606                 dma_bits = 32;
 607                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 608         }
 609         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 610         if (r) {
 611                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 612                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 613         }
 614
 615         r = gmc_v9_0_mc_init(adev);
 616         if (r)
 617                 return r;
 618
 619         /* Memory manager */
 620         r = amdgpu_bo_init(adev);
 621         if (r)
 622                 return r;
 623
 624         r = gmc_v9_0_gart_init(adev);
 625         if (r)
 626                 return r;
 627
 628         /*
 629          * number of VMs
 630          * VMID 0 is reserved for System
 631          * amdgpu graphics/compute will use VMIDs 1-7
 632          * amdkfd will use VMIDs 8-15
 633          */
 634         adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
 635         adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
 636
 637         amdgpu_vm_manager_init(adev);
 638
 639         return 0;
 640 }
 641
 642 /**
 643  * gmc_v8_0_gart_fini - vm fini callback
 644  *
 645  * @adev: amdgpu_device pointer
 646  *
 647  * Tears down the driver GART/VM setup (CIK).
 648  */
 649 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
 650 {
 651         amdgpu_gart_table_vram_free(adev);
 652         amdgpu_gart_fini(adev);
 653 }
 654
 655 static int gmc_v9_0_sw_fini(void *handle)
 656 {
 657         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 658
 659         amdgpu_vm_manager_fini(adev);
 660         gmc_v9_0_gart_fini(adev);
 661         amdgpu_gem_force_release(adev);
 662         amdgpu_bo_fini(adev);
 663
 664         return 0;
 665 }
 666
 667 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
 668 {
 669         switch (adev->asic_type) {
 670         case CHIP_VEGA10:
 671                 break;
 672         case CHIP_RAVEN:
 673                 break;
 674         default:
 675                 break;
 676         }
 677 }
 678
 679 /**
 680  * gmc_v9_0_gart_enable - gart enable
 681  *
 682  * @adev: amdgpu_device pointer
 683  */
 684 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 685 {
 686         int r;
 687         bool value;
 688         u32 tmp;
 689
 690         amdgpu_program_register_sequence(adev,
 691                 golden_settings_vega10_hdp,
 692                 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
 693
 694         if (adev->gart.robj == NULL) {
 695                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 696                 return -EINVAL;
 697         }
 698         r = amdgpu_gart_table_vram_pin(adev);
 699         if (r)
 700                 return r;
 701
 702         /* After HDP is initialized, flush HDP.*/
 703         if (adev->flags & AMD_IS_APU)
 704                 nbio_v7_0_hdp_flush(adev);
 705         else
 706                 nbio_v6_1_hdp_flush(adev);
 707
 708         switch (adev->asic_type) {
 709         case CHIP_RAVEN:
 710                 mmhub_v1_0_initialize_power_gating(adev);
 711                 mmhub_v1_0_update_power_gating(adev, true);
 712                 break;
 713         default:
 714                 break;
 715         }
 716
 717         r = gfxhub_v1_0_gart_enable(adev);
 718         if (r)
 719                 return r;
 720
 721         r = mmhub_v1_0_gart_enable(adev);
 722         if (r)
 723                 return r;
 724
 725         tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
 726         tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
 727         WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
 728
 729         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
 730         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 731
 732
 733         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 734                 value = false;
 735         else
 736                 value = true;
 737
 738         gfxhub_v1_0_set_fault_enable_default(adev, value);
 739         mmhub_v1_0_set_fault_enable_default(adev, value);
 740
 741         gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
 742
 743         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 744                  (unsigned)(adev->mc.gart_size >> 20),
 745                  (unsigned long long)adev->gart.table_addr);
 746         adev->gart.ready = true;
 747         return 0;
 748 }
 749
 750 static int gmc_v9_0_hw_init(void *handle)
 751 {
 752         int r;
 753         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 754
 755         /* The sequence of these two function calls matters.*/
 756         gmc_v9_0_init_golden_registers(adev);
 757
 758         if (adev->mode_info.num_crtc) {
 759                 u32 tmp;
 760
 761                 /* Lockout access through VGA aperture*/
 762                 tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL);
 763                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 764                 WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp);
 765
 766                 /* disable VGA render */
 767                 tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL);
 768                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 769                 WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp);
 770         }
 771
 772         r = gmc_v9_0_gart_enable(adev);
 773
 774         return r;
 775 }
 776
 777 /**
 778  * gmc_v9_0_gart_disable - gart disable
 779  *
 780  * @adev: amdgpu_device pointer
 781  *
 782  * This disables all VM page table.
 783  */
 784 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
 785 {
 786         gfxhub_v1_0_gart_disable(adev);
 787         mmhub_v1_0_gart_disable(adev);
 788         amdgpu_gart_table_vram_unpin(adev);
 789 }
 790
 791 static int gmc_v9_0_hw_fini(void *handle)
 792 {
 793         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 794
 795         if (amdgpu_sriov_vf(adev)) {
 796                 /* full access mode, so don't touch any GMC register */
 797                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 798                 return 0;
 799         }
 800
 801         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 802         gmc_v9_0_gart_disable(adev);
 803
 804         return 0;
 805 }
 806
 807 static int gmc_v9_0_suspend(void *handle)
 808 {
 809         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 810
 811         gmc_v9_0_hw_fini(adev);
 812
 813         return 0;
 814 }
 815
 816 static int gmc_v9_0_resume(void *handle)
 817 {
 818         int r;
 819         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 820
 821         r = gmc_v9_0_hw_init(adev);
 822         if (r)
 823                 return r;
 824
 825         amdgpu_vm_reset_all_ids(adev);
 826
 827         return 0;
 828 }
 829
 830 static bool gmc_v9_0_is_idle(void *handle)
 831 {
 832         /* MC is always ready in GMC v9.*/
 833         return true;
 834 }
 835
 836 static int gmc_v9_0_wait_for_idle(void *handle)
 837 {
 838         /* There is no need to wait for MC idle in GMC v9.*/
 839         return 0;
 840 }
 841
 842 static int gmc_v9_0_soft_reset(void *handle)
 843 {
 844         /* XXX for emulation.*/
 845         return 0;
 846 }
 847
 848 static int gmc_v9_0_set_clockgating_state(void *handle,
 849                                         enum amd_clockgating_state state)
 850 {
 851         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 852
 853         return mmhub_v1_0_set_clockgating(adev, state);
 854 }
 855
 856 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
 857 {
 858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 859
 860         mmhub_v1_0_get_clockgating(adev, flags);
 861 }
 862
 863 static int gmc_v9_0_set_powergating_state(void *handle,
 864                                         enum amd_powergating_state state)
 865 {
 866         return 0;
 867 }
 868
 869 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
 870         .name = "gmc_v9_0",
 871         .early_init = gmc_v9_0_early_init,
 872         .late_init = gmc_v9_0_late_init,
 873         .sw_init = gmc_v9_0_sw_init,
 874         .sw_fini = gmc_v9_0_sw_fini,
 875         .hw_init = gmc_v9_0_hw_init,
 876         .hw_fini = gmc_v9_0_hw_fini,
 877         .suspend = gmc_v9_0_suspend,
 878         .resume = gmc_v9_0_resume,
 879         .is_idle = gmc_v9_0_is_idle,
 880         .wait_for_idle = gmc_v9_0_wait_for_idle,
 881         .soft_reset = gmc_v9_0_soft_reset,
 882         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
 883         .set_powergating_state = gmc_v9_0_set_powergating_state,
 884         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
 885 };
 886
 887 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
 888 {
 889         .type = AMD_IP_BLOCK_TYPE_GMC,
 890         .major = 9,
 891         .minor = 0,
 892         .rev = 0,
 893         .funcs = &gmc_v9_0_ip_funcs,
 894 };