drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x00009010, 0x000000C7, 0x0 },
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x00007011, 0x000000C7, 0x0 },
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x00005012, 0x000000C7, 0x0 },
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x00007011, 0x00000087, 0x0 },
 149         { 0x80009010, 0x000000C7, 0x1 },        /* Uses I_boost level 0x1 */
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x00005012, 0x000000C7, 0x0 },
 152         { 0x00007011, 0x000000C7, 0x0 },
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x00005012, 0x000000C7, 0x0 },
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x00007011, 0x00000087, 0x0 },
 162         { 0x80009010, 0x000000C7, 0x3 },        /* Uses I_boost level 0x3 */
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x00005012, 0x000000C7, 0x0 },
 165         { 0x00007011, 0x000000C7, 0x0 },
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x00005012, 0x000000C7, 0x0 },
 168 };
 169
 170 /*
 171  * Skylake H and S
 172  * eDP 1.4 low vswing translation parameters
 173  */
 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 175         { 0x00000018, 0x000000A8, 0x0 },
 176         { 0x00004013, 0x000000A9, 0x0 },
 177         { 0x00007011, 0x000000A2, 0x0 },
 178         { 0x00009010, 0x0000009C, 0x0 },
 179         { 0x00000018, 0x000000A9, 0x0 },
 180         { 0x00006013, 0x000000A2, 0x0 },
 181         { 0x00007011, 0x000000A6, 0x0 },
 182         { 0x00000018, 0x000000AB, 0x0 },
 183         { 0x00007013, 0x0000009F, 0x0 },
 184         { 0x00000018, 0x000000DF, 0x0 },
 185 };
 186
 187 /*
 188  * Skylake U
 189  * eDP 1.4 low vswing translation parameters
 190  */
 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 192         { 0x00000018, 0x000000A8, 0x0 },
 193         { 0x00004013, 0x000000A9, 0x0 },
 194         { 0x00007011, 0x000000A2, 0x0 },
 195         { 0x00009010, 0x0000009C, 0x0 },
 196         { 0x00000018, 0x000000A9, 0x0 },
 197         { 0x00006013, 0x000000A2, 0x0 },
 198         { 0x00007011, 0x000000A6, 0x0 },
 199         { 0x00002016, 0x000000AB, 0x0 },
 200         { 0x00005013, 0x0000009F, 0x0 },
 201         { 0x00000018, 0x000000DF, 0x0 },
 202 };
 203
 204 /*
 205  * Skylake Y
 206  * eDP 1.4 low vswing translation parameters
 207  */
 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 209         { 0x00000018, 0x000000A8, 0x0 },
 210         { 0x00004013, 0x000000AB, 0x0 },
 211         { 0x00007011, 0x000000A4, 0x0 },
 212         { 0x00009010, 0x000000DF, 0x0 },
 213         { 0x00000018, 0x000000AA, 0x0 },
 214         { 0x00006013, 0x000000A4, 0x0 },
 215         { 0x00007011, 0x0000009D, 0x0 },
 216         { 0x00000018, 0x000000A0, 0x0 },
 217         { 0x00006012, 0x000000DF, 0x0 },
 218         { 0x00000018, 0x0000008A, 0x0 },
 219 };
 220
 221 /* Skylake U, H and S */
 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 223         { 0x00000018, 0x000000AC, 0x0 },
 224         { 0x00005012, 0x0000009D, 0x0 },
 225         { 0x00007011, 0x00000088, 0x0 },
 226         { 0x00000018, 0x000000A1, 0x0 },
 227         { 0x00000018, 0x00000098, 0x0 },
 228         { 0x00004013, 0x00000088, 0x0 },
 229         { 0x00006012, 0x00000087, 0x0 },
 230         { 0x00000018, 0x000000DF, 0x0 },
 231         { 0x00003015, 0x00000087, 0x0 },        /* Default */
 232         { 0x00003015, 0x000000C7, 0x0 },
 233         { 0x00000018, 0x000000C7, 0x0 },
 234 };
 235
 236 /* Skylake Y */
 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 238         { 0x00000018, 0x000000A1, 0x0 },
 239         { 0x00005012, 0x000000DF, 0x0 },
 240         { 0x00007011, 0x00000084, 0x0 },
 241         { 0x00000018, 0x000000A4, 0x0 },
 242         { 0x00000018, 0x0000009D, 0x0 },
 243         { 0x00004013, 0x00000080, 0x0 },
 244         { 0x00006013, 0x000000C7, 0x0 },
 245         { 0x00000018, 0x0000008A, 0x0 },
 246         { 0x00003015, 0x000000C7, 0x0 },        /* Default */
 247         { 0x80003015, 0x000000C7, 0x7 },        /* Uses I_boost level 0x7 */
 248         { 0x00000018, 0x000000C7, 0x0 },
 249 };
 250
 251 struct bxt_ddi_buf_trans {
 252         u32 margin;     /* swing value */
 253         u32 scale;      /* scale value */
 254         u32 enable;     /* scale enable */
 255         u32 deemphasis;
 256         bool default_index; /* true if the entry represents default value */
 257 };
 258
 259 /* BSpec does not define separate vswing/pre-emphasis values for eDP.
 260  * Using DP values for eDP as well.
 261  */
 262 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 263                                         /* Idx  NT mV diff      db  */
 264         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 265         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 266         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 267         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 268         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 269         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 270         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 271         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 272         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 273         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 274 };
 275
 276 /* BSpec has 2 recommended values - entries 0 and 8.
 277  * Using the entry with higher vswing.
 278  */
 279 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 280                                         /* Idx  NT mV diff      db  */
 281         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 282         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 283         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 284         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 285         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 286         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 287         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 288         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 289         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 290         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 291 };
 292
 293 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 294                                     enum port port, int type);
 295
 296 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
 297                                  struct intel_digital_port **dig_port,
 298                                  enum port *port)
 299 {
 300         struct drm_encoder *encoder = &intel_encoder->base;
 301         int type = intel_encoder->type;
 302
 303         if (type == INTEL_OUTPUT_DP_MST) {
 304                 *dig_port = enc_to_mst(encoder)->primary;
 305                 *port = (*dig_port)->port;
 306         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 307             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 308                 *dig_port = enc_to_dig_port(encoder);
 309                 *port = (*dig_port)->port;
 310         } else if (type == INTEL_OUTPUT_ANALOG) {
 311                 *dig_port = NULL;
 312                 *port = PORT_E;
 313         } else {
 314                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 315                 BUG();
 316         }
 317 }
 318
 319 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 320 {
 321         struct intel_digital_port *dig_port;
 322         enum port port;
 323
 324         ddi_get_encoder_port(intel_encoder, &dig_port, &port);
 325
 326         return port;
 327 }
 328
 329 static bool
 330 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
 331 {
 332         return intel_dig_port->hdmi.hdmi_reg;
 333 }
 334
 335 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
 336                                                         int *n_entries)
 337 {
 338         const struct ddi_buf_trans *ddi_translations;
 339
 340         if (IS_SKL_ULX(dev)) {
 341                 ddi_translations = skl_y_ddi_translations_dp;
 342                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 343         } else if (IS_SKL_ULT(dev)) {
 344                 ddi_translations = skl_u_ddi_translations_dp;
 345                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 346         } else {
 347                 ddi_translations = skl_ddi_translations_dp;
 348                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 349         }
 350
 351         return ddi_translations;
 352 }
 353
 354 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
 355                                                          int *n_entries)
 356 {
 357         struct drm_i915_private *dev_priv = dev->dev_private;
 358         const struct ddi_buf_trans *ddi_translations;
 359
 360         if (IS_SKL_ULX(dev)) {
 361                 if (dev_priv->edp_low_vswing) {
 362                         ddi_translations = skl_y_ddi_translations_edp;
 363                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 364                 } else {
 365                         ddi_translations = skl_y_ddi_translations_dp;
 366                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 367                 }
 368         } else if (IS_SKL_ULT(dev)) {
 369                 if (dev_priv->edp_low_vswing) {
 370                         ddi_translations = skl_u_ddi_translations_edp;
 371                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 372                 } else {
 373                         ddi_translations = skl_u_ddi_translations_dp;
 374                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 375                 }
 376         } else {
 377                 if (dev_priv->edp_low_vswing) {
 378                         ddi_translations = skl_ddi_translations_edp;
 379                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 380                 } else {
 381                         ddi_translations = skl_ddi_translations_dp;
 382                         *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 383                 }
 384         }
 385
 386         return ddi_translations;
 387 }
 388
 389 static const struct ddi_buf_trans *
 390 skl_get_buf_trans_hdmi(struct drm_device *dev,
 391                        int *n_entries)
 392 {
 393         const struct ddi_buf_trans *ddi_translations;
 394
 395         if (IS_SKL_ULX(dev)) {
 396                 ddi_translations = skl_y_ddi_translations_hdmi;
 397                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 398         } else {
 399                 ddi_translations = skl_ddi_translations_hdmi;
 400                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 401         }
 402
 403         return ddi_translations;
 404 }
 405
 406 /*
 407  * Starting with Haswell, DDI port buffers must be programmed with correct
 408  * values in advance. The buffer values are different for FDI and DP modes,
 409  * but the HDMI/DVI fields are shared among those. So we program the DDI
 410  * in either FDI or DP modes only, as HDMI connections will work with both
 411  * of those
 412  */
 413 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
 414                                       bool supports_hdmi)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         u32 reg;
 418         u32 iboost_bit = 0;
 419         int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 420             size;
 421         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 422         const struct ddi_buf_trans *ddi_translations_fdi;
 423         const struct ddi_buf_trans *ddi_translations_dp;
 424         const struct ddi_buf_trans *ddi_translations_edp;
 425         const struct ddi_buf_trans *ddi_translations_hdmi;
 426         const struct ddi_buf_trans *ddi_translations;
 427
 428         if (IS_BROXTON(dev)) {
 429                 if (!supports_hdmi)
 430                         return;
 431
 432                 /* Vswing programming for HDMI */
 433                 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
 434                                         INTEL_OUTPUT_HDMI);
 435                 return;
 436         } else if (IS_SKYLAKE(dev)) {
 437                 ddi_translations_fdi = NULL;
 438                 ddi_translations_dp =
 439                                 skl_get_buf_trans_dp(dev, &n_dp_entries);
 440                 ddi_translations_edp =
 441                                 skl_get_buf_trans_edp(dev, &n_edp_entries);
 442                 ddi_translations_hdmi =
 443                                 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
 444                 hdmi_default_entry = 8;
 445                 /* If we're boosting the current, set bit 31 of trans1 */
 446                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
 447                     dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 448                         iboost_bit = 1<<31;
 449         } else if (IS_BROADWELL(dev)) {
 450                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 451                 ddi_translations_dp = bdw_ddi_translations_dp;
 452                 ddi_translations_edp = bdw_ddi_translations_edp;
 453                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 454                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 455                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 456                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 457                 hdmi_default_entry = 7;
 458         } else if (IS_HASWELL(dev)) {
 459                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 460                 ddi_translations_dp = hsw_ddi_translations_dp;
 461                 ddi_translations_edp = hsw_ddi_translations_dp;
 462                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 463                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 464                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 465                 hdmi_default_entry = 6;
 466         } else {
 467                 WARN(1, "ddi translation table missing\n");
 468                 ddi_translations_edp = bdw_ddi_translations_dp;
 469                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 470                 ddi_translations_dp = bdw_ddi_translations_dp;
 471                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 472                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 473                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 474                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 475                 hdmi_default_entry = 7;
 476         }
 477
 478         switch (port) {
 479         case PORT_A:
 480                 ddi_translations = ddi_translations_edp;
 481                 size = n_edp_entries;
 482                 break;
 483         case PORT_B:
 484         case PORT_C:
 485                 ddi_translations = ddi_translations_dp;
 486                 size = n_dp_entries;
 487                 break;
 488         case PORT_D:
 489                 if (intel_dp_is_edp(dev, PORT_D)) {
 490                         ddi_translations = ddi_translations_edp;
 491                         size = n_edp_entries;
 492                 } else {
 493                         ddi_translations = ddi_translations_dp;
 494                         size = n_dp_entries;
 495                 }
 496                 break;
 497         case PORT_E:
 498                 if (ddi_translations_fdi)
 499                         ddi_translations = ddi_translations_fdi;
 500                 else
 501                         ddi_translations = ddi_translations_dp;
 502                 size = n_dp_entries;
 503                 break;
 504         default:
 505                 BUG();
 506         }
 507
 508         for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
 509                 I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit);
 510                 reg += 4;
 511                 I915_WRITE(reg, ddi_translations[i].trans2);
 512                 reg += 4;
 513         }
 514
 515         if (!supports_hdmi)
 516                 return;
 517
 518         /* Choose a good default if VBT is badly populated */
 519         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 520             hdmi_level >= n_hdmi_entries)
 521                 hdmi_level = hdmi_default_entry;
 522
 523         /* Entry 9 is for HDMI: */
 524         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 525         reg += 4;
 526         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 527         reg += 4;
 528 }
 529
 530 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 531  * mode and port E for FDI.
 532  */
 533 void intel_prepare_ddi(struct drm_device *dev)
 534 {
 535         struct intel_encoder *intel_encoder;
 536         bool visited[I915_MAX_PORTS] = { 0, };
 537
 538         if (!HAS_DDI(dev))
 539                 return;
 540
 541         for_each_intel_encoder(dev, intel_encoder) {
 542                 struct intel_digital_port *intel_dig_port;
 543                 enum port port;
 544                 bool supports_hdmi;
 545
 546                 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
 547
 548                 if (visited[port])
 549                         continue;
 550
 551                 supports_hdmi = intel_dig_port &&
 552                                 intel_dig_port_supports_hdmi(intel_dig_port);
 553
 554                 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
 555                 visited[port] = true;
 556         }
 557 }
 558
 559 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 560                                     enum port port)
 561 {
 562         uint32_t reg = DDI_BUF_CTL(port);
 563         int i;
 564
 565         for (i = 0; i < 16; i++) {
 566                 udelay(1);
 567                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 568                         return;
 569         }
 570         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 571 }
 572
 573 /* Starting with Haswell, different DDI ports can work in FDI mode for
 574  * connection to the PCH-located connectors. For this, it is necessary to train
 575  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 576  *
 577  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 578  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 579  * DDI A (which is used for eDP)
 580  */
 581
 582 void hsw_fdi_link_train(struct drm_crtc *crtc)
 583 {
 584         struct drm_device *dev = crtc->dev;
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 587         u32 temp, i, rx_ctl_val;
 588
 589         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 590          * mode set "sequence for CRT port" document:
 591          * - TP1 to TP2 time with the default value
 592          * - FDI delay to 90h
 593          *
 594          * WaFDIAutoLinkSetTimingOverrride:hsw
 595          */
 596         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 597                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 598                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 599
 600         /* Enable the PCH Receiver FDI PLL */
 601         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 602                      FDI_RX_PLL_ENABLE |
 603                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 604         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 605         POSTING_READ(_FDI_RXA_CTL);
 606         udelay(220);
 607
 608         /* Switch from Rawclk to PCDclk */
 609         rx_ctl_val |= FDI_PCDCLK;
 610         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 611
 612         /* Configure Port Clock Select */
 613         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 614         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 615
 616         /* Start the training iterating through available voltages and emphasis,
 617          * testing each value twice. */
 618         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 619                 /* Configure DP_TP_CTL with auto-training */
 620                 I915_WRITE(DP_TP_CTL(PORT_E),
 621                                         DP_TP_CTL_FDI_AUTOTRAIN |
 622                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 623                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 624                                         DP_TP_CTL_ENABLE);
 625
 626                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 627                  * DDI E does not support port reversal, the functionality is
 628                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 629                  * port reversal bit */
 630                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 631                            DDI_BUF_CTL_ENABLE |
 632                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 633                            DDI_BUF_TRANS_SELECT(i / 2));
 634                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 635
 636                 udelay(600);
 637
 638                 /* Program PCH FDI Receiver TU */
 639                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 640
 641                 /* Enable PCH FDI Receiver with auto-training */
 642                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 643                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 644                 POSTING_READ(_FDI_RXA_CTL);
 645
 646                 /* Wait for FDI receiver lane calibration */
 647                 udelay(30);
 648
 649                 /* Unset FDI_RX_MISC pwrdn lanes */
 650                 temp = I915_READ(_FDI_RXA_MISC);
 651                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 652                 I915_WRITE(_FDI_RXA_MISC, temp);
 653                 POSTING_READ(_FDI_RXA_MISC);
 654
 655                 /* Wait for FDI auto training time */
 656                 udelay(5);
 657
 658                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 659                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 660                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 661
 662                         /* Enable normal pixel sending for FDI */
 663                         I915_WRITE(DP_TP_CTL(PORT_E),
 664                                    DP_TP_CTL_FDI_AUTOTRAIN |
 665                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 666                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 667                                    DP_TP_CTL_ENABLE);
 668
 669                         return;
 670                 }
 671
 672                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 673                 temp &= ~DDI_BUF_CTL_ENABLE;
 674                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 675                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 676
 677                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 678                 temp = I915_READ(DP_TP_CTL(PORT_E));
 679                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 680                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 681                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 682                 POSTING_READ(DP_TP_CTL(PORT_E));
 683
 684                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 685
 686                 rx_ctl_val &= ~FDI_RX_ENABLE;
 687                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 688                 POSTING_READ(_FDI_RXA_CTL);
 689
 690                 /* Reset FDI_RX_MISC pwrdn lanes */
 691                 temp = I915_READ(_FDI_RXA_MISC);
 692                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 693                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 694                 I915_WRITE(_FDI_RXA_MISC, temp);
 695                 POSTING_READ(_FDI_RXA_MISC);
 696         }
 697
 698         DRM_ERROR("FDI link training failed!\n");
 699 }
 700
 701 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 702 {
 703         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 704         struct intel_digital_port *intel_dig_port =
 705                 enc_to_dig_port(&encoder->base);
 706
 707         intel_dp->DP = intel_dig_port->saved_port_bits |
 708                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 709         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 710
 711 }
 712
 713 static struct intel_encoder *
 714 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 715 {
 716         struct drm_device *dev = crtc->dev;
 717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 718         struct intel_encoder *intel_encoder, *ret = NULL;
 719         int num_encoders = 0;
 720
 721         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 722                 ret = intel_encoder;
 723                 num_encoders++;
 724         }
 725
 726         if (num_encoders != 1)
 727                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 728                      pipe_name(intel_crtc->pipe));
 729
 730         BUG_ON(ret == NULL);
 731         return ret;
 732 }
 733
 734 struct intel_encoder *
 735 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 736 {
 737         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 738         struct intel_encoder *ret = NULL;
 739         struct drm_atomic_state *state;
 740         struct drm_connector *connector;
 741         struct drm_connector_state *connector_state;
 742         int num_encoders = 0;
 743         int i;
 744
 745         state = crtc_state->base.state;
 746
 747         for_each_connector_in_state(state, connector, connector_state, i) {
 748                 if (connector_state->crtc != crtc_state->base.crtc)
 749                         continue;
 750
 751                 ret = to_intel_encoder(connector_state->best_encoder);
 752                 num_encoders++;
 753         }
 754
 755         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 756              pipe_name(crtc->pipe));
 757
 758         BUG_ON(ret == NULL);
 759         return ret;
 760 }
 761
 762 #define LC_FREQ 2700
 763 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 764
 765 #define P_MIN 2
 766 #define P_MAX 64
 767 #define P_INC 2
 768
 769 /* Constraints for PLL good behavior */
 770 #define REF_MIN 48
 771 #define REF_MAX 400
 772 #define VCO_MIN 2400
 773 #define VCO_MAX 4800
 774
 775 #define abs_diff(a, b) ({                       \
 776         typeof(a) __a = (a);                    \
 777         typeof(b) __b = (b);                    \
 778         (void) (&__a == &__b);                  \
 779         __a > __b ? (__a - __b) : (__b - __a); })
 780
 781 struct hsw_wrpll_rnp {
 782         unsigned p, n2, r2;
 783 };
 784
 785 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
 786 {
 787         unsigned budget;
 788
 789         switch (clock) {
 790         case 25175000:
 791         case 25200000:
 792         case 27000000:
 793         case 27027000:
 794         case 37762500:
 795         case 37800000:
 796         case 40500000:
 797         case 40541000:
 798         case 54000000:
 799         case 54054000:
 800         case 59341000:
 801         case 59400000:
 802         case 72000000:
 803         case 74176000:
 804         case 74250000:
 805         case 81000000:
 806         case 81081000:
 807         case 89012000:
 808         case 89100000:
 809         case 108000000:
 810         case 108108000:
 811         case 111264000:
 812         case 111375000:
 813         case 148352000:
 814         case 148500000:
 815         case 162000000:
 816         case 162162000:
 817         case 222525000:
 818         case 222750000:
 819         case 296703000:
 820         case 297000000:
 821                 budget = 0;
 822                 break;
 823         case 233500000:
 824         case 245250000:
 825         case 247750000:
 826         case 253250000:
 827         case 298000000:
 828                 budget = 1500;
 829                 break;
 830         case 169128000:
 831         case 169500000:
 832         case 179500000:
 833         case 202000000:
 834                 budget = 2000;
 835                 break;
 836         case 256250000:
 837         case 262500000:
 838         case 270000000:
 839         case 272500000:
 840         case 273750000:
 841         case 280750000:
 842         case 281250000:
 843         case 286000000:
 844         case 291750000:
 845                 budget = 4000;
 846                 break;
 847         case 267250000:
 848         case 268500000:
 849                 budget = 5000;
 850                 break;
 851         default:
 852                 budget = 1000;
 853                 break;
 854         }
 855
 856         return budget;
 857 }
 858
 859 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 860                                  unsigned r2, unsigned n2, unsigned p,
 861                                  struct hsw_wrpll_rnp *best)
 862 {
 863         uint64_t a, b, c, d, diff, diff_best;
 864
 865         /* No best (r,n,p) yet */
 866         if (best->p == 0) {
 867                 best->p = p;
 868                 best->n2 = n2;
 869                 best->r2 = r2;
 870                 return;
 871         }
 872
 873         /*
 874          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 875          * freq2k.
 876          *
 877          * delta = 1e6 *
 878          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 879          *         freq2k;
 880          *
 881          * and we would like delta <= budget.
 882          *
 883          * If the discrepancy is above the PPM-based budget, always prefer to
 884          * improve upon the previous solution.  However, if you're within the
 885          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 886          */
 887         a = freq2k * budget * p * r2;
 888         b = freq2k * budget * best->p * best->r2;
 889         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 890         diff_best = abs_diff(freq2k * best->p * best->r2,
 891                              LC_FREQ_2K * best->n2);
 892         c = 1000000 * diff;
 893         d = 1000000 * diff_best;
 894
 895         if (a < c && b < d) {
 896                 /* If both are above the budget, pick the closer */
 897                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 898                         best->p = p;
 899                         best->n2 = n2;
 900                         best->r2 = r2;
 901                 }
 902         } else if (a >= c && b < d) {
 903                 /* If A is below the threshold but B is above it?  Update. */
 904                 best->p = p;
 905                 best->n2 = n2;
 906                 best->r2 = r2;
 907         } else if (a >= c && b >= d) {
 908                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 909                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 910                         best->p = p;
 911                         best->n2 = n2;
 912                         best->r2 = r2;
 913                 }
 914         }
 915         /* Otherwise a < c && b >= d, do nothing */
 916 }
 917
 918 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
 919 {
 920         int refclk = LC_FREQ;
 921         int n, p, r;
 922         u32 wrpll;
 923
 924         wrpll = I915_READ(reg);
 925         switch (wrpll & WRPLL_PLL_REF_MASK) {
 926         case WRPLL_PLL_SSC:
 927         case WRPLL_PLL_NON_SSC:
 928                 /*
 929                  * We could calculate spread here, but our checking
 930                  * code only cares about 5% accuracy, and spread is a max of
 931                  * 0.5% downspread.
 932                  */
 933                 refclk = 135;
 934                 break;
 935         case WRPLL_PLL_LCPLL:
 936                 refclk = LC_FREQ;
 937                 break;
 938         default:
 939                 WARN(1, "bad wrpll refclk\n");
 940                 return 0;
 941         }
 942
 943         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 944         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 945         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 946
 947         /* Convert to KHz, p & r have a fixed point portion */
 948         return (refclk * n * 100) / (p * r);
 949 }
 950
 951 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 952                                uint32_t dpll)
 953 {
 954         uint32_t cfgcr1_reg, cfgcr2_reg;
 955         uint32_t cfgcr1_val, cfgcr2_val;
 956         uint32_t p0, p1, p2, dco_freq;
 957
 958         cfgcr1_reg = GET_CFG_CR1_REG(dpll);
 959         cfgcr2_reg = GET_CFG_CR2_REG(dpll);
 960
 961         cfgcr1_val = I915_READ(cfgcr1_reg);
 962         cfgcr2_val = I915_READ(cfgcr2_reg);
 963
 964         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 965         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 966
 967         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 968                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 969         else
 970                 p1 = 1;
 971
 972
 973         switch (p0) {
 974         case DPLL_CFGCR2_PDIV_1:
 975                 p0 = 1;
 976                 break;
 977         case DPLL_CFGCR2_PDIV_2:
 978                 p0 = 2;
 979                 break;
 980         case DPLL_CFGCR2_PDIV_3:
 981                 p0 = 3;
 982                 break;
 983         case DPLL_CFGCR2_PDIV_7:
 984                 p0 = 7;
 985                 break;
 986         }
 987
 988         switch (p2) {
 989         case DPLL_CFGCR2_KDIV_5:
 990                 p2 = 5;
 991                 break;
 992         case DPLL_CFGCR2_KDIV_2:
 993                 p2 = 2;
 994                 break;
 995         case DPLL_CFGCR2_KDIV_3:
 996                 p2 = 3;
 997                 break;
 998         case DPLL_CFGCR2_KDIV_1:
 999                 p2 = 1;
1000                 break;
1001         }
1002
1003         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1004
1005         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1006                 1000) / 0x8000;
1007
1008         return dco_freq / (p0 * p1 * p2 * 5);
1009 }
1010
1011 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1012 {
1013         int dotclock;
1014
1015         if (pipe_config->has_pch_encoder)
1016                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1017                                                     &pipe_config->fdi_m_n);
1018         else if (pipe_config->has_dp_encoder)
1019                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1020                                                     &pipe_config->dp_m_n);
1021         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1022                 dotclock = pipe_config->port_clock * 2 / 3;
1023         else
1024                 dotclock = pipe_config->port_clock;
1025
1026         if (pipe_config->pixel_multiplier)
1027                 dotclock /= pipe_config->pixel_multiplier;
1028
1029         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1030 }
1031
1032 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1033                                 struct intel_crtc_state *pipe_config)
1034 {
1035         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1036         int link_clock = 0;
1037         uint32_t dpll_ctl1, dpll;
1038
1039         dpll = pipe_config->ddi_pll_sel;
1040
1041         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1042
1043         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1044                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1045         } else {
1046                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1047                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1048
1049                 switch (link_clock) {
1050                 case DPLL_CTRL1_LINK_RATE_810:
1051                         link_clock = 81000;
1052                         break;
1053                 case DPLL_CTRL1_LINK_RATE_1080:
1054                         link_clock = 108000;
1055                         break;
1056                 case DPLL_CTRL1_LINK_RATE_1350:
1057                         link_clock = 135000;
1058                         break;
1059                 case DPLL_CTRL1_LINK_RATE_1620:
1060                         link_clock = 162000;
1061                         break;
1062                 case DPLL_CTRL1_LINK_RATE_2160:
1063                         link_clock = 216000;
1064                         break;
1065                 case DPLL_CTRL1_LINK_RATE_2700:
1066                         link_clock = 270000;
1067                         break;
1068                 default:
1069                         WARN(1, "Unsupported link rate\n");
1070                         break;
1071                 }
1072                 link_clock *= 2;
1073         }
1074
1075         pipe_config->port_clock = link_clock;
1076
1077         ddi_dotclock_get(pipe_config);
1078 }
1079
1080 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1081                               struct intel_crtc_state *pipe_config)
1082 {
1083         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1084         int link_clock = 0;
1085         u32 val, pll;
1086
1087         val = pipe_config->ddi_pll_sel;
1088         switch (val & PORT_CLK_SEL_MASK) {
1089         case PORT_CLK_SEL_LCPLL_810:
1090                 link_clock = 81000;
1091                 break;
1092         case PORT_CLK_SEL_LCPLL_1350:
1093                 link_clock = 135000;
1094                 break;
1095         case PORT_CLK_SEL_LCPLL_2700:
1096                 link_clock = 270000;
1097                 break;
1098         case PORT_CLK_SEL_WRPLL1:
1099                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
1100                 break;
1101         case PORT_CLK_SEL_WRPLL2:
1102                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
1103                 break;
1104         case PORT_CLK_SEL_SPLL:
1105                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1106                 if (pll == SPLL_PLL_FREQ_810MHz)
1107                         link_clock = 81000;
1108                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1109                         link_clock = 135000;
1110                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1111                         link_clock = 270000;
1112                 else {
1113                         WARN(1, "bad spll freq\n");
1114                         return;
1115                 }
1116                 break;
1117         default:
1118                 WARN(1, "bad port clock sel\n");
1119                 return;
1120         }
1121
1122         pipe_config->port_clock = link_clock * 2;
1123
1124         ddi_dotclock_get(pipe_config);
1125 }
1126
1127 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1128                                 enum intel_dpll_id dpll)
1129 {
1130         struct intel_shared_dpll *pll;
1131         struct intel_dpll_hw_state *state;
1132         intel_clock_t clock;
1133
1134         /* For DDI ports we always use a shared PLL. */
1135         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1136                 return 0;
1137
1138         pll = &dev_priv->shared_dplls[dpll];
1139         state = &pll->config.hw_state;
1140
1141         clock.m1 = 2;
1142         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1143         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1144                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1145         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1146         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1147         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1148
1149         return chv_calc_dpll_params(100000, &clock);
1150 }
1151
1152 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1153                                 struct intel_crtc_state *pipe_config)
1154 {
1155         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1156         enum port port = intel_ddi_get_encoder_port(encoder);
1157         uint32_t dpll = port;
1158
1159         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1160
1161         ddi_dotclock_get(pipe_config);
1162 }
1163
1164 void intel_ddi_clock_get(struct intel_encoder *encoder,
1165                          struct intel_crtc_state *pipe_config)
1166 {
1167         struct drm_device *dev = encoder->base.dev;
1168
1169         if (INTEL_INFO(dev)->gen <= 8)
1170                 hsw_ddi_clock_get(encoder, pipe_config);
1171         else if (IS_SKYLAKE(dev))
1172                 skl_ddi_clock_get(encoder, pipe_config);
1173         else if (IS_BROXTON(dev))
1174                 bxt_ddi_clock_get(encoder, pipe_config);
1175 }
1176
1177 static void
1178 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1179                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1180 {
1181         uint64_t freq2k;
1182         unsigned p, n2, r2;
1183         struct hsw_wrpll_rnp best = { 0, 0, 0 };
1184         unsigned budget;
1185
1186         freq2k = clock / 100;
1187
1188         budget = hsw_wrpll_get_budget_for_freq(clock);
1189
1190         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1191          * and directly pass the LC PLL to it. */
1192         if (freq2k == 5400000) {
1193                 *n2_out = 2;
1194                 *p_out = 1;
1195                 *r2_out = 2;
1196                 return;
1197         }
1198
1199         /*
1200          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1201          * the WR PLL.
1202          *
1203          * We want R so that REF_MIN <= Ref <= REF_MAX.
1204          * Injecting R2 = 2 * R gives:
1205          *   REF_MAX * r2 > LC_FREQ * 2 and
1206          *   REF_MIN * r2 < LC_FREQ * 2
1207          *
1208          * Which means the desired boundaries for r2 are:
1209          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1210          *
1211          */
1212         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1213              r2 <= LC_FREQ * 2 / REF_MIN;
1214              r2++) {
1215
1216                 /*
1217                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1218                  *
1219                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1220                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1221                  *   VCO_MAX * r2 > n2 * LC_FREQ and
1222                  *   VCO_MIN * r2 < n2 * LC_FREQ)
1223                  *
1224                  * Which means the desired boundaries for n2 are:
1225                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1226                  */
1227                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1228                      n2 <= VCO_MAX * r2 / LC_FREQ;
1229                      n2++) {
1230
1231                         for (p = P_MIN; p <= P_MAX; p += P_INC)
1232                                 hsw_wrpll_update_rnp(freq2k, budget,
1233                                                      r2, n2, p, &best);
1234                 }
1235         }
1236
1237         *n2_out = best.n2;
1238         *p_out = best.p;
1239         *r2_out = best.r2;
1240 }
1241
1242 static bool
1243 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1244                    struct intel_crtc_state *crtc_state,
1245                    struct intel_encoder *intel_encoder,
1246                    int clock)
1247 {
1248         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1249                 struct intel_shared_dpll *pll;
1250                 uint32_t val;
1251                 unsigned p, n2, r2;
1252
1253                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1254
1255                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1256                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1257                       WRPLL_DIVIDER_POST(p);
1258
1259                 memset(&crtc_state->dpll_hw_state, 0,
1260                        sizeof(crtc_state->dpll_hw_state));
1261
1262                 crtc_state->dpll_hw_state.wrpll = val;
1263
1264                 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1265                 if (pll == NULL) {
1266                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1267                                          pipe_name(intel_crtc->pipe));
1268                         return false;
1269                 }
1270
1271                 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1272         }
1273
1274         return true;
1275 }
1276
1277 struct skl_wrpll_context {
1278         uint64_t min_deviation;         /* current minimal deviation */
1279         uint64_t central_freq;          /* chosen central freq */
1280         uint64_t dco_freq;              /* chosen dco freq */
1281         unsigned int p;                 /* chosen divider */
1282 };
1283
1284 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1285 {
1286         memset(ctx, 0, sizeof(*ctx));
1287
1288         ctx->min_deviation = U64_MAX;
1289 }
1290
1291 /* DCO freq must be within +1%/-6%  of the DCO central freq */
1292 #define SKL_DCO_MAX_PDEVIATION  100
1293 #define SKL_DCO_MAX_NDEVIATION  600
1294
1295 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1296                                   uint64_t central_freq,
1297                                   uint64_t dco_freq,
1298                                   unsigned int divider)
1299 {
1300         uint64_t deviation;
1301
1302         deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1303                               central_freq);
1304
1305         /* positive deviation */
1306         if (dco_freq >= central_freq) {
1307                 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1308                     deviation < ctx->min_deviation) {
1309                         ctx->min_deviation = deviation;
1310                         ctx->central_freq = central_freq;
1311                         ctx->dco_freq = dco_freq;
1312                         ctx->p = divider;
1313                 }
1314         /* negative deviation */
1315         } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1316                    deviation < ctx->min_deviation) {
1317                 ctx->min_deviation = deviation;
1318                 ctx->central_freq = central_freq;
1319                 ctx->dco_freq = dco_freq;
1320                 ctx->p = divider;
1321         }
1322 }
1323
1324 static void skl_wrpll_get_multipliers(unsigned int p,
1325                                       unsigned int *p0 /* out */,
1326                                       unsigned int *p1 /* out */,
1327                                       unsigned int *p2 /* out */)
1328 {
1329         /* even dividers */
1330         if (p % 2 == 0) {
1331                 unsigned int half = p / 2;
1332
1333                 if (half == 1 || half == 2 || half == 3 || half == 5) {
1334                         *p0 = 2;
1335                         *p1 = 1;
1336                         *p2 = half;
1337                 } else if (half % 2 == 0) {
1338                         *p0 = 2;
1339                         *p1 = half / 2;
1340                         *p2 = 2;
1341                 } else if (half % 3 == 0) {
1342                         *p0 = 3;
1343                         *p1 = half / 3;
1344                         *p2 = 2;
1345                 } else if (half % 7 == 0) {
1346                         *p0 = 7;
1347                         *p1 = half / 7;
1348                         *p2 = 2;
1349                 }
1350         } else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
1351                 *p0 = 3;
1352                 *p1 = 1;
1353                 *p2 = p / 3;
1354         } else if (p == 5 || p == 7) {
1355                 *p0 = p;
1356                 *p1 = 1;
1357                 *p2 = 1;
1358         } else if (p == 15) {
1359                 *p0 = 3;
1360                 *p1 = 1;
1361                 *p2 = 5;
1362         } else if (p == 21) {
1363                 *p0 = 7;
1364                 *p1 = 1;
1365                 *p2 = 3;
1366         } else if (p == 35) {
1367                 *p0 = 7;
1368                 *p1 = 1;
1369                 *p2 = 5;
1370         }
1371 }
1372
1373 struct skl_wrpll_params {
1374         uint32_t        dco_fraction;
1375         uint32_t        dco_integer;
1376         uint32_t        qdiv_ratio;
1377         uint32_t        qdiv_mode;
1378         uint32_t        kdiv;
1379         uint32_t        pdiv;
1380         uint32_t        central_freq;
1381 };
1382
1383 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1384                                       uint64_t afe_clock,
1385                                       uint64_t central_freq,
1386                                       uint32_t p0, uint32_t p1, uint32_t p2)
1387 {
1388         uint64_t dco_freq;
1389
1390         switch (central_freq) {
1391         case 9600000000ULL:
1392                 params->central_freq = 0;
1393                 break;
1394         case 9000000000ULL:
1395                 params->central_freq = 1;
1396                 break;
1397         case 8400000000ULL:
1398                 params->central_freq = 3;
1399         }
1400
1401         switch (p0) {
1402         case 1:
1403                 params->pdiv = 0;
1404                 break;
1405         case 2:
1406                 params->pdiv = 1;
1407                 break;
1408         case 3:
1409                 params->pdiv = 2;
1410                 break;
1411         case 7:
1412                 params->pdiv = 4;
1413                 break;
1414         default:
1415                 WARN(1, "Incorrect PDiv\n");
1416         }
1417
1418         switch (p2) {
1419         case 5:
1420                 params->kdiv = 0;
1421                 break;
1422         case 2:
1423                 params->kdiv = 1;
1424                 break;
1425         case 3:
1426                 params->kdiv = 2;
1427                 break;
1428         case 1:
1429                 params->kdiv = 3;
1430                 break;
1431         default:
1432                 WARN(1, "Incorrect KDiv\n");
1433         }
1434
1435         params->qdiv_ratio = p1;
1436         params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1437
1438         dco_freq = p0 * p1 * p2 * afe_clock;
1439
1440         /*
1441          * Intermediate values are in Hz.
1442          * Divide by MHz to match bsepc
1443          */
1444         params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1445         params->dco_fraction =
1446                 div_u64((div_u64(dco_freq, 24) -
1447                          params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1448 }
1449
1450 static bool
1451 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1452                         struct skl_wrpll_params *wrpll_params)
1453 {
1454         uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1455         uint64_t dco_central_freq[3] = {8400000000ULL,
1456                                         9000000000ULL,
1457                                         9600000000ULL};
1458         static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
1459                                              24, 28, 30, 32, 36, 40, 42, 44,
1460                                              48, 52, 54, 56, 60, 64, 66, 68,
1461                                              70, 72, 76, 78, 80, 84, 88, 90,
1462                                              92, 96, 98 };
1463         static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1464         static const struct {
1465                 const int *list;
1466                 int n_dividers;
1467         } dividers[] = {
1468                 { even_dividers, ARRAY_SIZE(even_dividers) },
1469                 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1470         };
1471         struct skl_wrpll_context ctx;
1472         unsigned int dco, d, i;
1473         unsigned int p0, p1, p2;
1474
1475         skl_wrpll_context_init(&ctx);
1476
1477         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1478                 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1479                         for (i = 0; i < dividers[d].n_dividers; i++) {
1480                                 unsigned int p = dividers[d].list[i];
1481                                 uint64_t dco_freq = p * afe_clock;
1482
1483                                 skl_wrpll_try_divider(&ctx,
1484                                                       dco_central_freq[dco],
1485                                                       dco_freq,
1486                                                       p);
1487                                 /*
1488                                  * Skip the remaining dividers if we're sure to
1489                                  * have found the definitive divider, we can't
1490                                  * improve a 0 deviation.
1491                                  */
1492                                 if (ctx.min_deviation == 0)
1493                                         goto skip_remaining_dividers;
1494                         }
1495                 }
1496
1497 skip_remaining_dividers:
1498                 /*
1499                  * If a solution is found with an even divider, prefer
1500                  * this one.
1501                  */
1502                 if (d == 0 && ctx.p)
1503                         break;
1504         }
1505
1506         if (!ctx.p) {
1507                 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1508                 return false;
1509         }
1510
1511         /*
1512          * gcc incorrectly analyses that these can be used without being
1513          * initialized. To be fair, it's hard to guess.
1514          */
1515         p0 = p1 = p2 = 0;
1516         skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1517         skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1518                                   p0, p1, p2);
1519
1520         return true;
1521 }
1522
1523 static bool
1524 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1525                    struct intel_crtc_state *crtc_state,
1526                    struct intel_encoder *intel_encoder,
1527                    int clock)
1528 {
1529         struct intel_shared_dpll *pll;
1530         uint32_t ctrl1, cfgcr1, cfgcr2;
1531
1532         /*
1533          * See comment in intel_dpll_hw_state to understand why we always use 0
1534          * as the DPLL id in this function.
1535          */
1536
1537         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1538
1539         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1540                 struct skl_wrpll_params wrpll_params = { 0, };
1541
1542                 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1543
1544                 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1545                         return false;
1546
1547                 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1548                          DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1549                          wrpll_params.dco_integer;
1550
1551                 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1552                          DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1553                          DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1554                          DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1555                          wrpll_params.central_freq;
1556         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1557                 switch (crtc_state->port_clock / 2) {
1558                 case 81000:
1559                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1560                         break;
1561                 case 135000:
1562                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1563                         break;
1564                 case 270000:
1565                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1566                         break;
1567                 }
1568
1569                 cfgcr1 = cfgcr2 = 0;
1570         } else /* eDP */
1571                 return true;
1572
1573         memset(&crtc_state->dpll_hw_state, 0,
1574                sizeof(crtc_state->dpll_hw_state));
1575
1576         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1577         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1578         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1579
1580         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1581         if (pll == NULL) {
1582                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1583                                  pipe_name(intel_crtc->pipe));
1584                 return false;
1585         }
1586
1587         /* shared DPLL id 0 is DPLL 1 */
1588         crtc_state->ddi_pll_sel = pll->id + 1;
1589
1590         return true;
1591 }
1592
1593 /* bxt clock parameters */
1594 struct bxt_clk_div {
1595         int clock;
1596         uint32_t p1;
1597         uint32_t p2;
1598         uint32_t m2_int;
1599         uint32_t m2_frac;
1600         bool m2_frac_en;
1601         uint32_t n;
1602 };
1603
1604 /* pre-calculated values for DP linkrates */
1605 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1606         {162000, 4, 2, 32, 1677722, 1, 1},
1607         {270000, 4, 1, 27,       0, 0, 1},
1608         {540000, 2, 1, 27,       0, 0, 1},
1609         {216000, 3, 2, 32, 1677722, 1, 1},
1610         {243000, 4, 1, 24, 1258291, 1, 1},
1611         {324000, 4, 1, 32, 1677722, 1, 1},
1612         {432000, 3, 1, 32, 1677722, 1, 1}
1613 };
1614
1615 static bool
1616 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1617                    struct intel_crtc_state *crtc_state,
1618                    struct intel_encoder *intel_encoder,
1619                    int clock)
1620 {
1621         struct intel_shared_dpll *pll;
1622         struct bxt_clk_div clk_div = {0};
1623         int vco = 0;
1624         uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1625         uint32_t lanestagger;
1626
1627         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1628                 intel_clock_t best_clock;
1629
1630                 /* Calculate HDMI div */
1631                 /*
1632                  * FIXME: tie the following calculation into
1633                  * i9xx_crtc_compute_clock
1634                  */
1635                 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1636                         DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1637                                          clock, pipe_name(intel_crtc->pipe));
1638                         return false;
1639                 }
1640
1641                 clk_div.p1 = best_clock.p1;
1642                 clk_div.p2 = best_clock.p2;
1643                 WARN_ON(best_clock.m1 != 2);
1644                 clk_div.n = best_clock.n;
1645                 clk_div.m2_int = best_clock.m2 >> 22;
1646                 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1647                 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1648
1649                 vco = best_clock.vco;
1650         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1651                         intel_encoder->type == INTEL_OUTPUT_EDP) {
1652                 int i;
1653
1654                 clk_div = bxt_dp_clk_val[0];
1655                 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1656                         if (bxt_dp_clk_val[i].clock == clock) {
1657                                 clk_div = bxt_dp_clk_val[i];
1658                                 break;
1659                         }
1660                 }
1661                 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1662         }
1663
1664         if (vco >= 6200000 && vco <= 6700000) {
1665                 prop_coef = 4;
1666                 int_coef = 9;
1667                 gain_ctl = 3;
1668                 targ_cnt = 8;
1669         } else if ((vco > 5400000 && vco < 6200000) ||
1670                         (vco >= 4800000 && vco < 5400000)) {
1671                 prop_coef = 5;
1672                 int_coef = 11;
1673                 gain_ctl = 3;
1674                 targ_cnt = 9;
1675         } else if (vco == 5400000) {
1676                 prop_coef = 3;
1677                 int_coef = 8;
1678                 gain_ctl = 1;
1679                 targ_cnt = 9;
1680         } else {
1681                 DRM_ERROR("Invalid VCO\n");
1682                 return false;
1683         }
1684
1685         memset(&crtc_state->dpll_hw_state, 0,
1686                sizeof(crtc_state->dpll_hw_state));
1687
1688         if (clock > 270000)
1689                 lanestagger = 0x18;
1690         else if (clock > 135000)
1691                 lanestagger = 0x0d;
1692         else if (clock > 67000)
1693                 lanestagger = 0x07;
1694         else if (clock > 33000)
1695                 lanestagger = 0x04;
1696         else
1697                 lanestagger = 0x02;
1698
1699         crtc_state->dpll_hw_state.ebb0 =
1700                 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1701         crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1702         crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1703         crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1704
1705         if (clk_div.m2_frac_en)
1706                 crtc_state->dpll_hw_state.pll3 =
1707                         PORT_PLL_M2_FRAC_ENABLE;
1708
1709         crtc_state->dpll_hw_state.pll6 =
1710                 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1711         crtc_state->dpll_hw_state.pll6 |=
1712                 PORT_PLL_GAIN_CTL(gain_ctl);
1713
1714         crtc_state->dpll_hw_state.pll8 = targ_cnt;
1715
1716         crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1717
1718         crtc_state->dpll_hw_state.pll10 =
1719                 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1720                 | PORT_PLL_DCO_AMP_OVR_EN_H;
1721
1722         crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1723
1724         crtc_state->dpll_hw_state.pcsdw12 =
1725                 LANESTAGGER_STRAP_OVRD | lanestagger;
1726
1727         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1728         if (pll == NULL) {
1729                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1730                         pipe_name(intel_crtc->pipe));
1731                 return false;
1732         }
1733
1734         /* shared DPLL id 0 is DPLL A */
1735         crtc_state->ddi_pll_sel = pll->id;
1736
1737         return true;
1738 }
1739
1740 /*
1741  * Tries to find a *shared* PLL for the CRTC and store it in
1742  * intel_crtc->ddi_pll_sel.
1743  *
1744  * For private DPLLs, compute_config() should do the selection for us. This
1745  * function should be folded into compute_config() eventually.
1746  */
1747 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1748                           struct intel_crtc_state *crtc_state)
1749 {
1750         struct drm_device *dev = intel_crtc->base.dev;
1751         struct intel_encoder *intel_encoder =
1752                 intel_ddi_get_crtc_new_encoder(crtc_state);
1753         int clock = crtc_state->port_clock;
1754
1755         if (IS_SKYLAKE(dev))
1756                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1757                                           intel_encoder, clock);
1758         else if (IS_BROXTON(dev))
1759                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1760                                           intel_encoder, clock);
1761         else
1762                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1763                                           intel_encoder, clock);
1764 }
1765
1766 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1767 {
1768         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1770         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1771         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1772         int type = intel_encoder->type;
1773         uint32_t temp;
1774
1775         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1776                 temp = TRANS_MSA_SYNC_CLK;
1777                 switch (intel_crtc->config->pipe_bpp) {
1778                 case 18:
1779                         temp |= TRANS_MSA_6_BPC;
1780                         break;
1781                 case 24:
1782                         temp |= TRANS_MSA_8_BPC;
1783                         break;
1784                 case 30:
1785                         temp |= TRANS_MSA_10_BPC;
1786                         break;
1787                 case 36:
1788                         temp |= TRANS_MSA_12_BPC;
1789                         break;
1790                 default:
1791                         BUG();
1792                 }
1793                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1794         }
1795 }
1796
1797 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1798 {
1799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1800         struct drm_device *dev = crtc->dev;
1801         struct drm_i915_private *dev_priv = dev->dev_private;
1802         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1803         uint32_t temp;
1804         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1805         if (state == true)
1806                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1807         else
1808                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1809         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1810 }
1811
1812 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1813 {
1814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1815         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1816         struct drm_encoder *encoder = &intel_encoder->base;
1817         struct drm_device *dev = crtc->dev;
1818         struct drm_i915_private *dev_priv = dev->dev_private;
1819         enum pipe pipe = intel_crtc->pipe;
1820         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1821         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1822         int type = intel_encoder->type;
1823         uint32_t temp;
1824
1825         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1826         temp = TRANS_DDI_FUNC_ENABLE;
1827         temp |= TRANS_DDI_SELECT_PORT(port);
1828
1829         switch (intel_crtc->config->pipe_bpp) {
1830         case 18:
1831                 temp |= TRANS_DDI_BPC_6;
1832                 break;
1833         case 24:
1834                 temp |= TRANS_DDI_BPC_8;
1835                 break;
1836         case 30:
1837                 temp |= TRANS_DDI_BPC_10;
1838                 break;
1839         case 36:
1840                 temp |= TRANS_DDI_BPC_12;
1841                 break;
1842         default:
1843                 BUG();
1844         }
1845
1846         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1847                 temp |= TRANS_DDI_PVSYNC;
1848         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1849                 temp |= TRANS_DDI_PHSYNC;
1850
1851         if (cpu_transcoder == TRANSCODER_EDP) {
1852                 switch (pipe) {
1853                 case PIPE_A:
1854                         /* On Haswell, can only use the always-on power well for
1855                          * eDP when not using the panel fitter, and when not
1856                          * using motion blur mitigation (which we don't
1857                          * support). */
1858                         if (IS_HASWELL(dev) &&
1859                             (intel_crtc->config->pch_pfit.enabled ||
1860                              intel_crtc->config->pch_pfit.force_thru))
1861                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1862                         else
1863                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1864                         break;
1865                 case PIPE_B:
1866                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1867                         break;
1868                 case PIPE_C:
1869                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1870                         break;
1871                 default:
1872                         BUG();
1873                         break;
1874                 }
1875         }
1876
1877         if (type == INTEL_OUTPUT_HDMI) {
1878                 if (intel_crtc->config->has_hdmi_sink)
1879                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1880                 else
1881                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1882
1883         } else if (type == INTEL_OUTPUT_ANALOG) {
1884                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1885                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1886
1887         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1888                    type == INTEL_OUTPUT_EDP) {
1889                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1890
1891                 if (intel_dp->is_mst) {
1892                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1893                 } else
1894                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1895
1896                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1897         } else if (type == INTEL_OUTPUT_DP_MST) {
1898                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1899
1900                 if (intel_dp->is_mst) {
1901                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1902                 } else
1903                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1904
1905                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1906         } else {
1907                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1908                      intel_encoder->type, pipe_name(pipe));
1909         }
1910
1911         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1912 }
1913
1914 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1915                                        enum transcoder cpu_transcoder)
1916 {
1917         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1918         uint32_t val = I915_READ(reg);
1919
1920         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1921         val |= TRANS_DDI_PORT_NONE;
1922         I915_WRITE(reg, val);
1923 }
1924
1925 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1926 {
1927         struct drm_device *dev = intel_connector->base.dev;
1928         struct drm_i915_private *dev_priv = dev->dev_private;
1929         struct intel_encoder *intel_encoder = intel_connector->encoder;
1930         int type = intel_connector->base.connector_type;
1931         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1932         enum pipe pipe = 0;
1933         enum transcoder cpu_transcoder;
1934         enum intel_display_power_domain power_domain;
1935         uint32_t tmp;
1936
1937         power_domain = intel_display_port_power_domain(intel_encoder);
1938         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1939                 return false;
1940
1941         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1942                 return false;
1943
1944         if (port == PORT_A)
1945                 cpu_transcoder = TRANSCODER_EDP;
1946         else
1947                 cpu_transcoder = (enum transcoder) pipe;
1948
1949         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1950
1951         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1952         case TRANS_DDI_MODE_SELECT_HDMI:
1953         case TRANS_DDI_MODE_SELECT_DVI:
1954                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1955
1956         case TRANS_DDI_MODE_SELECT_DP_SST:
1957                 if (type == DRM_MODE_CONNECTOR_eDP)
1958                         return true;
1959                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1960         case TRANS_DDI_MODE_SELECT_DP_MST:
1961                 /* if the transcoder is in MST state then
1962                  * connector isn't connected */
1963                 return false;
1964
1965         case TRANS_DDI_MODE_SELECT_FDI:
1966                 return (type == DRM_MODE_CONNECTOR_VGA);
1967
1968         default:
1969                 return false;
1970         }
1971 }
1972
1973 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1974                             enum pipe *pipe)
1975 {
1976         struct drm_device *dev = encoder->base.dev;
1977         struct drm_i915_private *dev_priv = dev->dev_private;
1978         enum port port = intel_ddi_get_encoder_port(encoder);
1979         enum intel_display_power_domain power_domain;
1980         u32 tmp;
1981         int i;
1982
1983         power_domain = intel_display_port_power_domain(encoder);
1984         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1985                 return false;
1986
1987         tmp = I915_READ(DDI_BUF_CTL(port));
1988
1989         if (!(tmp & DDI_BUF_CTL_ENABLE))
1990                 return false;
1991
1992         if (port == PORT_A) {
1993                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1994
1995                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1996                 case TRANS_DDI_EDP_INPUT_A_ON:
1997                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1998                         *pipe = PIPE_A;
1999                         break;
2000                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2001                         *pipe = PIPE_B;
2002                         break;
2003                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2004                         *pipe = PIPE_C;
2005                         break;
2006                 }
2007
2008                 return true;
2009         } else {
2010                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2011                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2012
2013                         if ((tmp & TRANS_DDI_PORT_MASK)
2014                             == TRANS_DDI_SELECT_PORT(port)) {
2015                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2016                                         return false;
2017
2018                                 *pipe = i;
2019                                 return true;
2020                         }
2021                 }
2022         }
2023
2024         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2025
2026         return false;
2027 }
2028
2029 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2030 {
2031         struct drm_crtc *crtc = &intel_crtc->base;
2032         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2033         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2034         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2035         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2036
2037         if (cpu_transcoder != TRANSCODER_EDP)
2038                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2039                            TRANS_CLK_SEL_PORT(port));
2040 }
2041
2042 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2043 {
2044         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2045         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2046
2047         if (cpu_transcoder != TRANSCODER_EDP)
2048                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2049                            TRANS_CLK_SEL_DISABLED);
2050 }
2051
2052 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2053                                enum port port, int type)
2054 {
2055         struct drm_i915_private *dev_priv = dev->dev_private;
2056         const struct ddi_buf_trans *ddi_translations;
2057         uint8_t iboost;
2058         uint8_t dp_iboost, hdmi_iboost;
2059         int n_entries;
2060         u32 reg;
2061
2062         /* VBT may override standard boost values */
2063         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2064         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2065
2066         if (type == INTEL_OUTPUT_DISPLAYPORT) {
2067                 if (dp_iboost) {
2068                         iboost = dp_iboost;
2069                 } else {
2070                         ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2071                         iboost = ddi_translations[port].i_boost;
2072                 }
2073         } else if (type == INTEL_OUTPUT_EDP) {
2074                 if (dp_iboost) {
2075                         iboost = dp_iboost;
2076                 } else {
2077                         ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2078                         iboost = ddi_translations[port].i_boost;
2079                 }
2080         } else if (type == INTEL_OUTPUT_HDMI) {
2081                 if (hdmi_iboost) {
2082                         iboost = hdmi_iboost;
2083                 } else {
2084                         ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2085                         iboost = ddi_translations[port].i_boost;
2086                 }
2087         } else {
2088                 return;
2089         }
2090
2091         /* Make sure that the requested I_boost is valid */
2092         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2093                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2094                 return;
2095         }
2096
2097         reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2098         reg &= ~BALANCE_LEG_MASK(port);
2099         reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2100
2101         if (iboost)
2102                 reg |= iboost << BALANCE_LEG_SHIFT(port);
2103         else
2104                 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2105
2106         I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2107 }
2108
2109 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2110                                     enum port port, int type)
2111 {
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113         const struct bxt_ddi_buf_trans *ddi_translations;
2114         u32 n_entries, i;
2115         uint32_t val;
2116
2117         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2118                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2119                 ddi_translations = bxt_ddi_translations_dp;
2120         } else if (type == INTEL_OUTPUT_HDMI) {
2121                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2122                 ddi_translations = bxt_ddi_translations_hdmi;
2123         } else {
2124                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2125                                 type);
2126                 return;
2127         }
2128
2129         /* Check if default value has to be used */
2130         if (level >= n_entries ||
2131             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2132                 for (i = 0; i < n_entries; i++) {
2133                         if (ddi_translations[i].default_index) {
2134                                 level = i;
2135                                 break;
2136                         }
2137                 }
2138         }
2139
2140         /*
2141          * While we write to the group register to program all lanes at once we
2142          * can read only lane registers and we pick lanes 0/1 for that.
2143          */
2144         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2145         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2146         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2147
2148         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2149         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2150         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2151                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2152         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2153
2154         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2155         val &= ~UNIQE_TRANGE_EN_METHOD;
2156         if (ddi_translations[level].enable)
2157                 val |= UNIQE_TRANGE_EN_METHOD;
2158         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2159
2160         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2161         val &= ~DE_EMPHASIS;
2162         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2163         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2164
2165         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2166         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2167         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2168 }
2169
2170 static uint32_t translate_signal_level(int signal_levels)
2171 {
2172         uint32_t level;
2173
2174         switch (signal_levels) {
2175         default:
2176                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2177                               signal_levels);
2178         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2179                 level = 0;
2180                 break;
2181         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2182                 level = 1;
2183                 break;
2184         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2185                 level = 2;
2186                 break;
2187         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2188                 level = 3;
2189                 break;
2190
2191         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2192                 level = 4;
2193                 break;
2194         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2195                 level = 5;
2196                 break;
2197         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2198                 level = 6;
2199                 break;
2200
2201         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2202                 level = 7;
2203                 break;
2204         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2205                 level = 8;
2206                 break;
2207
2208         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2209                 level = 9;
2210                 break;
2211         }
2212
2213         return level;
2214 }
2215
2216 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2217 {
2218         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2219         struct drm_device *dev = dport->base.base.dev;
2220         struct intel_encoder *encoder = &dport->base;
2221         uint8_t train_set = intel_dp->train_set[0];
2222         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2223                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2224         enum port port = dport->port;
2225         uint32_t level;
2226
2227         level = translate_signal_level(signal_levels);
2228
2229         if (IS_SKYLAKE(dev))
2230                 skl_ddi_set_iboost(dev, level, port, encoder->type);
2231         else if (IS_BROXTON(dev))
2232                 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2233
2234         return DDI_BUF_TRANS_SELECT(level);
2235 }
2236
2237 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2238 {
2239         struct drm_encoder *encoder = &intel_encoder->base;
2240         struct drm_device *dev = encoder->dev;
2241         struct drm_i915_private *dev_priv = dev->dev_private;
2242         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2243         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2244         int type = intel_encoder->type;
2245         int hdmi_level;
2246
2247         if (type == INTEL_OUTPUT_EDP) {
2248                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2249                 intel_edp_panel_on(intel_dp);
2250         }
2251
2252         if (IS_SKYLAKE(dev)) {
2253                 uint32_t dpll = crtc->config->ddi_pll_sel;
2254                 uint32_t val;
2255
2256                 /*
2257                  * DPLL0 is used for eDP and is the only "private" DPLL (as
2258                  * opposed to shared) on SKL
2259                  */
2260                 if (type == INTEL_OUTPUT_EDP) {
2261                         WARN_ON(dpll != SKL_DPLL0);
2262
2263                         val = I915_READ(DPLL_CTRL1);
2264
2265                         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2266                                  DPLL_CTRL1_SSC(dpll) |
2267                                  DPLL_CTRL1_LINK_RATE_MASK(dpll));
2268                         val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
2269
2270                         I915_WRITE(DPLL_CTRL1, val);
2271                         POSTING_READ(DPLL_CTRL1);
2272                 }
2273
2274                 /* DDI -> PLL mapping  */
2275                 val = I915_READ(DPLL_CTRL2);
2276
2277                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2278                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2279                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2280                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2281
2282                 I915_WRITE(DPLL_CTRL2, val);
2283
2284         } else if (INTEL_INFO(dev)->gen < 9) {
2285                 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2286                 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
2287         }
2288
2289         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2290                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2291
2292                 intel_ddi_init_dp_buf_reg(intel_encoder);
2293
2294                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2295                 intel_dp_start_link_train(intel_dp);
2296                 intel_dp_complete_link_train(intel_dp);
2297                 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
2298                         intel_dp_stop_link_train(intel_dp);
2299         } else if (type == INTEL_OUTPUT_HDMI) {
2300                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2301
2302                 if (IS_BROXTON(dev)) {
2303                         hdmi_level = dev_priv->vbt.
2304                                 ddi_port_info[port].hdmi_level_shift;
2305                         bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2306                                         INTEL_OUTPUT_HDMI);
2307                 }
2308                 intel_hdmi->set_infoframes(encoder,
2309                                            crtc->config->has_hdmi_sink,
2310                                            &crtc->config->base.adjusted_mode);
2311         }
2312 }
2313
2314 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2315 {
2316         struct drm_encoder *encoder = &intel_encoder->base;
2317         struct drm_device *dev = encoder->dev;
2318         struct drm_i915_private *dev_priv = dev->dev_private;
2319         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2320         int type = intel_encoder->type;
2321         uint32_t val;
2322         bool wait = false;
2323
2324         val = I915_READ(DDI_BUF_CTL(port));
2325         if (val & DDI_BUF_CTL_ENABLE) {
2326                 val &= ~DDI_BUF_CTL_ENABLE;
2327                 I915_WRITE(DDI_BUF_CTL(port), val);
2328                 wait = true;
2329         }
2330
2331         val = I915_READ(DP_TP_CTL(port));
2332         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2333         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2334         I915_WRITE(DP_TP_CTL(port), val);
2335
2336         if (wait)
2337                 intel_wait_ddi_buf_idle(dev_priv, port);
2338
2339         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2340                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2341                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2342                 intel_edp_panel_vdd_on(intel_dp);
2343                 intel_edp_panel_off(intel_dp);
2344         }
2345
2346         if (IS_SKYLAKE(dev))
2347                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2348                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
2349         else if (INTEL_INFO(dev)->gen < 9)
2350                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2351 }
2352
2353 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2354 {
2355         struct drm_encoder *encoder = &intel_encoder->base;
2356         struct drm_crtc *crtc = encoder->crtc;
2357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2358         struct drm_device *dev = encoder->dev;
2359         struct drm_i915_private *dev_priv = dev->dev_private;
2360         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2361         int type = intel_encoder->type;
2362
2363         if (type == INTEL_OUTPUT_HDMI) {
2364                 struct intel_digital_port *intel_dig_port =
2365                         enc_to_dig_port(encoder);
2366
2367                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2368                  * are ignored so nothing special needs to be done besides
2369                  * enabling the port.
2370                  */
2371                 I915_WRITE(DDI_BUF_CTL(port),
2372                            intel_dig_port->saved_port_bits |
2373                            DDI_BUF_CTL_ENABLE);
2374         } else if (type == INTEL_OUTPUT_EDP) {
2375                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2376
2377                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2378                         intel_dp_stop_link_train(intel_dp);
2379
2380                 intel_edp_backlight_on(intel_dp);
2381                 intel_psr_enable(intel_dp);
2382                 intel_edp_drrs_enable(intel_dp);
2383         }
2384
2385         if (intel_crtc->config->has_audio) {
2386                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2387                 intel_audio_codec_enable(intel_encoder);
2388         }
2389 }
2390
2391 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2392 {
2393         struct drm_encoder *encoder = &intel_encoder->base;
2394         struct drm_crtc *crtc = encoder->crtc;
2395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2396         int type = intel_encoder->type;
2397         struct drm_device *dev = encoder->dev;
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399
2400         if (intel_crtc->config->has_audio) {
2401                 intel_audio_codec_disable(intel_encoder);
2402                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2403         }
2404
2405         if (type == INTEL_OUTPUT_EDP) {
2406                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2407
2408                 intel_edp_drrs_disable(intel_dp);
2409                 intel_psr_disable(intel_dp);
2410                 intel_edp_backlight_off(intel_dp);
2411         }
2412 }
2413
2414 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2415                                struct intel_shared_dpll *pll)
2416 {
2417         I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2418         POSTING_READ(WRPLL_CTL(pll->id));
2419         udelay(20);
2420 }
2421
2422 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2423                                 struct intel_shared_dpll *pll)
2424 {
2425         uint32_t val;
2426
2427         val = I915_READ(WRPLL_CTL(pll->id));
2428         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2429         POSTING_READ(WRPLL_CTL(pll->id));
2430 }
2431
2432 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2433                                      struct intel_shared_dpll *pll,
2434                                      struct intel_dpll_hw_state *hw_state)
2435 {
2436         uint32_t val;
2437
2438         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2439                 return false;
2440
2441         val = I915_READ(WRPLL_CTL(pll->id));
2442         hw_state->wrpll = val;
2443
2444         return val & WRPLL_PLL_ENABLE;
2445 }
2446
2447 static const char * const hsw_ddi_pll_names[] = {
2448         "WRPLL 1",
2449         "WRPLL 2",
2450 };
2451
2452 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2453 {
2454         int i;
2455
2456         dev_priv->num_shared_dpll = 2;
2457
2458         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2459                 dev_priv->shared_dplls[i].id = i;
2460                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2461                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
2462                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
2463                 dev_priv->shared_dplls[i].get_hw_state =
2464                         hsw_ddi_pll_get_hw_state;
2465         }
2466 }
2467
2468 static const char * const skl_ddi_pll_names[] = {
2469         "DPLL 1",
2470         "DPLL 2",
2471         "DPLL 3",
2472 };
2473
2474 struct skl_dpll_regs {
2475         u32 ctl, cfgcr1, cfgcr2;
2476 };
2477
2478 /* this array is indexed by the *shared* pll id */
2479 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2480         {
2481                 /* DPLL 1 */
2482                 .ctl = LCPLL2_CTL,
2483                 .cfgcr1 = DPLL1_CFGCR1,
2484                 .cfgcr2 = DPLL1_CFGCR2,
2485         },
2486         {
2487                 /* DPLL 2 */
2488                 .ctl = WRPLL_CTL1,
2489                 .cfgcr1 = DPLL2_CFGCR1,
2490                 .cfgcr2 = DPLL2_CFGCR2,
2491         },
2492         {
2493                 /* DPLL 3 */
2494                 .ctl = WRPLL_CTL2,
2495                 .cfgcr1 = DPLL3_CFGCR1,
2496                 .cfgcr2 = DPLL3_CFGCR2,
2497         },
2498 };
2499
2500 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2501                                struct intel_shared_dpll *pll)
2502 {
2503         uint32_t val;
2504         unsigned int dpll;
2505         const struct skl_dpll_regs *regs = skl_dpll_regs;
2506
2507         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2508         dpll = pll->id + 1;
2509
2510         val = I915_READ(DPLL_CTRL1);
2511
2512         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2513                  DPLL_CTRL1_LINK_RATE_MASK(dpll));
2514         val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2515
2516         I915_WRITE(DPLL_CTRL1, val);
2517         POSTING_READ(DPLL_CTRL1);
2518
2519         I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2520         I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2521         POSTING_READ(regs[pll->id].cfgcr1);
2522         POSTING_READ(regs[pll->id].cfgcr2);
2523
2524         /* the enable bit is always bit 31 */
2525         I915_WRITE(regs[pll->id].ctl,
2526                    I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2527
2528         if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2529                 DRM_ERROR("DPLL %d not locked\n", dpll);
2530 }
2531
2532 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2533                                 struct intel_shared_dpll *pll)
2534 {
2535         const struct skl_dpll_regs *regs = skl_dpll_regs;
2536
2537         /* the enable bit is always bit 31 */
2538         I915_WRITE(regs[pll->id].ctl,
2539                    I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2540         POSTING_READ(regs[pll->id].ctl);
2541 }
2542
2543 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2544                                      struct intel_shared_dpll *pll,
2545                                      struct intel_dpll_hw_state *hw_state)
2546 {
2547         uint32_t val;
2548         unsigned int dpll;
2549         const struct skl_dpll_regs *regs = skl_dpll_regs;
2550
2551         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2552                 return false;
2553
2554         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2555         dpll = pll->id + 1;
2556
2557         val = I915_READ(regs[pll->id].ctl);
2558         if (!(val & LCPLL_PLL_ENABLE))
2559                 return false;
2560
2561         val = I915_READ(DPLL_CTRL1);
2562         hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2563
2564         /* avoid reading back stale values if HDMI mode is not enabled */
2565         if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2566                 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2567                 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2568         }
2569
2570         return true;
2571 }
2572
2573 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2574 {
2575         int i;
2576
2577         dev_priv->num_shared_dpll = 3;
2578
2579         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2580                 dev_priv->shared_dplls[i].id = i;
2581                 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2582                 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2583                 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2584                 dev_priv->shared_dplls[i].get_hw_state =
2585                         skl_ddi_pll_get_hw_state;
2586         }
2587 }
2588
2589 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2590                              enum dpio_phy phy)
2591 {
2592         enum port port;
2593         uint32_t val;
2594
2595         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2596         val |= GT_DISPLAY_POWER_ON(phy);
2597         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2598
2599         /* Considering 10ms timeout until BSpec is updated */
2600         if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2601                 DRM_ERROR("timeout during PHY%d power on\n", phy);
2602
2603         for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2604              port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2605                 int lane;
2606
2607                 for (lane = 0; lane < 4; lane++) {
2608                         val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2609                         /*
2610                          * Note that on CHV this flag is called UPAR, but has
2611                          * the same function.
2612                          */
2613                         val &= ~LATENCY_OPTIM;
2614                         if (lane != 1)
2615                                 val |= LATENCY_OPTIM;
2616
2617                         I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2618                 }
2619         }
2620
2621         /* Program PLL Rcomp code offset */
2622         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2623         val &= ~IREF0RC_OFFSET_MASK;
2624         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2625         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2626
2627         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2628         val &= ~IREF1RC_OFFSET_MASK;
2629         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2630         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2631
2632         /* Program power gating */
2633         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2634         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2635                 SUS_CLK_CONFIG;
2636         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2637
2638         if (phy == DPIO_PHY0) {
2639                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2640                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2641                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2642         }
2643
2644         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2645         val &= ~OCL2_LDOFUSE_PWR_DIS;
2646         /*
2647          * On PHY1 disable power on the second channel, since no port is
2648          * connected there. On PHY0 both channels have a port, so leave it
2649          * enabled.
2650          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2651          * power down the second channel on PHY0 as well.
2652          */
2653         if (phy == DPIO_PHY1)
2654                 val |= OCL2_LDOFUSE_PWR_DIS;
2655         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2656
2657         if (phy == DPIO_PHY0) {
2658                 uint32_t grc_code;
2659                 /*
2660                  * PHY0 isn't connected to an RCOMP resistor so copy over
2661                  * the corresponding calibrated value from PHY1, and disable
2662                  * the automatic calibration on PHY0.
2663                  */
2664                 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2665                              10))
2666                         DRM_ERROR("timeout waiting for PHY1 GRC\n");
2667
2668                 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2669                 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2670                 grc_code = val << GRC_CODE_FAST_SHIFT |
2671                            val << GRC_CODE_SLOW_SHIFT |
2672                            val;
2673                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2674
2675                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2676                 val |= GRC_DIS | GRC_RDY_OVRD;
2677                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2678         }
2679
2680         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2681         val |= COMMON_RESET_DIS;
2682         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2683 }
2684
2685 void broxton_ddi_phy_init(struct drm_device *dev)
2686 {
2687         /* Enable PHY1 first since it provides Rcomp for PHY0 */
2688         broxton_phy_init(dev->dev_private, DPIO_PHY1);
2689         broxton_phy_init(dev->dev_private, DPIO_PHY0);
2690 }
2691
2692 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2693                                enum dpio_phy phy)
2694 {
2695         uint32_t val;
2696
2697         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2698         val &= ~COMMON_RESET_DIS;
2699         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2700 }
2701
2702 void broxton_ddi_phy_uninit(struct drm_device *dev)
2703 {
2704         struct drm_i915_private *dev_priv = dev->dev_private;
2705
2706         broxton_phy_uninit(dev_priv, DPIO_PHY1);
2707         broxton_phy_uninit(dev_priv, DPIO_PHY0);
2708
2709         /* FIXME: do this in broxton_phy_uninit per phy */
2710         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2711 }
2712
2713 static const char * const bxt_ddi_pll_names[] = {
2714         "PORT PLL A",
2715         "PORT PLL B",
2716         "PORT PLL C",
2717 };
2718
2719 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2720                                 struct intel_shared_dpll *pll)
2721 {
2722         uint32_t temp;
2723         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2724
2725         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2726         temp &= ~PORT_PLL_REF_SEL;
2727         /* Non-SSC reference */
2728         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2729
2730         /* Disable 10 bit clock */
2731         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2732         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2733         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2734
2735         /* Write P1 & P2 */
2736         temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2737         temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2738         temp |= pll->config.hw_state.ebb0;
2739         I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2740
2741         /* Write M2 integer */
2742         temp = I915_READ(BXT_PORT_PLL(port, 0));
2743         temp &= ~PORT_PLL_M2_MASK;
2744         temp |= pll->config.hw_state.pll0;
2745         I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2746
2747         /* Write N */
2748         temp = I915_READ(BXT_PORT_PLL(port, 1));
2749         temp &= ~PORT_PLL_N_MASK;
2750         temp |= pll->config.hw_state.pll1;
2751         I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2752
2753         /* Write M2 fraction */
2754         temp = I915_READ(BXT_PORT_PLL(port, 2));
2755         temp &= ~PORT_PLL_M2_FRAC_MASK;
2756         temp |= pll->config.hw_state.pll2;
2757         I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2758
2759         /* Write M2 fraction enable */
2760         temp = I915_READ(BXT_PORT_PLL(port, 3));
2761         temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2762         temp |= pll->config.hw_state.pll3;
2763         I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2764
2765         /* Write coeff */
2766         temp = I915_READ(BXT_PORT_PLL(port, 6));
2767         temp &= ~PORT_PLL_PROP_COEFF_MASK;
2768         temp &= ~PORT_PLL_INT_COEFF_MASK;
2769         temp &= ~PORT_PLL_GAIN_CTL_MASK;
2770         temp |= pll->config.hw_state.pll6;
2771         I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2772
2773         /* Write calibration val */
2774         temp = I915_READ(BXT_PORT_PLL(port, 8));
2775         temp &= ~PORT_PLL_TARGET_CNT_MASK;
2776         temp |= pll->config.hw_state.pll8;
2777         I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2778
2779         temp = I915_READ(BXT_PORT_PLL(port, 9));
2780         temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2781         temp |= pll->config.hw_state.pll9;
2782         I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2783
2784         temp = I915_READ(BXT_PORT_PLL(port, 10));
2785         temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2786         temp &= ~PORT_PLL_DCO_AMP_MASK;
2787         temp |= pll->config.hw_state.pll10;
2788         I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2789
2790         /* Recalibrate with new settings */
2791         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2792         temp |= PORT_PLL_RECALIBRATE;
2793         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2794         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2795         temp |= pll->config.hw_state.ebb4;
2796         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2797
2798         /* Enable PLL */
2799         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2800         temp |= PORT_PLL_ENABLE;
2801         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2802         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2803
2804         if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2805                         PORT_PLL_LOCK), 200))
2806                 DRM_ERROR("PLL %d not locked\n", port);
2807
2808         /*
2809          * While we write to the group register to program all lanes at once we
2810          * can read only lane registers and we pick lanes 0/1 for that.
2811          */
2812         temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2813         temp &= ~LANE_STAGGER_MASK;
2814         temp &= ~LANESTAGGER_STRAP_OVRD;
2815         temp |= pll->config.hw_state.pcsdw12;
2816         I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2817 }
2818
2819 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2820                                         struct intel_shared_dpll *pll)
2821 {
2822         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2823         uint32_t temp;
2824
2825         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2826         temp &= ~PORT_PLL_ENABLE;
2827         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2828         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2829 }
2830
2831 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2832                                         struct intel_shared_dpll *pll,
2833                                         struct intel_dpll_hw_state *hw_state)
2834 {
2835         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2836         uint32_t val;
2837
2838         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2839                 return false;
2840
2841         val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2842         if (!(val & PORT_PLL_ENABLE))
2843                 return false;
2844
2845         hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2846         hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2847
2848         hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2849         hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2850
2851         hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2852         hw_state->pll0 &= PORT_PLL_M2_MASK;
2853
2854         hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2855         hw_state->pll1 &= PORT_PLL_N_MASK;
2856
2857         hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2858         hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2859
2860         hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2861         hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2862
2863         hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2864         hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2865                           PORT_PLL_INT_COEFF_MASK |
2866                           PORT_PLL_GAIN_CTL_MASK;
2867
2868         hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2869         hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2870
2871         hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2872         hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2873
2874         hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2875         hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2876                            PORT_PLL_DCO_AMP_MASK;
2877
2878         /*
2879          * While we write to the group register to program all lanes at once we
2880          * can read only lane registers. We configure all lanes the same way, so
2881          * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2882          */
2883         hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2884         if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2885                 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2886                                  hw_state->pcsdw12,
2887                                  I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2888         hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2889
2890         return true;
2891 }
2892
2893 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2894 {
2895         int i;
2896
2897         dev_priv->num_shared_dpll = 3;
2898
2899         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2900                 dev_priv->shared_dplls[i].id = i;
2901                 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2902                 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2903                 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2904                 dev_priv->shared_dplls[i].get_hw_state =
2905                         bxt_ddi_pll_get_hw_state;
2906         }
2907 }
2908
2909 void intel_ddi_pll_init(struct drm_device *dev)
2910 {
2911         struct drm_i915_private *dev_priv = dev->dev_private;
2912         uint32_t val = I915_READ(LCPLL_CTL);
2913
2914         if (IS_SKYLAKE(dev))
2915                 skl_shared_dplls_init(dev_priv);
2916         else if (IS_BROXTON(dev))
2917                 bxt_shared_dplls_init(dev_priv);
2918         else
2919                 hsw_shared_dplls_init(dev_priv);
2920
2921         if (IS_SKYLAKE(dev)) {
2922                 int cdclk_freq;
2923
2924                 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2925                 dev_priv->skl_boot_cdclk = cdclk_freq;
2926                 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2927                         DRM_ERROR("LCPLL1 is disabled\n");
2928                 else
2929                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
2930         } else if (IS_BROXTON(dev)) {
2931                 broxton_init_cdclk(dev);
2932                 broxton_ddi_phy_init(dev);
2933         } else {
2934                 /*
2935                  * The LCPLL register should be turned on by the BIOS. For now
2936                  * let's just check its state and print errors in case
2937                  * something is wrong.  Don't even try to turn it on.
2938                  */
2939
2940                 if (val & LCPLL_CD_SOURCE_FCLK)
2941                         DRM_ERROR("CDCLK source is not LCPLL\n");
2942
2943                 if (val & LCPLL_PLL_DISABLE)
2944                         DRM_ERROR("LCPLL is disabled\n");
2945         }
2946 }
2947
2948 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2949 {
2950         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2951         struct intel_dp *intel_dp = &intel_dig_port->dp;
2952         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
2953         enum port port = intel_dig_port->port;
2954         uint32_t val;
2955         bool wait = false;
2956
2957         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2958                 val = I915_READ(DDI_BUF_CTL(port));
2959                 if (val & DDI_BUF_CTL_ENABLE) {
2960                         val &= ~DDI_BUF_CTL_ENABLE;
2961                         I915_WRITE(DDI_BUF_CTL(port), val);
2962                         wait = true;
2963                 }
2964
2965                 val = I915_READ(DP_TP_CTL(port));
2966                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2967                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2968                 I915_WRITE(DP_TP_CTL(port), val);
2969                 POSTING_READ(DP_TP_CTL(port));
2970
2971                 if (wait)
2972                         intel_wait_ddi_buf_idle(dev_priv, port);
2973         }
2974
2975         val = DP_TP_CTL_ENABLE |
2976               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2977         if (intel_dp->is_mst)
2978                 val |= DP_TP_CTL_MODE_MST;
2979         else {
2980                 val |= DP_TP_CTL_MODE_SST;
2981                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2982                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2983         }
2984         I915_WRITE(DP_TP_CTL(port), val);
2985         POSTING_READ(DP_TP_CTL(port));
2986
2987         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2988         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2989         POSTING_READ(DDI_BUF_CTL(port));
2990
2991         udelay(600);
2992 }
2993
2994 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2995 {
2996         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2997         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2998         uint32_t val;
2999
3000         intel_ddi_post_disable(intel_encoder);
3001
3002         val = I915_READ(_FDI_RXA_CTL);
3003         val &= ~FDI_RX_ENABLE;
3004         I915_WRITE(_FDI_RXA_CTL, val);
3005
3006         val = I915_READ(_FDI_RXA_MISC);
3007         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3008         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3009         I915_WRITE(_FDI_RXA_MISC, val);
3010
3011         val = I915_READ(_FDI_RXA_CTL);
3012         val &= ~FDI_PCDCLK;
3013         I915_WRITE(_FDI_RXA_CTL, val);
3014
3015         val = I915_READ(_FDI_RXA_CTL);
3016         val &= ~FDI_RX_PLL_ENABLE;
3017         I915_WRITE(_FDI_RXA_CTL, val);
3018 }
3019
3020 void intel_ddi_get_config(struct intel_encoder *encoder,
3021                           struct intel_crtc_state *pipe_config)
3022 {
3023         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3024         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3025         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3026         struct intel_hdmi *intel_hdmi;
3027         u32 temp, flags = 0;
3028
3029         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3030         if (temp & TRANS_DDI_PHSYNC)
3031                 flags |= DRM_MODE_FLAG_PHSYNC;
3032         else
3033                 flags |= DRM_MODE_FLAG_NHSYNC;
3034         if (temp & TRANS_DDI_PVSYNC)
3035                 flags |= DRM_MODE_FLAG_PVSYNC;
3036         else
3037                 flags |= DRM_MODE_FLAG_NVSYNC;
3038
3039         pipe_config->base.adjusted_mode.flags |= flags;
3040
3041         switch (temp & TRANS_DDI_BPC_MASK) {
3042         case TRANS_DDI_BPC_6:
3043                 pipe_config->pipe_bpp = 18;
3044                 break;
3045         case TRANS_DDI_BPC_8:
3046                 pipe_config->pipe_bpp = 24;
3047                 break;
3048         case TRANS_DDI_BPC_10:
3049                 pipe_config->pipe_bpp = 30;
3050                 break;
3051         case TRANS_DDI_BPC_12:
3052                 pipe_config->pipe_bpp = 36;
3053                 break;
3054         default:
3055                 break;
3056         }
3057
3058         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3059         case TRANS_DDI_MODE_SELECT_HDMI:
3060                 pipe_config->has_hdmi_sink = true;
3061                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3062
3063                 if (intel_hdmi->infoframe_enabled(&encoder->base))
3064                         pipe_config->has_infoframe = true;
3065                 break;
3066         case TRANS_DDI_MODE_SELECT_DVI:
3067         case TRANS_DDI_MODE_SELECT_FDI:
3068                 break;
3069         case TRANS_DDI_MODE_SELECT_DP_SST:
3070         case TRANS_DDI_MODE_SELECT_DP_MST:
3071                 pipe_config->has_dp_encoder = true;
3072                 intel_dp_get_m_n(intel_crtc, pipe_config);
3073                 break;
3074         default:
3075                 break;
3076         }
3077
3078         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3079                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3080                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3081                         pipe_config->has_audio = true;
3082         }
3083
3084         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3085             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3086                 /*
3087                  * This is a big fat ugly hack.
3088                  *
3089                  * Some machines in UEFI boot mode provide us a VBT that has 18
3090                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3091                  * unknown we fail to light up. Yet the same BIOS boots up with
3092                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3093                  * max, not what it tells us to use.
3094                  *
3095                  * Note: This will still be broken if the eDP panel is not lit
3096                  * up by the BIOS, and thus we can't get the mode at module
3097                  * load.
3098                  */
3099                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3100                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3101                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3102         }
3103
3104         intel_ddi_clock_get(encoder, pipe_config);
3105 }
3106
3107 static void intel_ddi_destroy(struct drm_encoder *encoder)
3108 {
3109         /* HDMI has nothing special to destroy, so we can go with this. */
3110         intel_dp_encoder_destroy(encoder);
3111 }
3112
3113 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3114                                      struct intel_crtc_state *pipe_config)
3115 {
3116         int type = encoder->type;
3117         int port = intel_ddi_get_encoder_port(encoder);
3118
3119         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3120
3121         if (port == PORT_A)
3122                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3123
3124         if (type == INTEL_OUTPUT_HDMI)
3125                 return intel_hdmi_compute_config(encoder, pipe_config);
3126         else
3127                 return intel_dp_compute_config(encoder, pipe_config);
3128 }
3129
3130 static const struct drm_encoder_funcs intel_ddi_funcs = {
3131         .destroy = intel_ddi_destroy,
3132 };
3133
3134 static struct intel_connector *
3135 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3136 {
3137         struct intel_connector *connector;
3138         enum port port = intel_dig_port->port;
3139
3140         connector = intel_connector_alloc();
3141         if (!connector)
3142                 return NULL;
3143
3144         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3145         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3146                 kfree(connector);
3147                 return NULL;
3148         }
3149
3150         return connector;
3151 }
3152
3153 static struct intel_connector *
3154 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3155 {
3156         struct intel_connector *connector;
3157         enum port port = intel_dig_port->port;
3158
3159         connector = intel_connector_alloc();
3160         if (!connector)
3161                 return NULL;
3162
3163         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3164         intel_hdmi_init_connector(intel_dig_port, connector);
3165
3166         return connector;
3167 }
3168
3169 void intel_ddi_init(struct drm_device *dev, enum port port)
3170 {
3171         struct drm_i915_private *dev_priv = dev->dev_private;
3172         struct intel_digital_port *intel_dig_port;
3173         struct intel_encoder *intel_encoder;
3174         struct drm_encoder *encoder;
3175         bool init_hdmi, init_dp;
3176
3177         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3178                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3179         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3180         if (!init_dp && !init_hdmi) {
3181                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3182                               port_name(port));
3183                 return;
3184         }
3185
3186         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3187         if (!intel_dig_port)
3188                 return;
3189
3190         intel_encoder = &intel_dig_port->base;
3191         encoder = &intel_encoder->base;
3192
3193         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3194                          DRM_MODE_ENCODER_TMDS);
3195
3196         intel_encoder->compute_config = intel_ddi_compute_config;
3197         intel_encoder->enable = intel_enable_ddi;
3198         intel_encoder->pre_enable = intel_ddi_pre_enable;
3199         intel_encoder->disable = intel_disable_ddi;
3200         intel_encoder->post_disable = intel_ddi_post_disable;
3201         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3202         intel_encoder->get_config = intel_ddi_get_config;
3203
3204         intel_dig_port->port = port;
3205         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3206                                           (DDI_BUF_PORT_REVERSAL |
3207                                            DDI_A_4_LANES);
3208
3209         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3210         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3211         intel_encoder->cloneable = 0;
3212
3213         if (init_dp) {
3214                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3215                         goto err;
3216
3217                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3218                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3219         }
3220
3221         /* In theory we don't need the encoder->type check, but leave it just in
3222          * case we have some really bad VBTs... */
3223         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3224                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3225                         goto err;
3226         }
3227
3228         return;
3229
3230 err:
3231         drm_encoder_cleanup(encoder);
3232         kfree(intel_dig_port);
3233 }