sound/pci/ens1370.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   4  *  Copyright (c) by Jaroslav Kysela <[email protected]>,
   5  *                   Thomas Sailer <[email protected]>
   6  */
   7
   8 /* Power-Management-Code ( CONFIG_PM )
   9  * for ens1371 only ( FIXME )
  10  * derived from cs4281.c, atiixp.c and via82xx.c
  11  * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
  12  * by Kurt J. Bosch
  13  */
  14
  15 #include <linux/io.h>
  16 #include <linux/delay.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/gameport.h>
  22 #include <linux/module.h>
  23 #include <linux/mutex.h>
  24
  25 #include <sound/core.h>
  26 #include <sound/control.h>
  27 #include <sound/pcm.h>
  28 #include <sound/rawmidi.h>
  29 #ifdef CHIP1371
  30 #include <sound/ac97_codec.h>
  31 #else
  32 #include <sound/ak4531_codec.h>
  33 #endif
  34 #include <sound/initval.h>
  35 #include <sound/asoundef.h>
  36
  37 #ifndef CHIP1371
  38 #undef CHIP1370
  39 #define CHIP1370
  40 #endif
  41
  42 #ifdef CHIP1370
  43 #define DRIVER_NAME "ENS1370"
  44 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
  45 #else
  46 #define DRIVER_NAME "ENS1371"
  47 #define CHIP_NAME "ES1371"
  48 #endif
  49
  50
  51 MODULE_AUTHOR("Jaroslav Kysela <[email protected]>, Thomas Sailer <[email protected]>");
  52 MODULE_LICENSE("GPL");
  53 #ifdef CHIP1370
  54 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  55 #endif
  56 #ifdef CHIP1371
  57 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  58 #endif
  59
  60 #if IS_REACHABLE(CONFIG_GAMEPORT)
  61 #define SUPPORT_JOYSTICK
  62 #endif
  63
  64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  65 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  66 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  67 #ifdef SUPPORT_JOYSTICK
  68 #ifdef CHIP1371
  69 static int joystick_port[SNDRV_CARDS];
  70 #else
  71 static bool joystick[SNDRV_CARDS];
  72 #endif
  73 #endif
  74 #ifdef CHIP1371
  75 static int spdif[SNDRV_CARDS];
  76 static int lineio[SNDRV_CARDS];
  77 #endif
  78
  79 module_param_array(index, int, NULL, 0444);
  80 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  81 module_param_array(id, charp, NULL, 0444);
  82 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  83 module_param_array(enable, bool, NULL, 0444);
  84 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  85 #ifdef SUPPORT_JOYSTICK
  86 #ifdef CHIP1371
  87 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  88 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  89 #else
  90 module_param_array(joystick, bool, NULL, 0444);
  91 MODULE_PARM_DESC(joystick, "Enable joystick.");
  92 #endif
  93 #endif /* SUPPORT_JOYSTICK */
  94 #ifdef CHIP1371
  95 module_param_array(spdif, int, NULL, 0444);
  96 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
  97 module_param_array(lineio, int, NULL, 0444);
  98 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
  99 #endif
 100
 101 /* ES1371 chip ID */
 102 /* This is a little confusing because all ES1371 compatible chips have the
 103    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 104    This is only significant if you want to enable features on the later parts.
 105    Yes, I know it's stupid and why didn't we use the sub IDs?
 106 */
 107 #define ES1371REV_ES1373_A  0x04
 108 #define ES1371REV_ES1373_B  0x06
 109 #define ES1371REV_CT5880_A  0x07
 110 #define CT5880REV_CT5880_C  0x02
 111 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 112 #define CT5880REV_CT5880_E  0x04        /* mw */
 113 #define ES1371REV_ES1371_B  0x09
 114 #define EV1938REV_EV1938_A  0x00
 115 #define ES1371REV_ES1373_8  0x08
 116
 117 /*
 118  * Direct registers
 119  */
 120
 121 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 122
 123 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 124 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 125 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 126 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 127 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 128 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 129 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 130 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 131 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 132 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 133 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 134 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 135 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 136 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 137 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 138 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 139 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 140 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 141 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 142 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 143 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 144 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 145 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 146 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 147 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 148 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 149 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 150 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 151 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 152 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 153 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 154 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 155 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 156 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 157 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 158 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 159 #define   ES_UART_EN            (1<<3)          /* UART enable */
 160 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 161 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 162 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 163 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 164 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 165 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 166 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 167 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 168 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 169 #define   ES_1373_REAR_BIT26    (1<<26)
 170 #define   ES_1373_REAR_BIT24    (1<<24)
 171 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 172 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 173 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 174 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 175 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 176 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 177 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 178 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 179 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 180 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 181 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 182 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 183 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 184 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 185 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 186 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 187 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 188 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 189 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 190 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 191 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 192 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 193 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 194 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 195 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 196 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 197 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 198 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 199 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 200 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 201 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 202 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 203 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 204 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 205 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 206 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 207 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 208 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 209 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 210 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 211 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 212 #define   EV_1938_CODEC_MAGIC      (1<<26)
 213 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 214 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 215 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 216 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 217
 218 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 219 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 220 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 221 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 222 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 223 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 224 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 225 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 226 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 227 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 228 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 229 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 230 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 231
 232 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 233 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 234 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 235 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 236 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 237 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 238 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 239 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 240 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 241 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 242 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 243 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 244 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 245 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 246 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 247 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 248 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 249 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 250 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 251 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 252 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 253 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 254 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 255
 256 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 257
 258 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 259 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 260 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 261 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 262 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 263 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 264 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 265 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 266 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 267 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 268 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 269 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 270 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 271 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 272 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 273 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 274 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 275 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 276 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 277 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 278 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 279 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 280 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 281 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 282 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 283 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 284 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 285
 286 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 287 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 288 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 289 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 290 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 291 #define   ES_REG_COUNTM         (0xffff<<0)
 292 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 293
 294 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 295 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 296 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 297 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 298 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 299 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 300 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 301 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 302 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 303 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 304 #define   ES_REG_FSIZEM          (0xffff<<0)
 305 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 306 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 307 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 308
 309 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 310 #define   ES_REG_UF_VALID        (1<<8)
 311 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 312 #define   ES_REG_UF_BYTEM        (0xff<<0)
 313 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 314
 315
 316 /*
 317  *  Pages
 318  */
 319
 320 #define ES_PAGE_DAC     0x0c
 321 #define ES_PAGE_ADC     0x0d
 322 #define ES_PAGE_UART    0x0e
 323 #define ES_PAGE_UART1   0x0f
 324
 325 /*
 326  *  Sample rate converter addresses
 327  */
 328
 329 #define ES_SMPREG_DAC1          0x70
 330 #define ES_SMPREG_DAC2          0x74
 331 #define ES_SMPREG_ADC           0x78
 332 #define ES_SMPREG_VOL_ADC       0x6c
 333 #define ES_SMPREG_VOL_DAC1      0x7c
 334 #define ES_SMPREG_VOL_DAC2      0x7e
 335 #define ES_SMPREG_TRUNC_N       0x00
 336 #define ES_SMPREG_INT_REGS      0x01
 337 #define ES_SMPREG_ACCUM_FRAC    0x02
 338 #define ES_SMPREG_VFREQ_FRAC    0x03
 339
 340 /*
 341  *  Some contants
 342  */
 343
 344 #define ES_1370_SRCLOCK    1411200
 345 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 346
 347 /*
 348  *  Open modes
 349  */
 350
 351 #define ES_MODE_PLAY1   0x0001
 352 #define ES_MODE_PLAY2   0x0002
 353 #define ES_MODE_CAPTURE 0x0004
 354
 355 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 356 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 357
 358 /*
 359
 360  */
 361
 362 struct ensoniq {
 363         spinlock_t reg_lock;
 364         struct mutex src_mutex;
 365
 366         int irq;
 367
 368         unsigned long playback1size;
 369         unsigned long playback2size;
 370         unsigned long capture3size;
 371
 372         unsigned long port;
 373         unsigned int mode;
 374         unsigned int uartm;     /* UART mode */
 375
 376         unsigned int ctrl;      /* control register */
 377         unsigned int sctrl;     /* serial control register */
 378         unsigned int cssr;      /* control status register */
 379         unsigned int uartc;     /* uart control register */
 380         unsigned int rev;       /* chip revision */
 381
 382         union {
 383 #ifdef CHIP1371
 384                 struct {
 385                         struct snd_ac97 *ac97;
 386                 } es1371;
 387 #else
 388                 struct {
 389                         int pclkdiv_lock;
 390                         struct snd_ak4531 *ak4531;
 391                 } es1370;
 392 #endif
 393         } u;
 394
 395         struct pci_dev *pci;
 396         struct snd_card *card;
 397         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
 398         struct snd_pcm *pcm2;   /* DAC2 PCM */
 399         struct snd_pcm_substream *playback1_substream;
 400         struct snd_pcm_substream *playback2_substream;
 401         struct snd_pcm_substream *capture_substream;
 402         unsigned int p1_dma_size;
 403         unsigned int p2_dma_size;
 404         unsigned int c_dma_size;
 405         unsigned int p1_period_size;
 406         unsigned int p2_period_size;
 407         unsigned int c_period_size;
 408         struct snd_rawmidi *rmidi;
 409         struct snd_rawmidi_substream *midi_input;
 410         struct snd_rawmidi_substream *midi_output;
 411
 412         unsigned int spdif;
 413         unsigned int spdif_default;
 414         unsigned int spdif_stream;
 415
 416 #ifdef CHIP1370
 417         struct snd_dma_buffer dma_bug;
 418 #endif
 419
 420 #ifdef SUPPORT_JOYSTICK
 421         struct gameport *gameport;
 422 #endif
 423 };
 424
 425 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
 426
 427 static const struct pci_device_id snd_audiopci_ids[] = {
 428 #ifdef CHIP1370
 429         { PCI_VDEVICE(ENSONIQ, 0x5000), 0, },   /* ES1370 */
 430 #endif
 431 #ifdef CHIP1371
 432         { PCI_VDEVICE(ENSONIQ, 0x1371), 0, },   /* ES1371 */
 433         { PCI_VDEVICE(ENSONIQ, 0x5880), 0, },   /* ES1373 - CT5880 */
 434         { PCI_VDEVICE(ECTIVA, 0x8938), 0, },    /* Ectiva EV1938 */
 435 #endif
 436         { 0, }
 437 };
 438
 439 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 440
 441 /*
 442  *  constants
 443  */
 444
 445 #define POLL_COUNT      0xa000
 446
 447 #ifdef CHIP1370
 448 static const unsigned int snd_es1370_fixed_rates[] =
 449         {5512, 11025, 22050, 44100};
 450 static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
 451         .count = 4,
 452         .list = snd_es1370_fixed_rates,
 453         .mask = 0,
 454 };
 455 static const struct snd_ratnum es1370_clock = {
 456         .num = ES_1370_SRCLOCK,
 457         .den_min = 29,
 458         .den_max = 353,
 459         .den_step = 1,
 460 };
 461 static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
 462         .nrats = 1,
 463         .rats = &es1370_clock,
 464 };
 465 #else
 466 static const struct snd_ratden es1371_dac_clock = {
 467         .num_min = 3000 * (1 << 15),
 468         .num_max = 48000 * (1 << 15),
 469         .num_step = 3000,
 470         .den = 1 << 15,
 471 };
 472 static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
 473         .nrats = 1,
 474         .rats = &es1371_dac_clock,
 475 };
 476 static const struct snd_ratnum es1371_adc_clock = {
 477         .num = 48000 << 15,
 478         .den_min = 32768,
 479         .den_max = 393216,
 480         .den_step = 1,
 481 };
 482 static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
 483         .nrats = 1,
 484         .rats = &es1371_adc_clock,
 485 };
 486 #endif
 487 static const unsigned int snd_ensoniq_sample_shift[] =
 488         {0, 1, 1, 2};
 489
 490 /*
 491  *  common I/O routines
 492  */
 493
 494 #ifdef CHIP1371
 495
 496 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
 497 {
 498         unsigned int t, r = 0;
 499
 500         for (t = 0; t < POLL_COUNT; t++) {
 501                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 502                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 503                         return r;
 504                 cond_resched();
 505         }
 506         dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
 507                    ES_REG(ensoniq, 1371_SMPRATE), r);
 508         return 0;
 509 }
 510
 511 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
 512 {
 513         unsigned int temp, i, orig, r;
 514
 515         /* wait for ready */
 516         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 517
 518         /* expose the SRC state bits */
 519         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 520                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 521         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 522         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 523
 524         /* now, wait for busy and the correct time to read */
 525         temp = snd_es1371_wait_src_ready(ensoniq);
 526
 527         if ((temp & 0x00870000) != 0x00010000) {
 528                 /* wait for the right state */
 529                 for (i = 0; i < POLL_COUNT; i++) {
 530                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 531                         if ((temp & 0x00870000) == 0x00010000)
 532                                 break;
 533                 }
 534         }
 535
 536         /* hide the state bits */
 537         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 538                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 539         r |= ES_1371_SRC_RAM_ADDRO(reg);
 540         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 541
 542         return temp;
 543 }
 544
 545 static void snd_es1371_src_write(struct ensoniq * ensoniq,
 546                                  unsigned short reg, unsigned short data)
 547 {
 548         unsigned int r;
 549
 550         r = snd_es1371_wait_src_ready(ensoniq) &
 551             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 552              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 553         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 554         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 555 }
 556
 557 #endif /* CHIP1371 */
 558
 559 #ifdef CHIP1370
 560
 561 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
 562                                    unsigned short reg, unsigned short val)
 563 {
 564         struct ensoniq *ensoniq = ak4531->private_data;
 565         unsigned long end_time = jiffies + HZ / 10;
 566
 567 #if 0
 568         dev_dbg(ensoniq->card->dev,
 569                "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
 570                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 571 #endif
 572         do {
 573                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 574                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 575                         return;
 576                 }
 577                 schedule_timeout_uninterruptible(1);
 578         } while (time_after(end_time, jiffies));
 579         dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
 580                    inl(ES_REG(ensoniq, STATUS)));
 581 }
 582
 583 #endif /* CHIP1370 */
 584
 585 #ifdef CHIP1371
 586
 587 static inline bool is_ev1938(struct ensoniq *ensoniq)
 588 {
 589         return ensoniq->pci->device == 0x8938;
 590 }
 591
 592 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
 593                                    unsigned short reg, unsigned short val)
 594 {
 595         struct ensoniq *ensoniq = ac97->private_data;
 596         unsigned int t, x, flag;
 597
 598         flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
 599         mutex_lock(&ensoniq->src_mutex);
 600         for (t = 0; t < POLL_COUNT; t++) {
 601                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 602                         /* save the current state for latter */
 603                         x = snd_es1371_wait_src_ready(ensoniq);
 604                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 605                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 606                              ES_REG(ensoniq, 1371_SMPRATE));
 607                         /* wait for not busy (state 0) first to avoid
 608                            transition states */
 609                         for (t = 0; t < POLL_COUNT; t++) {
 610                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 611                                     0x00000000)
 612                                         break;
 613                         }
 614                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 615                         for (t = 0; t < POLL_COUNT; t++) {
 616                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 617                                     0x00010000)
 618                                         break;
 619                         }
 620                         outl(ES_1371_CODEC_WRITE(reg, val) | flag,
 621                              ES_REG(ensoniq, 1371_CODEC));
 622                         /* restore SRC reg */
 623                         snd_es1371_wait_src_ready(ensoniq);
 624                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 625                         mutex_unlock(&ensoniq->src_mutex);
 626                         return;
 627                 }
 628         }
 629         mutex_unlock(&ensoniq->src_mutex);
 630         dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
 631                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 632 }
 633
 634 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
 635                                             unsigned short reg)
 636 {
 637         struct ensoniq *ensoniq = ac97->private_data;
 638         unsigned int t, x, flag, fail = 0;
 639
 640         flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
 641       __again:
 642         mutex_lock(&ensoniq->src_mutex);
 643         for (t = 0; t < POLL_COUNT; t++) {
 644                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 645                         /* save the current state for latter */
 646                         x = snd_es1371_wait_src_ready(ensoniq);
 647                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 648                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 649                              ES_REG(ensoniq, 1371_SMPRATE));
 650                         /* wait for not busy (state 0) first to avoid
 651                            transition states */
 652                         for (t = 0; t < POLL_COUNT; t++) {
 653                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 654                                     0x00000000)
 655                                         break;
 656                         }
 657                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 658                         for (t = 0; t < POLL_COUNT; t++) {
 659                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 660                                     0x00010000)
 661                                         break;
 662                         }
 663                         outl(ES_1371_CODEC_READS(reg) | flag,
 664                              ES_REG(ensoniq, 1371_CODEC));
 665                         /* restore SRC reg */
 666                         snd_es1371_wait_src_ready(ensoniq);
 667                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 668                         /* wait for WIP again */
 669                         for (t = 0; t < POLL_COUNT; t++) {
 670                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 671                                         break;
 672                         }
 673                         /* now wait for the stinkin' data (RDY) */
 674                         for (t = 0; t < POLL_COUNT; t++) {
 675                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 676                                         if (is_ev1938(ensoniq)) {
 677                                                 for (t = 0; t < 100; t++)
 678                                                         inl(ES_REG(ensoniq, CONTROL));
 679                                                 x = inl(ES_REG(ensoniq, 1371_CODEC));
 680                                         }
 681                                         mutex_unlock(&ensoniq->src_mutex);
 682                                         return ES_1371_CODEC_READ(x);
 683                                 }
 684                         }
 685                         mutex_unlock(&ensoniq->src_mutex);
 686                         if (++fail > 10) {
 687                                 dev_err(ensoniq->card->dev,
 688                                         "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
 689                                            ES_REG(ensoniq, 1371_CODEC), reg,
 690                                            inl(ES_REG(ensoniq, 1371_CODEC)));
 691                                 return 0;
 692                         }
 693                         goto __again;
 694                 }
 695         }
 696         mutex_unlock(&ensoniq->src_mutex);
 697         dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
 698                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 699         return 0;
 700 }
 701
 702 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
 703 {
 704         msleep(750);
 705         snd_es1371_codec_read(ac97, AC97_RESET);
 706         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
 707         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
 708         msleep(50);
 709 }
 710
 711 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
 712 {
 713         unsigned int n, truncm, freq;
 714
 715         mutex_lock(&ensoniq->src_mutex);
 716         n = rate / 3000;
 717         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 718                 n--;
 719         truncm = (21 * n - 1) | 1;
 720         freq = ((48000UL << 15) / rate) * n;
 721         if (rate >= 24000) {
 722                 if (truncm > 239)
 723                         truncm = 239;
 724                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 725                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 726         } else {
 727                 if (truncm > 119)
 728                         truncm = 119;
 729                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 730                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 731         }
 732         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 733                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
 734                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 735                              ((freq >> 5) & 0xfc00));
 736         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 737         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 738         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 739         mutex_unlock(&ensoniq->src_mutex);
 740 }
 741
 742 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
 743 {
 744         unsigned int freq, r;
 745
 746         mutex_lock(&ensoniq->src_mutex);
 747         freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
 748         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 749                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
 750                 ES_1371_DIS_P1;
 751         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 752         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 753                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
 754                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 755                              ((freq >> 5) & 0xfc00));
 756         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 757         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 758                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
 759         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 760         mutex_unlock(&ensoniq->src_mutex);
 761 }
 762
 763 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
 764 {
 765         unsigned int freq, r;
 766
 767         mutex_lock(&ensoniq->src_mutex);
 768         freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
 769         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 770                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
 771                 ES_1371_DIS_P2;
 772         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 773         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 774                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
 775                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 776                              ((freq >> 5) & 0xfc00));
 777         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
 778                              freq & 0x7fff);
 779         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 780                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
 781         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 782         mutex_unlock(&ensoniq->src_mutex);
 783 }
 784
 785 #endif /* CHIP1371 */
 786
 787 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
 788 {
 789         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 790         switch (cmd) {
 791         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 792         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 793         {
 794                 unsigned int what = 0;
 795                 struct snd_pcm_substream *s;
 796                 snd_pcm_group_for_each_entry(s, substream) {
 797                         if (s == ensoniq->playback1_substream) {
 798                                 what |= ES_P1_PAUSE;
 799                                 snd_pcm_trigger_done(s, substream);
 800                         } else if (s == ensoniq->playback2_substream) {
 801                                 what |= ES_P2_PAUSE;
 802                                 snd_pcm_trigger_done(s, substream);
 803                         } else if (s == ensoniq->capture_substream)
 804                                 return -EINVAL;
 805                 }
 806                 spin_lock(&ensoniq->reg_lock);
 807                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 808                         ensoniq->sctrl |= what;
 809                 else
 810                         ensoniq->sctrl &= ~what;
 811                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 812                 spin_unlock(&ensoniq->reg_lock);
 813                 break;
 814         }
 815         case SNDRV_PCM_TRIGGER_START:
 816         case SNDRV_PCM_TRIGGER_STOP:
 817         {
 818                 unsigned int what = 0;
 819                 struct snd_pcm_substream *s;
 820                 snd_pcm_group_for_each_entry(s, substream) {
 821                         if (s == ensoniq->playback1_substream) {
 822                                 what |= ES_DAC1_EN;
 823                                 snd_pcm_trigger_done(s, substream);
 824                         } else if (s == ensoniq->playback2_substream) {
 825                                 what |= ES_DAC2_EN;
 826                                 snd_pcm_trigger_done(s, substream);
 827                         } else if (s == ensoniq->capture_substream) {
 828                                 what |= ES_ADC_EN;
 829                                 snd_pcm_trigger_done(s, substream);
 830                         }
 831                 }
 832                 spin_lock(&ensoniq->reg_lock);
 833                 if (cmd == SNDRV_PCM_TRIGGER_START)
 834                         ensoniq->ctrl |= what;
 835                 else
 836                         ensoniq->ctrl &= ~what;
 837                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 838                 spin_unlock(&ensoniq->reg_lock);
 839                 break;
 840         }
 841         default:
 842                 return -EINVAL;
 843         }
 844         return 0;
 845 }
 846
 847 /*
 848  *  PCM part
 849  */
 850
 851 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
 852 {
 853         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 854         struct snd_pcm_runtime *runtime = substream->runtime;
 855         unsigned int mode = 0;
 856
 857         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 858         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 859         if (snd_pcm_format_width(runtime->format) == 16)
 860                 mode |= 0x02;
 861         if (runtime->channels > 1)
 862                 mode |= 0x01;
 863         spin_lock_irq(&ensoniq->reg_lock);
 864         ensoniq->ctrl &= ~ES_DAC1_EN;
 865 #ifdef CHIP1371
 866         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 867         if (runtime->rate == 48000)
 868                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 869         else
 870                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 871 #endif
 872         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 873         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 874         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 875         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 876         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 877         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 878         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 879         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 880              ES_REG(ensoniq, DAC1_COUNT));
 881 #ifdef CHIP1370
 882         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 883         switch (runtime->rate) {
 884         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 885         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 886         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 887         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 888         default: snd_BUG();
 889         }
 890 #endif
 891         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 892         spin_unlock_irq(&ensoniq->reg_lock);
 893 #ifndef CHIP1370
 894         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 895 #endif
 896         return 0;
 897 }
 898
 899 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
 900 {
 901         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 902         struct snd_pcm_runtime *runtime = substream->runtime;
 903         unsigned int mode = 0;
 904
 905         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 906         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 907         if (snd_pcm_format_width(runtime->format) == 16)
 908                 mode |= 0x02;
 909         if (runtime->channels > 1)
 910                 mode |= 0x01;
 911         spin_lock_irq(&ensoniq->reg_lock);
 912         ensoniq->ctrl &= ~ES_DAC2_EN;
 913         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 914         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 915         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 916         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 917         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 918                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 919         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 920                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 921         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 922         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 923              ES_REG(ensoniq, DAC2_COUNT));
 924 #ifdef CHIP1370
 925         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 926                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 927                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 928                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 929         }
 930 #endif
 931         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 932         spin_unlock_irq(&ensoniq->reg_lock);
 933 #ifndef CHIP1370
 934         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 935 #endif
 936         return 0;
 937 }
 938
 939 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
 940 {
 941         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 942         struct snd_pcm_runtime *runtime = substream->runtime;
 943         unsigned int mode = 0;
 944
 945         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 946         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 947         if (snd_pcm_format_width(runtime->format) == 16)
 948                 mode |= 0x02;
 949         if (runtime->channels > 1)
 950                 mode |= 0x01;
 951         spin_lock_irq(&ensoniq->reg_lock);
 952         ensoniq->ctrl &= ~ES_ADC_EN;
 953         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 954         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 955         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 956         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 957         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 958         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 959         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 960         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 961              ES_REG(ensoniq, ADC_COUNT));
 962 #ifdef CHIP1370
 963         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 964                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 965                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 966                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 967         }
 968 #endif
 969         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 970         spin_unlock_irq(&ensoniq->reg_lock);
 971 #ifndef CHIP1370
 972         snd_es1371_adc_rate(ensoniq, runtime->rate);
 973 #endif
 974         return 0;
 975 }
 976
 977 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
 978 {
 979         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 980         size_t ptr;
 981
 982         spin_lock(&ensoniq->reg_lock);
 983         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 984                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 985                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 986                 ptr = bytes_to_frames(substream->runtime, ptr);
 987         } else {
 988                 ptr = 0;
 989         }
 990         spin_unlock(&ensoniq->reg_lock);
 991         return ptr;
 992 }
 993
 994 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
 995 {
 996         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 997         size_t ptr;
 998
 999         spin_lock(&ensoniq->reg_lock);
1000         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1001                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1002                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1003                 ptr = bytes_to_frames(substream->runtime, ptr);
1004         } else {
1005                 ptr = 0;
1006         }
1007         spin_unlock(&ensoniq->reg_lock);
1008         return ptr;
1009 }
1010
1011 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1012 {
1013         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1014         size_t ptr;
1015
1016         spin_lock(&ensoniq->reg_lock);
1017         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1018                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1019                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1020                 ptr = bytes_to_frames(substream->runtime, ptr);
1021         } else {
1022                 ptr = 0;
1023         }
1024         spin_unlock(&ensoniq->reg_lock);
1025         return ptr;
1026 }
1027
1028 static const struct snd_pcm_hardware snd_ensoniq_playback1 =
1029 {
1030         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1031                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1032                                  SNDRV_PCM_INFO_MMAP_VALID |
1033                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1034         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1035         .rates =
1036 #ifndef CHIP1370
1037                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1038 #else
1039                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1040                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1041                                  SNDRV_PCM_RATE_44100),
1042 #endif
1043         .rate_min =             4000,
1044         .rate_max =             48000,
1045         .channels_min =         1,
1046         .channels_max =         2,
1047         .buffer_bytes_max =     (128*1024),
1048         .period_bytes_min =     64,
1049         .period_bytes_max =     (128*1024),
1050         .periods_min =          1,
1051         .periods_max =          1024,
1052         .fifo_size =            0,
1053 };
1054
1055 static const struct snd_pcm_hardware snd_ensoniq_playback2 =
1056 {
1057         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1058                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1059                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1060                                  SNDRV_PCM_INFO_SYNC_START),
1061         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1062         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1063         .rate_min =             4000,
1064         .rate_max =             48000,
1065         .channels_min =         1,
1066         .channels_max =         2,
1067         .buffer_bytes_max =     (128*1024),
1068         .period_bytes_min =     64,
1069         .period_bytes_max =     (128*1024),
1070         .periods_min =          1,
1071         .periods_max =          1024,
1072         .fifo_size =            0,
1073 };
1074
1075 static const struct snd_pcm_hardware snd_ensoniq_capture =
1076 {
1077         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1078                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1079                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1080         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1081         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1082         .rate_min =             4000,
1083         .rate_max =             48000,
1084         .channels_min =         1,
1085         .channels_max =         2,
1086         .buffer_bytes_max =     (128*1024),
1087         .period_bytes_min =     64,
1088         .period_bytes_max =     (128*1024),
1089         .periods_min =          1,
1090         .periods_max =          1024,
1091         .fifo_size =            0,
1092 };
1093
1094 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1095 {
1096         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1097         struct snd_pcm_runtime *runtime = substream->runtime;
1098
1099         ensoniq->mode |= ES_MODE_PLAY1;
1100         ensoniq->playback1_substream = substream;
1101         runtime->hw = snd_ensoniq_playback1;
1102         snd_pcm_set_sync(substream);
1103         spin_lock_irq(&ensoniq->reg_lock);
1104         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1105                 ensoniq->spdif_stream = ensoniq->spdif_default;
1106         spin_unlock_irq(&ensoniq->reg_lock);
1107 #ifdef CHIP1370
1108         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1109                                    &snd_es1370_hw_constraints_rates);
1110 #else
1111         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1112                                       &snd_es1371_hw_constraints_dac_clock);
1113 #endif
1114         return 0;
1115 }
1116
1117 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1118 {
1119         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1120         struct snd_pcm_runtime *runtime = substream->runtime;
1121
1122         ensoniq->mode |= ES_MODE_PLAY2;
1123         ensoniq->playback2_substream = substream;
1124         runtime->hw = snd_ensoniq_playback2;
1125         snd_pcm_set_sync(substream);
1126         spin_lock_irq(&ensoniq->reg_lock);
1127         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1128                 ensoniq->spdif_stream = ensoniq->spdif_default;
1129         spin_unlock_irq(&ensoniq->reg_lock);
1130 #ifdef CHIP1370
1131         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1132                                       &snd_es1370_hw_constraints_clock);
1133 #else
1134         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1135                                       &snd_es1371_hw_constraints_dac_clock);
1136 #endif
1137         return 0;
1138 }
1139
1140 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1141 {
1142         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1143         struct snd_pcm_runtime *runtime = substream->runtime;
1144
1145         ensoniq->mode |= ES_MODE_CAPTURE;
1146         ensoniq->capture_substream = substream;
1147         runtime->hw = snd_ensoniq_capture;
1148         snd_pcm_set_sync(substream);
1149 #ifdef CHIP1370
1150         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1151                                       &snd_es1370_hw_constraints_clock);
1152 #else
1153         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1154                                       &snd_es1371_hw_constraints_adc_clock);
1155 #endif
1156         return 0;
1157 }
1158
1159 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1160 {
1161         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1162
1163         ensoniq->playback1_substream = NULL;
1164         ensoniq->mode &= ~ES_MODE_PLAY1;
1165         return 0;
1166 }
1167
1168 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1169 {
1170         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1171
1172         ensoniq->playback2_substream = NULL;
1173         spin_lock_irq(&ensoniq->reg_lock);
1174 #ifdef CHIP1370
1175         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1176 #endif
1177         ensoniq->mode &= ~ES_MODE_PLAY2;
1178         spin_unlock_irq(&ensoniq->reg_lock);
1179         return 0;
1180 }
1181
1182 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1183 {
1184         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1185
1186         ensoniq->capture_substream = NULL;
1187         spin_lock_irq(&ensoniq->reg_lock);
1188 #ifdef CHIP1370
1189         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1190 #endif
1191         ensoniq->mode &= ~ES_MODE_CAPTURE;
1192         spin_unlock_irq(&ensoniq->reg_lock);
1193         return 0;
1194 }
1195
1196 static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1197         .open =         snd_ensoniq_playback1_open,
1198         .close =        snd_ensoniq_playback1_close,
1199         .prepare =      snd_ensoniq_playback1_prepare,
1200         .trigger =      snd_ensoniq_trigger,
1201         .pointer =      snd_ensoniq_playback1_pointer,
1202 };
1203
1204 static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1205         .open =         snd_ensoniq_playback2_open,
1206         .close =        snd_ensoniq_playback2_close,
1207         .prepare =      snd_ensoniq_playback2_prepare,
1208         .trigger =      snd_ensoniq_trigger,
1209         .pointer =      snd_ensoniq_playback2_pointer,
1210 };
1211
1212 static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
1213         .open =         snd_ensoniq_capture_open,
1214         .close =        snd_ensoniq_capture_close,
1215         .prepare =      snd_ensoniq_capture_prepare,
1216         .trigger =      snd_ensoniq_trigger,
1217         .pointer =      snd_ensoniq_capture_pointer,
1218 };
1219
1220 static const struct snd_pcm_chmap_elem surround_map[] = {
1221         { .channels = 1,
1222           .map = { SNDRV_CHMAP_MONO } },
1223         { .channels = 2,
1224           .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1225         { }
1226 };
1227
1228 static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
1229 {
1230         struct snd_pcm *pcm;
1231         int err;
1232
1233         err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1234         if (err < 0)
1235                 return err;
1236
1237 #ifdef CHIP1370
1238         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1239 #else
1240         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1241 #endif
1242         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1243
1244         pcm->private_data = ensoniq;
1245         pcm->info_flags = 0;
1246         strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1247         ensoniq->pcm1 = pcm;
1248
1249         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1250                                        &ensoniq->pci->dev, 64*1024, 128*1024);
1251
1252 #ifdef CHIP1370
1253         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1254                                      surround_map, 2, 0, NULL);
1255 #else
1256         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1257                                      snd_pcm_std_chmaps, 2, 0, NULL);
1258 #endif
1259         return err;
1260 }
1261
1262 static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
1263 {
1264         struct snd_pcm *pcm;
1265         int err;
1266
1267         err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1268         if (err < 0)
1269                 return err;
1270
1271 #ifdef CHIP1370
1272         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1273 #else
1274         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1275 #endif
1276         pcm->private_data = ensoniq;
1277         pcm->info_flags = 0;
1278         strcpy(pcm->name, CHIP_NAME " DAC1");
1279         ensoniq->pcm2 = pcm;
1280
1281         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1282                                        &ensoniq->pci->dev, 64*1024, 128*1024);
1283
1284 #ifdef CHIP1370
1285         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1286                                      snd_pcm_std_chmaps, 2, 0, NULL);
1287 #else
1288         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1289                                      surround_map, 2, 0, NULL);
1290 #endif
1291         return err;
1292 }
1293
1294 /*
1295  *  Mixer section
1296  */
1297
1298 /*
1299  * ENS1371 mixer (including SPDIF interface)
1300  */
1301 #ifdef CHIP1371
1302 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1303                                   struct snd_ctl_elem_info *uinfo)
1304 {
1305         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1306         uinfo->count = 1;
1307         return 0;
1308 }
1309
1310 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1311                                          struct snd_ctl_elem_value *ucontrol)
1312 {
1313         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1314         spin_lock_irq(&ensoniq->reg_lock);
1315         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1316         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1317         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1318         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1319         spin_unlock_irq(&ensoniq->reg_lock);
1320         return 0;
1321 }
1322
1323 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1324                                          struct snd_ctl_elem_value *ucontrol)
1325 {
1326         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1327         unsigned int val;
1328         int change;
1329
1330         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1331               ((u32)ucontrol->value.iec958.status[1] << 8) |
1332               ((u32)ucontrol->value.iec958.status[2] << 16) |
1333               ((u32)ucontrol->value.iec958.status[3] << 24);
1334         spin_lock_irq(&ensoniq->reg_lock);
1335         change = ensoniq->spdif_default != val;
1336         ensoniq->spdif_default = val;
1337         if (change && ensoniq->playback1_substream == NULL &&
1338             ensoniq->playback2_substream == NULL)
1339                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1340         spin_unlock_irq(&ensoniq->reg_lock);
1341         return change;
1342 }
1343
1344 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1345                                       struct snd_ctl_elem_value *ucontrol)
1346 {
1347         ucontrol->value.iec958.status[0] = 0xff;
1348         ucontrol->value.iec958.status[1] = 0xff;
1349         ucontrol->value.iec958.status[2] = 0xff;
1350         ucontrol->value.iec958.status[3] = 0xff;
1351         return 0;
1352 }
1353
1354 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1355                                         struct snd_ctl_elem_value *ucontrol)
1356 {
1357         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1358         spin_lock_irq(&ensoniq->reg_lock);
1359         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1360         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1361         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1362         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1363         spin_unlock_irq(&ensoniq->reg_lock);
1364         return 0;
1365 }
1366
1367 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1368                                         struct snd_ctl_elem_value *ucontrol)
1369 {
1370         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1371         unsigned int val;
1372         int change;
1373
1374         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1375               ((u32)ucontrol->value.iec958.status[1] << 8) |
1376               ((u32)ucontrol->value.iec958.status[2] << 16) |
1377               ((u32)ucontrol->value.iec958.status[3] << 24);
1378         spin_lock_irq(&ensoniq->reg_lock);
1379         change = ensoniq->spdif_stream != val;
1380         ensoniq->spdif_stream = val;
1381         if (change && (ensoniq->playback1_substream != NULL ||
1382                        ensoniq->playback2_substream != NULL))
1383                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1384         spin_unlock_irq(&ensoniq->reg_lock);
1385         return change;
1386 }
1387
1388 #define ES1371_SPDIF(xname) \
1389 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1390   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1391
1392 #define snd_es1371_spdif_info           snd_ctl_boolean_mono_info
1393
1394 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1395                                 struct snd_ctl_elem_value *ucontrol)
1396 {
1397         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1398
1399         spin_lock_irq(&ensoniq->reg_lock);
1400         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1401         spin_unlock_irq(&ensoniq->reg_lock);
1402         return 0;
1403 }
1404
1405 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1406                                 struct snd_ctl_elem_value *ucontrol)
1407 {
1408         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1409         unsigned int nval1, nval2;
1410         int change;
1411
1412         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1413         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1414         spin_lock_irq(&ensoniq->reg_lock);
1415         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1416         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1417         ensoniq->ctrl |= nval1;
1418         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1419         ensoniq->cssr |= nval2;
1420         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1421         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1422         spin_unlock_irq(&ensoniq->reg_lock);
1423         return change;
1424 }
1425
1426
1427 /* spdif controls */
1428 static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
1429         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1430         {
1431                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1432                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1433                 .info =         snd_ens1373_spdif_info,
1434                 .get =          snd_ens1373_spdif_default_get,
1435                 .put =          snd_ens1373_spdif_default_put,
1436         },
1437         {
1438                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1439                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1440                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1441                 .info =         snd_ens1373_spdif_info,
1442                 .get =          snd_ens1373_spdif_mask_get
1443         },
1444         {
1445                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1446                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1447                 .info =         snd_ens1373_spdif_info,
1448                 .get =          snd_ens1373_spdif_stream_get,
1449                 .put =          snd_ens1373_spdif_stream_put
1450         },
1451 };
1452
1453
1454 #define snd_es1373_rear_info            snd_ctl_boolean_mono_info
1455
1456 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1457                                struct snd_ctl_elem_value *ucontrol)
1458 {
1459         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1460         int val = 0;
1461
1462         spin_lock_irq(&ensoniq->reg_lock);
1463         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1464                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1465                 val = 1;
1466         ucontrol->value.integer.value[0] = val;
1467         spin_unlock_irq(&ensoniq->reg_lock);
1468         return 0;
1469 }
1470
1471 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1472                                struct snd_ctl_elem_value *ucontrol)
1473 {
1474         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1475         unsigned int nval1;
1476         int change;
1477
1478         nval1 = ucontrol->value.integer.value[0] ?
1479                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1480         spin_lock_irq(&ensoniq->reg_lock);
1481         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1482                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1483         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1484         ensoniq->cssr |= nval1;
1485         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1486         spin_unlock_irq(&ensoniq->reg_lock);
1487         return change;
1488 }
1489
1490 static const struct snd_kcontrol_new snd_ens1373_rear =
1491 {
1492         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1493         .name =         "AC97 2ch->4ch Copy Switch",
1494         .info =         snd_es1373_rear_info,
1495         .get =          snd_es1373_rear_get,
1496         .put =          snd_es1373_rear_put,
1497 };
1498
1499 #define snd_es1373_line_info            snd_ctl_boolean_mono_info
1500
1501 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1502                                struct snd_ctl_elem_value *ucontrol)
1503 {
1504         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1505         int val = 0;
1506
1507         spin_lock_irq(&ensoniq->reg_lock);
1508         if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
1509                 val = 1;
1510         ucontrol->value.integer.value[0] = val;
1511         spin_unlock_irq(&ensoniq->reg_lock);
1512         return 0;
1513 }
1514
1515 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1516                                struct snd_ctl_elem_value *ucontrol)
1517 {
1518         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1519         int changed;
1520         unsigned int ctrl;
1521
1522         spin_lock_irq(&ensoniq->reg_lock);
1523         ctrl = ensoniq->ctrl;
1524         if (ucontrol->value.integer.value[0])
1525                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1526         else
1527                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1528         changed = (ctrl != ensoniq->ctrl);
1529         if (changed)
1530                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1531         spin_unlock_irq(&ensoniq->reg_lock);
1532         return changed;
1533 }
1534
1535 static const struct snd_kcontrol_new snd_ens1373_line =
1536 {
1537         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1538         .name =         "Line In->Rear Out Switch",
1539         .info =         snd_es1373_line_info,
1540         .get =          snd_es1373_line_get,
1541         .put =          snd_es1373_line_put,
1542 };
1543
1544 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1545 {
1546         struct ensoniq *ensoniq = ac97->private_data;
1547         ensoniq->u.es1371.ac97 = NULL;
1548 }
1549
1550 struct es1371_quirk {
1551         unsigned short vid;             /* vendor ID */
1552         unsigned short did;             /* device ID */
1553         unsigned char rev;              /* revision */
1554 };
1555
1556 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1557                                const struct es1371_quirk *list)
1558 {
1559         while (list->vid != (unsigned short)PCI_ANY_ID) {
1560                 if (ensoniq->pci->vendor == list->vid &&
1561                     ensoniq->pci->device == list->did &&
1562                     ensoniq->rev == list->rev)
1563                         return 1;
1564                 list++;
1565         }
1566         return 0;
1567 }
1568
1569 static const struct es1371_quirk es1371_spdif_present[] = {
1570         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1571         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1572         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1573         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1574         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1575         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1576 };
1577
1578 static const struct snd_pci_quirk ens1373_line_quirk[] = {
1579         SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1580         SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1581         { } /* end */
1582 };
1583
1584 static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1585                                   int has_spdif, int has_line)
1586 {
1587         struct snd_card *card = ensoniq->card;
1588         struct snd_ac97_bus *pbus;
1589         struct snd_ac97_template ac97;
1590         int err;
1591         static const struct snd_ac97_bus_ops ops = {
1592                 .write = snd_es1371_codec_write,
1593                 .read = snd_es1371_codec_read,
1594                 .wait = snd_es1371_codec_wait,
1595         };
1596
1597         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1598                 return err;
1599
1600         memset(&ac97, 0, sizeof(ac97));
1601         ac97.private_data = ensoniq;
1602         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1603         ac97.pci = ensoniq->pci;
1604         ac97.scaps = AC97_SCAP_AUDIO;
1605         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1606                 return err;
1607         if (has_spdif > 0 ||
1608             (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1609                 struct snd_kcontrol *kctl;
1610                 int i, is_spdif = 0;
1611
1612                 ensoniq->spdif_default = ensoniq->spdif_stream =
1613                         SNDRV_PCM_DEFAULT_CON_SPDIF;
1614                 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1615
1616                 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1617                         is_spdif++;
1618
1619                 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1620                         kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1621                         if (!kctl)
1622                                 return -ENOMEM;
1623                         kctl->id.index = is_spdif;
1624                         err = snd_ctl_add(card, kctl);
1625                         if (err < 0)
1626                                 return err;
1627                 }
1628         }
1629         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1630                 /* mirror rear to front speakers */
1631                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1632                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1633                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1634                 if (err < 0)
1635                         return err;
1636         }
1637         if (has_line > 0 ||
1638             snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1639                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1640                                                       ensoniq));
1641                  if (err < 0)
1642                          return err;
1643         }
1644
1645         return 0;
1646 }
1647
1648 #endif /* CHIP1371 */
1649
1650 /* generic control callbacks for ens1370 */
1651 #ifdef CHIP1370
1652 #define ENSONIQ_CONTROL(xname, mask) \
1653 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1654   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1655   .private_value = mask }
1656
1657 #define snd_ensoniq_control_info        snd_ctl_boolean_mono_info
1658
1659 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1660                                    struct snd_ctl_elem_value *ucontrol)
1661 {
1662         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1663         int mask = kcontrol->private_value;
1664
1665         spin_lock_irq(&ensoniq->reg_lock);
1666         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1667         spin_unlock_irq(&ensoniq->reg_lock);
1668         return 0;
1669 }
1670
1671 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1672                                    struct snd_ctl_elem_value *ucontrol)
1673 {
1674         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1675         int mask = kcontrol->private_value;
1676         unsigned int nval;
1677         int change;
1678
1679         nval = ucontrol->value.integer.value[0] ? mask : 0;
1680         spin_lock_irq(&ensoniq->reg_lock);
1681         change = (ensoniq->ctrl & mask) != nval;
1682         ensoniq->ctrl &= ~mask;
1683         ensoniq->ctrl |= nval;
1684         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1685         spin_unlock_irq(&ensoniq->reg_lock);
1686         return change;
1687 }
1688
1689 /*
1690  * ENS1370 mixer
1691  */
1692
1693 static const struct snd_kcontrol_new snd_es1370_controls[2] = {
1694 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1695 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1696 };
1697
1698 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1699
1700 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1701 {
1702         struct ensoniq *ensoniq = ak4531->private_data;
1703         ensoniq->u.es1370.ak4531 = NULL;
1704 }
1705
1706 static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
1707 {
1708         struct snd_card *card = ensoniq->card;
1709         struct snd_ak4531 ak4531;
1710         unsigned int idx;
1711         int err;
1712
1713         /* try reset AK4531 */
1714         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1715         inw(ES_REG(ensoniq, 1370_CODEC));
1716         udelay(100);
1717         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1718         inw(ES_REG(ensoniq, 1370_CODEC));
1719         udelay(100);
1720
1721         memset(&ak4531, 0, sizeof(ak4531));
1722         ak4531.write = snd_es1370_codec_write;
1723         ak4531.private_data = ensoniq;
1724         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1725         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1726                 return err;
1727         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1728                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1729                 if (err < 0)
1730                         return err;
1731         }
1732         return 0;
1733 }
1734
1735 #endif /* CHIP1370 */
1736
1737 #ifdef SUPPORT_JOYSTICK
1738
1739 #ifdef CHIP1371
1740 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1741 {
1742         switch (joystick_port[dev]) {
1743         case 0: /* disabled */
1744         case 1: /* auto-detect */
1745         case 0x200:
1746         case 0x208:
1747         case 0x210:
1748         case 0x218:
1749                 return joystick_port[dev];
1750
1751         default:
1752                 dev_err(ensoniq->card->dev,
1753                         "invalid joystick port %#x", joystick_port[dev]);
1754                 return 0;
1755         }
1756 }
1757 #else
1758 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1759 {
1760         return joystick[dev] ? 0x200 : 0;
1761 }
1762 #endif
1763
1764 static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1765 {
1766         struct gameport *gp;
1767         int io_port;
1768
1769         io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
1770
1771         switch (io_port) {
1772         case 0:
1773                 return -ENOSYS;
1774
1775         case 1: /* auto_detect */
1776                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1777                         if (request_region(io_port, 8, "ens137x: gameport"))
1778                                 break;
1779                 if (io_port > 0x218) {
1780                         dev_warn(ensoniq->card->dev,
1781                                  "no gameport ports available\n");
1782                         return -EBUSY;
1783                 }
1784                 break;
1785
1786         default:
1787                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1788                         dev_warn(ensoniq->card->dev,
1789                                  "gameport io port %#x in use\n",
1790                                io_port);
1791                         return -EBUSY;
1792                 }
1793                 break;
1794         }
1795
1796         ensoniq->gameport = gp = gameport_allocate_port();
1797         if (!gp) {
1798                 dev_err(ensoniq->card->dev,
1799                         "cannot allocate memory for gameport\n");
1800                 release_region(io_port, 8);
1801                 return -ENOMEM;
1802         }
1803
1804         gameport_set_name(gp, "ES137x");
1805         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1806         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1807         gp->io = io_port;
1808
1809         ensoniq->ctrl |= ES_JYSTK_EN;
1810 #ifdef CHIP1371
1811         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1812         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1813 #endif
1814         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1815
1816         gameport_register_port(ensoniq->gameport);
1817
1818         return 0;
1819 }
1820
1821 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1822 {
1823         if (ensoniq->gameport) {
1824                 int port = ensoniq->gameport->io;
1825
1826                 gameport_unregister_port(ensoniq->gameport);
1827                 ensoniq->gameport = NULL;
1828                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1829                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1830                 release_region(port, 8);
1831         }
1832 }
1833 #else
1834 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1835 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1836 #endif /* SUPPORT_JOYSTICK */
1837
1838 /*
1839
1840  */
1841
1842 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1843                                   struct snd_info_buffer *buffer)
1844 {
1845         struct ensoniq *ensoniq = entry->private_data;
1846
1847         snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1848         snd_iprintf(buffer, "Joystick enable  : %s\n",
1849                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1850 #ifdef CHIP1370
1851         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1852                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1853         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1854                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1855 #else
1856         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1857                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1858 #endif
1859 }
1860
1861 static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
1862 {
1863         snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
1864                              snd_ensoniq_proc_read);
1865 }
1866
1867 /*
1868
1869  */
1870
1871 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1872 {
1873         snd_ensoniq_free_gameport(ensoniq);
1874         if (ensoniq->irq < 0)
1875                 goto __hw_end;
1876 #ifdef CHIP1370
1877         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1878         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1879 #else
1880         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1881         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1882 #endif
1883         pci_set_power_state(ensoniq->pci, PCI_D3hot);
1884       __hw_end:
1885 #ifdef CHIP1370
1886         if (ensoniq->dma_bug.area)
1887                 snd_dma_free_pages(&ensoniq->dma_bug);
1888 #endif
1889         if (ensoniq->irq >= 0)
1890                 free_irq(ensoniq->irq, ensoniq);
1891         pci_release_regions(ensoniq->pci);
1892         pci_disable_device(ensoniq->pci);
1893         kfree(ensoniq);
1894         return 0;
1895 }
1896
1897 static int snd_ensoniq_dev_free(struct snd_device *device)
1898 {
1899         struct ensoniq *ensoniq = device->device_data;
1900         return snd_ensoniq_free(ensoniq);
1901 }
1902
1903 #ifdef CHIP1371
1904 static const struct snd_pci_quirk es1371_amplifier_hack[] = {
1905         SND_PCI_QUIRK_ID(0x107b, 0x2150),       /* Gateway Solo 2150 */
1906         SND_PCI_QUIRK_ID(0x13bd, 0x100c),       /* EV1938 on Mebius PC-MJ100V */
1907         SND_PCI_QUIRK_ID(0x1102, 0x5938),       /* Targa Xtender300 */
1908         SND_PCI_QUIRK_ID(0x1102, 0x8938),       /* IPC Topnote G notebook */
1909         { } /* end */
1910 };
1911
1912 static const struct es1371_quirk es1371_ac97_reset_hack[] = {
1913         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1914         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1915         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1916         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1917         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1918         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1919 };
1920 #endif
1921
1922 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1923 {
1924 #ifdef CHIP1371
1925         int idx;
1926 #endif
1927         /* this code was part of snd_ensoniq_create before intruduction
1928           * of suspend/resume
1929           */
1930 #ifdef CHIP1370
1931         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1932         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1933         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1934         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1935         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1936 #else
1937         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1938         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1939         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1940         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1941             outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1942             /* need to delay around 20ms(bleech) to give
1943                some CODECs enough time to wakeup */
1944             msleep(20);
1945         }
1946         /* AC'97 warm reset to start the bitclk */
1947         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1948         inl(ES_REG(ensoniq, CONTROL));
1949         udelay(20);
1950         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1951         /* Init the sample rate converter */
1952         snd_es1371_wait_src_ready(ensoniq);
1953         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1954         for (idx = 0; idx < 0x80; idx++)
1955                 snd_es1371_src_write(ensoniq, idx, 0);
1956         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1957         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1958         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1959         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1960         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1961         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1962         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1963         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1964         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1965         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1966         snd_es1371_adc_rate(ensoniq, 22050);
1967         snd_es1371_dac1_rate(ensoniq, 22050);
1968         snd_es1371_dac2_rate(ensoniq, 22050);
1969         /* WARNING:
1970          * enabling the sample rate converter without properly programming
1971          * its parameters causes the chip to lock up (the SRC busy bit will
1972          * be stuck high, and I've found no way to rectify this other than
1973          * power cycle) - Thomas Sailer
1974          */
1975         snd_es1371_wait_src_ready(ensoniq);
1976         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1977         /* try reset codec directly */
1978         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1979 #endif
1980         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1981         outb(0x00, ES_REG(ensoniq, UART_RES));
1982         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1983 }
1984
1985 #ifdef CONFIG_PM_SLEEP
1986 static int snd_ensoniq_suspend(struct device *dev)
1987 {
1988         struct snd_card *card = dev_get_drvdata(dev);
1989         struct ensoniq *ensoniq = card->private_data;
1990
1991         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1992
1993 #ifdef CHIP1371
1994         snd_ac97_suspend(ensoniq->u.es1371.ac97);
1995 #else
1996         /* try to reset AK4531 */
1997         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1998         inw(ES_REG(ensoniq, 1370_CODEC));
1999         udelay(100);
2000         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2001         inw(ES_REG(ensoniq, 1370_CODEC));
2002         udelay(100);
2003         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2004 #endif
2005         return 0;
2006 }
2007
2008 static int snd_ensoniq_resume(struct device *dev)
2009 {
2010         struct snd_card *card = dev_get_drvdata(dev);
2011         struct ensoniq *ensoniq = card->private_data;
2012
2013         snd_ensoniq_chip_init(ensoniq);
2014
2015 #ifdef CHIP1371
2016         snd_ac97_resume(ensoniq->u.es1371.ac97);
2017 #else
2018         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2019 #endif
2020         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2021         return 0;
2022 }
2023
2024 static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2025 #define SND_ENSONIQ_PM_OPS      &snd_ensoniq_pm
2026 #else
2027 #define SND_ENSONIQ_PM_OPS      NULL
2028 #endif /* CONFIG_PM_SLEEP */
2029
2030 static int snd_ensoniq_create(struct snd_card *card,
2031                               struct pci_dev *pci,
2032                               struct ensoniq **rensoniq)
2033 {
2034         struct ensoniq *ensoniq;
2035         int err;
2036         static const struct snd_device_ops ops = {
2037                 .dev_free =     snd_ensoniq_dev_free,
2038         };
2039
2040         *rensoniq = NULL;
2041         if ((err = pci_enable_device(pci)) < 0)
2042                 return err;
2043         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2044         if (ensoniq == NULL) {
2045                 pci_disable_device(pci);
2046                 return -ENOMEM;
2047         }
2048         spin_lock_init(&ensoniq->reg_lock);
2049         mutex_init(&ensoniq->src_mutex);
2050         ensoniq->card = card;
2051         ensoniq->pci = pci;
2052         ensoniq->irq = -1;
2053         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2054                 kfree(ensoniq);
2055                 pci_disable_device(pci);
2056                 return err;
2057         }
2058         ensoniq->port = pci_resource_start(pci, 0);
2059         if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2060                         KBUILD_MODNAME, ensoniq)) {
2061                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2062                 snd_ensoniq_free(ensoniq);
2063                 return -EBUSY;
2064         }
2065         ensoniq->irq = pci->irq;
2066         card->sync_irq = ensoniq->irq;
2067 #ifdef CHIP1370
2068         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
2069                                 16, &ensoniq->dma_bug) < 0) {
2070                 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
2071                 snd_ensoniq_free(ensoniq);
2072                 return -EBUSY;
2073         }
2074 #endif
2075         pci_set_master(pci);
2076         ensoniq->rev = pci->revision;
2077 #ifdef CHIP1370
2078 #if 0
2079         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2080                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2081 #else   /* get microphone working */
2082         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2083 #endif
2084         ensoniq->sctrl = 0;
2085 #else
2086         ensoniq->ctrl = 0;
2087         ensoniq->sctrl = 0;
2088         ensoniq->cssr = 0;
2089         if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2090                 ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2091
2092         if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2093                 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2094 #endif
2095
2096         snd_ensoniq_chip_init(ensoniq);
2097
2098         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2099                 snd_ensoniq_free(ensoniq);
2100                 return err;
2101         }
2102
2103         snd_ensoniq_proc_init(ensoniq);
2104
2105         *rensoniq = ensoniq;
2106         return 0;
2107 }
2108
2109 /*
2110  *  MIDI section
2111  */
2112
2113 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2114 {
2115         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2116         unsigned char status, mask, byte;
2117
2118         if (rmidi == NULL)
2119                 return;
2120         /* do Rx at first */
2121         spin_lock(&ensoniq->reg_lock);
2122         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2123         while (mask) {
2124                 status = inb(ES_REG(ensoniq, UART_STATUS));
2125                 if ((status & mask) == 0)
2126                         break;
2127                 byte = inb(ES_REG(ensoniq, UART_DATA));
2128                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2129         }
2130         spin_unlock(&ensoniq->reg_lock);
2131
2132         /* do Tx at second */
2133         spin_lock(&ensoniq->reg_lock);
2134         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2135         while (mask) {
2136                 status = inb(ES_REG(ensoniq, UART_STATUS));
2137                 if ((status & mask) == 0)
2138                         break;
2139                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2140                         ensoniq->uartc &= ~ES_TXINTENM;
2141                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2142                         mask &= ~ES_TXRDY;
2143                 } else {
2144                         outb(byte, ES_REG(ensoniq, UART_DATA));
2145                 }
2146         }
2147         spin_unlock(&ensoniq->reg_lock);
2148 }
2149
2150 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2151 {
2152         struct ensoniq *ensoniq = substream->rmidi->private_data;
2153
2154         spin_lock_irq(&ensoniq->reg_lock);
2155         ensoniq->uartm |= ES_MODE_INPUT;
2156         ensoniq->midi_input = substream;
2157         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2158                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2159                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2160                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2161         }
2162         spin_unlock_irq(&ensoniq->reg_lock);
2163         return 0;
2164 }
2165
2166 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2167 {
2168         struct ensoniq *ensoniq = substream->rmidi->private_data;
2169
2170         spin_lock_irq(&ensoniq->reg_lock);
2171         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2172                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2173                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2174         } else {
2175                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2176         }
2177         ensoniq->midi_input = NULL;
2178         ensoniq->uartm &= ~ES_MODE_INPUT;
2179         spin_unlock_irq(&ensoniq->reg_lock);
2180         return 0;
2181 }
2182
2183 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2184 {
2185         struct ensoniq *ensoniq = substream->rmidi->private_data;
2186
2187         spin_lock_irq(&ensoniq->reg_lock);
2188         ensoniq->uartm |= ES_MODE_OUTPUT;
2189         ensoniq->midi_output = substream;
2190         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2191                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2192                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2193                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2194         }
2195         spin_unlock_irq(&ensoniq->reg_lock);
2196         return 0;
2197 }
2198
2199 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2200 {
2201         struct ensoniq *ensoniq = substream->rmidi->private_data;
2202
2203         spin_lock_irq(&ensoniq->reg_lock);
2204         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2205                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2206                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2207         } else {
2208                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2209         }
2210         ensoniq->midi_output = NULL;
2211         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2212         spin_unlock_irq(&ensoniq->reg_lock);
2213         return 0;
2214 }
2215
2216 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2217 {
2218         unsigned long flags;
2219         struct ensoniq *ensoniq = substream->rmidi->private_data;
2220         int idx;
2221
2222         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2223         if (up) {
2224                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2225                         /* empty input FIFO */
2226                         for (idx = 0; idx < 32; idx++)
2227                                 inb(ES_REG(ensoniq, UART_DATA));
2228                         ensoniq->uartc |= ES_RXINTEN;
2229                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2230                 }
2231         } else {
2232                 if (ensoniq->uartc & ES_RXINTEN) {
2233                         ensoniq->uartc &= ~ES_RXINTEN;
2234                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2235                 }
2236         }
2237         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2238 }
2239
2240 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2241 {
2242         unsigned long flags;
2243         struct ensoniq *ensoniq = substream->rmidi->private_data;
2244         unsigned char byte;
2245
2246         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2247         if (up) {
2248                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2249                         ensoniq->uartc |= ES_TXINTENO(1);
2250                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2251                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2252                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2253                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2254                                         ensoniq->uartc &= ~ES_TXINTENM;
2255                                 } else {
2256                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2257                                 }
2258                         }
2259                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2260                 }
2261         } else {
2262                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2263                         ensoniq->uartc &= ~ES_TXINTENM;
2264                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2265                 }
2266         }
2267         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2268 }
2269
2270 static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
2271 {
2272         .open =         snd_ensoniq_midi_output_open,
2273         .close =        snd_ensoniq_midi_output_close,
2274         .trigger =      snd_ensoniq_midi_output_trigger,
2275 };
2276
2277 static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
2278 {
2279         .open =         snd_ensoniq_midi_input_open,
2280         .close =        snd_ensoniq_midi_input_close,
2281         .trigger =      snd_ensoniq_midi_input_trigger,
2282 };
2283
2284 static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
2285 {
2286         struct snd_rawmidi *rmidi;
2287         int err;
2288
2289         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2290                 return err;
2291         strcpy(rmidi->name, CHIP_NAME);
2292         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2293         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2294         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2295                 SNDRV_RAWMIDI_INFO_DUPLEX;
2296         rmidi->private_data = ensoniq;
2297         ensoniq->rmidi = rmidi;
2298         return 0;
2299 }
2300
2301 /*
2302  *  Interrupt handler
2303  */
2304
2305 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2306 {
2307         struct ensoniq *ensoniq = dev_id;
2308         unsigned int status, sctrl;
2309
2310         if (ensoniq == NULL)
2311                 return IRQ_NONE;
2312
2313         status = inl(ES_REG(ensoniq, STATUS));
2314         if (!(status & ES_INTR))
2315                 return IRQ_NONE;
2316
2317         spin_lock(&ensoniq->reg_lock);
2318         sctrl = ensoniq->sctrl;
2319         if (status & ES_DAC1)
2320                 sctrl &= ~ES_P1_INT_EN;
2321         if (status & ES_DAC2)
2322                 sctrl &= ~ES_P2_INT_EN;
2323         if (status & ES_ADC)
2324                 sctrl &= ~ES_R1_INT_EN;
2325         outl(sctrl, ES_REG(ensoniq, SERIAL));
2326         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2327         spin_unlock(&ensoniq->reg_lock);
2328
2329         if (status & ES_UART)
2330                 snd_ensoniq_midi_interrupt(ensoniq);
2331         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2332                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2333         if ((status & ES_ADC) && ensoniq->capture_substream)
2334                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2335         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2336                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2337         return IRQ_HANDLED;
2338 }
2339
2340 static int snd_audiopci_probe(struct pci_dev *pci,
2341                               const struct pci_device_id *pci_id)
2342 {
2343         static int dev;
2344         struct snd_card *card;
2345         struct ensoniq *ensoniq;
2346         int err;
2347
2348         if (dev >= SNDRV_CARDS)
2349                 return -ENODEV;
2350         if (!enable[dev]) {
2351                 dev++;
2352                 return -ENOENT;
2353         }
2354
2355         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2356                            0, &card);
2357         if (err < 0)
2358                 return err;
2359
2360         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2361                 snd_card_free(card);
2362                 return err;
2363         }
2364         card->private_data = ensoniq;
2365
2366 #ifdef CHIP1370
2367         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2368                 snd_card_free(card);
2369                 return err;
2370         }
2371 #endif
2372 #ifdef CHIP1371
2373         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2374                 snd_card_free(card);
2375                 return err;
2376         }
2377 #endif
2378         if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) {
2379                 snd_card_free(card);
2380                 return err;
2381         }
2382         if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) {
2383                 snd_card_free(card);
2384                 return err;
2385         }
2386         if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) {
2387                 snd_card_free(card);
2388                 return err;
2389         }
2390
2391         snd_ensoniq_create_gameport(ensoniq, dev);
2392
2393         strcpy(card->driver, DRIVER_NAME);
2394
2395         strcpy(card->shortname, "Ensoniq AudioPCI");
2396         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2397                 card->shortname,
2398                 card->driver,
2399                 ensoniq->port,
2400                 ensoniq->irq);
2401
2402         if ((err = snd_card_register(card)) < 0) {
2403                 snd_card_free(card);
2404                 return err;
2405         }
2406
2407         pci_set_drvdata(pci, card);
2408         dev++;
2409         return 0;
2410 }
2411
2412 static void snd_audiopci_remove(struct pci_dev *pci)
2413 {
2414         snd_card_free(pci_get_drvdata(pci));
2415 }
2416
2417 static struct pci_driver ens137x_driver = {
2418         .name = KBUILD_MODNAME,
2419         .id_table = snd_audiopci_ids,
2420         .probe = snd_audiopci_probe,
2421         .remove = snd_audiopci_remove,
2422         .driver = {
2423                 .pm = SND_ENSONIQ_PM_OPS,
2424         },
2425 };
2426
2427 module_pci_driver(ens137x_driver);