drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string_helpers.h>
  27 #include <linux/uaccess.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_debugfs.h"
  33 #include "dm_helpers.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "resource.h"
  36 #include "dsc.h"
  37 #include "dc_link_dp.h"
  38 #include "link_hwss.h"
  39 #include "dc/dc_dmub_srv.h"
  40
  41 struct dmub_debugfs_trace_header {
  42         uint32_t entry_count;
  43         uint32_t reserved[3];
  44 };
  45
  46 struct dmub_debugfs_trace_entry {
  47         uint32_t trace_code;
  48         uint32_t tick_count;
  49         uint32_t param0;
  50         uint32_t param1;
  51 };
  52
  53 static const char *const mst_progress_status[] = {
  54         "probe",
  55         "remote_edid",
  56         "allocate_new_payload",
  57         "clear_allocated_payload",
  58 };
  59
  60 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  61  *
  62  * Function takes in attributes passed to debugfs write entry
  63  * and writes into param array.
  64  * The user passes max_param_num to identify maximum number of
  65  * parameters that could be parsed.
  66  *
  67  */
  68 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  69                                           long *param, const char __user *buf,
  70                                           int max_param_num,
  71                                           uint8_t *param_nums)
  72 {
  73         char *wr_buf_ptr = NULL;
  74         uint32_t wr_buf_count = 0;
  75         int r;
  76         char *sub_str = NULL;
  77         const char delimiter[3] = {' ', '\n', '\0'};
  78         uint8_t param_index = 0;
  79
  80         *param_nums = 0;
  81
  82         wr_buf_ptr = wr_buf;
  83
  84         /* r is bytes not be copied */
  85         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  86                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  87                 return -EFAULT;
  88         }
  89
  90         /* check number of parameters. isspace could not differ space and \n */
  91         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  92                 /* skip space*/
  93                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  94                         wr_buf_ptr++;
  95                         wr_buf_count++;
  96                         }
  97
  98                 if (wr_buf_count == wr_buf_size)
  99                         break;
 100
 101                 /* skip non-space*/
 102                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 103                         wr_buf_ptr++;
 104                         wr_buf_count++;
 105                 }
 106
 107                 (*param_nums)++;
 108
 109                 if (wr_buf_count == wr_buf_size)
 110                         break;
 111         }
 112
 113         if (*param_nums > max_param_num)
 114                 *param_nums = max_param_num;
 115
 116         wr_buf_ptr = wr_buf; /* reset buf pointer */
 117         wr_buf_count = 0; /* number of char already checked */
 118
 119         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 120                 wr_buf_ptr++;
 121                 wr_buf_count++;
 122         }
 123
 124         while (param_index < *param_nums) {
 125                 /* after strsep, wr_buf_ptr will be moved to after space */
 126                 sub_str = strsep(&wr_buf_ptr, delimiter);
 127
 128                 r = kstrtol(sub_str, 16, &(param[param_index]));
 129
 130                 if (r)
 131                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 132
 133                 param_index++;
 134         }
 135
 136         return 0;
 137 }
 138
 139 /* function description
 140  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 141  *
 142  * valid lane count value: 1, 2, 4
 143  * valid link rate value:
 144  * 06h = 1.62Gbps per lane
 145  * 0Ah = 2.7Gbps per lane
 146  * 0Ch = 3.24Gbps per lane
 147  * 14h = 5.4Gbps per lane
 148  * 1Eh = 8.1Gbps per lane
 149  *
 150  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 151  *
 152  * --- to get dp configuration
 153  *
 154  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 155  *
 156  * It will list current, verified, reported, preferred dp configuration.
 157  * current -- for current video mode
 158  * verified --- maximum configuration which pass link training
 159  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 160  * preferred --- user force settings
 161  *
 162  * --- set (or force) dp configuration
 163  *
 164  * echo <lane_count>  <link_rate> > link_settings
 165  *
 166  * for example, to force to  2 lane, 2.7GHz,
 167  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 168  *
 169  * spread_spectrum could not be changed dynamically.
 170  *
 171  * in case invalid lane count, link rate are force, no hw programming will be
 172  * done. please check link settings after force operation to see if HW get
 173  * programming.
 174  *
 175  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 176  *
 177  * check current and preferred settings.
 178  *
 179  */
 180 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 181                                  size_t size, loff_t *pos)
 182 {
 183         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 184         struct dc_link *link = connector->dc_link;
 185         char *rd_buf = NULL;
 186         char *rd_buf_ptr = NULL;
 187         const uint32_t rd_buf_size = 100;
 188         uint32_t result = 0;
 189         uint8_t str_len = 0;
 190         int r;
 191
 192         if (*pos & 3 || size & 3)
 193                 return -EINVAL;
 194
 195         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 196         if (!rd_buf)
 197                 return 0;
 198
 199         rd_buf_ptr = rd_buf;
 200
 201         str_len = strlen("Current:  %d  0x%x  %d  ");
 202         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 203                         link->cur_link_settings.lane_count,
 204                         link->cur_link_settings.link_rate,
 205                         link->cur_link_settings.link_spread);
 206         rd_buf_ptr += str_len;
 207
 208         str_len = strlen("Verified:  %d  0x%x  %d  ");
 209         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 210                         link->verified_link_cap.lane_count,
 211                         link->verified_link_cap.link_rate,
 212                         link->verified_link_cap.link_spread);
 213         rd_buf_ptr += str_len;
 214
 215         str_len = strlen("Reported:  %d  0x%x  %d  ");
 216         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 217                         link->reported_link_cap.lane_count,
 218                         link->reported_link_cap.link_rate,
 219                         link->reported_link_cap.link_spread);
 220         rd_buf_ptr += str_len;
 221
 222         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 223         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 224                         link->preferred_link_setting.lane_count,
 225                         link->preferred_link_setting.link_rate,
 226                         link->preferred_link_setting.link_spread);
 227
 228         while (size) {
 229                 if (*pos >= rd_buf_size)
 230                         break;
 231
 232                 r = put_user(*(rd_buf + result), buf);
 233                 if (r) {
 234                         kfree(rd_buf);
 235                         return r; /* r = -EFAULT */
 236                 }
 237
 238                 buf += 1;
 239                 size -= 1;
 240                 *pos += 1;
 241                 result += 1;
 242         }
 243
 244         kfree(rd_buf);
 245         return result;
 246 }
 247
 248 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 249                                  size_t size, loff_t *pos)
 250 {
 251         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 252         struct dc_link *link = connector->dc_link;
 253         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 254         struct dc *dc = (struct dc *)link->dc;
 255         struct dc_link_settings prefer_link_settings;
 256         char *wr_buf = NULL;
 257         const uint32_t wr_buf_size = 40;
 258         /* 0: lane_count; 1: link_rate */
 259         int max_param_num = 2;
 260         uint8_t param_nums = 0;
 261         long param[2];
 262         bool valid_input = true;
 263
 264         if (size == 0)
 265                 return -EINVAL;
 266
 267         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 268         if (!wr_buf)
 269                 return -ENOSPC;
 270
 271         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 272                                            (long *)param, buf,
 273                                            max_param_num,
 274                                            &param_nums)) {
 275                 kfree(wr_buf);
 276                 return -EINVAL;
 277         }
 278
 279         if (param_nums <= 0) {
 280                 kfree(wr_buf);
 281                 DRM_DEBUG_DRIVER("user data not be read\n");
 282                 return -EINVAL;
 283         }
 284
 285         switch (param[0]) {
 286         case LANE_COUNT_ONE:
 287         case LANE_COUNT_TWO:
 288         case LANE_COUNT_FOUR:
 289                 break;
 290         default:
 291                 valid_input = false;
 292                 break;
 293         }
 294
 295         switch (param[1]) {
 296         case LINK_RATE_LOW:
 297         case LINK_RATE_HIGH:
 298         case LINK_RATE_RBR2:
 299         case LINK_RATE_HIGH2:
 300         case LINK_RATE_HIGH3:
 301         case LINK_RATE_UHBR10:
 302                 break;
 303         default:
 304                 valid_input = false;
 305                 break;
 306         }
 307
 308         if (!valid_input) {
 309                 kfree(wr_buf);
 310                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 311                 mutex_lock(&adev->dm.dc_lock);
 312                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 313                 mutex_unlock(&adev->dm.dc_lock);
 314                 return size;
 315         }
 316
 317         /* save user force lane_count, link_rate to preferred settings
 318          * spread spectrum will not be changed
 319          */
 320         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 321         prefer_link_settings.use_link_rate_set = false;
 322         prefer_link_settings.lane_count = param[0];
 323         prefer_link_settings.link_rate = param[1];
 324
 325         mutex_lock(&adev->dm.dc_lock);
 326         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 327         mutex_unlock(&adev->dm.dc_lock);
 328
 329         kfree(wr_buf);
 330         return size;
 331 }
 332
 333 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 334  * post-cursor2 (defined by VESA DP specification)
 335  *
 336  * valid values
 337  * voltage swing: 0,1,2,3
 338  * pre-emphasis : 0,1,2,3
 339  * post cursor2 : 0,1,2,3
 340  *
 341  *
 342  * how to use this debugfs
 343  *
 344  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 345  *
 346  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 347  *
 348  * To figure out which DP-x is the display for DP to be check,
 349  * cd DP-x
 350  * ls -ll
 351  * There should be debugfs file, like link_settings, phy_settings.
 352  * cat link_settings
 353  * from lane_count, link_rate to figure which DP-x is for display to be worked
 354  * on
 355  *
 356  * To get current DP PHY settings,
 357  * cat phy_settings
 358  *
 359  * To change DP PHY settings,
 360  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 361  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 362  * 0,
 363  * echo 2 3 0 > phy_settings
 364  *
 365  * To check if change be applied, get current phy settings by
 366  * cat phy_settings
 367  *
 368  * In case invalid values are set by user, like
 369  * echo 1 4 0 > phy_settings
 370  *
 371  * HW will NOT be programmed by these settings.
 372  * cat phy_settings will show the previous valid settings.
 373  */
 374 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 375                                  size_t size, loff_t *pos)
 376 {
 377         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 378         struct dc_link *link = connector->dc_link;
 379         char *rd_buf = NULL;
 380         const uint32_t rd_buf_size = 20;
 381         uint32_t result = 0;
 382         int r;
 383
 384         if (*pos & 3 || size & 3)
 385                 return -EINVAL;
 386
 387         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 388         if (!rd_buf)
 389                 return -EINVAL;
 390
 391         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 392                         link->cur_lane_setting[0].VOLTAGE_SWING,
 393                         link->cur_lane_setting[0].PRE_EMPHASIS,
 394                         link->cur_lane_setting[0].POST_CURSOR2);
 395
 396         while (size) {
 397                 if (*pos >= rd_buf_size)
 398                         break;
 399
 400                 r = put_user((*(rd_buf + result)), buf);
 401                 if (r) {
 402                         kfree(rd_buf);
 403                         return r; /* r = -EFAULT */
 404                 }
 405
 406                 buf += 1;
 407                 size -= 1;
 408                 *pos += 1;
 409                 result += 1;
 410         }
 411
 412         kfree(rd_buf);
 413         return result;
 414 }
 415
 416 static int dp_lttpr_status_show(struct seq_file *m, void *d)
 417 {
 418         char *data;
 419         struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
 420         struct dc_link *link = connector->dc_link;
 421         uint32_t read_size = 1;
 422         uint8_t repeater_count = 0;
 423
 424         data = kzalloc(read_size, GFP_KERNEL);
 425         if (!data)
 426                 return 0;
 427
 428         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
 429
 430         switch ((uint8_t)*data) {
 431         case 0x80:
 432                 repeater_count = 1;
 433                 break;
 434         case 0x40:
 435                 repeater_count = 2;
 436                 break;
 437         case 0x20:
 438                 repeater_count = 3;
 439                 break;
 440         case 0x10:
 441                 repeater_count = 4;
 442                 break;
 443         case 0x8:
 444                 repeater_count = 5;
 445                 break;
 446         case 0x4:
 447                 repeater_count = 6;
 448                 break;
 449         case 0x2:
 450                 repeater_count = 7;
 451                 break;
 452         case 0x1:
 453                 repeater_count = 8;
 454                 break;
 455         case 0x0:
 456                 repeater_count = 0;
 457                 break;
 458         default:
 459                 repeater_count = (uint8_t)*data;
 460                 break;
 461         }
 462
 463         seq_printf(m, "phy repeater count: %d\n", repeater_count);
 464
 465         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
 466
 467         if ((uint8_t)*data == 0x55)
 468                 seq_printf(m, "phy repeater mode: transparent\n");
 469         else if ((uint8_t)*data == 0xAA)
 470                 seq_printf(m, "phy repeater mode: non-transparent\n");
 471         else if ((uint8_t)*data == 0x00)
 472                 seq_printf(m, "phy repeater mode: non lttpr\n");
 473         else
 474                 seq_printf(m, "phy repeater mode: read error\n");
 475
 476         kfree(data);
 477         return 0;
 478 }
 479
 480 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 481                                  size_t size, loff_t *pos)
 482 {
 483         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 484         struct dc_link *link = connector->dc_link;
 485         struct dc *dc = (struct dc *)link->dc;
 486         char *wr_buf = NULL;
 487         uint32_t wr_buf_size = 40;
 488         long param[3];
 489         bool use_prefer_link_setting;
 490         struct link_training_settings link_lane_settings;
 491         int max_param_num = 3;
 492         uint8_t param_nums = 0;
 493         int r = 0;
 494
 495
 496         if (size == 0)
 497                 return -EINVAL;
 498
 499         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 500         if (!wr_buf)
 501                 return -ENOSPC;
 502
 503         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 504                                            (long *)param, buf,
 505                                            max_param_num,
 506                                            &param_nums)) {
 507                 kfree(wr_buf);
 508                 return -EINVAL;
 509         }
 510
 511         if (param_nums <= 0) {
 512                 kfree(wr_buf);
 513                 DRM_DEBUG_DRIVER("user data not be read\n");
 514                 return -EINVAL;
 515         }
 516
 517         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 518                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 519                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 520                 kfree(wr_buf);
 521                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 522                 return size;
 523         }
 524
 525         /* get link settings: lane count, link rate */
 526         use_prefer_link_setting =
 527                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 528                 (link->test_pattern_enabled));
 529
 530         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 531
 532         if (use_prefer_link_setting) {
 533                 link_lane_settings.link_settings.lane_count =
 534                                 link->preferred_link_setting.lane_count;
 535                 link_lane_settings.link_settings.link_rate =
 536                                 link->preferred_link_setting.link_rate;
 537                 link_lane_settings.link_settings.link_spread =
 538                                 link->preferred_link_setting.link_spread;
 539         } else {
 540                 link_lane_settings.link_settings.lane_count =
 541                                 link->cur_link_settings.lane_count;
 542                 link_lane_settings.link_settings.link_rate =
 543                                 link->cur_link_settings.link_rate;
 544                 link_lane_settings.link_settings.link_spread =
 545                                 link->cur_link_settings.link_spread;
 546         }
 547
 548         /* apply phy settings from user */
 549         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 550                 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 551                                 (enum dc_voltage_swing) (param[0]);
 552                 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 553                                 (enum dc_pre_emphasis) (param[1]);
 554                 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 555                                 (enum dc_post_cursor2) (param[2]);
 556         }
 557
 558         /* program ASIC registers and DPCD registers */
 559         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 560
 561         kfree(wr_buf);
 562         return size;
 563 }
 564
 565 /* function description
 566  *
 567  * set PHY layer or Link layer test pattern
 568  * PHY test pattern is used for PHY SI check.
 569  * Link layer test will not affect PHY SI.
 570  *
 571  * Reset Test Pattern:
 572  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 573  *
 574  * PHY test pattern supported:
 575  * 1 = DP_TEST_PATTERN_D102
 576  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 577  * 3 = DP_TEST_PATTERN_PRBS7
 578  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 579  * 5 = DP_TEST_PATTERN_CP2520_1
 580  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 581  * 7 = DP_TEST_PATTERN_CP2520_3
 582  *
 583  * DP PHY Link Training Patterns
 584  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 585  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 586  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 587  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 588  *
 589  * DP Link Layer Test pattern
 590  * c = DP_TEST_PATTERN_COLOR_SQUARES
 591  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 592  * e = DP_TEST_PATTERN_VERTICAL_BARS
 593  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 594  * 10= DP_TEST_PATTERN_COLOR_RAMP
 595  *
 596  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 597  *
 598  * --- set test pattern
 599  * echo <test pattern #> > test_pattern
 600  *
 601  * If test pattern # is not supported, NO HW programming will be done.
 602  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 603  * for the user pattern. input 10 bytes data are separated by space
 604  *
 605  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 606  *
 607  * --- reset test pattern
 608  * echo 0 > test_pattern
 609  *
 610  * --- HPD detection is disabled when set PHY test pattern
 611  *
 612  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 613  * is disable. User could unplug DP display from DP connected and plug scope to
 614  * check test pattern PHY SI.
 615  * If there is need unplug scope and plug DP display back, do steps below:
 616  * echo 0 > phy_test_pattern
 617  * unplug scope
 618  * plug DP display.
 619  *
 620  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 621  * driver could detect "unplug scope" and "plug DP display"
 622  */
 623 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 624                                  size_t size, loff_t *pos)
 625 {
 626         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 627         struct dc_link *link = connector->dc_link;
 628         char *wr_buf = NULL;
 629         uint32_t wr_buf_size = 100;
 630         long param[11] = {0x0};
 631         int max_param_num = 11;
 632         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 633         bool disable_hpd = false;
 634         bool valid_test_pattern = false;
 635         uint8_t param_nums = 0;
 636         /* init with default 80bit custom pattern */
 637         uint8_t custom_pattern[10] = {
 638                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 639                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 640                         };
 641         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 642                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 643         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 644                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 645         struct link_training_settings link_training_settings;
 646         int i;
 647
 648         if (size == 0)
 649                 return -EINVAL;
 650
 651         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 652         if (!wr_buf)
 653                 return -ENOSPC;
 654
 655         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 656                                            (long *)param, buf,
 657                                            max_param_num,
 658                                            &param_nums)) {
 659                 kfree(wr_buf);
 660                 return -EINVAL;
 661         }
 662
 663         if (param_nums <= 0) {
 664                 kfree(wr_buf);
 665                 DRM_DEBUG_DRIVER("user data not be read\n");
 666                 return -EINVAL;
 667         }
 668
 669
 670         test_pattern = param[0];
 671
 672         switch (test_pattern) {
 673         case DP_TEST_PATTERN_VIDEO_MODE:
 674         case DP_TEST_PATTERN_COLOR_SQUARES:
 675         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 676         case DP_TEST_PATTERN_VERTICAL_BARS:
 677         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 678         case DP_TEST_PATTERN_COLOR_RAMP:
 679                 valid_test_pattern = true;
 680                 break;
 681
 682         case DP_TEST_PATTERN_D102:
 683         case DP_TEST_PATTERN_SYMBOL_ERROR:
 684         case DP_TEST_PATTERN_PRBS7:
 685         case DP_TEST_PATTERN_80BIT_CUSTOM:
 686         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 687         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 688                 disable_hpd = true;
 689                 valid_test_pattern = true;
 690                 break;
 691
 692         default:
 693                 valid_test_pattern = false;
 694                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 695                 break;
 696         }
 697
 698         if (!valid_test_pattern) {
 699                 kfree(wr_buf);
 700                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 701                 return size;
 702         }
 703
 704         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 705                 for (i = 0; i < 10; i++) {
 706                         if ((uint8_t) param[i + 1] != 0x0)
 707                                 break;
 708                 }
 709
 710                 if (i < 10) {
 711                         /* not use default value */
 712                         for (i = 0; i < 10; i++)
 713                                 custom_pattern[i] = (uint8_t) param[i + 1];
 714                 }
 715         }
 716
 717         /* Usage: set DP physical test pattern using debugfs with normal DP
 718          * panel. Then plug out DP panel and connect a scope to measure
 719          * For normal video mode and test pattern generated from CRCT,
 720          * they are visibile to user. So do not disable HPD.
 721          * Video Mode is also set to clear the test pattern, so enable HPD
 722          * because it might have been disabled after a test pattern was set.
 723          * AUX depends on HPD * sequence dependent, do not move!
 724          */
 725         if (!disable_hpd)
 726                 dc_link_enable_hpd(link);
 727
 728         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 729         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 730         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 731
 732         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 733         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 734         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 735
 736         link_training_settings.link_settings = cur_link_settings;
 737
 738
 739         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 740                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 741                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 742                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 743                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 744                         link_training_settings.link_settings = prefer_link_settings;
 745         }
 746
 747         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 748                 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 749
 750         dc_link_set_test_pattern(
 751                 link,
 752                 test_pattern,
 753                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 754                 &link_training_settings,
 755                 custom_pattern,
 756                 10);
 757
 758         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 759          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 760          * Need disable interrupt to avoid SW driver disable DP output. This is
 761          * done after the test pattern is set.
 762          */
 763         if (valid_test_pattern && disable_hpd)
 764                 dc_link_disable_hpd(link);
 765
 766         kfree(wr_buf);
 767
 768         return size;
 769 }
 770
 771 /*
 772  * Returns the DMCUB tracebuffer contents.
 773  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 774  */
 775 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 776 {
 777         struct amdgpu_device *adev = m->private;
 778         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 779         struct dmub_debugfs_trace_entry *entries;
 780         uint8_t *tbuf_base;
 781         uint32_t tbuf_size, max_entries, num_entries, i;
 782
 783         if (!fb_info)
 784                 return 0;
 785
 786         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 787         if (!tbuf_base)
 788                 return 0;
 789
 790         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 791         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 792                       sizeof(struct dmub_debugfs_trace_entry);
 793
 794         num_entries =
 795                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 796
 797         num_entries = min(num_entries, max_entries);
 798
 799         entries = (struct dmub_debugfs_trace_entry
 800                            *)(tbuf_base +
 801                               sizeof(struct dmub_debugfs_trace_header));
 802
 803         for (i = 0; i < num_entries; ++i) {
 804                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 805
 806                 seq_printf(m,
 807                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 808                            entry->trace_code, entry->tick_count, entry->param0,
 809                            entry->param1);
 810         }
 811
 812         return 0;
 813 }
 814
 815 /*
 816  * Returns the DMCUB firmware state contents.
 817  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 818  */
 819 static int dmub_fw_state_show(struct seq_file *m, void *data)
 820 {
 821         struct amdgpu_device *adev = m->private;
 822         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 823         uint8_t *state_base;
 824         uint32_t state_size;
 825
 826         if (!fb_info)
 827                 return 0;
 828
 829         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 830         if (!state_base)
 831                 return 0;
 832
 833         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 834
 835         return seq_write(m, state_base, state_size);
 836 }
 837
 838 /* psr_capability_show() - show eDP panel PSR capability
 839  *
 840  * The read function: sink_psr_capability_show
 841  * Shows if sink has PSR capability or not.
 842  * If yes - the PSR version is appended
 843  *
 844  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 845  *
 846  * Expected output:
 847  * "Sink support: no\n" - if panel doesn't support PSR
 848  * "Sink support: yes [0x01]\n" - if panel supports PSR1
 849  * "Driver support: no\n" - if driver doesn't support PSR
 850  * "Driver support: yes [0x01]\n" - if driver supports PSR1
 851  */
 852 static int psr_capability_show(struct seq_file *m, void *data)
 853 {
 854         struct drm_connector *connector = m->private;
 855         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 856         struct dc_link *link = aconnector->dc_link;
 857
 858         if (!link)
 859                 return -ENODEV;
 860
 861         if (link->type == dc_connection_none)
 862                 return -ENODEV;
 863
 864         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 865                 return -ENODEV;
 866
 867         seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
 868         if (link->dpcd_caps.psr_info.psr_version)
 869                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
 870         seq_puts(m, "\n");
 871
 872         seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
 873         if (link->psr_settings.psr_version)
 874                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
 875         seq_puts(m, "\n");
 876
 877         return 0;
 878 }
 879
 880 /*
 881  * Returns the current bpc for the crtc.
 882  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
 883  */
 884 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
 885 {
 886         struct drm_crtc *crtc = m->private;
 887         struct drm_device *dev = crtc->dev;
 888         struct dm_crtc_state *dm_crtc_state = NULL;
 889         int res = -ENODEV;
 890         unsigned int bpc;
 891
 892         mutex_lock(&dev->mode_config.mutex);
 893         drm_modeset_lock(&crtc->mutex, NULL);
 894         if (crtc->state == NULL)
 895                 goto unlock;
 896
 897         dm_crtc_state = to_dm_crtc_state(crtc->state);
 898         if (dm_crtc_state->stream == NULL)
 899                 goto unlock;
 900
 901         switch (dm_crtc_state->stream->timing.display_color_depth) {
 902         case COLOR_DEPTH_666:
 903                 bpc = 6;
 904                 break;
 905         case COLOR_DEPTH_888:
 906                 bpc = 8;
 907                 break;
 908         case COLOR_DEPTH_101010:
 909                 bpc = 10;
 910                 break;
 911         case COLOR_DEPTH_121212:
 912                 bpc = 12;
 913                 break;
 914         case COLOR_DEPTH_161616:
 915                 bpc = 16;
 916                 break;
 917         default:
 918                 goto unlock;
 919         }
 920
 921         seq_printf(m, "Current: %u\n", bpc);
 922         res = 0;
 923
 924 unlock:
 925         drm_modeset_unlock(&crtc->mutex);
 926         mutex_unlock(&dev->mode_config.mutex);
 927
 928         return res;
 929 }
 930 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
 931
 932 /*
 933  * Example usage:
 934  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 935  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 936  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 937  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 938  */
 939 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 940                                  size_t size, loff_t *pos)
 941 {
 942         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 943         char *wr_buf = NULL;
 944         uint32_t wr_buf_size = 42;
 945         int max_param_num = 1;
 946         long param;
 947         uint8_t param_nums = 0;
 948
 949         if (size == 0)
 950                 return -EINVAL;
 951
 952         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 953
 954         if (!wr_buf) {
 955                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 956                 return -ENOSPC;
 957         }
 958
 959         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 960                                            &param, buf,
 961                                            max_param_num,
 962                                            &param_nums)) {
 963                 kfree(wr_buf);
 964                 return -EINVAL;
 965         }
 966
 967         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 968
 969         kfree(wr_buf);
 970         return 0;
 971 }
 972
 973 #ifdef CONFIG_DRM_AMD_DC_HDCP
 974 /*
 975  * Returns the HDCP capability of the Display (1.4 for now).
 976  *
 977  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 978  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 979  *
 980  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 981  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 982  */
 983 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 984 {
 985         struct drm_connector *connector = m->private;
 986         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 987         bool hdcp_cap, hdcp2_cap;
 988
 989         if (connector->status != connector_status_connected)
 990                 return -ENODEV;
 991
 992         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 993
 994         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 995         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 996
 997
 998         if (hdcp_cap)
 999                 seq_printf(m, "%s ", "HDCP1.4");
1000         if (hdcp2_cap)
1001                 seq_printf(m, "%s ", "HDCP2.2");
1002
1003         if (!hdcp_cap && !hdcp2_cap)
1004                 seq_printf(m, "%s ", "None");
1005
1006         seq_puts(m, "\n");
1007
1008         return 0;
1009 }
1010 #endif
1011
1012 /*
1013  * Returns whether the connected display is internal and not hotpluggable.
1014  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1015  */
1016 static int internal_display_show(struct seq_file *m, void *data)
1017 {
1018         struct drm_connector *connector = m->private;
1019         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1020         struct dc_link *link = aconnector->dc_link;
1021
1022         seq_printf(m, "Internal: %u\n", link->is_internal_display);
1023
1024         return 0;
1025 }
1026
1027 /* function description
1028  *
1029  * generic SDP message access for testing
1030  *
1031  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1032  *
1033  * SDP header
1034  * Hb0 : Secondary-Data Packet ID
1035  * Hb1 : Secondary-Data Packet type
1036  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1037  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1038  *
1039  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1040  */
1041 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1042                                  size_t size, loff_t *pos)
1043 {
1044         int r;
1045         uint8_t data[36];
1046         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1047         struct dm_crtc_state *acrtc_state;
1048         uint32_t write_size = 36;
1049
1050         if (connector->base.status != connector_status_connected)
1051                 return -ENODEV;
1052
1053         if (size == 0)
1054                 return 0;
1055
1056         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1057
1058         r = copy_from_user(data, buf, write_size);
1059
1060         write_size -= r;
1061
1062         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1063
1064         return write_size;
1065 }
1066
1067 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1068                                  size_t size, loff_t *pos)
1069 {
1070         int r;
1071         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1072
1073         if (size < sizeof(connector->debugfs_dpcd_address))
1074                 return -EINVAL;
1075
1076         r = copy_from_user(&connector->debugfs_dpcd_address,
1077                         buf, sizeof(connector->debugfs_dpcd_address));
1078
1079         return size - r;
1080 }
1081
1082 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1083                                  size_t size, loff_t *pos)
1084 {
1085         int r;
1086         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1087
1088         if (size < sizeof(connector->debugfs_dpcd_size))
1089                 return -EINVAL;
1090
1091         r = copy_from_user(&connector->debugfs_dpcd_size,
1092                         buf, sizeof(connector->debugfs_dpcd_size));
1093
1094         if (connector->debugfs_dpcd_size > 256)
1095                 connector->debugfs_dpcd_size = 0;
1096
1097         return size - r;
1098 }
1099
1100 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1101                                  size_t size, loff_t *pos)
1102 {
1103         int r;
1104         char *data;
1105         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1106         struct dc_link *link = connector->dc_link;
1107         uint32_t write_size = connector->debugfs_dpcd_size;
1108
1109         if (!write_size || size < write_size)
1110                 return -EINVAL;
1111
1112         data = kzalloc(write_size, GFP_KERNEL);
1113         if (!data)
1114                 return 0;
1115
1116         r = copy_from_user(data, buf, write_size);
1117
1118         dm_helpers_dp_write_dpcd(link->ctx, link,
1119                         connector->debugfs_dpcd_address, data, write_size - r);
1120         kfree(data);
1121         return write_size - r;
1122 }
1123
1124 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1125                                  size_t size, loff_t *pos)
1126 {
1127         int r;
1128         char *data;
1129         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1130         struct dc_link *link = connector->dc_link;
1131         uint32_t read_size = connector->debugfs_dpcd_size;
1132
1133         if (!read_size || size < read_size)
1134                 return 0;
1135
1136         data = kzalloc(read_size, GFP_KERNEL);
1137         if (!data)
1138                 return 0;
1139
1140         dm_helpers_dp_read_dpcd(link->ctx, link,
1141                         connector->debugfs_dpcd_address, data, read_size);
1142
1143         r = copy_to_user(buf, data, read_size);
1144
1145         kfree(data);
1146         return read_size - r;
1147 }
1148
1149 /* function: Read link's DSC & FEC capabilities
1150  *
1151  *
1152  * Access it with the following command (you need to specify
1153  * connector like DP-1):
1154  *
1155  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1156  *
1157  */
1158 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1159 {
1160         struct drm_connector *connector = m->private;
1161         struct drm_modeset_acquire_ctx ctx;
1162         struct drm_device *dev = connector->dev;
1163         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1164         int ret = 0;
1165         bool try_again = false;
1166         bool is_fec_supported = false;
1167         bool is_dsc_supported = false;
1168         struct dpcd_caps dpcd_caps;
1169
1170         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1171         do {
1172                 try_again = false;
1173                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1174                 if (ret) {
1175                         if (ret == -EDEADLK) {
1176                                 ret = drm_modeset_backoff(&ctx);
1177                                 if (!ret) {
1178                                         try_again = true;
1179                                         continue;
1180                                 }
1181                         }
1182                         break;
1183                 }
1184                 if (connector->status != connector_status_connected) {
1185                         ret = -ENODEV;
1186                         break;
1187                 }
1188                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1189                 if (aconnector->port) {
1190                         /* aconnector sets dsc_aux during get_modes call
1191                          * if MST connector has it means it can either
1192                          * enable DSC on the sink device or on MST branch
1193                          * its connected to.
1194                          */
1195                         if (aconnector->dsc_aux) {
1196                                 is_fec_supported = true;
1197                                 is_dsc_supported = true;
1198                         }
1199                 } else {
1200                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1201                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1202                 }
1203         } while (try_again);
1204
1205         drm_modeset_drop_locks(&ctx);
1206         drm_modeset_acquire_fini(&ctx);
1207
1208         seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1209         seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1210
1211         return ret;
1212 }
1213
1214 /* function: Trigger virtual HPD redetection on connector
1215  *
1216  * This function will perform link rediscovery, link disable
1217  * and enable, and dm connector state update.
1218  *
1219  * Retrigger HPD on an existing connector by echoing 1 into
1220  * its respectful "trigger_hotplug" debugfs entry:
1221  *
1222  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1223  *
1224  * This function can perform HPD unplug:
1225  *
1226  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1227  *
1228  */
1229 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1230                                                         size_t size, loff_t *pos)
1231 {
1232         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1233         struct drm_connector *connector = &aconnector->base;
1234         struct dc_link *link = NULL;
1235         struct drm_device *dev = connector->dev;
1236         struct amdgpu_device *adev = drm_to_adev(dev);
1237         enum dc_connection_type new_connection_type = dc_connection_none;
1238         char *wr_buf = NULL;
1239         uint32_t wr_buf_size = 42;
1240         int max_param_num = 1;
1241         long param[1] = {0};
1242         uint8_t param_nums = 0;
1243         bool ret = false;
1244
1245         if (!aconnector || !aconnector->dc_link)
1246                 return -EINVAL;
1247
1248         if (size == 0)
1249                 return -EINVAL;
1250
1251         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1252
1253         if (!wr_buf) {
1254                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1255                 return -ENOSPC;
1256         }
1257
1258         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1259                                                 (long *)param, buf,
1260                                                 max_param_num,
1261                                                 &param_nums)) {
1262                 kfree(wr_buf);
1263                 return -EINVAL;
1264         }
1265
1266         kfree(wr_buf);
1267
1268         if (param_nums <= 0) {
1269                 DRM_DEBUG_DRIVER("user data not be read\n");
1270                 return -EINVAL;
1271         }
1272
1273         mutex_lock(&aconnector->hpd_lock);
1274
1275         /* Don't support for mst end device*/
1276         if (aconnector->mst_port) {
1277                 mutex_unlock(&aconnector->hpd_lock);
1278                 return -EINVAL;
1279         }
1280
1281         if (param[0] == 1) {
1282
1283                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1284                         new_connection_type != dc_connection_none)
1285                         goto unlock;
1286
1287                 mutex_lock(&adev->dm.dc_lock);
1288                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1289                 mutex_unlock(&adev->dm.dc_lock);
1290
1291                 if (!ret)
1292                         goto unlock;
1293
1294                 amdgpu_dm_update_connector_after_detect(aconnector);
1295
1296                 drm_modeset_lock_all(dev);
1297                 dm_restore_drm_connector_state(dev, connector);
1298                 drm_modeset_unlock_all(dev);
1299
1300                 drm_kms_helper_connector_hotplug_event(connector);
1301         } else if (param[0] == 0) {
1302                 if (!aconnector->dc_link)
1303                         goto unlock;
1304
1305                 link = aconnector->dc_link;
1306
1307                 if (link->local_sink) {
1308                         dc_sink_release(link->local_sink);
1309                         link->local_sink = NULL;
1310                 }
1311
1312                 link->dpcd_sink_count = 0;
1313                 link->type = dc_connection_none;
1314                 link->dongle_max_pix_clk = 0;
1315
1316                 amdgpu_dm_update_connector_after_detect(aconnector);
1317
1318                 /* If the aconnector is the root node in mst topology */
1319                 if (aconnector->mst_mgr.mst_state == true)
1320                         reset_cur_dp_mst_topology(link);
1321
1322                 drm_modeset_lock_all(dev);
1323                 dm_restore_drm_connector_state(dev, connector);
1324                 drm_modeset_unlock_all(dev);
1325
1326                 drm_kms_helper_connector_hotplug_event(connector);
1327         }
1328
1329 unlock:
1330         mutex_unlock(&aconnector->hpd_lock);
1331
1332         return size;
1333 }
1334
1335 /* function: read DSC status on the connector
1336  *
1337  * The read function: dp_dsc_clock_en_read
1338  * returns current status of DSC clock on the connector.
1339  * The return is a boolean flag: 1 or 0.
1340  *
1341  * Access it with the following command (you need to specify
1342  * connector like DP-1):
1343  *
1344  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1345  *
1346  * Expected output:
1347  * 1 - means that DSC is currently enabled
1348  * 0 - means that DSC is disabled
1349  */
1350 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1351                                     size_t size, loff_t *pos)
1352 {
1353         char *rd_buf = NULL;
1354         char *rd_buf_ptr = NULL;
1355         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1356         struct display_stream_compressor *dsc;
1357         struct dcn_dsc_state dsc_state = {0};
1358         const uint32_t rd_buf_size = 10;
1359         struct pipe_ctx *pipe_ctx;
1360         ssize_t result = 0;
1361         int i, r, str_len = 30;
1362
1363         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1364
1365         if (!rd_buf)
1366                 return -ENOMEM;
1367
1368         rd_buf_ptr = rd_buf;
1369
1370         for (i = 0; i < MAX_PIPES; i++) {
1371                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1372                 if (pipe_ctx && pipe_ctx->stream &&
1373                     pipe_ctx->stream->link == aconnector->dc_link)
1374                         break;
1375         }
1376
1377         if (!pipe_ctx) {
1378                 kfree(rd_buf);
1379                 return -ENXIO;
1380         }
1381
1382         dsc = pipe_ctx->stream_res.dsc;
1383         if (dsc)
1384                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1385
1386         snprintf(rd_buf_ptr, str_len,
1387                 "%d\n",
1388                 dsc_state.dsc_clock_en);
1389         rd_buf_ptr += str_len;
1390
1391         while (size) {
1392                 if (*pos >= rd_buf_size)
1393                         break;
1394
1395                 r = put_user(*(rd_buf + result), buf);
1396                 if (r) {
1397                         kfree(rd_buf);
1398                         return r; /* r = -EFAULT */
1399                 }
1400
1401                 buf += 1;
1402                 size -= 1;
1403                 *pos += 1;
1404                 result += 1;
1405         }
1406
1407         kfree(rd_buf);
1408         return result;
1409 }
1410
1411 /* function: write force DSC on the connector
1412  *
1413  * The write function: dp_dsc_clock_en_write
1414  * enables to force DSC on the connector.
1415  * User can write to either force enable or force disable DSC
1416  * on the next modeset or set it to driver default
1417  *
1418  * Accepted inputs:
1419  * 0 - default DSC enablement policy
1420  * 1 - force enable DSC on the connector
1421  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1422  *
1423  * Writing DSC settings is done with the following command:
1424  * - To force enable DSC (you need to specify
1425  * connector like DP-1):
1426  *
1427  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1428  *
1429  * - To return to default state set the flag to zero and
1430  * let driver deal with DSC automatically
1431  * (you need to specify connector like DP-1):
1432  *
1433  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1434  *
1435  */
1436 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1437                                      size_t size, loff_t *pos)
1438 {
1439         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1440         struct drm_connector *connector = &aconnector->base;
1441         struct drm_device *dev = connector->dev;
1442         struct drm_crtc *crtc = NULL;
1443         struct dm_crtc_state *dm_crtc_state = NULL;
1444         struct pipe_ctx *pipe_ctx;
1445         int i;
1446         char *wr_buf = NULL;
1447         uint32_t wr_buf_size = 42;
1448         int max_param_num = 1;
1449         long param[1] = {0};
1450         uint8_t param_nums = 0;
1451
1452         if (size == 0)
1453                 return -EINVAL;
1454
1455         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1456
1457         if (!wr_buf) {
1458                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1459                 return -ENOSPC;
1460         }
1461
1462         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1463                                             (long *)param, buf,
1464                                             max_param_num,
1465                                             &param_nums)) {
1466                 kfree(wr_buf);
1467                 return -EINVAL;
1468         }
1469
1470         if (param_nums <= 0) {
1471                 DRM_DEBUG_DRIVER("user data not be read\n");
1472                 kfree(wr_buf);
1473                 return -EINVAL;
1474         }
1475
1476         for (i = 0; i < MAX_PIPES; i++) {
1477                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1478                 if (pipe_ctx && pipe_ctx->stream &&
1479                     pipe_ctx->stream->link == aconnector->dc_link)
1480                         break;
1481         }
1482
1483         if (!pipe_ctx || !pipe_ctx->stream)
1484                 goto done;
1485
1486         // Get CRTC state
1487         mutex_lock(&dev->mode_config.mutex);
1488         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1489
1490         if (connector->state == NULL)
1491                 goto unlock;
1492
1493         crtc = connector->state->crtc;
1494         if (crtc == NULL)
1495                 goto unlock;
1496
1497         drm_modeset_lock(&crtc->mutex, NULL);
1498         if (crtc->state == NULL)
1499                 goto unlock;
1500
1501         dm_crtc_state = to_dm_crtc_state(crtc->state);
1502         if (dm_crtc_state->stream == NULL)
1503                 goto unlock;
1504
1505         if (param[0] == 1)
1506                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1507         else if (param[0] == 2)
1508                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1509         else
1510                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1511
1512         dm_crtc_state->dsc_force_changed = true;
1513
1514 unlock:
1515         if (crtc)
1516                 drm_modeset_unlock(&crtc->mutex);
1517         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1518         mutex_unlock(&dev->mode_config.mutex);
1519
1520 done:
1521         kfree(wr_buf);
1522         return size;
1523 }
1524
1525 /* function: read DSC slice width parameter on the connector
1526  *
1527  * The read function: dp_dsc_slice_width_read
1528  * returns dsc slice width used in the current configuration
1529  * The return is an integer: 0 or other positive number
1530  *
1531  * Access the status with the following command:
1532  *
1533  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1534  *
1535  * 0 - means that DSC is disabled
1536  *
1537  * Any other number more than zero represents the
1538  * slice width currently used by DSC in pixels
1539  *
1540  */
1541 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1542                                     size_t size, loff_t *pos)
1543 {
1544         char *rd_buf = NULL;
1545         char *rd_buf_ptr = NULL;
1546         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1547         struct display_stream_compressor *dsc;
1548         struct dcn_dsc_state dsc_state = {0};
1549         const uint32_t rd_buf_size = 100;
1550         struct pipe_ctx *pipe_ctx;
1551         ssize_t result = 0;
1552         int i, r, str_len = 30;
1553
1554         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1555
1556         if (!rd_buf)
1557                 return -ENOMEM;
1558
1559         rd_buf_ptr = rd_buf;
1560
1561         for (i = 0; i < MAX_PIPES; i++) {
1562                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1563                 if (pipe_ctx && pipe_ctx->stream &&
1564                     pipe_ctx->stream->link == aconnector->dc_link)
1565                         break;
1566         }
1567
1568         if (!pipe_ctx) {
1569                 kfree(rd_buf);
1570                 return -ENXIO;
1571         }
1572
1573         dsc = pipe_ctx->stream_res.dsc;
1574         if (dsc)
1575                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1576
1577         snprintf(rd_buf_ptr, str_len,
1578                 "%d\n",
1579                 dsc_state.dsc_slice_width);
1580         rd_buf_ptr += str_len;
1581
1582         while (size) {
1583                 if (*pos >= rd_buf_size)
1584                         break;
1585
1586                 r = put_user(*(rd_buf + result), buf);
1587                 if (r) {
1588                         kfree(rd_buf);
1589                         return r; /* r = -EFAULT */
1590                 }
1591
1592                 buf += 1;
1593                 size -= 1;
1594                 *pos += 1;
1595                 result += 1;
1596         }
1597
1598         kfree(rd_buf);
1599         return result;
1600 }
1601
1602 /* function: write DSC slice width parameter
1603  *
1604  * The write function: dp_dsc_slice_width_write
1605  * overwrites automatically generated DSC configuration
1606  * of slice width.
1607  *
1608  * The user has to write the slice width divisible by the
1609  * picture width.
1610  *
1611  * Also the user has to write width in hexidecimal
1612  * rather than in decimal.
1613  *
1614  * Writing DSC settings is done with the following command:
1615  * - To force overwrite slice width: (example sets to 1920 pixels)
1616  *
1617  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1618  *
1619  *  - To stop overwriting and let driver find the optimal size,
1620  * set the width to zero:
1621  *
1622  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1623  *
1624  */
1625 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1626                                      size_t size, loff_t *pos)
1627 {
1628         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1629         struct pipe_ctx *pipe_ctx;
1630         struct drm_connector *connector = &aconnector->base;
1631         struct drm_device *dev = connector->dev;
1632         struct drm_crtc *crtc = NULL;
1633         struct dm_crtc_state *dm_crtc_state = NULL;
1634         int i;
1635         char *wr_buf = NULL;
1636         uint32_t wr_buf_size = 42;
1637         int max_param_num = 1;
1638         long param[1] = {0};
1639         uint8_t param_nums = 0;
1640
1641         if (size == 0)
1642                 return -EINVAL;
1643
1644         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1645
1646         if (!wr_buf) {
1647                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1648                 return -ENOSPC;
1649         }
1650
1651         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1652                                             (long *)param, buf,
1653                                             max_param_num,
1654                                             &param_nums)) {
1655                 kfree(wr_buf);
1656                 return -EINVAL;
1657         }
1658
1659         if (param_nums <= 0) {
1660                 DRM_DEBUG_DRIVER("user data not be read\n");
1661                 kfree(wr_buf);
1662                 return -EINVAL;
1663         }
1664
1665         for (i = 0; i < MAX_PIPES; i++) {
1666                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1667                 if (pipe_ctx && pipe_ctx->stream &&
1668                     pipe_ctx->stream->link == aconnector->dc_link)
1669                         break;
1670         }
1671
1672         if (!pipe_ctx || !pipe_ctx->stream)
1673                 goto done;
1674
1675         // Safely get CRTC state
1676         mutex_lock(&dev->mode_config.mutex);
1677         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1678
1679         if (connector->state == NULL)
1680                 goto unlock;
1681
1682         crtc = connector->state->crtc;
1683         if (crtc == NULL)
1684                 goto unlock;
1685
1686         drm_modeset_lock(&crtc->mutex, NULL);
1687         if (crtc->state == NULL)
1688                 goto unlock;
1689
1690         dm_crtc_state = to_dm_crtc_state(crtc->state);
1691         if (dm_crtc_state->stream == NULL)
1692                 goto unlock;
1693
1694         if (param[0] > 0)
1695                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1696                                         pipe_ctx->stream->timing.h_addressable,
1697                                         param[0]);
1698         else
1699                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1700
1701         dm_crtc_state->dsc_force_changed = true;
1702
1703 unlock:
1704         if (crtc)
1705                 drm_modeset_unlock(&crtc->mutex);
1706         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1707         mutex_unlock(&dev->mode_config.mutex);
1708
1709 done:
1710         kfree(wr_buf);
1711         return size;
1712 }
1713
1714 /* function: read DSC slice height parameter on the connector
1715  *
1716  * The read function: dp_dsc_slice_height_read
1717  * returns dsc slice height used in the current configuration
1718  * The return is an integer: 0 or other positive number
1719  *
1720  * Access the status with the following command:
1721  *
1722  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1723  *
1724  * 0 - means that DSC is disabled
1725  *
1726  * Any other number more than zero represents the
1727  * slice height currently used by DSC in pixels
1728  *
1729  */
1730 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1731                                     size_t size, loff_t *pos)
1732 {
1733         char *rd_buf = NULL;
1734         char *rd_buf_ptr = NULL;
1735         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1736         struct display_stream_compressor *dsc;
1737         struct dcn_dsc_state dsc_state = {0};
1738         const uint32_t rd_buf_size = 100;
1739         struct pipe_ctx *pipe_ctx;
1740         ssize_t result = 0;
1741         int i, r, str_len = 30;
1742
1743         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1744
1745         if (!rd_buf)
1746                 return -ENOMEM;
1747
1748         rd_buf_ptr = rd_buf;
1749
1750         for (i = 0; i < MAX_PIPES; i++) {
1751                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1752                 if (pipe_ctx && pipe_ctx->stream &&
1753                     pipe_ctx->stream->link == aconnector->dc_link)
1754                         break;
1755         }
1756
1757         if (!pipe_ctx) {
1758                 kfree(rd_buf);
1759                 return -ENXIO;
1760         }
1761
1762         dsc = pipe_ctx->stream_res.dsc;
1763         if (dsc)
1764                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1765
1766         snprintf(rd_buf_ptr, str_len,
1767                 "%d\n",
1768                 dsc_state.dsc_slice_height);
1769         rd_buf_ptr += str_len;
1770
1771         while (size) {
1772                 if (*pos >= rd_buf_size)
1773                         break;
1774
1775                 r = put_user(*(rd_buf + result), buf);
1776                 if (r) {
1777                         kfree(rd_buf);
1778                         return r; /* r = -EFAULT */
1779                 }
1780
1781                 buf += 1;
1782                 size -= 1;
1783                 *pos += 1;
1784                 result += 1;
1785         }
1786
1787         kfree(rd_buf);
1788         return result;
1789 }
1790
1791 /* function: write DSC slice height parameter
1792  *
1793  * The write function: dp_dsc_slice_height_write
1794  * overwrites automatically generated DSC configuration
1795  * of slice height.
1796  *
1797  * The user has to write the slice height divisible by the
1798  * picture height.
1799  *
1800  * Also the user has to write height in hexidecimal
1801  * rather than in decimal.
1802  *
1803  * Writing DSC settings is done with the following command:
1804  * - To force overwrite slice height (example sets to 128 pixels):
1805  *
1806  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1807  *
1808  *  - To stop overwriting and let driver find the optimal size,
1809  * set the height to zero:
1810  *
1811  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1812  *
1813  */
1814 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1815                                      size_t size, loff_t *pos)
1816 {
1817         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1818         struct drm_connector *connector = &aconnector->base;
1819         struct drm_device *dev = connector->dev;
1820         struct drm_crtc *crtc = NULL;
1821         struct dm_crtc_state *dm_crtc_state = NULL;
1822         struct pipe_ctx *pipe_ctx;
1823         int i;
1824         char *wr_buf = NULL;
1825         uint32_t wr_buf_size = 42;
1826         int max_param_num = 1;
1827         uint8_t param_nums = 0;
1828         long param[1] = {0};
1829
1830         if (size == 0)
1831                 return -EINVAL;
1832
1833         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1834
1835         if (!wr_buf) {
1836                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1837                 return -ENOSPC;
1838         }
1839
1840         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1841                                             (long *)param, buf,
1842                                             max_param_num,
1843                                             &param_nums)) {
1844                 kfree(wr_buf);
1845                 return -EINVAL;
1846         }
1847
1848         if (param_nums <= 0) {
1849                 DRM_DEBUG_DRIVER("user data not be read\n");
1850                 kfree(wr_buf);
1851                 return -EINVAL;
1852         }
1853
1854         for (i = 0; i < MAX_PIPES; i++) {
1855                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1856                 if (pipe_ctx && pipe_ctx->stream &&
1857                     pipe_ctx->stream->link == aconnector->dc_link)
1858                         break;
1859         }
1860
1861         if (!pipe_ctx || !pipe_ctx->stream)
1862                 goto done;
1863
1864         // Get CRTC state
1865         mutex_lock(&dev->mode_config.mutex);
1866         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1867
1868         if (connector->state == NULL)
1869                 goto unlock;
1870
1871         crtc = connector->state->crtc;
1872         if (crtc == NULL)
1873                 goto unlock;
1874
1875         drm_modeset_lock(&crtc->mutex, NULL);
1876         if (crtc->state == NULL)
1877                 goto unlock;
1878
1879         dm_crtc_state = to_dm_crtc_state(crtc->state);
1880         if (dm_crtc_state->stream == NULL)
1881                 goto unlock;
1882
1883         if (param[0] > 0)
1884                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1885                                         pipe_ctx->stream->timing.v_addressable,
1886                                         param[0]);
1887         else
1888                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1889
1890         dm_crtc_state->dsc_force_changed = true;
1891
1892 unlock:
1893         if (crtc)
1894                 drm_modeset_unlock(&crtc->mutex);
1895         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1896         mutex_unlock(&dev->mode_config.mutex);
1897
1898 done:
1899         kfree(wr_buf);
1900         return size;
1901 }
1902
1903 /* function: read DSC target rate on the connector in bits per pixel
1904  *
1905  * The read function: dp_dsc_bits_per_pixel_read
1906  * returns target rate of compression in bits per pixel
1907  * The return is an integer: 0 or other positive integer
1908  *
1909  * Access it with the following command:
1910  *
1911  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1912  *
1913  *  0 - means that DSC is disabled
1914  */
1915 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1916                                     size_t size, loff_t *pos)
1917 {
1918         char *rd_buf = NULL;
1919         char *rd_buf_ptr = NULL;
1920         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1921         struct display_stream_compressor *dsc;
1922         struct dcn_dsc_state dsc_state = {0};
1923         const uint32_t rd_buf_size = 100;
1924         struct pipe_ctx *pipe_ctx;
1925         ssize_t result = 0;
1926         int i, r, str_len = 30;
1927
1928         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1929
1930         if (!rd_buf)
1931                 return -ENOMEM;
1932
1933         rd_buf_ptr = rd_buf;
1934
1935         for (i = 0; i < MAX_PIPES; i++) {
1936                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1937                 if (pipe_ctx && pipe_ctx->stream &&
1938                     pipe_ctx->stream->link == aconnector->dc_link)
1939                         break;
1940         }
1941
1942         if (!pipe_ctx) {
1943                 kfree(rd_buf);
1944                 return -ENXIO;
1945         }
1946
1947         dsc = pipe_ctx->stream_res.dsc;
1948         if (dsc)
1949                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1950
1951         snprintf(rd_buf_ptr, str_len,
1952                 "%d\n",
1953                 dsc_state.dsc_bits_per_pixel);
1954         rd_buf_ptr += str_len;
1955
1956         while (size) {
1957                 if (*pos >= rd_buf_size)
1958                         break;
1959
1960                 r = put_user(*(rd_buf + result), buf);
1961                 if (r) {
1962                         kfree(rd_buf);
1963                         return r; /* r = -EFAULT */
1964                 }
1965
1966                 buf += 1;
1967                 size -= 1;
1968                 *pos += 1;
1969                 result += 1;
1970         }
1971
1972         kfree(rd_buf);
1973         return result;
1974 }
1975
1976 /* function: write DSC target rate in bits per pixel
1977  *
1978  * The write function: dp_dsc_bits_per_pixel_write
1979  * overwrites automatically generated DSC configuration
1980  * of DSC target bit rate.
1981  *
1982  * Also the user has to write bpp in hexidecimal
1983  * rather than in decimal.
1984  *
1985  * Writing DSC settings is done with the following command:
1986  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1987  *
1988  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1989  *
1990  *  - To stop overwriting and let driver find the optimal rate,
1991  * set the rate to zero:
1992  *
1993  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1994  *
1995  */
1996 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1997                                      size_t size, loff_t *pos)
1998 {
1999         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2000         struct drm_connector *connector = &aconnector->base;
2001         struct drm_device *dev = connector->dev;
2002         struct drm_crtc *crtc = NULL;
2003         struct dm_crtc_state *dm_crtc_state = NULL;
2004         struct pipe_ctx *pipe_ctx;
2005         int i;
2006         char *wr_buf = NULL;
2007         uint32_t wr_buf_size = 42;
2008         int max_param_num = 1;
2009         uint8_t param_nums = 0;
2010         long param[1] = {0};
2011
2012         if (size == 0)
2013                 return -EINVAL;
2014
2015         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2016
2017         if (!wr_buf) {
2018                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2019                 return -ENOSPC;
2020         }
2021
2022         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2023                                             (long *)param, buf,
2024                                             max_param_num,
2025                                             &param_nums)) {
2026                 kfree(wr_buf);
2027                 return -EINVAL;
2028         }
2029
2030         if (param_nums <= 0) {
2031                 DRM_DEBUG_DRIVER("user data not be read\n");
2032                 kfree(wr_buf);
2033                 return -EINVAL;
2034         }
2035
2036         for (i = 0; i < MAX_PIPES; i++) {
2037                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2038                 if (pipe_ctx && pipe_ctx->stream &&
2039                     pipe_ctx->stream->link == aconnector->dc_link)
2040                         break;
2041         }
2042
2043         if (!pipe_ctx || !pipe_ctx->stream)
2044                 goto done;
2045
2046         // Get CRTC state
2047         mutex_lock(&dev->mode_config.mutex);
2048         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2049
2050         if (connector->state == NULL)
2051                 goto unlock;
2052
2053         crtc = connector->state->crtc;
2054         if (crtc == NULL)
2055                 goto unlock;
2056
2057         drm_modeset_lock(&crtc->mutex, NULL);
2058         if (crtc->state == NULL)
2059                 goto unlock;
2060
2061         dm_crtc_state = to_dm_crtc_state(crtc->state);
2062         if (dm_crtc_state->stream == NULL)
2063                 goto unlock;
2064
2065         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2066
2067         dm_crtc_state->dsc_force_changed = true;
2068
2069 unlock:
2070         if (crtc)
2071                 drm_modeset_unlock(&crtc->mutex);
2072         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2073         mutex_unlock(&dev->mode_config.mutex);
2074
2075 done:
2076         kfree(wr_buf);
2077         return size;
2078 }
2079
2080 /* function: read DSC picture width parameter on the connector
2081  *
2082  * The read function: dp_dsc_pic_width_read
2083  * returns dsc picture width used in the current configuration
2084  * It is the same as h_addressable of the current
2085  * display's timing
2086  * The return is an integer: 0 or other positive integer
2087  * If 0 then DSC is disabled.
2088  *
2089  * Access it with the following command:
2090  *
2091  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2092  *
2093  * 0 - means that DSC is disabled
2094  */
2095 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2096                                     size_t size, loff_t *pos)
2097 {
2098         char *rd_buf = NULL;
2099         char *rd_buf_ptr = NULL;
2100         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2101         struct display_stream_compressor *dsc;
2102         struct dcn_dsc_state dsc_state = {0};
2103         const uint32_t rd_buf_size = 100;
2104         struct pipe_ctx *pipe_ctx;
2105         ssize_t result = 0;
2106         int i, r, str_len = 30;
2107
2108         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2109
2110         if (!rd_buf)
2111                 return -ENOMEM;
2112
2113         rd_buf_ptr = rd_buf;
2114
2115         for (i = 0; i < MAX_PIPES; i++) {
2116                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2117                 if (pipe_ctx && pipe_ctx->stream &&
2118                     pipe_ctx->stream->link == aconnector->dc_link)
2119                         break;
2120         }
2121
2122         if (!pipe_ctx) {
2123                 kfree(rd_buf);
2124                 return -ENXIO;
2125         }
2126
2127         dsc = pipe_ctx->stream_res.dsc;
2128         if (dsc)
2129                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2130
2131         snprintf(rd_buf_ptr, str_len,
2132                 "%d\n",
2133                 dsc_state.dsc_pic_width);
2134         rd_buf_ptr += str_len;
2135
2136         while (size) {
2137                 if (*pos >= rd_buf_size)
2138                         break;
2139
2140                 r = put_user(*(rd_buf + result), buf);
2141                 if (r) {
2142                         kfree(rd_buf);
2143                         return r; /* r = -EFAULT */
2144                 }
2145
2146                 buf += 1;
2147                 size -= 1;
2148                 *pos += 1;
2149                 result += 1;
2150         }
2151
2152         kfree(rd_buf);
2153         return result;
2154 }
2155
2156 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2157                                     size_t size, loff_t *pos)
2158 {
2159         char *rd_buf = NULL;
2160         char *rd_buf_ptr = NULL;
2161         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2162         struct display_stream_compressor *dsc;
2163         struct dcn_dsc_state dsc_state = {0};
2164         const uint32_t rd_buf_size = 100;
2165         struct pipe_ctx *pipe_ctx;
2166         ssize_t result = 0;
2167         int i, r, str_len = 30;
2168
2169         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2170
2171         if (!rd_buf)
2172                 return -ENOMEM;
2173
2174         rd_buf_ptr = rd_buf;
2175
2176         for (i = 0; i < MAX_PIPES; i++) {
2177                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2178                 if (pipe_ctx && pipe_ctx->stream &&
2179                     pipe_ctx->stream->link == aconnector->dc_link)
2180                         break;
2181         }
2182
2183         if (!pipe_ctx) {
2184                 kfree(rd_buf);
2185                 return -ENXIO;
2186         }
2187
2188         dsc = pipe_ctx->stream_res.dsc;
2189         if (dsc)
2190                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2191
2192         snprintf(rd_buf_ptr, str_len,
2193                 "%d\n",
2194                 dsc_state.dsc_pic_height);
2195         rd_buf_ptr += str_len;
2196
2197         while (size) {
2198                 if (*pos >= rd_buf_size)
2199                         break;
2200
2201                 r = put_user(*(rd_buf + result), buf);
2202                 if (r) {
2203                         kfree(rd_buf);
2204                         return r; /* r = -EFAULT */
2205                 }
2206
2207                 buf += 1;
2208                 size -= 1;
2209                 *pos += 1;
2210                 result += 1;
2211         }
2212
2213         kfree(rd_buf);
2214         return result;
2215 }
2216
2217 /* function: read DSC chunk size parameter on the connector
2218  *
2219  * The read function: dp_dsc_chunk_size_read
2220  * returns dsc chunk size set in the current configuration
2221  * The value is calculated automatically by DSC code
2222  * and depends on slice parameters and bpp target rate
2223  * The return is an integer: 0 or other positive integer
2224  * If 0 then DSC is disabled.
2225  *
2226  * Access it with the following command:
2227  *
2228  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2229  *
2230  * 0 - means that DSC is disabled
2231  */
2232 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2233                                     size_t size, loff_t *pos)
2234 {
2235         char *rd_buf = NULL;
2236         char *rd_buf_ptr = NULL;
2237         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2238         struct display_stream_compressor *dsc;
2239         struct dcn_dsc_state dsc_state = {0};
2240         const uint32_t rd_buf_size = 100;
2241         struct pipe_ctx *pipe_ctx;
2242         ssize_t result = 0;
2243         int i, r, str_len = 30;
2244
2245         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2246
2247         if (!rd_buf)
2248                 return -ENOMEM;
2249
2250         rd_buf_ptr = rd_buf;
2251
2252         for (i = 0; i < MAX_PIPES; i++) {
2253                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2254                 if (pipe_ctx && pipe_ctx->stream &&
2255                     pipe_ctx->stream->link == aconnector->dc_link)
2256                         break;
2257         }
2258
2259         if (!pipe_ctx) {
2260                 kfree(rd_buf);
2261                 return -ENXIO;
2262         }
2263
2264         dsc = pipe_ctx->stream_res.dsc;
2265         if (dsc)
2266                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2267
2268         snprintf(rd_buf_ptr, str_len,
2269                 "%d\n",
2270                 dsc_state.dsc_chunk_size);
2271         rd_buf_ptr += str_len;
2272
2273         while (size) {
2274                 if (*pos >= rd_buf_size)
2275                         break;
2276
2277                 r = put_user(*(rd_buf + result), buf);
2278                 if (r) {
2279                         kfree(rd_buf);
2280                         return r; /* r = -EFAULT */
2281                 }
2282
2283                 buf += 1;
2284                 size -= 1;
2285                 *pos += 1;
2286                 result += 1;
2287         }
2288
2289         kfree(rd_buf);
2290         return result;
2291 }
2292
2293 /* function: read DSC slice bpg offset on the connector
2294  *
2295  * The read function: dp_dsc_slice_bpg_offset_read
2296  * returns dsc bpg slice offset set in the current configuration
2297  * The value is calculated automatically by DSC code
2298  * and depends on slice parameters and bpp target rate
2299  * The return is an integer: 0 or other positive integer
2300  * If 0 then DSC is disabled.
2301  *
2302  * Access it with the following command:
2303  *
2304  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2305  *
2306  * 0 - means that DSC is disabled
2307  */
2308 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2309                                     size_t size, loff_t *pos)
2310 {
2311         char *rd_buf = NULL;
2312         char *rd_buf_ptr = NULL;
2313         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2314         struct display_stream_compressor *dsc;
2315         struct dcn_dsc_state dsc_state = {0};
2316         const uint32_t rd_buf_size = 100;
2317         struct pipe_ctx *pipe_ctx;
2318         ssize_t result = 0;
2319         int i, r, str_len = 30;
2320
2321         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2322
2323         if (!rd_buf)
2324                 return -ENOMEM;
2325
2326         rd_buf_ptr = rd_buf;
2327
2328         for (i = 0; i < MAX_PIPES; i++) {
2329                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2330                 if (pipe_ctx && pipe_ctx->stream &&
2331                     pipe_ctx->stream->link == aconnector->dc_link)
2332                         break;
2333         }
2334
2335         if (!pipe_ctx) {
2336                 kfree(rd_buf);
2337                 return -ENXIO;
2338         }
2339
2340         dsc = pipe_ctx->stream_res.dsc;
2341         if (dsc)
2342                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2343
2344         snprintf(rd_buf_ptr, str_len,
2345                 "%d\n",
2346                 dsc_state.dsc_slice_bpg_offset);
2347         rd_buf_ptr += str_len;
2348
2349         while (size) {
2350                 if (*pos >= rd_buf_size)
2351                         break;
2352
2353                 r = put_user(*(rd_buf + result), buf);
2354                 if (r) {
2355                         kfree(rd_buf);
2356                         return r; /* r = -EFAULT */
2357                 }
2358
2359                 buf += 1;
2360                 size -= 1;
2361                 *pos += 1;
2362                 result += 1;
2363         }
2364
2365         kfree(rd_buf);
2366         return result;
2367 }
2368
2369
2370 /*
2371  * function description: Read max_requested_bpc property from the connector
2372  *
2373  * Access it with the following command:
2374  *
2375  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2376  *
2377  */
2378 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2379                 size_t size, loff_t *pos)
2380 {
2381         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2382         struct drm_connector *connector = &aconnector->base;
2383         struct drm_device *dev = connector->dev;
2384         struct dm_connector_state *state;
2385         ssize_t result = 0;
2386         char *rd_buf = NULL;
2387         char *rd_buf_ptr = NULL;
2388         const uint32_t rd_buf_size = 10;
2389         int r;
2390
2391         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2392
2393         if (!rd_buf)
2394                 return -ENOMEM;
2395
2396         mutex_lock(&dev->mode_config.mutex);
2397         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2398
2399         if (connector->state == NULL)
2400                 goto unlock;
2401
2402         state = to_dm_connector_state(connector->state);
2403
2404         rd_buf_ptr = rd_buf;
2405         snprintf(rd_buf_ptr, rd_buf_size,
2406                 "%u\n",
2407                 state->base.max_requested_bpc);
2408
2409         while (size) {
2410                 if (*pos >= rd_buf_size)
2411                         break;
2412
2413                 r = put_user(*(rd_buf + result), buf);
2414                 if (r) {
2415                         result = r; /* r = -EFAULT */
2416                         goto unlock;
2417                 }
2418                 buf += 1;
2419                 size -= 1;
2420                 *pos += 1;
2421                 result += 1;
2422         }
2423 unlock:
2424         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2425         mutex_unlock(&dev->mode_config.mutex);
2426         kfree(rd_buf);
2427         return result;
2428 }
2429
2430
2431 /*
2432  * function description: Set max_requested_bpc property on the connector
2433  *
2434  * This function will not force the input BPC on connector, it will only
2435  * change the max value. This is equivalent to setting max_bpc through
2436  * xrandr.
2437  *
2438  * The BPC value written must be >= 6 and <= 16. Values outside of this
2439  * range will result in errors.
2440  *
2441  * BPC values:
2442  *      0x6 - 6 BPC
2443  *      0x8 - 8 BPC
2444  *      0xa - 10 BPC
2445  *      0xc - 12 BPC
2446  *      0x10 - 16 BPC
2447  *
2448  * Write the max_bpc in the following way:
2449  *
2450  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2451  *
2452  */
2453 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2454                                      size_t size, loff_t *pos)
2455 {
2456         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2457         struct drm_connector *connector = &aconnector->base;
2458         struct dm_connector_state *state;
2459         struct drm_device *dev = connector->dev;
2460         char *wr_buf = NULL;
2461         uint32_t wr_buf_size = 42;
2462         int max_param_num = 1;
2463         long param[1] = {0};
2464         uint8_t param_nums = 0;
2465
2466         if (size == 0)
2467                 return -EINVAL;
2468
2469         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2470
2471         if (!wr_buf) {
2472                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2473                 return -ENOSPC;
2474         }
2475
2476         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2477                                            (long *)param, buf,
2478                                            max_param_num,
2479                                            &param_nums)) {
2480                 kfree(wr_buf);
2481                 return -EINVAL;
2482         }
2483
2484         if (param_nums <= 0) {
2485                 DRM_DEBUG_DRIVER("user data not be read\n");
2486                 kfree(wr_buf);
2487                 return -EINVAL;
2488         }
2489
2490         if (param[0] < 6 || param[0] > 16) {
2491                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2492                 kfree(wr_buf);
2493                 return -EINVAL;
2494         }
2495
2496         mutex_lock(&dev->mode_config.mutex);
2497         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2498
2499         if (connector->state == NULL)
2500                 goto unlock;
2501
2502         state = to_dm_connector_state(connector->state);
2503         state->base.max_requested_bpc = param[0];
2504 unlock:
2505         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2506         mutex_unlock(&dev->mode_config.mutex);
2507
2508         kfree(wr_buf);
2509         return size;
2510 }
2511
2512 /*
2513  * Backlight at this moment.  Read only.
2514  * As written to display, taking ABM and backlight lut into account.
2515  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2516  *
2517  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2518  */
2519 static int current_backlight_show(struct seq_file *m, void *unused)
2520 {
2521         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2522         struct dc_link *link = aconnector->dc_link;
2523         unsigned int backlight;
2524
2525         backlight = dc_link_get_backlight_level(link);
2526         seq_printf(m, "0x%x\n", backlight);
2527
2528         return 0;
2529 }
2530
2531 /*
2532  * Backlight value that is being approached.  Read only.
2533  * As written to display, taking ABM and backlight lut into account.
2534  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2535  *
2536  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2537  */
2538 static int target_backlight_show(struct seq_file *m, void *unused)
2539 {
2540         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2541         struct dc_link *link = aconnector->dc_link;
2542         unsigned int backlight;
2543
2544         backlight = dc_link_get_target_backlight_pwm(link);
2545         seq_printf(m, "0x%x\n", backlight);
2546
2547         return 0;
2548 }
2549
2550 /*
2551  * function description: Determine if the connector is mst connector
2552  *
2553  * This function helps to determine whether a connector is a mst connector.
2554  * - "root" stands for the root connector of the topology
2555  * - "branch" stands for branch device of the topology
2556  * - "end" stands for leaf node connector of the topology
2557  * - "no" stands for the connector is not a device of a mst topology
2558  * Access it with the following command:
2559  *
2560  *      cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2561  *
2562  */
2563 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2564 {
2565         struct drm_connector *connector = m->private;
2566         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2567         struct drm_dp_mst_topology_mgr *mgr = NULL;
2568         struct drm_dp_mst_port *port = NULL;
2569         char *role = NULL;
2570
2571         mutex_lock(&aconnector->hpd_lock);
2572
2573         if (aconnector->mst_mgr.mst_state) {
2574                 role = "root";
2575         } else if (aconnector->mst_port &&
2576                 aconnector->mst_port->mst_mgr.mst_state) {
2577
2578                 role = "end";
2579
2580                 mgr = &aconnector->mst_port->mst_mgr;
2581                 port = aconnector->port;
2582
2583                 drm_modeset_lock(&mgr->base.lock, NULL);
2584                 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2585                         port->mcs)
2586                         role = "branch";
2587                 drm_modeset_unlock(&mgr->base.lock);
2588
2589         } else {
2590                 role = "no";
2591         }
2592
2593         seq_printf(m, "%s\n", role);
2594
2595         mutex_unlock(&aconnector->hpd_lock);
2596
2597         return 0;
2598 }
2599
2600 /*
2601  * function description: Read out the mst progress status
2602  *
2603  * This function helps to determine the mst progress status of
2604  * a mst connector.
2605  *
2606  * Access it with the following command:
2607  *
2608  *      cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2609  *
2610  */
2611 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2612 {
2613         struct drm_connector *connector = m->private;
2614         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2615         struct amdgpu_device *adev = drm_to_adev(connector->dev);
2616         int i;
2617
2618         mutex_lock(&aconnector->hpd_lock);
2619         mutex_lock(&adev->dm.dc_lock);
2620
2621         if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2622                 seq_puts(m, "disabled\n");
2623         } else {
2624                 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2625                         seq_printf(m, "%s:%s\n",
2626                                 mst_progress_status[i],
2627                                 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2628         }
2629
2630         mutex_unlock(&adev->dm.dc_lock);
2631         mutex_unlock(&aconnector->hpd_lock);
2632
2633         return 0;
2634 }
2635
2636 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2637 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2638 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2639 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2640 #ifdef CONFIG_DRM_AMD_DC_HDCP
2641 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2642 #endif
2643 DEFINE_SHOW_ATTRIBUTE(internal_display);
2644 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2645 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2646 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2647
2648 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2649         .owner = THIS_MODULE,
2650         .read = dp_dsc_clock_en_read,
2651         .write = dp_dsc_clock_en_write,
2652         .llseek = default_llseek
2653 };
2654
2655 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2656         .owner = THIS_MODULE,
2657         .read = dp_dsc_slice_width_read,
2658         .write = dp_dsc_slice_width_write,
2659         .llseek = default_llseek
2660 };
2661
2662 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2663         .owner = THIS_MODULE,
2664         .read = dp_dsc_slice_height_read,
2665         .write = dp_dsc_slice_height_write,
2666         .llseek = default_llseek
2667 };
2668
2669 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2670         .owner = THIS_MODULE,
2671         .read = dp_dsc_bits_per_pixel_read,
2672         .write = dp_dsc_bits_per_pixel_write,
2673         .llseek = default_llseek
2674 };
2675
2676 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2677         .owner = THIS_MODULE,
2678         .read = dp_dsc_pic_width_read,
2679         .llseek = default_llseek
2680 };
2681
2682 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2683         .owner = THIS_MODULE,
2684         .read = dp_dsc_pic_height_read,
2685         .llseek = default_llseek
2686 };
2687
2688 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2689         .owner = THIS_MODULE,
2690         .read = dp_dsc_chunk_size_read,
2691         .llseek = default_llseek
2692 };
2693
2694 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2695         .owner = THIS_MODULE,
2696         .read = dp_dsc_slice_bpg_offset_read,
2697         .llseek = default_llseek
2698 };
2699
2700 static const struct file_operations trigger_hotplug_debugfs_fops = {
2701         .owner = THIS_MODULE,
2702         .write = trigger_hotplug,
2703         .llseek = default_llseek
2704 };
2705
2706 static const struct file_operations dp_link_settings_debugfs_fops = {
2707         .owner = THIS_MODULE,
2708         .read = dp_link_settings_read,
2709         .write = dp_link_settings_write,
2710         .llseek = default_llseek
2711 };
2712
2713 static const struct file_operations dp_phy_settings_debugfs_fop = {
2714         .owner = THIS_MODULE,
2715         .read = dp_phy_settings_read,
2716         .write = dp_phy_settings_write,
2717         .llseek = default_llseek
2718 };
2719
2720 static const struct file_operations dp_phy_test_pattern_fops = {
2721         .owner = THIS_MODULE,
2722         .write = dp_phy_test_pattern_debugfs_write,
2723         .llseek = default_llseek
2724 };
2725
2726 static const struct file_operations sdp_message_fops = {
2727         .owner = THIS_MODULE,
2728         .write = dp_sdp_message_debugfs_write,
2729         .llseek = default_llseek
2730 };
2731
2732 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2733         .owner = THIS_MODULE,
2734         .write = dp_dpcd_address_write,
2735         .llseek = default_llseek
2736 };
2737
2738 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2739         .owner = THIS_MODULE,
2740         .write = dp_dpcd_size_write,
2741         .llseek = default_llseek
2742 };
2743
2744 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2745         .owner = THIS_MODULE,
2746         .read = dp_dpcd_data_read,
2747         .write = dp_dpcd_data_write,
2748         .llseek = default_llseek
2749 };
2750
2751 static const struct file_operations dp_max_bpc_debugfs_fops = {
2752         .owner = THIS_MODULE,
2753         .read = dp_max_bpc_read,
2754         .write = dp_max_bpc_write,
2755         .llseek = default_llseek
2756 };
2757
2758 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2759         .owner = THIS_MODULE,
2760         .write = dp_dsc_passthrough_set,
2761         .llseek = default_llseek
2762 };
2763
2764 static const struct {
2765         char *name;
2766         const struct file_operations *fops;
2767 } dp_debugfs_entries[] = {
2768                 {"link_settings", &dp_link_settings_debugfs_fops},
2769                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2770                 {"lttpr_status", &dp_lttpr_status_fops},
2771                 {"test_pattern", &dp_phy_test_pattern_fops},
2772 #ifdef CONFIG_DRM_AMD_DC_HDCP
2773                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2774 #endif
2775                 {"sdp_message", &sdp_message_fops},
2776                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2777                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2778                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2779                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2780                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2781                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2782                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2783                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2784                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2785                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2786                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2787                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2788                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2789                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2790                 {"is_mst_connector", &dp_is_mst_connector_fops},
2791                 {"mst_progress_status", &dp_mst_progress_status_fops}
2792 };
2793
2794 #ifdef CONFIG_DRM_AMD_DC_HDCP
2795 static const struct {
2796         char *name;
2797         const struct file_operations *fops;
2798 } hdmi_debugfs_entries[] = {
2799                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2800 };
2801 #endif
2802 /*
2803  * Force YUV420 output if available from the given mode
2804  */
2805 static int force_yuv420_output_set(void *data, u64 val)
2806 {
2807         struct amdgpu_dm_connector *connector = data;
2808
2809         connector->force_yuv420_output = (bool)val;
2810
2811         return 0;
2812 }
2813
2814 /*
2815  * Check if YUV420 is forced when available from the given mode
2816  */
2817 static int force_yuv420_output_get(void *data, u64 *val)
2818 {
2819         struct amdgpu_dm_connector *connector = data;
2820
2821         *val = connector->force_yuv420_output;
2822
2823         return 0;
2824 }
2825
2826 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2827                          force_yuv420_output_set, "%llu\n");
2828
2829 /*
2830  *  Read PSR state
2831  */
2832 static int psr_get(void *data, u64 *val)
2833 {
2834         struct amdgpu_dm_connector *connector = data;
2835         struct dc_link *link = connector->dc_link;
2836         enum dc_psr_state state = PSR_STATE0;
2837
2838         dc_link_get_psr_state(link, &state);
2839
2840         *val = state;
2841
2842         return 0;
2843 }
2844
2845 /*
2846  * Set dmcub trace event IRQ enable or disable.
2847  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2848  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2849  */
2850 static int dmcub_trace_event_state_set(void *data, u64 val)
2851 {
2852         struct amdgpu_device *adev = data;
2853
2854         if (val == 1 || val == 0) {
2855                 dc_dmub_trace_event_control(adev->dm.dc, val);
2856                 adev->dm.dmcub_trace_event_en = (bool)val;
2857         } else
2858                 return 0;
2859
2860         return 0;
2861 }
2862
2863 /*
2864  * The interface doesn't need get function, so it will return the
2865  * value of zero
2866  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2867  */
2868 static int dmcub_trace_event_state_get(void *data, u64 *val)
2869 {
2870         struct amdgpu_device *adev = data;
2871
2872         *val = adev->dm.dmcub_trace_event_en;
2873         return 0;
2874 }
2875
2876 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2877                          dmcub_trace_event_state_set, "%llu\n");
2878
2879 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2880
2881 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2882 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2883
2884 static const struct {
2885         char *name;
2886         const struct file_operations *fops;
2887 } connector_debugfs_entries[] = {
2888                 {"force_yuv420_output", &force_yuv420_output_fops},
2889                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2890                 {"internal_display", &internal_display_fops}
2891 };
2892
2893 /*
2894  * Returns supported customized link rates by this eDP panel.
2895  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2896  */
2897 static int edp_ilr_show(struct seq_file *m, void *unused)
2898 {
2899         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2900         struct dc_link *link = aconnector->dc_link;
2901         uint8_t supported_link_rates[16];
2902         uint32_t link_rate_in_khz;
2903         uint32_t entry = 0;
2904         uint8_t dpcd_rev;
2905
2906         memset(supported_link_rates, 0, sizeof(supported_link_rates));
2907         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
2908                 supported_link_rates, sizeof(supported_link_rates));
2909
2910         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
2911
2912         if (dpcd_rev >= DP_DPCD_REV_13 &&
2913                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
2914
2915                 for (entry = 0; entry < 16; entry += 2) {
2916                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2917                                                                                 supported_link_rates[entry]) * 200;
2918                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
2919                 }
2920         } else {
2921                 seq_printf(m, "ILR is not supported by this eDP panel.\n");
2922         }
2923
2924         return 0;
2925 }
2926
2927 /*
2928  * Set supported customized link rate to eDP panel.
2929  *
2930  * echo <lane_count>  <link_rate option> > ilr_setting
2931  *
2932  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
2933  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2934  * to set 4 lanes and 2.16 GHz
2935  */
2936 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
2937                                  size_t size, loff_t *pos)
2938 {
2939         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
2940         struct dc_link *link = connector->dc_link;
2941         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
2942         struct dc *dc = (struct dc *)link->dc;
2943         struct dc_link_settings prefer_link_settings;
2944         char *wr_buf = NULL;
2945         const uint32_t wr_buf_size = 40;
2946         /* 0: lane_count; 1: link_rate */
2947         int max_param_num = 2;
2948         uint8_t param_nums = 0;
2949         long param[2];
2950         bool valid_input = true;
2951
2952         if (size == 0)
2953                 return -EINVAL;
2954
2955         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2956         if (!wr_buf)
2957                 return -ENOMEM;
2958
2959         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2960                                            (long *)param, buf,
2961                                            max_param_num,
2962                                            &param_nums)) {
2963                 kfree(wr_buf);
2964                 return -EINVAL;
2965         }
2966
2967         if (param_nums <= 0) {
2968                 kfree(wr_buf);
2969                 return -EINVAL;
2970         }
2971
2972         switch (param[0]) {
2973         case LANE_COUNT_ONE:
2974         case LANE_COUNT_TWO:
2975         case LANE_COUNT_FOUR:
2976                 break;
2977         default:
2978                 valid_input = false;
2979                 break;
2980         }
2981
2982         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
2983                 valid_input = false;
2984
2985         if (!valid_input) {
2986                 kfree(wr_buf);
2987                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
2988                 prefer_link_settings.use_link_rate_set = false;
2989                 mutex_lock(&adev->dm.dc_lock);
2990                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
2991                 mutex_unlock(&adev->dm.dc_lock);
2992                 return size;
2993         }
2994
2995         /* save user force lane_count, link_rate to preferred settings
2996          * spread spectrum will not be changed
2997          */
2998         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
2999         prefer_link_settings.lane_count = param[0];
3000         prefer_link_settings.use_link_rate_set = true;
3001         prefer_link_settings.link_rate_set = param[1];
3002         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
3003
3004         mutex_lock(&adev->dm.dc_lock);
3005         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3006                                                 NULL, link, false);
3007         mutex_unlock(&adev->dm.dc_lock);
3008
3009         kfree(wr_buf);
3010         return size;
3011 }
3012
3013 static int edp_ilr_open(struct inode *inode, struct file *file)
3014 {
3015         return single_open(file, edp_ilr_show, inode->i_private);
3016 }
3017
3018 static const struct file_operations edp_ilr_debugfs_fops = {
3019         .owner = THIS_MODULE,
3020         .open = edp_ilr_open,
3021         .read = seq_read,
3022         .llseek = seq_lseek,
3023         .release = single_release,
3024         .write = edp_ilr_write
3025 };
3026
3027 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3028 {
3029         int i;
3030         struct dentry *dir = connector->base.debugfs_entry;
3031
3032         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3033             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3034                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3035                         debugfs_create_file(dp_debugfs_entries[i].name,
3036                                             0644, dir, connector,
3037                                             dp_debugfs_entries[i].fops);
3038                 }
3039         }
3040         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3041                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3042                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3043                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3044                                     &current_backlight_fops);
3045                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3046                                     &target_backlight_fops);
3047                 debugfs_create_file("ilr_setting", 0644, dir, connector,
3048                                         &edp_ilr_debugfs_fops);
3049         }
3050
3051         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3052                 debugfs_create_file(connector_debugfs_entries[i].name,
3053                                     0644, dir, connector,
3054                                     connector_debugfs_entries[i].fops);
3055         }
3056
3057         connector->debugfs_dpcd_address = 0;
3058         connector->debugfs_dpcd_size = 0;
3059
3060 #ifdef CONFIG_DRM_AMD_DC_HDCP
3061         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3062                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3063                         debugfs_create_file(hdmi_debugfs_entries[i].name,
3064                                             0644, dir, connector,
3065                                             hdmi_debugfs_entries[i].fops);
3066                 }
3067         }
3068 #endif
3069 }
3070
3071 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3072 /*
3073  * Set crc window coordinate x start
3074  */
3075 static int crc_win_x_start_set(void *data, u64 val)
3076 {
3077         struct drm_crtc *crtc = data;
3078         struct drm_device *drm_dev = crtc->dev;
3079         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3080
3081         spin_lock_irq(&drm_dev->event_lock);
3082         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
3083         acrtc->dm_irq_params.crc_window.update_win = false;
3084         spin_unlock_irq(&drm_dev->event_lock);
3085
3086         return 0;
3087 }
3088
3089 /*
3090  * Get crc window coordinate x start
3091  */
3092 static int crc_win_x_start_get(void *data, u64 *val)
3093 {
3094         struct drm_crtc *crtc = data;
3095         struct drm_device *drm_dev = crtc->dev;
3096         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3097
3098         spin_lock_irq(&drm_dev->event_lock);
3099         *val = acrtc->dm_irq_params.crc_window.x_start;
3100         spin_unlock_irq(&drm_dev->event_lock);
3101
3102         return 0;
3103 }
3104
3105 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3106                          crc_win_x_start_set, "%llu\n");
3107
3108
3109 /*
3110  * Set crc window coordinate y start
3111  */
3112 static int crc_win_y_start_set(void *data, u64 val)
3113 {
3114         struct drm_crtc *crtc = data;
3115         struct drm_device *drm_dev = crtc->dev;
3116         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3117
3118         spin_lock_irq(&drm_dev->event_lock);
3119         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
3120         acrtc->dm_irq_params.crc_window.update_win = false;
3121         spin_unlock_irq(&drm_dev->event_lock);
3122
3123         return 0;
3124 }
3125
3126 /*
3127  * Get crc window coordinate y start
3128  */
3129 static int crc_win_y_start_get(void *data, u64 *val)
3130 {
3131         struct drm_crtc *crtc = data;
3132         struct drm_device *drm_dev = crtc->dev;
3133         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3134
3135         spin_lock_irq(&drm_dev->event_lock);
3136         *val = acrtc->dm_irq_params.crc_window.y_start;
3137         spin_unlock_irq(&drm_dev->event_lock);
3138
3139         return 0;
3140 }
3141
3142 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3143                          crc_win_y_start_set, "%llu\n");
3144
3145 /*
3146  * Set crc window coordinate x end
3147  */
3148 static int crc_win_x_end_set(void *data, u64 val)
3149 {
3150         struct drm_crtc *crtc = data;
3151         struct drm_device *drm_dev = crtc->dev;
3152         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3153
3154         spin_lock_irq(&drm_dev->event_lock);
3155         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
3156         acrtc->dm_irq_params.crc_window.update_win = false;
3157         spin_unlock_irq(&drm_dev->event_lock);
3158
3159         return 0;
3160 }
3161
3162 /*
3163  * Get crc window coordinate x end
3164  */
3165 static int crc_win_x_end_get(void *data, u64 *val)
3166 {
3167         struct drm_crtc *crtc = data;
3168         struct drm_device *drm_dev = crtc->dev;
3169         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3170
3171         spin_lock_irq(&drm_dev->event_lock);
3172         *val = acrtc->dm_irq_params.crc_window.x_end;
3173         spin_unlock_irq(&drm_dev->event_lock);
3174
3175         return 0;
3176 }
3177
3178 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3179                          crc_win_x_end_set, "%llu\n");
3180
3181 /*
3182  * Set crc window coordinate y end
3183  */
3184 static int crc_win_y_end_set(void *data, u64 val)
3185 {
3186         struct drm_crtc *crtc = data;
3187         struct drm_device *drm_dev = crtc->dev;
3188         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3189
3190         spin_lock_irq(&drm_dev->event_lock);
3191         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
3192         acrtc->dm_irq_params.crc_window.update_win = false;
3193         spin_unlock_irq(&drm_dev->event_lock);
3194
3195         return 0;
3196 }
3197
3198 /*
3199  * Get crc window coordinate y end
3200  */
3201 static int crc_win_y_end_get(void *data, u64 *val)
3202 {
3203         struct drm_crtc *crtc = data;
3204         struct drm_device *drm_dev = crtc->dev;
3205         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3206
3207         spin_lock_irq(&drm_dev->event_lock);
3208         *val = acrtc->dm_irq_params.crc_window.y_end;
3209         spin_unlock_irq(&drm_dev->event_lock);
3210
3211         return 0;
3212 }
3213
3214 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3215                          crc_win_y_end_set, "%llu\n");
3216 /*
3217  * Trigger to commit crc window
3218  */
3219 static int crc_win_update_set(void *data, u64 val)
3220 {
3221         struct drm_crtc *new_crtc = data;
3222         struct drm_crtc *old_crtc = NULL;
3223         struct amdgpu_crtc *new_acrtc, *old_acrtc;
3224         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
3225         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
3226
3227         if (!crc_rd_wrk)
3228                 return 0;
3229
3230         if (val) {
3231                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3232                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
3233                 if (crc_rd_wrk->crtc) {
3234                         old_crtc = crc_rd_wrk->crtc;
3235                         old_acrtc = to_amdgpu_crtc(old_crtc);
3236                 }
3237                 new_acrtc = to_amdgpu_crtc(new_crtc);
3238
3239                 if (old_crtc && old_crtc != new_crtc) {
3240                         old_acrtc->dm_irq_params.crc_window.activated = false;
3241                         old_acrtc->dm_irq_params.crc_window.update_win = false;
3242                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3243
3244                         new_acrtc->dm_irq_params.crc_window.activated = true;
3245                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3246                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3247                         crc_rd_wrk->crtc = new_crtc;
3248                 } else {
3249                         new_acrtc->dm_irq_params.crc_window.activated = true;
3250                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3251                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3252                         crc_rd_wrk->crtc = new_crtc;
3253                 }
3254                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
3255                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3256         }
3257
3258         return 0;
3259 }
3260
3261 /*
3262  * Get crc window update flag
3263  */
3264 static int crc_win_update_get(void *data, u64 *val)
3265 {
3266         *val = 0;
3267         return 0;
3268 }
3269
3270 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3271                          crc_win_update_set, "%llu\n");
3272 #endif
3273 void crtc_debugfs_init(struct drm_crtc *crtc)
3274 {
3275 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3276         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3277
3278         if (!dir)
3279                 return;
3280
3281         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3282                                    &crc_win_x_start_fops);
3283         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3284                                    &crc_win_y_start_fops);
3285         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3286                                    &crc_win_x_end_fops);
3287         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3288                                    &crc_win_y_end_fops);
3289         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3290                                    &crc_win_update_fops);
3291 #endif
3292         debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3293                             crtc, &amdgpu_current_bpc_fops);
3294 }
3295
3296 /*
3297  * Writes DTN log state to the user supplied buffer.
3298  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3299  */
3300 static ssize_t dtn_log_read(
3301         struct file *f,
3302         char __user *buf,
3303         size_t size,
3304         loff_t *pos)
3305 {
3306         struct amdgpu_device *adev = file_inode(f)->i_private;
3307         struct dc *dc = adev->dm.dc;
3308         struct dc_log_buffer_ctx log_ctx = { 0 };
3309         ssize_t result = 0;
3310
3311         if (!buf || !size)
3312                 return -EINVAL;
3313
3314         if (!dc->hwss.log_hw_state)
3315                 return 0;
3316
3317         dc->hwss.log_hw_state(dc, &log_ctx);
3318
3319         if (*pos < log_ctx.pos) {
3320                 size_t to_copy = log_ctx.pos - *pos;
3321
3322                 to_copy = min(to_copy, size);
3323
3324                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3325                         *pos += to_copy;
3326                         result = to_copy;
3327                 }
3328         }
3329
3330         kfree(log_ctx.buf);
3331
3332         return result;
3333 }
3334
3335 /*
3336  * Writes DTN log state to dmesg when triggered via a write.
3337  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3338  */
3339 static ssize_t dtn_log_write(
3340         struct file *f,
3341         const char __user *buf,
3342         size_t size,
3343         loff_t *pos)
3344 {
3345         struct amdgpu_device *adev = file_inode(f)->i_private;
3346         struct dc *dc = adev->dm.dc;
3347
3348         /* Write triggers log output via dmesg. */
3349         if (size == 0)
3350                 return 0;
3351
3352         if (dc->hwss.log_hw_state)
3353                 dc->hwss.log_hw_state(dc, NULL);
3354
3355         return size;
3356 }
3357
3358 static int mst_topo_show(struct seq_file *m, void *unused)
3359 {
3360         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3361         struct drm_device *dev = adev_to_drm(adev);
3362         struct drm_connector *connector;
3363         struct drm_connector_list_iter conn_iter;
3364         struct amdgpu_dm_connector *aconnector;
3365
3366         drm_connector_list_iter_begin(dev, &conn_iter);
3367         drm_for_each_connector_iter(connector, &conn_iter) {
3368                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3369                         continue;
3370
3371                 aconnector = to_amdgpu_dm_connector(connector);
3372
3373                 /* Ensure we're only dumping the topology of a root mst node */
3374                 if (!aconnector->mst_mgr.mst_state)
3375                         continue;
3376
3377                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3378                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3379         }
3380         drm_connector_list_iter_end(&conn_iter);
3381
3382         return 0;
3383 }
3384
3385 /*
3386  * Sets trigger hpd for MST topologies.
3387  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3388  * All topologies will be disconnected if val of 0 is set .
3389  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3390  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3391  */
3392 static int trigger_hpd_mst_set(void *data, u64 val)
3393 {
3394         struct amdgpu_device *adev = data;
3395         struct drm_device *dev = adev_to_drm(adev);
3396         struct drm_connector_list_iter iter;
3397         struct amdgpu_dm_connector *aconnector;
3398         struct drm_connector *connector;
3399         struct dc_link *link = NULL;
3400
3401         if (val == 1) {
3402                 drm_connector_list_iter_begin(dev, &iter);
3403                 drm_for_each_connector_iter(connector, &iter) {
3404                         aconnector = to_amdgpu_dm_connector(connector);
3405                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3406                             aconnector->mst_mgr.aux) {
3407                                 mutex_lock(&adev->dm.dc_lock);
3408                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3409                                 mutex_unlock(&adev->dm.dc_lock);
3410
3411                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3412                         }
3413                 }
3414         } else if (val == 0) {
3415                 drm_connector_list_iter_begin(dev, &iter);
3416                 drm_for_each_connector_iter(connector, &iter) {
3417                         aconnector = to_amdgpu_dm_connector(connector);
3418                         if (!aconnector->dc_link)
3419                                 continue;
3420
3421                         if (!aconnector->mst_port)
3422                                 continue;
3423
3424                         link = aconnector->dc_link;
3425                         dp_receiver_power_ctrl(link, false);
3426                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false);
3427                         link->mst_stream_alloc_table.stream_count = 0;
3428                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3429                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3430                 }
3431         } else {
3432                 return 0;
3433         }
3434         drm_kms_helper_hotplug_event(dev);
3435
3436         return 0;
3437 }
3438
3439 /*
3440  * The interface doesn't need get function, so it will return the
3441  * value of zero
3442  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3443  */
3444 static int trigger_hpd_mst_get(void *data, u64 *val)
3445 {
3446         *val = 0;
3447         return 0;
3448 }
3449
3450 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3451                          trigger_hpd_mst_set, "%llu\n");
3452
3453
3454 /*
3455  * Sets the force_timing_sync debug option from the given string.
3456  * All connected displays will be force synchronized immediately.
3457  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3458  */
3459 static int force_timing_sync_set(void *data, u64 val)
3460 {
3461         struct amdgpu_device *adev = data;
3462
3463         adev->dm.force_timing_sync = (bool)val;
3464
3465         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3466
3467         return 0;
3468 }
3469
3470 /*
3471  * Gets the force_timing_sync debug option value into the given buffer.
3472  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3473  */
3474 static int force_timing_sync_get(void *data, u64 *val)
3475 {
3476         struct amdgpu_device *adev = data;
3477
3478         *val = adev->dm.force_timing_sync;
3479
3480         return 0;
3481 }
3482
3483 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3484                          force_timing_sync_set, "%llu\n");
3485
3486
3487 /*
3488  * Disables all HPD and HPD RX interrupt handling in the
3489  * driver when set to 1. Default is 0.
3490  */
3491 static int disable_hpd_set(void *data, u64 val)
3492 {
3493         struct amdgpu_device *adev = data;
3494
3495         adev->dm.disable_hpd_irq = (bool)val;
3496
3497         return 0;
3498 }
3499
3500
3501 /*
3502  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3503  * 0 otherwise.
3504  */
3505 static int disable_hpd_get(void *data, u64 *val)
3506 {
3507         struct amdgpu_device *adev = data;
3508
3509         *val = adev->dm.disable_hpd_irq;
3510
3511         return 0;
3512 }
3513
3514 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3515                          disable_hpd_set, "%llu\n");
3516
3517 /*
3518  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3519  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3520  */
3521 static int dp_force_sst_set(void *data, u64 val)
3522 {
3523         struct amdgpu_device *adev = data;
3524
3525         adev->dm.dc->debug.set_mst_en_for_sst = val;
3526
3527         return 0;
3528 }
3529
3530 static int dp_force_sst_get(void *data, u64 *val)
3531 {
3532         struct amdgpu_device *adev = data;
3533
3534         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3535
3536         return 0;
3537 }
3538 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3539                          dp_force_sst_set, "%llu\n");
3540
3541 /*
3542  * Force DP2 sequence without VESA certified cable.
3543  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3544  */
3545 static int dp_ignore_cable_id_set(void *data, u64 val)
3546 {
3547         struct amdgpu_device *adev = data;
3548
3549         adev->dm.dc->debug.ignore_cable_id = val;
3550
3551         return 0;
3552 }
3553
3554 static int dp_ignore_cable_id_get(void *data, u64 *val)
3555 {
3556         struct amdgpu_device *adev = data;
3557
3558         *val = adev->dm.dc->debug.ignore_cable_id;
3559
3560         return 0;
3561 }
3562 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3563                          dp_ignore_cable_id_set, "%llu\n");
3564
3565 /*
3566  * Sets the DC visual confirm debug option from the given string.
3567  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3568  */
3569 static int visual_confirm_set(void *data, u64 val)
3570 {
3571         struct amdgpu_device *adev = data;
3572
3573         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3574
3575         return 0;
3576 }
3577
3578 /*
3579  * Reads the DC visual confirm debug option value into the given buffer.
3580  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3581  */
3582 static int visual_confirm_get(void *data, u64 *val)
3583 {
3584         struct amdgpu_device *adev = data;
3585
3586         *val = adev->dm.dc->debug.visual_confirm;
3587
3588         return 0;
3589 }
3590
3591 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3592 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3593                          visual_confirm_set, "%llu\n");
3594
3595
3596 /*
3597  * Sets the DC skip_detection_link_training debug option from the given string.
3598  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
3599  */
3600 static int skip_detection_link_training_set(void *data, u64 val)
3601 {
3602         struct amdgpu_device *adev = data;
3603
3604         if (val == 0)
3605                 adev->dm.dc->debug.skip_detection_link_training = false;
3606         else
3607                 adev->dm.dc->debug.skip_detection_link_training = true;
3608
3609         return 0;
3610 }
3611
3612 /*
3613  * Reads the DC skip_detection_link_training debug option value into the given buffer.
3614  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
3615  */
3616 static int skip_detection_link_training_get(void *data, u64 *val)
3617 {
3618         struct amdgpu_device *adev = data;
3619
3620         *val = adev->dm.dc->debug.skip_detection_link_training;
3621
3622         return 0;
3623 }
3624
3625 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
3626                          skip_detection_link_training_get,
3627                          skip_detection_link_training_set, "%llu\n");
3628
3629 /*
3630  * Dumps the DCC_EN bit for each pipe.
3631  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3632  */
3633 static ssize_t dcc_en_bits_read(
3634         struct file *f,
3635         char __user *buf,
3636         size_t size,
3637         loff_t *pos)
3638 {
3639         struct amdgpu_device *adev = file_inode(f)->i_private;
3640         struct dc *dc = adev->dm.dc;
3641         char *rd_buf = NULL;
3642         const uint32_t rd_buf_size = 32;
3643         uint32_t result = 0;
3644         int offset = 0;
3645         int num_pipes = dc->res_pool->pipe_count;
3646         int *dcc_en_bits;
3647         int i, r;
3648
3649         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3650         if (!dcc_en_bits)
3651                 return -ENOMEM;
3652
3653         if (!dc->hwss.get_dcc_en_bits) {
3654                 kfree(dcc_en_bits);
3655                 return 0;
3656         }
3657
3658         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3659
3660         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3661         if (!rd_buf) {
3662                 kfree(dcc_en_bits);
3663                 return -ENOMEM;
3664         }
3665
3666         for (i = 0; i < num_pipes; i++)
3667                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3668                                    "%d  ", dcc_en_bits[i]);
3669         rd_buf[strlen(rd_buf)] = '\n';
3670
3671         kfree(dcc_en_bits);
3672
3673         while (size) {
3674                 if (*pos >= rd_buf_size)
3675                         break;
3676                 r = put_user(*(rd_buf + result), buf);
3677                 if (r) {
3678                         kfree(rd_buf);
3679                         return r; /* r = -EFAULT */
3680                 }
3681                 buf += 1;
3682                 size -= 1;
3683                 *pos += 1;
3684                 result += 1;
3685         }
3686
3687         kfree(rd_buf);
3688         return result;
3689 }
3690
3691 void dtn_debugfs_init(struct amdgpu_device *adev)
3692 {
3693         static const struct file_operations dtn_log_fops = {
3694                 .owner = THIS_MODULE,
3695                 .read = dtn_log_read,
3696                 .write = dtn_log_write,
3697                 .llseek = default_llseek
3698         };
3699         static const struct file_operations dcc_en_bits_fops = {
3700                 .owner = THIS_MODULE,
3701                 .read = dcc_en_bits_read,
3702                 .llseek = default_llseek
3703         };
3704
3705         struct drm_minor *minor = adev_to_drm(adev)->primary;
3706         struct dentry *root = minor->debugfs_root;
3707
3708         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3709                             adev, &mst_topo_fops);
3710         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3711                             &dtn_log_fops);
3712         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
3713                                 &dp_set_mst_en_for_sst_ops);
3714         debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
3715                                 &dp_ignore_cable_id_ops);
3716
3717         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3718                                    &visual_confirm_fops);
3719
3720         debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
3721                                    &skip_detection_link_training_fops);
3722
3723         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3724                                    adev, &dmub_tracebuffer_fops);
3725
3726         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3727                                    adev, &dmub_fw_state_fops);
3728
3729         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3730                                    adev, &force_timing_sync_ops);
3731
3732         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3733                                    adev, &dmcub_trace_event_state_fops);
3734
3735         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3736                                    adev, &trigger_hpd_mst_ops);
3737
3738         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3739                                    &dcc_en_bits_fops);
3740
3741         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3742                                    &disable_hpd_ops);
3743
3744 }