drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_7.h"
  26
  27 #include "nbio/nbio_7_7_0_offset.h"
  28 #include "nbio/nbio_7_7_0_sh_mask.h"
  29 #include <uapi/linux/kfd_ioctl.h>
  30
  31 static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
  32 {
  33         u32 tmp;
  34
  35         tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
  36         tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  37         tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  38
  39         return tmp;
  40 }
  41
  42 static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)
  43 {
  44         if (enable)
  45                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
  46                         BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
  47                         BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
  48         else
  49                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
  50 }
  51
  52 static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev)
  53 {
  54         return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
  55 }
  56
  57 static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  58                                           bool use_doorbell, int doorbell_index,
  59                                           int doorbell_size)
  60 {
  61         u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
  62         u32 doorbell_range = RREG32_PCIE_PORT(reg);
  63
  64         if (use_doorbell) {
  65                 doorbell_range = REG_SET_FIELD(doorbell_range,
  66                                                GDC0_BIF_CSDMA_DOORBELL_RANGE,
  67                                                OFFSET, doorbell_index);
  68                 doorbell_range = REG_SET_FIELD(doorbell_range,
  69                                                GDC0_BIF_CSDMA_DOORBELL_RANGE,
  70                                                SIZE, doorbell_size);
  71                 doorbell_range = REG_SET_FIELD(doorbell_range,
  72                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  73                                                OFFSET, doorbell_index);
  74                 doorbell_range = REG_SET_FIELD(doorbell_range,
  75                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  76                                                SIZE, doorbell_size);
  77         } else {
  78                 doorbell_range = REG_SET_FIELD(doorbell_range,
  79                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  80                                                SIZE, 0);
  81         }
  82
  83         WREG32_PCIE_PORT(reg, doorbell_range);
  84 }
  85
  86 static void nbio_v7_7_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
  87                                         int doorbell_index, int instance)
  88 {
  89         u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
  90         u32 doorbell_range = RREG32_PCIE_PORT(reg);
  91
  92         if (use_doorbell) {
  93                 doorbell_range = REG_SET_FIELD(doorbell_range,
  94                                                GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
  95                                                doorbell_index);
  96                 doorbell_range = REG_SET_FIELD(doorbell_range,
  97                                                GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
  98         } else {
  99                 doorbell_range = REG_SET_FIELD(doorbell_range,
 100                                                GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
 101         }
 102
 103         WREG32_PCIE_PORT(reg, doorbell_range);
 104 }
 105
 106 static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
 107                                                bool enable)
 108 {
 109         u32 reg;
 110
 111         reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
 112         reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
 113                             BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 114
 115         WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
 116 }
 117
 118 static void nbio_v7_7_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 119                                                         bool enable)
 120 {
 121         u32 tmp = 0;
 122
 123         if (enable) {
 124                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 125                                 DOORBELL_SELFRING_GPA_APER_EN, 1) |
 126                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 127                                 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 128                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 129                                 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 130
 131                 WREG32_SOC15(NBIO, 0,
 132                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 133                         lower_32_bits(adev->doorbell.base));
 134                 WREG32_SOC15(NBIO, 0,
 135                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 136                         upper_32_bits(adev->doorbell.base));
 137         }
 138
 139         WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 140                 tmp);
 141 }
 142
 143
 144 static void nbio_v7_7_ih_doorbell_range(struct amdgpu_device *adev,
 145                                         bool use_doorbell, int doorbell_index)
 146 {
 147         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,
 148                                                                 regGDC0_BIF_IH_DOORBELL_RANGE);
 149
 150         if (use_doorbell) {
 151                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 152                                                   GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
 153                                                   doorbell_index);
 154                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 155                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 156                                                   2);
 157         } else {
 158                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 159                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 160                                                   0);
 161         }
 162
 163         WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
 164                          ih_doorbell_range);
 165 }
 166
 167 static void nbio_v7_7_ih_control(struct amdgpu_device *adev)
 168 {
 169         u32 interrupt_cntl;
 170
 171         /* setup interrupt control */
 172         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
 173                      adev->dummy_page_addr >> 8);
 174
 175         interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
 176         /*
 177          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 178          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 179          */
 180         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 181                                        IH_DUMMY_RD_OVERRIDE, 0);
 182
 183         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 184         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 185                                        IH_REQ_NONSNOOP_EN, 0);
 186
 187         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
 188 }
 189
 190 static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 191 {
 192         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 193 }
 194
 195 static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 196 {
 197         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 198 }
 199
 200 static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev)
 201 {
 202         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
 203 }
 204
 205 static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev)
 206 {
 207         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
 208 }
 209
 210 static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev)
 211 {
 212         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
 213 }
 214
 215 static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev)
 216 {
 217         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
 218 }
 219
 220 const struct nbio_hdp_flush_reg nbio_v7_7_hdp_flush_reg = {
 221         .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
 222         .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
 223         .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
 224         .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
 225         .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
 226         .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
 227         .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
 228         .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
 229         .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
 230         .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
 231         .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 232         .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 233 };
 234
 235 static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
 236 {
 237         uint32_t def, data;
 238
 239         def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
 240         data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
 241                              CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 242         data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
 243                              CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 244
 245         if (def != data)
 246                 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
 247
 248 }
 249
 250 static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 251                                                        bool enable)
 252 {
 253         uint32_t def, data;
 254
 255         if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 256                 return;
 257
 258         def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
 259         if (enable) {
 260                 data |= (BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 261                          BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 262                          BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 263                          BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 264                          BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 265                          BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 266         } else {
 267                 data &= ~(BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 268                           BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 269                           BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 270                           BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 271                           BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 272                           BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 273         }
 274
 275         if (def != data)
 276                 WREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL, data);
 277 }
 278
 279 static void nbio_v7_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 280                                                       bool enable)
 281 {
 282         uint32_t def, data;
 283
 284         if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
 285                 return;
 286
 287         def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
 288         if (enable)
 289                 data |= BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
 290         else
 291                 data &= ~BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
 292
 293         if (def != data)
 294                 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2, data);
 295
 296         def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1);
 297         if (enable) {
 298                 data |= (BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
 299                         BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
 300         } else {
 301                 data &= ~(BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
 302                         BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
 303         }
 304
 305         if (def != data)
 306                 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1, data);
 307 }
 308
 309 static void nbio_v7_7_get_clockgating_state(struct amdgpu_device *adev,
 310                                             u64 *flags)
 311 {
 312         uint32_t data;
 313
 314         /* AMD_CG_SUPPORT_BIF_MGCG */
 315         data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
 316         if (data & BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 317                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 318
 319         /* AMD_CG_SUPPORT_BIF_LS */
 320         data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
 321         if (data & BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 322                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 323 }
 324
 325 const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
 326         .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
 327         .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
 328         .get_pcie_index_offset = nbio_v7_7_get_pcie_index_offset,
 329         .get_pcie_data_offset = nbio_v7_7_get_pcie_data_offset,
 330         .get_pcie_port_index_offset = nbio_v7_7_get_pcie_port_index_offset,
 331         .get_pcie_port_data_offset = nbio_v7_7_get_pcie_port_data_offset,
 332         .get_rev_id = nbio_v7_7_get_rev_id,
 333         .mc_access_enable = nbio_v7_7_mc_access_enable,
 334         .get_memsize = nbio_v7_7_get_memsize,
 335         .sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
 336         .vcn_doorbell_range = nbio_v7_7_vcn_doorbell_range,
 337         .enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
 338         .enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
 339         .ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
 340         .update_medium_grain_clock_gating = nbio_v7_7_update_medium_grain_clock_gating,
 341         .update_medium_grain_light_sleep = nbio_v7_7_update_medium_grain_light_sleep,
 342         .get_clockgating_state = nbio_v7_7_get_clockgating_state,
 343         .ih_control = nbio_v7_7_ih_control,
 344         .init_registers = nbio_v7_7_init_registers,
 345 };