drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v12_0.h"
  30
  31 #include "mp/mp_12_0_0_offset.h"
  32 #include "mp/mp_12_0_0_sh_mask.h"
  33 #include "gc/gc_9_0_offset.h"
  34 #include "sdma0/sdma0_4_0_offset.h"
  35 #include "nbio/nbio_7_4_offset.h"
  36
  37 #include "oss/osssys_4_0_offset.h"
  38 #include "oss/osssys_4_0_sh_mask.h"
  39
  40 MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
  41 MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
  42 MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
  44
  45 /* address block */
  46 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  47
  48 static int psp_v12_0_init_microcode(struct psp_context *psp)
  49 {
  50         struct amdgpu_device *adev = psp->adev;
  51         const char *chip_name;
  52         char fw_name[30];
  53         int err = 0;
  54         const struct ta_firmware_header_v1_0 *ta_hdr;
  55         DRM_DEBUG("\n");
  56
  57         switch (adev->asic_type) {
  58         case CHIP_RENOIR:
  59                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
  60                         chip_name = "renoir";
  61                 else
  62                         chip_name = "green_sardine";
  63                 break;
  64         default:
  65                 BUG();
  66         }
  67
  68         err = psp_init_asd_microcode(psp, chip_name);
  69         if (err)
  70                 return err;
  71
  72         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
  73         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
  74         if (err) {
  75                 release_firmware(adev->psp.ta_fw);
  76                 adev->psp.ta_fw = NULL;
  77                 dev_info(adev->dev,
  78                          "psp v12.0: Failed to load firmware \"%s\"\n",
  79                          fw_name);
  80         } else {
  81                 err = amdgpu_ucode_validate(adev->psp.ta_fw);
  82                 if (err)
  83                         goto out;
  84
  85                 ta_hdr = (const struct ta_firmware_header_v1_0 *)
  86                                  adev->psp.ta_fw->data;
  87                 adev->psp.hdcp_context.context.bin_desc.fw_version =
  88                         le32_to_cpu(ta_hdr->hdcp.fw_version);
  89                 adev->psp.hdcp_context.context.bin_desc.size_bytes =
  90                         le32_to_cpu(ta_hdr->hdcp.size_bytes);
  91                 adev->psp.hdcp_context.context.bin_desc.start_addr =
  92                         (uint8_t *)ta_hdr +
  93                         le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
  94
  95                 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
  96
  97                 adev->psp.dtm_context.context.bin_desc.fw_version =
  98                         le32_to_cpu(ta_hdr->dtm.fw_version);
  99                 adev->psp.dtm_context.context.bin_desc.size_bytes =
 100                         le32_to_cpu(ta_hdr->dtm.size_bytes);
 101                 adev->psp.dtm_context.context.bin_desc.start_addr =
 102                         (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
 103                         le32_to_cpu(ta_hdr->dtm.offset_bytes);
 104
 105                 if (adev->apu_flags & AMD_APU_IS_RENOIR) {
 106                         adev->psp.securedisplay_context.context.bin_desc.fw_version =
 107                                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
 108                         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
 109                                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
 110                         adev->psp.securedisplay_context.context.bin_desc.start_addr =
 111                                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
 112                                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
 113                 }
 114         }
 115
 116         return 0;
 117
 118 out:
 119         release_firmware(adev->psp.ta_fw);
 120         adev->psp.ta_fw = NULL;
 121         if (err) {
 122                 dev_err(adev->dev,
 123                         "psp v12.0: Failed to load firmware \"%s\"\n",
 124                         fw_name);
 125         }
 126
 127         return err;
 128 }
 129
 130 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
 131 {
 132         int ret;
 133         uint32_t psp_gfxdrv_command_reg = 0;
 134         struct amdgpu_device *adev = psp->adev;
 135         uint32_t sol_reg;
 136
 137         /* Check sOS sign of life register to confirm sys driver and sOS
 138          * are already been loaded.
 139          */
 140         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 141         if (sol_reg)
 142                 return 0;
 143
 144         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 145         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 146                            0x80000000, 0x80000000, false);
 147         if (ret)
 148                 return ret;
 149
 150         /* Copy PSP System Driver binary to memory */
 151         psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
 152
 153         /* Provide the sys driver to bootloader */
 154         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 155                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 156         psp_gfxdrv_command_reg = 1 << 16;
 157         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 158                psp_gfxdrv_command_reg);
 159
 160         /* there might be handshake issue with hardware which needs delay */
 161         mdelay(20);
 162
 163         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 164                            0x80000000, 0x80000000, false);
 165
 166         return ret;
 167 }
 168
 169 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
 170 {
 171         int ret;
 172         unsigned int psp_gfxdrv_command_reg = 0;
 173         struct amdgpu_device *adev = psp->adev;
 174         uint32_t sol_reg;
 175
 176         /* Check sOS sign of life register to confirm sys driver and sOS
 177          * are already been loaded.
 178          */
 179         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 180         if (sol_reg)
 181                 return 0;
 182
 183         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 184         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 185                            0x80000000, 0x80000000, false);
 186         if (ret)
 187                 return ret;
 188
 189         /* Copy Secure OS binary to PSP memory */
 190         psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
 191
 192         /* Provide the PSP secure OS to bootloader */
 193         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 194                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 195         psp_gfxdrv_command_reg = 2 << 16;
 196         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 197                psp_gfxdrv_command_reg);
 198
 199         /* there might be handshake issue with hardware which needs delay */
 200         mdelay(20);
 201         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 202                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 203                            0, true);
 204
 205         return ret;
 206 }
 207
 208 static void psp_v12_0_reroute_ih(struct psp_context *psp)
 209 {
 210         struct amdgpu_device *adev = psp->adev;
 211         uint32_t tmp;
 212
 213         /* Change IH ring for VMC */
 214         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 215         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 216         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 217
 218         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 219         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 220         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 221
 222         mdelay(20);
 223         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 224                      0x80000000, 0x8000FFFF, false);
 225
 226         /* Change IH ring for UMC */
 227         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 228         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 229
 230         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 231         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 232         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 233
 234         mdelay(20);
 235         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 236                      0x80000000, 0x8000FFFF, false);
 237 }
 238
 239 static int psp_v12_0_ring_create(struct psp_context *psp,
 240                                 enum psp_ring_type ring_type)
 241 {
 242         int ret = 0;
 243         unsigned int psp_ring_reg = 0;
 244         struct psp_ring *ring = &psp->km_ring;
 245         struct amdgpu_device *adev = psp->adev;
 246
 247         psp_v12_0_reroute_ih(psp);
 248
 249         if (amdgpu_sriov_vf(psp->adev)) {
 250                 /* Write low address of the ring to C2PMSG_102 */
 251                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 252                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 253                 /* Write high address of the ring to C2PMSG_103 */
 254                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 255                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 256
 257                 /* Write the ring initialization command to C2PMSG_101 */
 258                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 259                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 260
 261                 /* there might be handshake issue with hardware which needs delay */
 262                 mdelay(20);
 263
 264                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 265                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 266                                    0x80000000, 0x8000FFFF, false);
 267
 268         } else {
 269                 /* Write low address of the ring to C2PMSG_69 */
 270                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 271                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 272                 /* Write high address of the ring to C2PMSG_70 */
 273                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 274                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 275                 /* Write size of ring to C2PMSG_71 */
 276                 psp_ring_reg = ring->ring_size;
 277                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 278                 /* Write the ring initialization command to C2PMSG_64 */
 279                 psp_ring_reg = ring_type;
 280                 psp_ring_reg = psp_ring_reg << 16;
 281                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 282
 283                 /* there might be handshake issue with hardware which needs delay */
 284                 mdelay(20);
 285
 286                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 287                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 288                                    0x80000000, 0x8000FFFF, false);
 289         }
 290
 291         return ret;
 292 }
 293
 294 static int psp_v12_0_ring_stop(struct psp_context *psp,
 295                               enum psp_ring_type ring_type)
 296 {
 297         int ret = 0;
 298         struct amdgpu_device *adev = psp->adev;
 299
 300         /* Write the ring destroy command*/
 301         if (amdgpu_sriov_vf(adev))
 302                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 303                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 304         else
 305                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 306                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 307
 308         /* there might be handshake issue with hardware which needs delay */
 309         mdelay(20);
 310
 311         /* Wait for response flag (bit 31) */
 312         if (amdgpu_sriov_vf(adev))
 313                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 314                                    0x80000000, 0x80000000, false);
 315         else
 316                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 317                                    0x80000000, 0x80000000, false);
 318
 319         return ret;
 320 }
 321
 322 static int psp_v12_0_ring_destroy(struct psp_context *psp,
 323                                  enum psp_ring_type ring_type)
 324 {
 325         int ret = 0;
 326         struct psp_ring *ring = &psp->km_ring;
 327         struct amdgpu_device *adev = psp->adev;
 328
 329         ret = psp_v12_0_ring_stop(psp, ring_type);
 330         if (ret)
 331                 DRM_ERROR("Fail to stop psp ring\n");
 332
 333         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 334                               &ring->ring_mem_mc_addr,
 335                               (void **)&ring->ring_mem);
 336
 337         return ret;
 338 }
 339
 340 static int psp_v12_0_mode1_reset(struct psp_context *psp)
 341 {
 342         int ret;
 343         uint32_t offset;
 344         struct amdgpu_device *adev = psp->adev;
 345
 346         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 347
 348         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 349
 350         if (ret) {
 351                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 352                 return -EINVAL;
 353         }
 354
 355         /*send the mode 1 reset command*/
 356         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 357
 358         msleep(500);
 359
 360         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 361
 362         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 363
 364         if (ret) {
 365                 DRM_INFO("psp mode 1 reset failed!\n");
 366                 return -EINVAL;
 367         }
 368
 369         DRM_INFO("psp mode1 reset succeed \n");
 370
 371         return 0;
 372 }
 373
 374 static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
 375 {
 376         uint32_t data;
 377         struct amdgpu_device *adev = psp->adev;
 378
 379         if (amdgpu_sriov_vf(adev))
 380                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 381         else
 382                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 383
 384         return data;
 385 }
 386
 387 static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 388 {
 389         struct amdgpu_device *adev = psp->adev;
 390
 391         if (amdgpu_sriov_vf(adev)) {
 392                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
 393                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 394         } else
 395                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 396 }
 397
 398 static const struct psp_funcs psp_v12_0_funcs = {
 399         .init_microcode = psp_v12_0_init_microcode,
 400         .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
 401         .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
 402         .ring_create = psp_v12_0_ring_create,
 403         .ring_stop = psp_v12_0_ring_stop,
 404         .ring_destroy = psp_v12_0_ring_destroy,
 405         .mode1_reset = psp_v12_0_mode1_reset,
 406         .ring_get_wptr = psp_v12_0_ring_get_wptr,
 407         .ring_set_wptr = psp_v12_0_ring_set_wptr,
 408 };
 409
 410 void psp_v12_0_set_psp_funcs(struct psp_context *psp)
 411 {
 412         psp->funcs = &psp_v12_0_funcs;
 413 }