drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM,
  70                                       &adev->firmware.rbuf,
  71                                       &ring->ring_mem_mc_addr,
  72                                       (void **)&ring->ring_mem);
  73         if (ret) {
  74                 ring->ring_size = 0;
  75                 return ret;
  76         }
  77
  78         return 0;
  79 }
  80
  81 /*
  82  * Due to DF Cstate management centralized to PMFW, the firmware
  83  * loading sequence will be updated as below:
  84  *   - Load KDB
  85  *   - Load SYS_DRV
  86  *   - Load tOS
  87  *   - Load PMFW
  88  *   - Setup TMR
  89  *   - Load other non-psp fw
  90  *   - Load ASD
  91  *   - Load XGMI/RAS/HDCP/DTM TA if any
  92  *
  93  * This new sequence is required for
  94  *   - Arcturus and onwards
  95  */
  96 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  97 {
  98         struct amdgpu_device *adev = psp->adev;
  99
 100         if (amdgpu_sriov_vf(adev)) {
 101                 psp->pmfw_centralized_cstate_management = false;
 102                 return;
 103         }
 104
 105         switch (adev->ip_versions[MP0_HWIP][0]) {
 106         case IP_VERSION(11, 0, 0):
 107         case IP_VERSION(11, 0, 4):
 108         case IP_VERSION(11, 0, 5):
 109         case IP_VERSION(11, 0, 7):
 110         case IP_VERSION(11, 0, 9):
 111         case IP_VERSION(11, 0, 11):
 112         case IP_VERSION(11, 0, 12):
 113         case IP_VERSION(11, 0, 13):
 114         case IP_VERSION(13, 0, 0):
 115         case IP_VERSION(13, 0, 2):
 116         case IP_VERSION(13, 0, 7):
 117                 psp->pmfw_centralized_cstate_management = true;
 118                 break;
 119         default:
 120                 psp->pmfw_centralized_cstate_management = false;
 121                 break;
 122         }
 123 }
 124
 125 static int psp_early_init(void *handle)
 126 {
 127         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 128         struct psp_context *psp = &adev->psp;
 129
 130         switch (adev->ip_versions[MP0_HWIP][0]) {
 131         case IP_VERSION(9, 0, 0):
 132                 psp_v3_1_set_psp_funcs(psp);
 133                 psp->autoload_supported = false;
 134                 break;
 135         case IP_VERSION(10, 0, 0):
 136         case IP_VERSION(10, 0, 1):
 137                 psp_v10_0_set_psp_funcs(psp);
 138                 psp->autoload_supported = false;
 139                 break;
 140         case IP_VERSION(11, 0, 2):
 141         case IP_VERSION(11, 0, 4):
 142                 psp_v11_0_set_psp_funcs(psp);
 143                 psp->autoload_supported = false;
 144                 break;
 145         case IP_VERSION(11, 0, 0):
 146         case IP_VERSION(11, 0, 5):
 147         case IP_VERSION(11, 0, 9):
 148         case IP_VERSION(11, 0, 7):
 149         case IP_VERSION(11, 0, 11):
 150         case IP_VERSION(11, 5, 0):
 151         case IP_VERSION(11, 0, 12):
 152         case IP_VERSION(11, 0, 13):
 153                 psp_v11_0_set_psp_funcs(psp);
 154                 psp->autoload_supported = true;
 155                 break;
 156         case IP_VERSION(11, 0, 3):
 157         case IP_VERSION(12, 0, 1):
 158                 psp_v12_0_set_psp_funcs(psp);
 159                 break;
 160         case IP_VERSION(13, 0, 2):
 161                 psp_v13_0_set_psp_funcs(psp);
 162                 break;
 163         case IP_VERSION(13, 0, 1):
 164         case IP_VERSION(13, 0, 3):
 165         case IP_VERSION(13, 0, 5):
 166         case IP_VERSION(13, 0, 8):
 167         case IP_VERSION(13, 0, 10):
 168         case IP_VERSION(13, 0, 11):
 169                 psp_v13_0_set_psp_funcs(psp);
 170                 psp->autoload_supported = true;
 171                 break;
 172         case IP_VERSION(11, 0, 8):
 173                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 174                         psp_v11_0_8_set_psp_funcs(psp);
 175                         psp->autoload_supported = false;
 176                 }
 177                 break;
 178         case IP_VERSION(13, 0, 0):
 179         case IP_VERSION(13, 0, 7):
 180                 psp_v13_0_set_psp_funcs(psp);
 181                 psp->autoload_supported = true;
 182                 break;
 183         case IP_VERSION(13, 0, 4):
 184                 psp_v13_0_4_set_psp_funcs(psp);
 185                 psp->autoload_supported = true;
 186                 break;
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         psp->adev = adev;
 192
 193         psp_check_pmfw_centralized_cstate_management(psp);
 194
 195         return 0;
 196 }
 197
 198 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 199 {
 200         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 201                               &mem_ctx->shared_buf);
 202         mem_ctx->shared_bo = NULL;
 203 }
 204
 205 static void psp_free_shared_bufs(struct psp_context *psp)
 206 {
 207         void *tmr_buf;
 208         void **pptr;
 209
 210         /* free TMR memory buffer */
 211         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 212         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 213         psp->tmr_bo = NULL;
 214
 215         /* free xgmi shared memory */
 216         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 217
 218         /* free ras shared memory */
 219         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 220
 221         /* free hdcp shared memory */
 222         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 223
 224         /* free dtm shared memory */
 225         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 226
 227         /* free rap shared memory */
 228         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 229
 230         /* free securedisplay shared memory */
 231         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 232
 233
 234 }
 235
 236 static void psp_memory_training_fini(struct psp_context *psp)
 237 {
 238         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 239
 240         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 241         kfree(ctx->sys_cache);
 242         ctx->sys_cache = NULL;
 243 }
 244
 245 static int psp_memory_training_init(struct psp_context *psp)
 246 {
 247         int ret;
 248         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 249
 250         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 251                 DRM_DEBUG("memory training is not supported!\n");
 252                 return 0;
 253         }
 254
 255         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 256         if (ctx->sys_cache == NULL) {
 257                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 258                 ret = -ENOMEM;
 259                 goto Err_out;
 260         }
 261
 262         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 263                   ctx->train_data_size,
 264                   ctx->p2c_train_data_offset,
 265                   ctx->c2p_train_data_offset);
 266         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 267         return 0;
 268
 269 Err_out:
 270         psp_memory_training_fini(psp);
 271         return ret;
 272 }
 273
 274 /*
 275  * Helper funciton to query psp runtime database entry
 276  *
 277  * @adev: amdgpu_device pointer
 278  * @entry_type: the type of psp runtime database entry
 279  * @db_entry: runtime database entry pointer
 280  *
 281  * Return false if runtime database doesn't exit or entry is invalid
 282  * or true if the specific database entry is found, and copy to @db_entry
 283  */
 284 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 285                                      enum psp_runtime_entry_type entry_type,
 286                                      void *db_entry)
 287 {
 288         uint64_t db_header_pos, db_dir_pos;
 289         struct psp_runtime_data_header db_header = {0};
 290         struct psp_runtime_data_directory db_dir = {0};
 291         bool ret = false;
 292         int i;
 293
 294         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 295         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 296
 297         /* read runtime db header from vram */
 298         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 299                         sizeof(struct psp_runtime_data_header), false);
 300
 301         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 302                 /* runtime db doesn't exist, exit */
 303                 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
 304                 return false;
 305         }
 306
 307         /* read runtime database entry from vram */
 308         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 309                         sizeof(struct psp_runtime_data_directory), false);
 310
 311         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 312                 /* invalid db entry count, exit */
 313                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 314                 return false;
 315         }
 316
 317         /* look up for requested entry type */
 318         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 319                 if (db_dir.entry_list[i].entry_type == entry_type) {
 320                         switch (entry_type) {
 321                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 322                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 323                                         /* invalid db entry size */
 324                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 325                                         return false;
 326                                 }
 327                                 /* read runtime database entry */
 328                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 329                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 330                                 ret = true;
 331                                 break;
 332                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 333                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 334                                         /* invalid db entry size */
 335                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 336                                         return false;
 337                                 }
 338                                 /* read runtime database entry */
 339                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 340                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 341                                 ret = true;
 342                                 break;
 343                         default:
 344                                 ret = false;
 345                                 break;
 346                         }
 347                 }
 348         }
 349
 350         return ret;
 351 }
 352
 353 static int psp_init_sriov_microcode(struct psp_context *psp)
 354 {
 355         struct amdgpu_device *adev = psp->adev;
 356         int ret = 0;
 357
 358         switch (adev->ip_versions[MP0_HWIP][0]) {
 359         case IP_VERSION(9, 0, 0):
 360                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 361                 ret = psp_init_cap_microcode(psp, "vega10");
 362                 break;
 363         case IP_VERSION(11, 0, 9):
 364                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 365                 ret = psp_init_cap_microcode(psp, "navi12");
 366                 break;
 367         case IP_VERSION(11, 0, 7):
 368                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 369                 ret = psp_init_cap_microcode(psp, "sienna_cichlid");
 370                 break;
 371         case IP_VERSION(13, 0, 2):
 372                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 373                 ret = psp_init_cap_microcode(psp, "aldebaran");
 374                 ret &= psp_init_ta_microcode(psp, "aldebaran");
 375                 break;
 376         case IP_VERSION(13, 0, 0):
 377                 adev->virt.autoload_ucode_id = 0;
 378                 break;
 379         case IP_VERSION(13, 0, 10):
 380                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 381                 break;
 382         default:
 383                 BUG();
 384                 break;
 385         }
 386         return ret;
 387 }
 388
 389 static int psp_sw_init(void *handle)
 390 {
 391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 392         struct psp_context *psp = &adev->psp;
 393         int ret;
 394         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 395         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 396         struct psp_runtime_scpm_entry scpm_entry;
 397
 398         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 399         if (!psp->cmd) {
 400                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 401                 ret = -ENOMEM;
 402         }
 403
 404         if (amdgpu_sriov_vf(adev))
 405                 ret = psp_init_sriov_microcode(psp);
 406         else
 407                 ret = psp_init_microcode(psp);
 408         if (ret) {
 409                 DRM_ERROR("Failed to load psp firmware!\n");
 410                 return ret;
 411         }
 412
 413         adev->psp.xgmi_context.supports_extended_data =
 414                 !adev->gmc.xgmi.connected_to_cpu &&
 415                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 416
 417         memset(&scpm_entry, 0, sizeof(scpm_entry));
 418         if ((psp_get_runtime_db_entry(adev,
 419                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 420                                 &scpm_entry)) &&
 421             (SCPM_DISABLE != scpm_entry.scpm_status)) {
 422                 adev->scpm_enabled = true;
 423                 adev->scpm_status = scpm_entry.scpm_status;
 424         } else {
 425                 adev->scpm_enabled = false;
 426                 adev->scpm_status = SCPM_DISABLE;
 427         }
 428
 429         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 430
 431         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 432         if (psp_get_runtime_db_entry(adev,
 433                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 434                                 &boot_cfg_entry)) {
 435                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 436                 if ((psp->boot_cfg_bitmask) &
 437                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 438                         /* If psp runtime database exists, then
 439                          * only enable two stage memory training
 440                          * when TWO_STAGE_DRAM_TRAINING bit is set
 441                          * in runtime database */
 442                         mem_training_ctx->enable_mem_training = true;
 443                 }
 444
 445         } else {
 446                 /* If psp runtime database doesn't exist or
 447                  * is invalid, force enable two stage memory
 448                  * training */
 449                 mem_training_ctx->enable_mem_training = true;
 450         }
 451
 452         if (mem_training_ctx->enable_mem_training) {
 453                 ret = psp_memory_training_init(psp);
 454                 if (ret) {
 455                         DRM_ERROR("Failed to initialize memory training!\n");
 456                         return ret;
 457                 }
 458
 459                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 460                 if (ret) {
 461                         DRM_ERROR("Failed to process memory training!\n");
 462                         return ret;
 463                 }
 464         }
 465
 466         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 467             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 468                 ret= psp_sysfs_init(adev);
 469                 if (ret) {
 470                         return ret;
 471                 }
 472         }
 473
 474         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 475                                       amdgpu_sriov_vf(adev) ?
 476                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 477                                       &psp->fw_pri_bo,
 478                                       &psp->fw_pri_mc_addr,
 479                                       &psp->fw_pri_buf);
 480         if (ret)
 481                 return ret;
 482
 483         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 484                                       AMDGPU_GEM_DOMAIN_VRAM,
 485                                       &psp->fence_buf_bo,
 486                                       &psp->fence_buf_mc_addr,
 487                                       &psp->fence_buf);
 488         if (ret)
 489                 goto failed1;
 490
 491         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 492                                       AMDGPU_GEM_DOMAIN_VRAM,
 493                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 494                                       (void **)&psp->cmd_buf_mem);
 495         if (ret)
 496                 goto failed2;
 497
 498         return 0;
 499
 500 failed2:
 501         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 502                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 503 failed1:
 504         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 505                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 506         return ret;
 507 }
 508
 509 static int psp_sw_fini(void *handle)
 510 {
 511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 512         struct psp_context *psp = &adev->psp;
 513         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 514
 515         psp_memory_training_fini(psp);
 516
 517         release_firmware(psp->sos_fw);
 518         psp->sos_fw = NULL;
 519
 520         release_firmware(psp->asd_fw);
 521         psp->asd_fw = NULL;
 522
 523         release_firmware(psp->ta_fw);
 524         psp->ta_fw = NULL;
 525
 526         release_firmware(psp->cap_fw);
 527         psp->cap_fw = NULL;
 528
 529         release_firmware(psp->toc_fw);
 530         psp->toc_fw = NULL;
 531
 532         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 533             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 534                 psp_sysfs_fini(adev);
 535
 536         kfree(cmd);
 537         cmd = NULL;
 538
 539         if (psp->km_ring.ring_mem)
 540                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 541                                       &psp->km_ring.ring_mem_mc_addr,
 542                                       (void **)&psp->km_ring.ring_mem);
 543
 544         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 545                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 546         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 547                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 548         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 549                               (void **)&psp->cmd_buf_mem);
 550
 551         return 0;
 552 }
 553
 554 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 555                  uint32_t reg_val, uint32_t mask, bool check_changed)
 556 {
 557         uint32_t val;
 558         int i;
 559         struct amdgpu_device *adev = psp->adev;
 560
 561         if (psp->adev->no_hw_access)
 562                 return 0;
 563
 564         for (i = 0; i < adev->usec_timeout; i++) {
 565                 val = RREG32(reg_index);
 566                 if (check_changed) {
 567                         if (val != reg_val)
 568                                 return 0;
 569                 } else {
 570                         if ((val & mask) == reg_val)
 571                                 return 0;
 572                 }
 573                 udelay(1);
 574         }
 575
 576         return -ETIME;
 577 }
 578
 579 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 580 {
 581         switch (cmd_id) {
 582         case GFX_CMD_ID_LOAD_TA:
 583                 return "LOAD_TA";
 584         case GFX_CMD_ID_UNLOAD_TA:
 585                 return "UNLOAD_TA";
 586         case GFX_CMD_ID_INVOKE_CMD:
 587                 return "INVOKE_CMD";
 588         case GFX_CMD_ID_LOAD_ASD:
 589                 return "LOAD_ASD";
 590         case GFX_CMD_ID_SETUP_TMR:
 591                 return "SETUP_TMR";
 592         case GFX_CMD_ID_LOAD_IP_FW:
 593                 return "LOAD_IP_FW";
 594         case GFX_CMD_ID_DESTROY_TMR:
 595                 return "DESTROY_TMR";
 596         case GFX_CMD_ID_SAVE_RESTORE:
 597                 return "SAVE_RESTORE_IP_FW";
 598         case GFX_CMD_ID_SETUP_VMR:
 599                 return "SETUP_VMR";
 600         case GFX_CMD_ID_DESTROY_VMR:
 601                 return "DESTROY_VMR";
 602         case GFX_CMD_ID_PROG_REG:
 603                 return "PROG_REG";
 604         case GFX_CMD_ID_GET_FW_ATTESTATION:
 605                 return "GET_FW_ATTESTATION";
 606         case GFX_CMD_ID_LOAD_TOC:
 607                 return "ID_LOAD_TOC";
 608         case GFX_CMD_ID_AUTOLOAD_RLC:
 609                 return "AUTOLOAD_RLC";
 610         case GFX_CMD_ID_BOOT_CFG:
 611                 return "BOOT_CFG";
 612         default:
 613                 return "UNKNOWN CMD";
 614         }
 615 }
 616
 617 static int
 618 psp_cmd_submit_buf(struct psp_context *psp,
 619                    struct amdgpu_firmware_info *ucode,
 620                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 621 {
 622         int ret;
 623         int index, idx;
 624         int timeout = 20000;
 625         bool ras_intr = false;
 626         bool skip_unsupport = false;
 627
 628         if (psp->adev->no_hw_access)
 629                 return 0;
 630
 631         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
 632                 return 0;
 633
 634         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 635
 636         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 637
 638         index = atomic_inc_return(&psp->fence_value);
 639         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 640         if (ret) {
 641                 atomic_dec(&psp->fence_value);
 642                 goto exit;
 643         }
 644
 645         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 646         while (*((unsigned int *)psp->fence_buf) != index) {
 647                 if (--timeout == 0)
 648                         break;
 649                 /*
 650                  * Shouldn't wait for timeout when err_event_athub occurs,
 651                  * because gpu reset thread triggered and lock resource should
 652                  * be released for psp resume sequence.
 653                  */
 654                 ras_intr = amdgpu_ras_intr_triggered();
 655                 if (ras_intr)
 656                         break;
 657                 usleep_range(10, 100);
 658                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 659         }
 660
 661         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 662         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 663                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 664
 665         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 666
 667         /* In some cases, psp response status is not 0 even there is no
 668          * problem while the command is submitted. Some version of PSP FW
 669          * doesn't write 0 to that field.
 670          * So here we would like to only print a warning instead of an error
 671          * during psp initialization to avoid breaking hw_init and it doesn't
 672          * return -EINVAL.
 673          */
 674         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 675                 if (ucode)
 676                         DRM_WARN("failed to load ucode %s(0x%X) ",
 677                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 678                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 679                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 680                          psp->cmd_buf_mem->resp.status);
 681                 /* If any firmware (including CAP) load fails under SRIOV, it should
 682                  * return failure to stop the VF from initializing.
 683                  * Also return failure in case of timeout
 684                  */
 685                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 686                         ret = -EINVAL;
 687                         goto exit;
 688                 }
 689         }
 690
 691         if (ucode) {
 692                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 693                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 694         }
 695
 696 exit:
 697         drm_dev_exit(idx);
 698         return ret;
 699 }
 700
 701 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 702 {
 703         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 704
 705         mutex_lock(&psp->mutex);
 706
 707         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 708
 709         return cmd;
 710 }
 711
 712 static void release_psp_cmd_buf(struct psp_context *psp)
 713 {
 714         mutex_unlock(&psp->mutex);
 715 }
 716
 717 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 718                                  struct psp_gfx_cmd_resp *cmd,
 719                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 720 {
 721         struct amdgpu_device *adev = psp->adev;
 722         uint32_t size = amdgpu_bo_size(tmr_bo);
 723         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 724
 725         if (amdgpu_sriov_vf(psp->adev))
 726                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 727         else
 728                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 729         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 730         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 731         cmd->cmd.cmd_setup_tmr.buf_size = size;
 732         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 733         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 734         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 735 }
 736
 737 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 738                                       uint64_t pri_buf_mc, uint32_t size)
 739 {
 740         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 741         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 742         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 743         cmd->cmd.cmd_load_toc.toc_size = size;
 744 }
 745
 746 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 747 static int psp_load_toc(struct psp_context *psp,
 748                         uint32_t *tmr_size)
 749 {
 750         int ret;
 751         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 752
 753         /* Copy toc to psp firmware private buffer */
 754         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 755
 756         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 757
 758         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 759                                  psp->fence_buf_mc_addr);
 760         if (!ret)
 761                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 762
 763         release_psp_cmd_buf(psp);
 764
 765         return ret;
 766 }
 767
 768 /* Set up Trusted Memory Region */
 769 static int psp_tmr_init(struct psp_context *psp)
 770 {
 771         int ret = 0;
 772         int tmr_size;
 773         void *tmr_buf;
 774         void **pptr;
 775
 776         /*
 777          * According to HW engineer, they prefer the TMR address be "naturally
 778          * aligned" , e.g. the start address be an integer divide of TMR size.
 779          *
 780          * Note: this memory need be reserved till the driver
 781          * uninitializes.
 782          */
 783         tmr_size = PSP_TMR_SIZE(psp->adev);
 784
 785         /* For ASICs support RLC autoload, psp will parse the toc
 786          * and calculate the total size of TMR needed */
 787         if (!amdgpu_sriov_vf(psp->adev) &&
 788             psp->toc.start_addr &&
 789             psp->toc.size_bytes &&
 790             psp->fw_pri_buf) {
 791                 ret = psp_load_toc(psp, &tmr_size);
 792                 if (ret) {
 793                         DRM_ERROR("Failed to load toc\n");
 794                         return ret;
 795                 }
 796         }
 797
 798         if (!psp->tmr_bo) {
 799                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 800                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
 801                                               AMDGPU_GEM_DOMAIN_VRAM,
 802                                               &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 803         }
 804
 805         return ret;
 806 }
 807
 808 static bool psp_skip_tmr(struct psp_context *psp)
 809 {
 810         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 811         case IP_VERSION(11, 0, 9):
 812         case IP_VERSION(11, 0, 7):
 813         case IP_VERSION(13, 0, 2):
 814         case IP_VERSION(13, 0, 10):
 815                 return true;
 816         default:
 817                 return false;
 818         }
 819 }
 820
 821 static int psp_tmr_load(struct psp_context *psp)
 822 {
 823         int ret;
 824         struct psp_gfx_cmd_resp *cmd;
 825
 826         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 827          * Already set up by host driver.
 828          */
 829         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 830                 return 0;
 831
 832         cmd = acquire_psp_cmd_buf(psp);
 833
 834         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 835         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 836                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 837
 838         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 839                                  psp->fence_buf_mc_addr);
 840
 841         release_psp_cmd_buf(psp);
 842
 843         return ret;
 844 }
 845
 846 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 847                                         struct psp_gfx_cmd_resp *cmd)
 848 {
 849         if (amdgpu_sriov_vf(psp->adev))
 850                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 851         else
 852                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 853 }
 854
 855 static int psp_tmr_unload(struct psp_context *psp)
 856 {
 857         int ret;
 858         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 859
 860         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 861         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 862
 863         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 864                                  psp->fence_buf_mc_addr);
 865
 866         release_psp_cmd_buf(psp);
 867
 868         return ret;
 869 }
 870
 871 static int psp_tmr_terminate(struct psp_context *psp)
 872 {
 873         return psp_tmr_unload(psp);
 874 }
 875
 876 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 877                                         uint64_t *output_ptr)
 878 {
 879         int ret;
 880         struct psp_gfx_cmd_resp *cmd;
 881
 882         if (!output_ptr)
 883                 return -EINVAL;
 884
 885         if (amdgpu_sriov_vf(psp->adev))
 886                 return 0;
 887
 888         cmd = acquire_psp_cmd_buf(psp);
 889
 890         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 891
 892         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 893                                  psp->fence_buf_mc_addr);
 894
 895         if (!ret) {
 896                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 897                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 898         }
 899
 900         release_psp_cmd_buf(psp);
 901
 902         return ret;
 903 }
 904
 905 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 906 {
 907         struct psp_context *psp = &adev->psp;
 908         struct psp_gfx_cmd_resp *cmd;
 909         int ret;
 910
 911         if (amdgpu_sriov_vf(adev))
 912                 return 0;
 913
 914         cmd = acquire_psp_cmd_buf(psp);
 915
 916         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 917         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 918
 919         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 920         if (!ret) {
 921                 *boot_cfg =
 922                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 923         }
 924
 925         release_psp_cmd_buf(psp);
 926
 927         return ret;
 928 }
 929
 930 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 931 {
 932         int ret;
 933         struct psp_context *psp = &adev->psp;
 934         struct psp_gfx_cmd_resp *cmd;
 935
 936         if (amdgpu_sriov_vf(adev))
 937                 return 0;
 938
 939         cmd = acquire_psp_cmd_buf(psp);
 940
 941         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 942         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 943         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 944         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 945
 946         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 947
 948         release_psp_cmd_buf(psp);
 949
 950         return ret;
 951 }
 952
 953 static int psp_rl_load(struct amdgpu_device *adev)
 954 {
 955         int ret;
 956         struct psp_context *psp = &adev->psp;
 957         struct psp_gfx_cmd_resp *cmd;
 958
 959         if (!is_psp_fw_valid(psp->rl))
 960                 return 0;
 961
 962         cmd = acquire_psp_cmd_buf(psp);
 963
 964         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 965         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 966
 967         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 968         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 969         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 970         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 971         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 972
 973         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 974
 975         release_psp_cmd_buf(psp);
 976
 977         return ret;
 978 }
 979
 980 static int psp_asd_initialize(struct psp_context *psp)
 981 {
 982         int ret;
 983
 984         /* If PSP version doesn't match ASD version, asd loading will be failed.
 985          * add workaround to bypass it for sriov now.
 986          * TODO: add version check to make it common
 987          */
 988         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 989                 return 0;
 990
 991         psp->asd_context.mem_context.shared_mc_addr  = 0;
 992         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 993         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 994
 995         ret = psp_ta_load(psp, &psp->asd_context);
 996         if (!ret)
 997                 psp->asd_context.initialized = true;
 998
 999         return ret;
1000 }
1001
1002 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1003                                        uint32_t session_id)
1004 {
1005         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1006         cmd->cmd.cmd_unload_ta.session_id = session_id;
1007 }
1008
1009 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1010 {
1011         int ret;
1012         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1013
1014         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1015
1016         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1017
1018         context->resp_status = cmd->resp.status;
1019
1020         release_psp_cmd_buf(psp);
1021
1022         return ret;
1023 }
1024
1025 static int psp_asd_terminate(struct psp_context *psp)
1026 {
1027         int ret;
1028
1029         if (amdgpu_sriov_vf(psp->adev))
1030                 return 0;
1031
1032         if (!psp->asd_context.initialized)
1033                 return 0;
1034
1035         ret = psp_ta_unload(psp, &psp->asd_context);
1036         if (!ret)
1037                 psp->asd_context.initialized = false;
1038
1039         return ret;
1040 }
1041
1042 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1043                 uint32_t id, uint32_t value)
1044 {
1045         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1046         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1047         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1048 }
1049
1050 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1051                 uint32_t value)
1052 {
1053         struct psp_gfx_cmd_resp *cmd;
1054         int ret = 0;
1055
1056         if (reg >= PSP_REG_LAST)
1057                 return -EINVAL;
1058
1059         cmd = acquire_psp_cmd_buf(psp);
1060
1061         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1062         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1063         if (ret)
1064                 DRM_ERROR("PSP failed to program reg id %d", reg);
1065
1066         release_psp_cmd_buf(psp);
1067
1068         return ret;
1069 }
1070
1071 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1072                                      uint64_t ta_bin_mc,
1073                                      struct ta_context *context)
1074 {
1075         cmd->cmd_id                             = context->ta_load_type;
1076         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1077         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1078         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1079
1080         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1081                 lower_32_bits(context->mem_context.shared_mc_addr);
1082         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1083                 upper_32_bits(context->mem_context.shared_mc_addr);
1084         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1085 }
1086
1087 int psp_ta_init_shared_buf(struct psp_context *psp,
1088                                   struct ta_mem_context *mem_ctx)
1089 {
1090         /*
1091         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1092         * physical) for ta to host memory
1093         */
1094         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1095                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1096                                       &mem_ctx->shared_bo,
1097                                       &mem_ctx->shared_mc_addr,
1098                                       &mem_ctx->shared_buf);
1099 }
1100
1101 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1102                                        uint32_t ta_cmd_id,
1103                                        uint32_t session_id)
1104 {
1105         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1106         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1107         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1108 }
1109
1110 int psp_ta_invoke(struct psp_context *psp,
1111                   uint32_t ta_cmd_id,
1112                   struct ta_context *context)
1113 {
1114         int ret;
1115         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1116
1117         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1118
1119         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1120                                  psp->fence_buf_mc_addr);
1121
1122         context->resp_status = cmd->resp.status;
1123
1124         release_psp_cmd_buf(psp);
1125
1126         return ret;
1127 }
1128
1129 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1130 {
1131         int ret;
1132         struct psp_gfx_cmd_resp *cmd;
1133
1134         cmd = acquire_psp_cmd_buf(psp);
1135
1136         psp_copy_fw(psp, context->bin_desc.start_addr,
1137                     context->bin_desc.size_bytes);
1138
1139         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1140
1141         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1142                                  psp->fence_buf_mc_addr);
1143
1144         context->resp_status = cmd->resp.status;
1145
1146         if (!ret) {
1147                 context->session_id = cmd->resp.session_id;
1148         }
1149
1150         release_psp_cmd_buf(psp);
1151
1152         return ret;
1153 }
1154
1155 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1156 {
1157         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1158 }
1159
1160 int psp_xgmi_terminate(struct psp_context *psp)
1161 {
1162         int ret;
1163         struct amdgpu_device *adev = psp->adev;
1164
1165         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1166         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1167             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1168              adev->gmc.xgmi.connected_to_cpu))
1169                 return 0;
1170
1171         if (!psp->xgmi_context.context.initialized)
1172                 return 0;
1173
1174         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1175
1176         psp->xgmi_context.context.initialized = false;
1177
1178         return ret;
1179 }
1180
1181 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1182 {
1183         struct ta_xgmi_shared_memory *xgmi_cmd;
1184         int ret;
1185
1186         if (!psp->ta_fw ||
1187             !psp->xgmi_context.context.bin_desc.size_bytes ||
1188             !psp->xgmi_context.context.bin_desc.start_addr)
1189                 return -ENOENT;
1190
1191         if (!load_ta)
1192                 goto invoke;
1193
1194         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1195         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1196
1197         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1198                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1199                 if (ret)
1200                         return ret;
1201         }
1202
1203         /* Load XGMI TA */
1204         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1205         if (!ret)
1206                 psp->xgmi_context.context.initialized = true;
1207         else
1208                 return ret;
1209
1210 invoke:
1211         /* Initialize XGMI session */
1212         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1213         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1214         xgmi_cmd->flag_extend_link_record = set_extended_data;
1215         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1216
1217         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1218
1219         return ret;
1220 }
1221
1222 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1223 {
1224         struct ta_xgmi_shared_memory *xgmi_cmd;
1225         int ret;
1226
1227         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1228         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1229
1230         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1231
1232         /* Invoke xgmi ta to get hive id */
1233         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1234         if (ret)
1235                 return ret;
1236
1237         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1238
1239         return 0;
1240 }
1241
1242 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1243 {
1244         struct ta_xgmi_shared_memory *xgmi_cmd;
1245         int ret;
1246
1247         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1248         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1249
1250         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1251
1252         /* Invoke xgmi ta to get the node id */
1253         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1254         if (ret)
1255                 return ret;
1256
1257         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1258
1259         return 0;
1260 }
1261
1262 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1263 {
1264         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1265                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1266 }
1267
1268 /*
1269  * Chips that support extended topology information require the driver to
1270  * reflect topology information in the opposite direction.  This is
1271  * because the TA has already exceeded its link record limit and if the
1272  * TA holds bi-directional information, the driver would have to do
1273  * multiple fetches instead of just two.
1274  */
1275 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1276                                         struct psp_xgmi_node_info node_info)
1277 {
1278         struct amdgpu_device *mirror_adev;
1279         struct amdgpu_hive_info *hive;
1280         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1281         uint64_t dst_node_id = node_info.node_id;
1282         uint8_t dst_num_hops = node_info.num_hops;
1283         uint8_t dst_num_links = node_info.num_links;
1284
1285         hive = amdgpu_get_xgmi_hive(psp->adev);
1286         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1287                 struct psp_xgmi_topology_info *mirror_top_info;
1288                 int j;
1289
1290                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1291                         continue;
1292
1293                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1294                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1295                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1296                                 continue;
1297
1298                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1299                         /*
1300                          * prevent 0 num_links value re-reflection since reflection
1301                          * criteria is based on num_hops (direct or indirect).
1302                          *
1303                          */
1304                         if (dst_num_links)
1305                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1306
1307                         break;
1308                 }
1309
1310                 break;
1311         }
1312
1313         amdgpu_put_xgmi_hive(hive);
1314 }
1315
1316 int psp_xgmi_get_topology_info(struct psp_context *psp,
1317                                int number_devices,
1318                                struct psp_xgmi_topology_info *topology,
1319                                bool get_extended_data)
1320 {
1321         struct ta_xgmi_shared_memory *xgmi_cmd;
1322         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1323         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1324         int i;
1325         int ret;
1326
1327         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1328                 return -EINVAL;
1329
1330         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1331         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1332         xgmi_cmd->flag_extend_link_record = get_extended_data;
1333
1334         /* Fill in the shared memory with topology information as input */
1335         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1336         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1337         topology_info_input->num_nodes = number_devices;
1338
1339         for (i = 0; i < topology_info_input->num_nodes; i++) {
1340                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1341                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1342                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1343                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1344         }
1345
1346         /* Invoke xgmi ta to get the topology information */
1347         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1348         if (ret)
1349                 return ret;
1350
1351         /* Read the output topology information from the shared memory */
1352         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1353         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1354         for (i = 0; i < topology->num_nodes; i++) {
1355                 /* extended data will either be 0 or equal to non-extended data */
1356                 if (topology_info_output->nodes[i].num_hops)
1357                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1358
1359                 /* non-extended data gets everything here so no need to update */
1360                 if (!get_extended_data) {
1361                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1362                         topology->nodes[i].is_sharing_enabled =
1363                                         topology_info_output->nodes[i].is_sharing_enabled;
1364                         topology->nodes[i].sdma_engine =
1365                                         topology_info_output->nodes[i].sdma_engine;
1366                 }
1367
1368         }
1369
1370         /* Invoke xgmi ta again to get the link information */
1371         if (psp_xgmi_peer_link_info_supported(psp)) {
1372                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1373
1374                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1375
1376                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1377
1378                 if (ret)
1379                         return ret;
1380
1381                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1382                 for (i = 0; i < topology->num_nodes; i++) {
1383                         /* accumulate num_links on extended data */
1384                         topology->nodes[i].num_links = get_extended_data ?
1385                                         topology->nodes[i].num_links +
1386                                                         link_info_output->nodes[i].num_links :
1387                                         link_info_output->nodes[i].num_links;
1388
1389                         /* reflect the topology information for bi-directionality */
1390                         if (psp->xgmi_context.supports_extended_data &&
1391                                         get_extended_data && topology->nodes[i].num_hops)
1392                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1393                 }
1394         }
1395
1396         return 0;
1397 }
1398
1399 int psp_xgmi_set_topology_info(struct psp_context *psp,
1400                                int number_devices,
1401                                struct psp_xgmi_topology_info *topology)
1402 {
1403         struct ta_xgmi_shared_memory *xgmi_cmd;
1404         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1405         int i;
1406
1407         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1408                 return -EINVAL;
1409
1410         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1411         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1412
1413         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1414         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1415         topology_info_input->num_nodes = number_devices;
1416
1417         for (i = 0; i < topology_info_input->num_nodes; i++) {
1418                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1419                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1420                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1421                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1422         }
1423
1424         /* Invoke xgmi ta to set topology information */
1425         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1426 }
1427
1428 // ras begin
1429 static void psp_ras_ta_check_status(struct psp_context *psp)
1430 {
1431         struct ta_ras_shared_memory *ras_cmd =
1432                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1433
1434         switch (ras_cmd->ras_status) {
1435         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1436                 dev_warn(psp->adev->dev,
1437                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1438                 break;
1439         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1440                 dev_warn(psp->adev->dev,
1441                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1442                 break;
1443         case TA_RAS_STATUS__SUCCESS:
1444                 break;
1445         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1446                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1447                         dev_warn(psp->adev->dev,
1448                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1449                 break;
1450         default:
1451                 dev_warn(psp->adev->dev,
1452                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1453                 break;
1454         }
1455 }
1456
1457 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1458 {
1459         struct ta_ras_shared_memory *ras_cmd;
1460         int ret;
1461
1462         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1463
1464         /*
1465          * TODO: bypass the loading in sriov for now
1466          */
1467         if (amdgpu_sriov_vf(psp->adev))
1468                 return 0;
1469
1470         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1471
1472         if (amdgpu_ras_intr_triggered())
1473                 return ret;
1474
1475         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1476         {
1477                 DRM_WARN("RAS: Unsupported Interface");
1478                 return -EINVAL;
1479         }
1480
1481         if (!ret) {
1482                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1483                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1484
1485                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1486                 }
1487                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1488                         dev_warn(psp->adev->dev,
1489                                  "RAS internal register access blocked\n");
1490
1491                 psp_ras_ta_check_status(psp);
1492         }
1493
1494         return ret;
1495 }
1496
1497 int psp_ras_enable_features(struct psp_context *psp,
1498                 union ta_ras_cmd_input *info, bool enable)
1499 {
1500         struct ta_ras_shared_memory *ras_cmd;
1501         int ret;
1502
1503         if (!psp->ras_context.context.initialized)
1504                 return -EINVAL;
1505
1506         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1507         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1508
1509         if (enable)
1510                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1511         else
1512                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1513
1514         ras_cmd->ras_in_message = *info;
1515
1516         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1517         if (ret)
1518                 return -EINVAL;
1519
1520         return 0;
1521 }
1522
1523 int psp_ras_terminate(struct psp_context *psp)
1524 {
1525         int ret;
1526
1527         /*
1528          * TODO: bypass the terminate in sriov for now
1529          */
1530         if (amdgpu_sriov_vf(psp->adev))
1531                 return 0;
1532
1533         if (!psp->ras_context.context.initialized)
1534                 return 0;
1535
1536         ret = psp_ta_unload(psp, &psp->ras_context.context);
1537
1538         psp->ras_context.context.initialized = false;
1539
1540         return ret;
1541 }
1542
1543 int psp_ras_initialize(struct psp_context *psp)
1544 {
1545         int ret;
1546         uint32_t boot_cfg = 0xFF;
1547         struct amdgpu_device *adev = psp->adev;
1548         struct ta_ras_shared_memory *ras_cmd;
1549
1550         /*
1551          * TODO: bypass the initialize in sriov for now
1552          */
1553         if (amdgpu_sriov_vf(adev))
1554                 return 0;
1555
1556         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1557             !adev->psp.ras_context.context.bin_desc.start_addr) {
1558                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1559                 return 0;
1560         }
1561
1562         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1563                 /* query GECC enablement status from boot config
1564                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1565                  */
1566                 ret = psp_boot_config_get(adev, &boot_cfg);
1567                 if (ret)
1568                         dev_warn(adev->dev, "PSP get boot config failed\n");
1569
1570                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1571                         if (!boot_cfg) {
1572                                 dev_info(adev->dev, "GECC is disabled\n");
1573                         } else {
1574                                 /* disable GECC in next boot cycle if ras is
1575                                  * disabled by module parameter amdgpu_ras_enable
1576                                  * and/or amdgpu_ras_mask, or boot_config_get call
1577                                  * is failed
1578                                  */
1579                                 ret = psp_boot_config_set(adev, 0);
1580                                 if (ret)
1581                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1582                                 else
1583                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1584                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1585                         }
1586                 } else {
1587                         if (1 == boot_cfg) {
1588                                 dev_info(adev->dev, "GECC is enabled\n");
1589                         } else {
1590                                 /* enable GECC in next boot cycle if it is disabled
1591                                  * in boot config, or force enable GECC if failed to
1592                                  * get boot configuration
1593                                  */
1594                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1595                                 if (ret)
1596                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1597                                 else
1598                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1599                         }
1600                 }
1601         }
1602
1603         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1604         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1605
1606         if (!psp->ras_context.context.mem_context.shared_buf) {
1607                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1608                 if (ret)
1609                         return ret;
1610         }
1611
1612         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1613         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1614
1615         if (amdgpu_ras_is_poison_mode_supported(adev))
1616                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1617         if (!adev->gmc.xgmi.connected_to_cpu)
1618                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1619
1620         ret = psp_ta_load(psp, &psp->ras_context.context);
1621
1622         if (!ret && !ras_cmd->ras_status)
1623                 psp->ras_context.context.initialized = true;
1624         else {
1625                 if (ras_cmd->ras_status)
1626                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1627
1628                 /* fail to load RAS TA */
1629                 psp->ras_context.context.initialized = false;
1630         }
1631
1632         return ret;
1633 }
1634
1635 int psp_ras_trigger_error(struct psp_context *psp,
1636                           struct ta_ras_trigger_error_input *info)
1637 {
1638         struct ta_ras_shared_memory *ras_cmd;
1639         int ret;
1640
1641         if (!psp->ras_context.context.initialized)
1642                 return -EINVAL;
1643
1644         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1645         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1646
1647         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1648         ras_cmd->ras_in_message.trigger_error = *info;
1649
1650         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1651         if (ret)
1652                 return -EINVAL;
1653
1654         /* If err_event_athub occurs error inject was successful, however
1655            return status from TA is no long reliable */
1656         if (amdgpu_ras_intr_triggered())
1657                 return 0;
1658
1659         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1660                 return -EACCES;
1661         else if (ras_cmd->ras_status)
1662                 return -EINVAL;
1663
1664         return 0;
1665 }
1666 // ras end
1667
1668 // HDCP start
1669 static int psp_hdcp_initialize(struct psp_context *psp)
1670 {
1671         int ret;
1672
1673         /*
1674          * TODO: bypass the initialize in sriov for now
1675          */
1676         if (amdgpu_sriov_vf(psp->adev))
1677                 return 0;
1678
1679         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1680             !psp->hdcp_context.context.bin_desc.start_addr) {
1681                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1682                 return 0;
1683         }
1684
1685         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1686         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1687
1688         if (!psp->hdcp_context.context.initialized) {
1689                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1690                 if (ret)
1691                         return ret;
1692         }
1693
1694         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1695         if (!ret) {
1696                 psp->hdcp_context.context.initialized = true;
1697                 mutex_init(&psp->hdcp_context.mutex);
1698         }
1699
1700         return ret;
1701 }
1702
1703 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1704 {
1705         /*
1706          * TODO: bypass the loading in sriov for now
1707          */
1708         if (amdgpu_sriov_vf(psp->adev))
1709                 return 0;
1710
1711         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1712 }
1713
1714 static int psp_hdcp_terminate(struct psp_context *psp)
1715 {
1716         int ret;
1717
1718         /*
1719          * TODO: bypass the terminate in sriov for now
1720          */
1721         if (amdgpu_sriov_vf(psp->adev))
1722                 return 0;
1723
1724         if (!psp->hdcp_context.context.initialized)
1725                 return 0;
1726
1727         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1728
1729         psp->hdcp_context.context.initialized = false;
1730
1731         return ret;
1732 }
1733 // HDCP end
1734
1735 // DTM start
1736 static int psp_dtm_initialize(struct psp_context *psp)
1737 {
1738         int ret;
1739
1740         /*
1741          * TODO: bypass the initialize in sriov for now
1742          */
1743         if (amdgpu_sriov_vf(psp->adev))
1744                 return 0;
1745
1746         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1747             !psp->dtm_context.context.bin_desc.start_addr) {
1748                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1749                 return 0;
1750         }
1751
1752         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1753         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1754
1755         if (!psp->dtm_context.context.initialized) {
1756                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1757                 if (ret)
1758                         return ret;
1759         }
1760
1761         ret = psp_ta_load(psp, &psp->dtm_context.context);
1762         if (!ret) {
1763                 psp->dtm_context.context.initialized = true;
1764                 mutex_init(&psp->dtm_context.mutex);
1765         }
1766
1767         return ret;
1768 }
1769
1770 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1771 {
1772         /*
1773          * TODO: bypass the loading in sriov for now
1774          */
1775         if (amdgpu_sriov_vf(psp->adev))
1776                 return 0;
1777
1778         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1779 }
1780
1781 static int psp_dtm_terminate(struct psp_context *psp)
1782 {
1783         int ret;
1784
1785         /*
1786          * TODO: bypass the terminate in sriov for now
1787          */
1788         if (amdgpu_sriov_vf(psp->adev))
1789                 return 0;
1790
1791         if (!psp->dtm_context.context.initialized)
1792                 return 0;
1793
1794         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1795
1796         psp->dtm_context.context.initialized = false;
1797
1798         return ret;
1799 }
1800 // DTM end
1801
1802 // RAP start
1803 static int psp_rap_initialize(struct psp_context *psp)
1804 {
1805         int ret;
1806         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1807
1808         /*
1809          * TODO: bypass the initialize in sriov for now
1810          */
1811         if (amdgpu_sriov_vf(psp->adev))
1812                 return 0;
1813
1814         if (!psp->rap_context.context.bin_desc.size_bytes ||
1815             !psp->rap_context.context.bin_desc.start_addr) {
1816                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1817                 return 0;
1818         }
1819
1820         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1821         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1822
1823         if (!psp->rap_context.context.initialized) {
1824                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1825                 if (ret)
1826                         return ret;
1827         }
1828
1829         ret = psp_ta_load(psp, &psp->rap_context.context);
1830         if (!ret) {
1831                 psp->rap_context.context.initialized = true;
1832                 mutex_init(&psp->rap_context.mutex);
1833         } else
1834                 return ret;
1835
1836         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1837         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1838                 psp_rap_terminate(psp);
1839                 /* free rap shared memory */
1840                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1841
1842                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1843                          ret, status);
1844
1845                 return ret;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static int psp_rap_terminate(struct psp_context *psp)
1852 {
1853         int ret;
1854
1855         if (!psp->rap_context.context.initialized)
1856                 return 0;
1857
1858         ret = psp_ta_unload(psp, &psp->rap_context.context);
1859
1860         psp->rap_context.context.initialized = false;
1861
1862         return ret;
1863 }
1864
1865 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1866 {
1867         struct ta_rap_shared_memory *rap_cmd;
1868         int ret = 0;
1869
1870         if (!psp->rap_context.context.initialized)
1871                 return 0;
1872
1873         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1874             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1875                 return -EINVAL;
1876
1877         mutex_lock(&psp->rap_context.mutex);
1878
1879         rap_cmd = (struct ta_rap_shared_memory *)
1880                   psp->rap_context.context.mem_context.shared_buf;
1881         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1882
1883         rap_cmd->cmd_id = ta_cmd_id;
1884         rap_cmd->validation_method_id = METHOD_A;
1885
1886         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1887         if (ret)
1888                 goto out_unlock;
1889
1890         if (status)
1891                 *status = rap_cmd->rap_status;
1892
1893 out_unlock:
1894         mutex_unlock(&psp->rap_context.mutex);
1895
1896         return ret;
1897 }
1898 // RAP end
1899
1900 /* securedisplay start */
1901 static int psp_securedisplay_initialize(struct psp_context *psp)
1902 {
1903         int ret;
1904         struct securedisplay_cmd *securedisplay_cmd;
1905
1906         /*
1907          * TODO: bypass the initialize in sriov for now
1908          */
1909         if (amdgpu_sriov_vf(psp->adev))
1910                 return 0;
1911
1912         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1913             !psp->securedisplay_context.context.bin_desc.start_addr) {
1914                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1915                 return 0;
1916         }
1917
1918         psp->securedisplay_context.context.mem_context.shared_mem_size =
1919                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1920         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1921
1922         if (!psp->securedisplay_context.context.initialized) {
1923                 ret = psp_ta_init_shared_buf(psp,
1924                                              &psp->securedisplay_context.context.mem_context);
1925                 if (ret)
1926                         return ret;
1927         }
1928
1929         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1930         if (!ret) {
1931                 psp->securedisplay_context.context.initialized = true;
1932                 mutex_init(&psp->securedisplay_context.mutex);
1933         } else
1934                 return ret;
1935
1936         mutex_lock(&psp->securedisplay_context.mutex);
1937
1938         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1939                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1940
1941         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1942
1943         mutex_unlock(&psp->securedisplay_context.mutex);
1944
1945         if (ret) {
1946                 psp_securedisplay_terminate(psp);
1947                 /* free securedisplay shared memory */
1948                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1949                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1950                 return -EINVAL;
1951         }
1952
1953         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1954                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1955                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1956                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1957         }
1958
1959         return 0;
1960 }
1961
1962 static int psp_securedisplay_terminate(struct psp_context *psp)
1963 {
1964         int ret;
1965
1966         /*
1967          * TODO:bypass the terminate in sriov for now
1968          */
1969         if (amdgpu_sriov_vf(psp->adev))
1970                 return 0;
1971
1972         if (!psp->securedisplay_context.context.initialized)
1973                 return 0;
1974
1975         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1976
1977         psp->securedisplay_context.context.initialized = false;
1978
1979         return ret;
1980 }
1981
1982 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1983 {
1984         int ret;
1985
1986         if (!psp->securedisplay_context.context.initialized)
1987                 return -EINVAL;
1988
1989         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1990             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1991                 return -EINVAL;
1992
1993         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1994
1995         return ret;
1996 }
1997 /* SECUREDISPLAY end */
1998
1999 static int psp_hw_start(struct psp_context *psp)
2000 {
2001         struct amdgpu_device *adev = psp->adev;
2002         int ret;
2003
2004         if (!amdgpu_sriov_vf(adev)) {
2005                 if ((is_psp_fw_valid(psp->kdb)) &&
2006                     (psp->funcs->bootloader_load_kdb != NULL)) {
2007                         ret = psp_bootloader_load_kdb(psp);
2008                         if (ret) {
2009                                 DRM_ERROR("PSP load kdb failed!\n");
2010                                 return ret;
2011                         }
2012                 }
2013
2014                 if ((is_psp_fw_valid(psp->spl)) &&
2015                     (psp->funcs->bootloader_load_spl != NULL)) {
2016                         ret = psp_bootloader_load_spl(psp);
2017                         if (ret) {
2018                                 DRM_ERROR("PSP load spl failed!\n");
2019                                 return ret;
2020                         }
2021                 }
2022
2023                 if ((is_psp_fw_valid(psp->sys)) &&
2024                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2025                         ret = psp_bootloader_load_sysdrv(psp);
2026                         if (ret) {
2027                                 DRM_ERROR("PSP load sys drv failed!\n");
2028                                 return ret;
2029                         }
2030                 }
2031
2032                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2033                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2034                         ret = psp_bootloader_load_soc_drv(psp);
2035                         if (ret) {
2036                                 DRM_ERROR("PSP load soc drv failed!\n");
2037                                 return ret;
2038                         }
2039                 }
2040
2041                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2042                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2043                         ret = psp_bootloader_load_intf_drv(psp);
2044                         if (ret) {
2045                                 DRM_ERROR("PSP load intf drv failed!\n");
2046                                 return ret;
2047                         }
2048                 }
2049
2050                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2051                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2052                         ret = psp_bootloader_load_dbg_drv(psp);
2053                         if (ret) {
2054                                 DRM_ERROR("PSP load dbg drv failed!\n");
2055                                 return ret;
2056                         }
2057                 }
2058
2059                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2060                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2061                         ret = psp_bootloader_load_ras_drv(psp);
2062                         if (ret) {
2063                                 DRM_ERROR("PSP load ras_drv failed!\n");
2064                                 return ret;
2065                         }
2066                 }
2067
2068                 if ((is_psp_fw_valid(psp->sos)) &&
2069                     (psp->funcs->bootloader_load_sos != NULL)) {
2070                         ret = psp_bootloader_load_sos(psp);
2071                         if (ret) {
2072                                 DRM_ERROR("PSP load sos failed!\n");
2073                                 return ret;
2074                         }
2075                 }
2076         }
2077
2078         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2079         if (ret) {
2080                 DRM_ERROR("PSP create ring failed!\n");
2081                 return ret;
2082         }
2083
2084         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2085                 goto skip_pin_bo;
2086
2087         ret = psp_tmr_init(psp);
2088         if (ret) {
2089                 DRM_ERROR("PSP tmr init failed!\n");
2090                 return ret;
2091         }
2092
2093 skip_pin_bo:
2094         /*
2095          * For ASICs with DF Cstate management centralized
2096          * to PMFW, TMR setup should be performed after PMFW
2097          * loaded and before other non-psp firmware loaded.
2098          */
2099         if (psp->pmfw_centralized_cstate_management) {
2100                 ret = psp_load_smu_fw(psp);
2101                 if (ret)
2102                         return ret;
2103         }
2104
2105         ret = psp_tmr_load(psp);
2106         if (ret) {
2107                 DRM_ERROR("PSP load tmr failed!\n");
2108                 return ret;
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2115                            enum psp_gfx_fw_type *type)
2116 {
2117         switch (ucode->ucode_id) {
2118         case AMDGPU_UCODE_ID_CAP:
2119                 *type = GFX_FW_TYPE_CAP;
2120                 break;
2121         case AMDGPU_UCODE_ID_SDMA0:
2122                 *type = GFX_FW_TYPE_SDMA0;
2123                 break;
2124         case AMDGPU_UCODE_ID_SDMA1:
2125                 *type = GFX_FW_TYPE_SDMA1;
2126                 break;
2127         case AMDGPU_UCODE_ID_SDMA2:
2128                 *type = GFX_FW_TYPE_SDMA2;
2129                 break;
2130         case AMDGPU_UCODE_ID_SDMA3:
2131                 *type = GFX_FW_TYPE_SDMA3;
2132                 break;
2133         case AMDGPU_UCODE_ID_SDMA4:
2134                 *type = GFX_FW_TYPE_SDMA4;
2135                 break;
2136         case AMDGPU_UCODE_ID_SDMA5:
2137                 *type = GFX_FW_TYPE_SDMA5;
2138                 break;
2139         case AMDGPU_UCODE_ID_SDMA6:
2140                 *type = GFX_FW_TYPE_SDMA6;
2141                 break;
2142         case AMDGPU_UCODE_ID_SDMA7:
2143                 *type = GFX_FW_TYPE_SDMA7;
2144                 break;
2145         case AMDGPU_UCODE_ID_CP_MES:
2146                 *type = GFX_FW_TYPE_CP_MES;
2147                 break;
2148         case AMDGPU_UCODE_ID_CP_MES_DATA:
2149                 *type = GFX_FW_TYPE_MES_STACK;
2150                 break;
2151         case AMDGPU_UCODE_ID_CP_MES1:
2152                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2153                 break;
2154         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2155                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2156                 break;
2157         case AMDGPU_UCODE_ID_CP_CE:
2158                 *type = GFX_FW_TYPE_CP_CE;
2159                 break;
2160         case AMDGPU_UCODE_ID_CP_PFP:
2161                 *type = GFX_FW_TYPE_CP_PFP;
2162                 break;
2163         case AMDGPU_UCODE_ID_CP_ME:
2164                 *type = GFX_FW_TYPE_CP_ME;
2165                 break;
2166         case AMDGPU_UCODE_ID_CP_MEC1:
2167                 *type = GFX_FW_TYPE_CP_MEC;
2168                 break;
2169         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2170                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2171                 break;
2172         case AMDGPU_UCODE_ID_CP_MEC2:
2173                 *type = GFX_FW_TYPE_CP_MEC;
2174                 break;
2175         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2176                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2177                 break;
2178         case AMDGPU_UCODE_ID_RLC_P:
2179                 *type = GFX_FW_TYPE_RLC_P;
2180                 break;
2181         case AMDGPU_UCODE_ID_RLC_V:
2182                 *type = GFX_FW_TYPE_RLC_V;
2183                 break;
2184         case AMDGPU_UCODE_ID_RLC_G:
2185                 *type = GFX_FW_TYPE_RLC_G;
2186                 break;
2187         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2188                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2189                 break;
2190         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2191                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2192                 break;
2193         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2194                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2195                 break;
2196         case AMDGPU_UCODE_ID_RLC_IRAM:
2197                 *type = GFX_FW_TYPE_RLC_IRAM;
2198                 break;
2199         case AMDGPU_UCODE_ID_RLC_DRAM:
2200                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2201                 break;
2202         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2203                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2204                 break;
2205         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2206                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2207                 break;
2208         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2209                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2210                 break;
2211         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2212                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2213                 break;
2214         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2215                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2216                 break;
2217         case AMDGPU_UCODE_ID_SMC:
2218                 *type = GFX_FW_TYPE_SMU;
2219                 break;
2220         case AMDGPU_UCODE_ID_PPTABLE:
2221                 *type = GFX_FW_TYPE_PPTABLE;
2222                 break;
2223         case AMDGPU_UCODE_ID_UVD:
2224                 *type = GFX_FW_TYPE_UVD;
2225                 break;
2226         case AMDGPU_UCODE_ID_UVD1:
2227                 *type = GFX_FW_TYPE_UVD1;
2228                 break;
2229         case AMDGPU_UCODE_ID_VCE:
2230                 *type = GFX_FW_TYPE_VCE;
2231                 break;
2232         case AMDGPU_UCODE_ID_VCN:
2233                 *type = GFX_FW_TYPE_VCN;
2234                 break;
2235         case AMDGPU_UCODE_ID_VCN1:
2236                 *type = GFX_FW_TYPE_VCN1;
2237                 break;
2238         case AMDGPU_UCODE_ID_DMCU_ERAM:
2239                 *type = GFX_FW_TYPE_DMCU_ERAM;
2240                 break;
2241         case AMDGPU_UCODE_ID_DMCU_INTV:
2242                 *type = GFX_FW_TYPE_DMCU_ISR;
2243                 break;
2244         case AMDGPU_UCODE_ID_VCN0_RAM:
2245                 *type = GFX_FW_TYPE_VCN0_RAM;
2246                 break;
2247         case AMDGPU_UCODE_ID_VCN1_RAM:
2248                 *type = GFX_FW_TYPE_VCN1_RAM;
2249                 break;
2250         case AMDGPU_UCODE_ID_DMCUB:
2251                 *type = GFX_FW_TYPE_DMUB;
2252                 break;
2253         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2254                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2255                 break;
2256         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2257                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2258                 break;
2259         case AMDGPU_UCODE_ID_IMU_I:
2260                 *type = GFX_FW_TYPE_IMU_I;
2261                 break;
2262         case AMDGPU_UCODE_ID_IMU_D:
2263                 *type = GFX_FW_TYPE_IMU_D;
2264                 break;
2265         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2266                 *type = GFX_FW_TYPE_RS64_PFP;
2267                 break;
2268         case AMDGPU_UCODE_ID_CP_RS64_ME:
2269                 *type = GFX_FW_TYPE_RS64_ME;
2270                 break;
2271         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2272                 *type = GFX_FW_TYPE_RS64_MEC;
2273                 break;
2274         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2275                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2276                 break;
2277         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2278                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2279                 break;
2280         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2281                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2282                 break;
2283         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2284                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2285                 break;
2286         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2287                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2288                 break;
2289         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2290                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2291                 break;
2292         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2293                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2294                 break;
2295         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2296                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2297                 break;
2298         case AMDGPU_UCODE_ID_MAXIMUM:
2299         default:
2300                 return -EINVAL;
2301         }
2302
2303         return 0;
2304 }
2305
2306 static void psp_print_fw_hdr(struct psp_context *psp,
2307                              struct amdgpu_firmware_info *ucode)
2308 {
2309         struct amdgpu_device *adev = psp->adev;
2310         struct common_firmware_header *hdr;
2311
2312         switch (ucode->ucode_id) {
2313         case AMDGPU_UCODE_ID_SDMA0:
2314         case AMDGPU_UCODE_ID_SDMA1:
2315         case AMDGPU_UCODE_ID_SDMA2:
2316         case AMDGPU_UCODE_ID_SDMA3:
2317         case AMDGPU_UCODE_ID_SDMA4:
2318         case AMDGPU_UCODE_ID_SDMA5:
2319         case AMDGPU_UCODE_ID_SDMA6:
2320         case AMDGPU_UCODE_ID_SDMA7:
2321                 hdr = (struct common_firmware_header *)
2322                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2323                 amdgpu_ucode_print_sdma_hdr(hdr);
2324                 break;
2325         case AMDGPU_UCODE_ID_CP_CE:
2326                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2327                 amdgpu_ucode_print_gfx_hdr(hdr);
2328                 break;
2329         case AMDGPU_UCODE_ID_CP_PFP:
2330                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2331                 amdgpu_ucode_print_gfx_hdr(hdr);
2332                 break;
2333         case AMDGPU_UCODE_ID_CP_ME:
2334                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2335                 amdgpu_ucode_print_gfx_hdr(hdr);
2336                 break;
2337         case AMDGPU_UCODE_ID_CP_MEC1:
2338                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2339                 amdgpu_ucode_print_gfx_hdr(hdr);
2340                 break;
2341         case AMDGPU_UCODE_ID_RLC_G:
2342                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2343                 amdgpu_ucode_print_rlc_hdr(hdr);
2344                 break;
2345         case AMDGPU_UCODE_ID_SMC:
2346                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2347                 amdgpu_ucode_print_smc_hdr(hdr);
2348                 break;
2349         default:
2350                 break;
2351         }
2352 }
2353
2354 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2355                                        struct psp_gfx_cmd_resp *cmd)
2356 {
2357         int ret;
2358         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2359
2360         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2361         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2362         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2363         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2364
2365         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2366         if (ret)
2367                 DRM_ERROR("Unknown firmware type\n");
2368
2369         return ret;
2370 }
2371
2372 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2373                                   struct amdgpu_firmware_info *ucode)
2374 {
2375         int ret = 0;
2376         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2377
2378         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2379         if (!ret) {
2380                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2381                                          psp->fence_buf_mc_addr);
2382         }
2383
2384         release_psp_cmd_buf(psp);
2385
2386         return ret;
2387 }
2388
2389 static int psp_load_smu_fw(struct psp_context *psp)
2390 {
2391         int ret;
2392         struct amdgpu_device *adev = psp->adev;
2393         struct amdgpu_firmware_info *ucode =
2394                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2395         struct amdgpu_ras *ras = psp->ras_context.ras;
2396
2397         /*
2398          * Skip SMU FW reloading in case of using BACO for runpm only,
2399          * as SMU is always alive.
2400          */
2401         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2402                 return 0;
2403
2404         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2405                 return 0;
2406
2407         if ((amdgpu_in_reset(adev) &&
2408              ras && adev->ras_enabled &&
2409              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2410               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2411                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2412                 if (ret) {
2413                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2414                 }
2415         }
2416
2417         ret = psp_execute_non_psp_fw_load(psp, ucode);
2418
2419         if (ret)
2420                 DRM_ERROR("PSP load smu failed!\n");
2421
2422         return ret;
2423 }
2424
2425 static bool fw_load_skip_check(struct psp_context *psp,
2426                                struct amdgpu_firmware_info *ucode)
2427 {
2428         if (!ucode->fw || !ucode->ucode_size)
2429                 return true;
2430
2431         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2432             (psp_smu_reload_quirk(psp) ||
2433              psp->autoload_supported ||
2434              psp->pmfw_centralized_cstate_management))
2435                 return true;
2436
2437         if (amdgpu_sriov_vf(psp->adev) &&
2438             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2439                 return true;
2440
2441         if (psp->autoload_supported &&
2442             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2443              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2444                 /* skip mec JT when autoload is enabled */
2445                 return true;
2446
2447         return false;
2448 }
2449
2450 int psp_load_fw_list(struct psp_context *psp,
2451                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2452 {
2453         int ret = 0, i;
2454         struct amdgpu_firmware_info *ucode;
2455
2456         for (i = 0; i < ucode_count; ++i) {
2457                 ucode = ucode_list[i];
2458                 psp_print_fw_hdr(psp, ucode);
2459                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2460                 if (ret)
2461                         return ret;
2462         }
2463         return ret;
2464 }
2465
2466 static int psp_load_non_psp_fw(struct psp_context *psp)
2467 {
2468         int i, ret;
2469         struct amdgpu_firmware_info *ucode;
2470         struct amdgpu_device *adev = psp->adev;
2471
2472         if (psp->autoload_supported &&
2473             !psp->pmfw_centralized_cstate_management) {
2474                 ret = psp_load_smu_fw(psp);
2475                 if (ret)
2476                         return ret;
2477         }
2478
2479         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2480                 ucode = &adev->firmware.ucode[i];
2481
2482                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2483                     !fw_load_skip_check(psp, ucode)) {
2484                         ret = psp_load_smu_fw(psp);
2485                         if (ret)
2486                                 return ret;
2487                         continue;
2488                 }
2489
2490                 if (fw_load_skip_check(psp, ucode))
2491                         continue;
2492
2493                 if (psp->autoload_supported &&
2494                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2495                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2496                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2497                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2498                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2499                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2500                         /* PSP only receive one SDMA fw for sienna_cichlid,
2501                          * as all four sdma fw are same */
2502                         continue;
2503
2504                 psp_print_fw_hdr(psp, ucode);
2505
2506                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2507                 if (ret)
2508                         return ret;
2509
2510                 /* Start rlc autoload after psp recieved all the gfx firmware */
2511                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2512                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2513                         ret = psp_rlc_autoload_start(psp);
2514                         if (ret) {
2515                                 DRM_ERROR("Failed to start rlc autoload\n");
2516                                 return ret;
2517                         }
2518                 }
2519         }
2520
2521         return 0;
2522 }
2523
2524 static int psp_load_fw(struct amdgpu_device *adev)
2525 {
2526         int ret;
2527         struct psp_context *psp = &adev->psp;
2528
2529         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2530                 /* should not destroy ring, only stop */
2531                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2532         } else {
2533                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2534
2535                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2536                 if (ret) {
2537                         DRM_ERROR("PSP ring init failed!\n");
2538                         goto failed;
2539                 }
2540         }
2541
2542         ret = psp_hw_start(psp);
2543         if (ret)
2544                 goto failed;
2545
2546         ret = psp_load_non_psp_fw(psp);
2547         if (ret)
2548                 goto failed1;
2549
2550         ret = psp_asd_initialize(psp);
2551         if (ret) {
2552                 DRM_ERROR("PSP load asd failed!\n");
2553                 goto failed1;
2554         }
2555
2556         ret = psp_rl_load(adev);
2557         if (ret) {
2558                 DRM_ERROR("PSP load RL failed!\n");
2559                 goto failed1;
2560         }
2561
2562         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2563                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2564                         ret = psp_xgmi_initialize(psp, false, true);
2565                         /* Warning the XGMI seesion initialize failure
2566                         * Instead of stop driver initialization
2567                         */
2568                         if (ret)
2569                                 dev_err(psp->adev->dev,
2570                                         "XGMI: Failed to initialize XGMI session\n");
2571                 }
2572         }
2573
2574         if (psp->ta_fw) {
2575                 ret = psp_ras_initialize(psp);
2576                 if (ret)
2577                         dev_err(psp->adev->dev,
2578                                         "RAS: Failed to initialize RAS\n");
2579
2580                 ret = psp_hdcp_initialize(psp);
2581                 if (ret)
2582                         dev_err(psp->adev->dev,
2583                                 "HDCP: Failed to initialize HDCP\n");
2584
2585                 ret = psp_dtm_initialize(psp);
2586                 if (ret)
2587                         dev_err(psp->adev->dev,
2588                                 "DTM: Failed to initialize DTM\n");
2589
2590                 ret = psp_rap_initialize(psp);
2591                 if (ret)
2592                         dev_err(psp->adev->dev,
2593                                 "RAP: Failed to initialize RAP\n");
2594
2595                 ret = psp_securedisplay_initialize(psp);
2596                 if (ret)
2597                         dev_err(psp->adev->dev,
2598                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2599         }
2600
2601         return 0;
2602
2603 failed1:
2604         psp_free_shared_bufs(psp);
2605 failed:
2606         /*
2607          * all cleanup jobs (xgmi terminate, ras terminate,
2608          * ring destroy, cmd/fence/fw buffers destory,
2609          * psp->cmd destory) are delayed to psp_hw_fini
2610          */
2611         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2612         return ret;
2613 }
2614
2615 static int psp_hw_init(void *handle)
2616 {
2617         int ret;
2618         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2619
2620         mutex_lock(&adev->firmware.mutex);
2621         /*
2622          * This sequence is just used on hw_init only once, no need on
2623          * resume.
2624          */
2625         ret = amdgpu_ucode_init_bo(adev);
2626         if (ret)
2627                 goto failed;
2628
2629         ret = psp_load_fw(adev);
2630         if (ret) {
2631                 DRM_ERROR("PSP firmware loading failed\n");
2632                 goto failed;
2633         }
2634
2635         mutex_unlock(&adev->firmware.mutex);
2636         return 0;
2637
2638 failed:
2639         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2640         mutex_unlock(&adev->firmware.mutex);
2641         return -EINVAL;
2642 }
2643
2644 static int psp_hw_fini(void *handle)
2645 {
2646         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2647         struct psp_context *psp = &adev->psp;
2648
2649         if (psp->ta_fw) {
2650                 psp_ras_terminate(psp);
2651                 psp_securedisplay_terminate(psp);
2652                 psp_rap_terminate(psp);
2653                 psp_dtm_terminate(psp);
2654                 psp_hdcp_terminate(psp);
2655
2656                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2657                         psp_xgmi_terminate(psp);
2658         }
2659
2660         psp_asd_terminate(psp);
2661         psp_tmr_terminate(psp);
2662
2663         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2664
2665         psp_free_shared_bufs(psp);
2666
2667         return 0;
2668 }
2669
2670 static int psp_suspend(void *handle)
2671 {
2672         int ret = 0;
2673         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2674         struct psp_context *psp = &adev->psp;
2675
2676         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2677             psp->xgmi_context.context.initialized) {
2678                 ret = psp_xgmi_terminate(psp);
2679                 if (ret) {
2680                         DRM_ERROR("Failed to terminate xgmi ta\n");
2681                         goto out;
2682                 }
2683         }
2684
2685         if (psp->ta_fw) {
2686                 ret = psp_ras_terminate(psp);
2687                 if (ret) {
2688                         DRM_ERROR("Failed to terminate ras ta\n");
2689                         goto out;
2690                 }
2691                 ret = psp_hdcp_terminate(psp);
2692                 if (ret) {
2693                         DRM_ERROR("Failed to terminate hdcp ta\n");
2694                         goto out;
2695                 }
2696                 ret = psp_dtm_terminate(psp);
2697                 if (ret) {
2698                         DRM_ERROR("Failed to terminate dtm ta\n");
2699                         goto out;
2700                 }
2701                 ret = psp_rap_terminate(psp);
2702                 if (ret) {
2703                         DRM_ERROR("Failed to terminate rap ta\n");
2704                         goto out;
2705                 }
2706                 ret = psp_securedisplay_terminate(psp);
2707                 if (ret) {
2708                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2709                         goto out;
2710                 }
2711         }
2712
2713         ret = psp_asd_terminate(psp);
2714         if (ret) {
2715                 DRM_ERROR("Failed to terminate asd\n");
2716                 goto out;
2717         }
2718
2719         ret = psp_tmr_terminate(psp);
2720         if (ret) {
2721                 DRM_ERROR("Failed to terminate tmr\n");
2722                 goto out;
2723         }
2724
2725         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2726         if (ret) {
2727                 DRM_ERROR("PSP ring stop failed\n");
2728         }
2729
2730 out:
2731         return ret;
2732 }
2733
2734 static int psp_resume(void *handle)
2735 {
2736         int ret;
2737         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2738         struct psp_context *psp = &adev->psp;
2739
2740         DRM_INFO("PSP is resuming...\n");
2741
2742         if (psp->mem_train_ctx.enable_mem_training) {
2743                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2744                 if (ret) {
2745                         DRM_ERROR("Failed to process memory training!\n");
2746                         return ret;
2747                 }
2748         }
2749
2750         mutex_lock(&adev->firmware.mutex);
2751
2752         ret = psp_hw_start(psp);
2753         if (ret)
2754                 goto failed;
2755
2756         ret = psp_load_non_psp_fw(psp);
2757         if (ret)
2758                 goto failed;
2759
2760         ret = psp_asd_initialize(psp);
2761         if (ret) {
2762                 DRM_ERROR("PSP load asd failed!\n");
2763                 goto failed;
2764         }
2765
2766         ret = psp_rl_load(adev);
2767         if (ret) {
2768                 dev_err(adev->dev, "PSP load RL failed!\n");
2769                 goto failed;
2770         }
2771
2772         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2773                 ret = psp_xgmi_initialize(psp, false, true);
2774                 /* Warning the XGMI seesion initialize failure
2775                  * Instead of stop driver initialization
2776                  */
2777                 if (ret)
2778                         dev_err(psp->adev->dev,
2779                                 "XGMI: Failed to initialize XGMI session\n");
2780         }
2781
2782         if (psp->ta_fw) {
2783                 ret = psp_ras_initialize(psp);
2784                 if (ret)
2785                         dev_err(psp->adev->dev,
2786                                         "RAS: Failed to initialize RAS\n");
2787
2788                 ret = psp_hdcp_initialize(psp);
2789                 if (ret)
2790                         dev_err(psp->adev->dev,
2791                                 "HDCP: Failed to initialize HDCP\n");
2792
2793                 ret = psp_dtm_initialize(psp);
2794                 if (ret)
2795                         dev_err(psp->adev->dev,
2796                                 "DTM: Failed to initialize DTM\n");
2797
2798                 ret = psp_rap_initialize(psp);
2799                 if (ret)
2800                         dev_err(psp->adev->dev,
2801                                 "RAP: Failed to initialize RAP\n");
2802
2803                 ret = psp_securedisplay_initialize(psp);
2804                 if (ret)
2805                         dev_err(psp->adev->dev,
2806                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2807         }
2808
2809         mutex_unlock(&adev->firmware.mutex);
2810
2811         return 0;
2812
2813 failed:
2814         DRM_ERROR("PSP resume failed\n");
2815         mutex_unlock(&adev->firmware.mutex);
2816         return ret;
2817 }
2818
2819 int psp_gpu_reset(struct amdgpu_device *adev)
2820 {
2821         int ret;
2822
2823         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2824                 return 0;
2825
2826         mutex_lock(&adev->psp.mutex);
2827         ret = psp_mode1_reset(&adev->psp);
2828         mutex_unlock(&adev->psp.mutex);
2829
2830         return ret;
2831 }
2832
2833 int psp_rlc_autoload_start(struct psp_context *psp)
2834 {
2835         int ret;
2836         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2837
2838         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2839
2840         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2841                                  psp->fence_buf_mc_addr);
2842
2843         release_psp_cmd_buf(psp);
2844
2845         return ret;
2846 }
2847
2848 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2849                         uint64_t cmd_gpu_addr, int cmd_size)
2850 {
2851         struct amdgpu_firmware_info ucode = {0};
2852
2853         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2854                 AMDGPU_UCODE_ID_VCN0_RAM;
2855         ucode.mc_addr = cmd_gpu_addr;
2856         ucode.ucode_size = cmd_size;
2857
2858         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2859 }
2860
2861 int psp_ring_cmd_submit(struct psp_context *psp,
2862                         uint64_t cmd_buf_mc_addr,
2863                         uint64_t fence_mc_addr,
2864                         int index)
2865 {
2866         unsigned int psp_write_ptr_reg = 0;
2867         struct psp_gfx_rb_frame *write_frame;
2868         struct psp_ring *ring = &psp->km_ring;
2869         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2870         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2871                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2872         struct amdgpu_device *adev = psp->adev;
2873         uint32_t ring_size_dw = ring->ring_size / 4;
2874         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2875
2876         /* KM (GPCOM) prepare write pointer */
2877         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2878
2879         /* Update KM RB frame pointer to new frame */
2880         /* write_frame ptr increments by size of rb_frame in bytes */
2881         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2882         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2883                 write_frame = ring_buffer_start;
2884         else
2885                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2886         /* Check invalid write_frame ptr address */
2887         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2888                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2889                           ring_buffer_start, ring_buffer_end, write_frame);
2890                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2891                 return -EINVAL;
2892         }
2893
2894         /* Initialize KM RB frame */
2895         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2896
2897         /* Update KM RB frame */
2898         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2899         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2900         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2901         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2902         write_frame->fence_value = index;
2903         amdgpu_device_flush_hdp(adev, NULL);
2904
2905         /* Update the write Pointer in DWORDs */
2906         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2907         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2908         return 0;
2909 }
2910
2911 int psp_init_asd_microcode(struct psp_context *psp,
2912                            const char *chip_name)
2913 {
2914         struct amdgpu_device *adev = psp->adev;
2915         char fw_name[PSP_FW_NAME_LEN];
2916         const struct psp_firmware_header_v1_0 *asd_hdr;
2917         int err = 0;
2918
2919         if (!chip_name) {
2920                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2921                 return -EINVAL;
2922         }
2923
2924         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2925         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2926         if (err)
2927                 goto out;
2928
2929         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2930         if (err)
2931                 goto out;
2932
2933         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2934         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2935         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2936         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2937         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2938                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2939         return 0;
2940 out:
2941         dev_err(adev->dev, "fail to initialize asd microcode\n");
2942         release_firmware(adev->psp.asd_fw);
2943         adev->psp.asd_fw = NULL;
2944         return err;
2945 }
2946
2947 int psp_init_toc_microcode(struct psp_context *psp,
2948                            const char *chip_name)
2949 {
2950         struct amdgpu_device *adev = psp->adev;
2951         char fw_name[PSP_FW_NAME_LEN];
2952         const struct psp_firmware_header_v1_0 *toc_hdr;
2953         int err = 0;
2954
2955         if (!chip_name) {
2956                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2957                 return -EINVAL;
2958         }
2959
2960         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2961         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2962         if (err)
2963                 goto out;
2964
2965         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2966         if (err)
2967                 goto out;
2968
2969         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2970         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2971         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2972         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2973         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2974                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2975         return 0;
2976 out:
2977         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2978         release_firmware(adev->psp.toc_fw);
2979         adev->psp.toc_fw = NULL;
2980         return err;
2981 }
2982
2983 static int parse_sos_bin_descriptor(struct psp_context *psp,
2984                                    const struct psp_fw_bin_desc *desc,
2985                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2986 {
2987         uint8_t *ucode_start_addr  = NULL;
2988
2989         if (!psp || !desc || !sos_hdr)
2990                 return -EINVAL;
2991
2992         ucode_start_addr  = (uint8_t *)sos_hdr +
2993                             le32_to_cpu(desc->offset_bytes) +
2994                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2995
2996         switch (desc->fw_type) {
2997         case PSP_FW_TYPE_PSP_SOS:
2998                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2999                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3000                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3001                 psp->sos.start_addr        = ucode_start_addr;
3002                 break;
3003         case PSP_FW_TYPE_PSP_SYS_DRV:
3004                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3005                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3006                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3007                 psp->sys.start_addr        = ucode_start_addr;
3008                 break;
3009         case PSP_FW_TYPE_PSP_KDB:
3010                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3011                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3012                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3013                 psp->kdb.start_addr        = ucode_start_addr;
3014                 break;
3015         case PSP_FW_TYPE_PSP_TOC:
3016                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3017                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3018                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3019                 psp->toc.start_addr        = ucode_start_addr;
3020                 break;
3021         case PSP_FW_TYPE_PSP_SPL:
3022                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3023                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3024                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3025                 psp->spl.start_addr        = ucode_start_addr;
3026                 break;
3027         case PSP_FW_TYPE_PSP_RL:
3028                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3029                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3030                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3031                 psp->rl.start_addr         = ucode_start_addr;
3032                 break;
3033         case PSP_FW_TYPE_PSP_SOC_DRV:
3034                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3035                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3036                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3037                 psp->soc_drv.start_addr         = ucode_start_addr;
3038                 break;
3039         case PSP_FW_TYPE_PSP_INTF_DRV:
3040                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3041                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3042                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3043                 psp->intf_drv.start_addr        = ucode_start_addr;
3044                 break;
3045         case PSP_FW_TYPE_PSP_DBG_DRV:
3046                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3047                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3048                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3049                 psp->dbg_drv.start_addr         = ucode_start_addr;
3050                 break;
3051         case PSP_FW_TYPE_PSP_RAS_DRV:
3052                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3053                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3054                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3055                 psp->ras_drv.start_addr         = ucode_start_addr;
3056                 break;
3057         default:
3058                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3059                 break;
3060         }
3061
3062         return 0;
3063 }
3064
3065 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3066 {
3067         const struct psp_firmware_header_v1_0 *sos_hdr;
3068         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3069         uint8_t *ucode_array_start_addr;
3070
3071         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3072         ucode_array_start_addr = (uint8_t *)sos_hdr +
3073                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3074
3075         if (adev->gmc.xgmi.connected_to_cpu ||
3076             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3077                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3078                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3079
3080                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3081                 adev->psp.sys.start_addr = ucode_array_start_addr;
3082
3083                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3084                 adev->psp.sos.start_addr = ucode_array_start_addr +
3085                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3086         } else {
3087                 /* Load alternate PSP SOS FW */
3088                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3089
3090                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3091                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3092
3093                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3094                 adev->psp.sys.start_addr = ucode_array_start_addr +
3095                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3096
3097                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3098                 adev->psp.sos.start_addr = ucode_array_start_addr +
3099                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3100         }
3101
3102         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3103                 dev_warn(adev->dev, "PSP SOS FW not available");
3104                 return -EINVAL;
3105         }
3106
3107         return 0;
3108 }
3109
3110 int psp_init_sos_microcode(struct psp_context *psp,
3111                            const char *chip_name)
3112 {
3113         struct amdgpu_device *adev = psp->adev;
3114         char fw_name[PSP_FW_NAME_LEN];
3115         const struct psp_firmware_header_v1_0 *sos_hdr;
3116         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3117         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3118         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3119         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3120         int err = 0;
3121         uint8_t *ucode_array_start_addr;
3122         int fw_index = 0;
3123
3124         if (!chip_name) {
3125                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3126                 return -EINVAL;
3127         }
3128
3129         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3130         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3131         if (err)
3132                 goto out;
3133
3134         err = amdgpu_ucode_validate(adev->psp.sos_fw);
3135         if (err)
3136                 goto out;
3137
3138         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3139         ucode_array_start_addr = (uint8_t *)sos_hdr +
3140                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3141         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3142
3143         switch (sos_hdr->header.header_version_major) {
3144         case 1:
3145                 err = psp_init_sos_base_fw(adev);
3146                 if (err)
3147                         goto out;
3148
3149                 if (sos_hdr->header.header_version_minor == 1) {
3150                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3151                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3152                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3153                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3154                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3155                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3156                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3157                 }
3158                 if (sos_hdr->header.header_version_minor == 2) {
3159                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3160                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3161                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3162                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3163                 }
3164                 if (sos_hdr->header.header_version_minor == 3) {
3165                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3166                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3167                         adev->psp.toc.start_addr = ucode_array_start_addr +
3168                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3169                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3170                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3171                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3172                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3173                         adev->psp.spl.start_addr = ucode_array_start_addr +
3174                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3175                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3176                         adev->psp.rl.start_addr = ucode_array_start_addr +
3177                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3178                 }
3179                 break;
3180         case 2:
3181                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3182
3183                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3184                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3185                         err = -EINVAL;
3186                         goto out;
3187                 }
3188
3189                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3190                         err = parse_sos_bin_descriptor(psp,
3191                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3192                                                        sos_hdr_v2_0);
3193                         if (err)
3194                                 goto out;
3195                 }
3196                 break;
3197         default:
3198                 dev_err(adev->dev,
3199                         "unsupported psp sos firmware\n");
3200                 err = -EINVAL;
3201                 goto out;
3202         }
3203
3204         return 0;
3205 out:
3206         dev_err(adev->dev,
3207                 "failed to init sos firmware\n");
3208         release_firmware(adev->psp.sos_fw);
3209         adev->psp.sos_fw = NULL;
3210
3211         return err;
3212 }
3213
3214 static int parse_ta_bin_descriptor(struct psp_context *psp,
3215                                    const struct psp_fw_bin_desc *desc,
3216                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3217 {
3218         uint8_t *ucode_start_addr  = NULL;
3219
3220         if (!psp || !desc || !ta_hdr)
3221                 return -EINVAL;
3222
3223         ucode_start_addr  = (uint8_t *)ta_hdr +
3224                             le32_to_cpu(desc->offset_bytes) +
3225                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3226
3227         switch (desc->fw_type) {
3228         case TA_FW_TYPE_PSP_ASD:
3229                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3230                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3231                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3232                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3233                 break;
3234         case TA_FW_TYPE_PSP_XGMI:
3235                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3236                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3237                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3238                 break;
3239         case TA_FW_TYPE_PSP_RAS:
3240                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3241                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3242                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3243                 break;
3244         case TA_FW_TYPE_PSP_HDCP:
3245                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3246                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3247                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3248                 break;
3249         case TA_FW_TYPE_PSP_DTM:
3250                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3251                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3252                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3253                 break;
3254         case TA_FW_TYPE_PSP_RAP:
3255                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3256                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3257                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3258                 break;
3259         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3260                 psp->securedisplay_context.context.bin_desc.fw_version =
3261                         le32_to_cpu(desc->fw_version);
3262                 psp->securedisplay_context.context.bin_desc.size_bytes =
3263                         le32_to_cpu(desc->size_bytes);
3264                 psp->securedisplay_context.context.bin_desc.start_addr =
3265                         ucode_start_addr;
3266                 break;
3267         default:
3268                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3269                 break;
3270         }
3271
3272         return 0;
3273 }
3274
3275 int psp_init_ta_microcode(struct psp_context *psp,
3276                           const char *chip_name)
3277 {
3278         struct amdgpu_device *adev = psp->adev;
3279         char fw_name[PSP_FW_NAME_LEN];
3280         const struct ta_firmware_header_v2_0 *ta_hdr;
3281         int err = 0;
3282         int ta_index = 0;
3283
3284         if (!chip_name) {
3285                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3286                 return -EINVAL;
3287         }
3288
3289         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3290         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3291         if (err)
3292                 goto out;
3293
3294         err = amdgpu_ucode_validate(adev->psp.ta_fw);
3295         if (err)
3296                 goto out;
3297
3298         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3299
3300         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3301                 dev_err(adev->dev, "unsupported TA header version\n");
3302                 err = -EINVAL;
3303                 goto out;
3304         }
3305
3306         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3307                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3308                 err = -EINVAL;
3309                 goto out;
3310         }
3311
3312         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3313                 err = parse_ta_bin_descriptor(psp,
3314                                               &ta_hdr->ta_fw_bin[ta_index],
3315                                               ta_hdr);
3316                 if (err)
3317                         goto out;
3318         }
3319
3320         return 0;
3321 out:
3322         dev_err(adev->dev, "fail to initialize ta microcode\n");
3323         release_firmware(adev->psp.ta_fw);
3324         adev->psp.ta_fw = NULL;
3325         return err;
3326 }
3327
3328 int psp_init_cap_microcode(struct psp_context *psp,
3329                           const char *chip_name)
3330 {
3331         struct amdgpu_device *adev = psp->adev;
3332         char fw_name[PSP_FW_NAME_LEN];
3333         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3334         struct amdgpu_firmware_info *info = NULL;
3335         int err = 0;
3336
3337         if (!chip_name) {
3338                 dev_err(adev->dev, "invalid chip name for cap microcode\n");
3339                 return -EINVAL;
3340         }
3341
3342         if (!amdgpu_sriov_vf(adev)) {
3343                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3344                 return -EINVAL;
3345         }
3346
3347         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3348         err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3349         if (err) {
3350                 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3351                 err = 0;
3352                 goto out;
3353         }
3354
3355         err = amdgpu_ucode_validate(adev->psp.cap_fw);
3356         if (err) {
3357                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3358                 goto out;
3359         }
3360
3361         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3362         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3363         info->fw = adev->psp.cap_fw;
3364         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3365                 adev->psp.cap_fw->data;
3366         adev->firmware.fw_size += ALIGN(
3367                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3368         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3369         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3370         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3371
3372         return 0;
3373
3374 out:
3375         release_firmware(adev->psp.cap_fw);
3376         adev->psp.cap_fw = NULL;
3377         return err;
3378 }
3379
3380 static int psp_set_clockgating_state(void *handle,
3381                                      enum amd_clockgating_state state)
3382 {
3383         return 0;
3384 }
3385
3386 static int psp_set_powergating_state(void *handle,
3387                                      enum amd_powergating_state state)
3388 {
3389         return 0;
3390 }
3391
3392 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3393                                          struct device_attribute *attr,
3394                                          char *buf)
3395 {
3396         struct drm_device *ddev = dev_get_drvdata(dev);
3397         struct amdgpu_device *adev = drm_to_adev(ddev);
3398         uint32_t fw_ver;
3399         int ret;
3400
3401         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3402                 DRM_INFO("PSP block is not ready yet.");
3403                 return -EBUSY;
3404         }
3405
3406         mutex_lock(&adev->psp.mutex);
3407         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3408         mutex_unlock(&adev->psp.mutex);
3409
3410         if (ret) {
3411                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3412                 return ret;
3413         }
3414
3415         return sysfs_emit(buf, "%x\n", fw_ver);
3416 }
3417
3418 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3419                                                        struct device_attribute *attr,
3420                                                        const char *buf,
3421                                                        size_t count)
3422 {
3423         struct drm_device *ddev = dev_get_drvdata(dev);
3424         struct amdgpu_device *adev = drm_to_adev(ddev);
3425         int ret, idx;
3426         char fw_name[100];
3427         const struct firmware *usbc_pd_fw;
3428         struct amdgpu_bo *fw_buf_bo = NULL;
3429         uint64_t fw_pri_mc_addr;
3430         void *fw_pri_cpu_addr;
3431
3432         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3433                 DRM_INFO("PSP block is not ready yet.");
3434                 return -EBUSY;
3435         }
3436
3437         if (!drm_dev_enter(ddev, &idx))
3438                 return -ENODEV;
3439
3440         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3441         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3442         if (ret)
3443                 goto fail;
3444
3445         /* LFB address which is aligned to 1MB boundary per PSP request */
3446         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3447                                                 AMDGPU_GEM_DOMAIN_VRAM,
3448                                                 &fw_buf_bo,
3449                                                 &fw_pri_mc_addr,
3450                                                 &fw_pri_cpu_addr);
3451         if (ret)
3452                 goto rel_buf;
3453
3454         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3455
3456         mutex_lock(&adev->psp.mutex);
3457         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3458         mutex_unlock(&adev->psp.mutex);
3459
3460         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3461
3462 rel_buf:
3463         release_firmware(usbc_pd_fw);
3464 fail:
3465         if (ret) {
3466                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3467                 count = ret;
3468         }
3469
3470         drm_dev_exit(idx);
3471         return count;
3472 }
3473
3474 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3475 {
3476         int idx;
3477
3478         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3479                 return;
3480
3481         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3482         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3483
3484         drm_dev_exit(idx);
3485 }
3486
3487 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3488                    psp_usbc_pd_fw_sysfs_read,
3489                    psp_usbc_pd_fw_sysfs_write);
3490
3491 int is_psp_fw_valid(struct psp_bin_desc bin)
3492 {
3493         return bin.size_bytes;
3494 }
3495
3496 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3497                                         struct bin_attribute *bin_attr,
3498                                         char *buffer, loff_t pos, size_t count)
3499 {
3500         struct device *dev = kobj_to_dev(kobj);
3501         struct drm_device *ddev = dev_get_drvdata(dev);
3502         struct amdgpu_device *adev = drm_to_adev(ddev);
3503
3504         adev->psp.vbflash_done = false;
3505
3506         /* Safeguard against memory drain */
3507         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3508                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3509                 kvfree(adev->psp.vbflash_tmp_buf);
3510                 adev->psp.vbflash_tmp_buf = NULL;
3511                 adev->psp.vbflash_image_size = 0;
3512                 return -ENOMEM;
3513         }
3514
3515         /* TODO Just allocate max for now and optimize to realloc later if needed */
3516         if (!adev->psp.vbflash_tmp_buf) {
3517                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3518                 if (!adev->psp.vbflash_tmp_buf)
3519                         return -ENOMEM;
3520         }
3521
3522         mutex_lock(&adev->psp.mutex);
3523         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3524         adev->psp.vbflash_image_size += count;
3525         mutex_unlock(&adev->psp.mutex);
3526
3527         dev_info(adev->dev, "VBIOS flash write PSP done");
3528
3529         return count;
3530 }
3531
3532 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3533                                        struct bin_attribute *bin_attr, char *buffer,
3534                                        loff_t pos, size_t count)
3535 {
3536         struct device *dev = kobj_to_dev(kobj);
3537         struct drm_device *ddev = dev_get_drvdata(dev);
3538         struct amdgpu_device *adev = drm_to_adev(ddev);
3539         struct amdgpu_bo *fw_buf_bo = NULL;
3540         uint64_t fw_pri_mc_addr;
3541         void *fw_pri_cpu_addr;
3542         int ret;
3543
3544         dev_info(adev->dev, "VBIOS flash to PSP started");
3545
3546         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3547                                         AMDGPU_GPU_PAGE_SIZE,
3548                                         AMDGPU_GEM_DOMAIN_VRAM,
3549                                         &fw_buf_bo,
3550                                         &fw_pri_mc_addr,
3551                                         &fw_pri_cpu_addr);
3552         if (ret)
3553                 goto rel_buf;
3554
3555         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3556
3557         mutex_lock(&adev->psp.mutex);
3558         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3559         mutex_unlock(&adev->psp.mutex);
3560
3561         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3562
3563 rel_buf:
3564         kvfree(adev->psp.vbflash_tmp_buf);
3565         adev->psp.vbflash_tmp_buf = NULL;
3566         adev->psp.vbflash_image_size = 0;
3567
3568         if (ret) {
3569                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3570                 return ret;
3571         }
3572
3573         dev_info(adev->dev, "VBIOS flash to PSP done");
3574         return 0;
3575 }
3576
3577 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3578                                          struct device_attribute *attr,
3579                                          char *buf)
3580 {
3581         struct drm_device *ddev = dev_get_drvdata(dev);
3582         struct amdgpu_device *adev = drm_to_adev(ddev);
3583         uint32_t vbflash_status;
3584
3585         vbflash_status = psp_vbflash_status(&adev->psp);
3586         if (!adev->psp.vbflash_done)
3587                 vbflash_status = 0;
3588         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3589                 vbflash_status = 1;
3590
3591         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3592 }
3593
3594 static const struct bin_attribute psp_vbflash_bin_attr = {
3595         .attr = {.name = "psp_vbflash", .mode = 0664},
3596         .size = 0,
3597         .write = amdgpu_psp_vbflash_write,
3598         .read = amdgpu_psp_vbflash_read,
3599 };
3600
3601 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3602
3603 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3604 {
3605         int ret = 0;
3606         struct psp_context *psp = &adev->psp;
3607
3608         if (amdgpu_sriov_vf(adev))
3609                 return -EINVAL;
3610
3611         switch (adev->ip_versions[MP0_HWIP][0]) {
3612         case IP_VERSION(13, 0, 0):
3613         case IP_VERSION(13, 0, 7):
3614                 if (!psp->adev) {
3615                         psp->adev = adev;
3616                         psp_v13_0_set_psp_funcs(psp);
3617                 }
3618                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3619                 if (ret)
3620                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3621                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3622                 if (ret)
3623                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3624                 return ret;
3625         default:
3626                 return 0;
3627         }
3628 }
3629
3630 const struct amd_ip_funcs psp_ip_funcs = {
3631         .name = "psp",
3632         .early_init = psp_early_init,
3633         .late_init = NULL,
3634         .sw_init = psp_sw_init,
3635         .sw_fini = psp_sw_fini,
3636         .hw_init = psp_hw_init,
3637         .hw_fini = psp_hw_fini,
3638         .suspend = psp_suspend,
3639         .resume = psp_resume,
3640         .is_idle = NULL,
3641         .check_soft_reset = NULL,
3642         .wait_for_idle = NULL,
3643         .soft_reset = NULL,
3644         .set_clockgating_state = psp_set_clockgating_state,
3645         .set_powergating_state = psp_set_powergating_state,
3646 };
3647
3648 static int psp_sysfs_init(struct amdgpu_device *adev)
3649 {
3650         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3651
3652         if (ret)
3653                 DRM_ERROR("Failed to create USBC PD FW control file!");
3654
3655         return ret;
3656 }
3657
3658 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3659 {
3660         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3661         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3662 }
3663
3664 static void psp_sysfs_fini(struct amdgpu_device *adev)
3665 {
3666         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3667 }
3668
3669 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3670 {
3671         .type = AMD_IP_BLOCK_TYPE_PSP,
3672         .major = 3,
3673         .minor = 1,
3674         .rev = 0,
3675         .funcs = &psp_ip_funcs,
3676 };
3677
3678 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3679 {
3680         .type = AMD_IP_BLOCK_TYPE_PSP,
3681         .major = 10,
3682         .minor = 0,
3683         .rev = 0,
3684         .funcs = &psp_ip_funcs,
3685 };
3686
3687 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3688 {
3689         .type = AMD_IP_BLOCK_TYPE_PSP,
3690         .major = 11,
3691         .minor = 0,
3692         .rev = 0,
3693         .funcs = &psp_ip_funcs,
3694 };
3695
3696 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3697         .type = AMD_IP_BLOCK_TYPE_PSP,
3698         .major = 11,
3699         .minor = 0,
3700         .rev = 8,
3701         .funcs = &psp_ip_funcs,
3702 };
3703
3704 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3705 {
3706         .type = AMD_IP_BLOCK_TYPE_PSP,
3707         .major = 12,
3708         .minor = 0,
3709         .rev = 0,
3710         .funcs = &psp_ip_funcs,
3711 };
3712
3713 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3714         .type = AMD_IP_BLOCK_TYPE_PSP,
3715         .major = 13,
3716         .minor = 0,
3717         .rev = 0,
3718         .funcs = &psp_ip_funcs,
3719 };
3720
3721 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3722         .type = AMD_IP_BLOCK_TYPE_PSP,
3723         .major = 13,
3724         .minor = 0,
3725         .rev = 4,
3726         .funcs = &psp_ip_funcs,
3727 };