drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_GFX_H__
  25 #define __AMDGPU_GFX_H__
  26
  27 /*
  28  * GFX stuff
  29  */
  30 #include "clearstate_defs.h"
  31 #include "amdgpu_ring.h"
  32 #include "amdgpu_rlc.h"
  33 #include "amdgpu_imu.h"
  34 #include "soc15.h"
  35 #include "amdgpu_ras.h"
  36 #include "amdgpu_ring_mux.h"
  37
  38 /* GFX current status */
  39 #define AMDGPU_GFX_NORMAL_MODE                  0x00000000L
  40 #define AMDGPU_GFX_SAFE_MODE                    0x00000001L
  41 #define AMDGPU_GFX_PG_DISABLED_MODE             0x00000002L
  42 #define AMDGPU_GFX_CG_DISABLED_MODE             0x00000004L
  43 #define AMDGPU_GFX_LBPW_DISABLED_MODE           0x00000008L
  44
  45 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
  46 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
  47
  48 enum amdgpu_gfx_pipe_priority {
  49         AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
  50         AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
  51 };
  52
  53 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
  54 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
  55
  56 struct amdgpu_mec {
  57         struct amdgpu_bo        *hpd_eop_obj;
  58         u64                     hpd_eop_gpu_addr;
  59         struct amdgpu_bo        *mec_fw_obj;
  60         u64                     mec_fw_gpu_addr;
  61         struct amdgpu_bo        *mec_fw_data_obj;
  62         u64                     mec_fw_data_gpu_addr;
  63
  64         u32 num_mec;
  65         u32 num_pipe_per_mec;
  66         u32 num_queue_per_pipe;
  67         void                    *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
  68
  69         /* These are the resources for which amdgpu takes ownership */
  70         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
  71 };
  72
  73 enum amdgpu_unmap_queues_action {
  74         PREEMPT_QUEUES = 0,
  75         RESET_QUEUES,
  76         DISABLE_PROCESS_QUEUES,
  77         PREEMPT_QUEUES_NO_UNMAP,
  78 };
  79
  80 struct kiq_pm4_funcs {
  81         /* Support ASIC-specific kiq pm4 packets*/
  82         void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
  83                                         uint64_t queue_mask);
  84         void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
  85                                         struct amdgpu_ring *ring);
  86         void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
  87                                  struct amdgpu_ring *ring,
  88                                  enum amdgpu_unmap_queues_action action,
  89                                  u64 gpu_addr, u64 seq);
  90         void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
  91                                         struct amdgpu_ring *ring,
  92                                         u64 addr,
  93                                         u64 seq);
  94         void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
  95                                 uint16_t pasid, uint32_t flush_type,
  96                                 bool all_hub);
  97         /* Packet sizes */
  98         int set_resources_size;
  99         int map_queues_size;
 100         int unmap_queues_size;
 101         int query_status_size;
 102         int invalidate_tlbs_size;
 103 };
 104
 105 struct amdgpu_kiq {
 106         u64                     eop_gpu_addr;
 107         struct amdgpu_bo        *eop_obj;
 108         spinlock_t              ring_lock;
 109         struct amdgpu_ring      ring;
 110         struct amdgpu_irq_src   irq;
 111         const struct kiq_pm4_funcs *pmf;
 112 };
 113
 114 /*
 115  * GFX configurations
 116  */
 117 #define AMDGPU_GFX_MAX_SE 4
 118 #define AMDGPU_GFX_MAX_SH_PER_SE 2
 119
 120 struct amdgpu_rb_config {
 121         uint32_t rb_backend_disable;
 122         uint32_t user_rb_backend_disable;
 123         uint32_t raster_config;
 124         uint32_t raster_config_1;
 125 };
 126
 127 struct gb_addr_config {
 128         uint16_t pipe_interleave_size;
 129         uint8_t num_pipes;
 130         uint8_t max_compress_frags;
 131         uint8_t num_banks;
 132         uint8_t num_se;
 133         uint8_t num_rb_per_se;
 134         uint8_t num_pkrs;
 135 };
 136
 137 struct amdgpu_gfx_config {
 138         unsigned max_shader_engines;
 139         unsigned max_tile_pipes;
 140         unsigned max_cu_per_sh;
 141         unsigned max_sh_per_se;
 142         unsigned max_backends_per_se;
 143         unsigned max_texture_channel_caches;
 144         unsigned max_gprs;
 145         unsigned max_gs_threads;
 146         unsigned max_hw_contexts;
 147         unsigned sc_prim_fifo_size_frontend;
 148         unsigned sc_prim_fifo_size_backend;
 149         unsigned sc_hiz_tile_fifo_size;
 150         unsigned sc_earlyz_tile_fifo_size;
 151
 152         unsigned num_tile_pipes;
 153         unsigned backend_enable_mask;
 154         unsigned mem_max_burst_length_bytes;
 155         unsigned mem_row_size_in_kb;
 156         unsigned shader_engine_tile_size;
 157         unsigned num_gpus;
 158         unsigned multi_gpu_tile_size;
 159         unsigned mc_arb_ramcfg;
 160         unsigned num_banks;
 161         unsigned num_ranks;
 162         unsigned gb_addr_config;
 163         unsigned num_rbs;
 164         unsigned gs_vgt_table_depth;
 165         unsigned gs_prim_buffer_depth;
 166
 167         uint32_t tile_mode_array[32];
 168         uint32_t macrotile_mode_array[16];
 169
 170         struct gb_addr_config gb_addr_config_fields;
 171         struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 172
 173         /* gfx configure feature */
 174         uint32_t double_offchip_lds_buf;
 175         /* cached value of DB_DEBUG2 */
 176         uint32_t db_debug2;
 177         /* gfx10 specific config */
 178         uint32_t num_sc_per_sh;
 179         uint32_t num_packer_per_sc;
 180         uint32_t pa_sc_tile_steering_override;
 181         uint64_t tcc_disabled_mask;
 182         uint32_t gc_num_tcp_per_sa;
 183         uint32_t gc_num_sdp_interface;
 184         uint32_t gc_num_tcps;
 185         uint32_t gc_num_tcp_per_wpg;
 186         uint32_t gc_tcp_l1_size;
 187         uint32_t gc_num_sqc_per_wgp;
 188         uint32_t gc_l1_instruction_cache_size_per_sqc;
 189         uint32_t gc_l1_data_cache_size_per_sqc;
 190         uint32_t gc_gl1c_per_sa;
 191         uint32_t gc_gl1c_size_per_instance;
 192         uint32_t gc_gl2c_per_gpu;
 193 };
 194
 195 struct amdgpu_cu_info {
 196         uint32_t simd_per_cu;
 197         uint32_t max_waves_per_simd;
 198         uint32_t wave_front_size;
 199         uint32_t max_scratch_slots_per_cu;
 200         uint32_t lds_size;
 201
 202         /* total active CU number */
 203         uint32_t number;
 204         uint32_t ao_cu_mask;
 205         uint32_t ao_cu_bitmap[4][4];
 206         uint32_t bitmap[4][4];
 207 };
 208
 209 struct amdgpu_gfx_ras {
 210         struct amdgpu_ras_block_object  ras_block;
 211         void (*enable_watchdog_timer)(struct amdgpu_device *adev);
 212         bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
 213 };
 214
 215 struct amdgpu_gfx_funcs {
 216         /* get the gpu clock counter */
 217         uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
 218         void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
 219                              u32 sh_num, u32 instance);
 220         void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
 221                                uint32_t wave, uint32_t *dst, int *no_fields);
 222         void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
 223                                 uint32_t wave, uint32_t thread, uint32_t start,
 224                                 uint32_t size, uint32_t *dst);
 225         void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
 226                                 uint32_t wave, uint32_t start, uint32_t size,
 227                                 uint32_t *dst);
 228         void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
 229                                  u32 queue, u32 vmid);
 230         void (*init_spm_golden)(struct amdgpu_device *adev);
 231         void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
 232 };
 233
 234 struct sq_work {
 235         struct work_struct      work;
 236         unsigned ih_data;
 237 };
 238
 239 struct amdgpu_pfp {
 240         struct amdgpu_bo                *pfp_fw_obj;
 241         uint64_t                        pfp_fw_gpu_addr;
 242         uint32_t                        *pfp_fw_ptr;
 243
 244         struct amdgpu_bo                *pfp_fw_data_obj;
 245         uint64_t                        pfp_fw_data_gpu_addr;
 246         uint32_t                        *pfp_fw_data_ptr;
 247 };
 248
 249 struct amdgpu_ce {
 250         struct amdgpu_bo                *ce_fw_obj;
 251         uint64_t                        ce_fw_gpu_addr;
 252         uint32_t                        *ce_fw_ptr;
 253 };
 254
 255 struct amdgpu_me {
 256         struct amdgpu_bo                *me_fw_obj;
 257         uint64_t                        me_fw_gpu_addr;
 258         uint32_t                        *me_fw_ptr;
 259
 260         struct amdgpu_bo                *me_fw_data_obj;
 261         uint64_t                        me_fw_data_gpu_addr;
 262         uint32_t                        *me_fw_data_ptr;
 263
 264         uint32_t                        num_me;
 265         uint32_t                        num_pipe_per_me;
 266         uint32_t                        num_queue_per_pipe;
 267         void                            *mqd_backup[AMDGPU_MAX_GFX_RINGS];
 268
 269         /* These are the resources for which amdgpu takes ownership */
 270         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 271 };
 272
 273 struct amdgpu_gfx {
 274         struct mutex                    gpu_clock_mutex;
 275         struct amdgpu_gfx_config        config;
 276         struct amdgpu_rlc               rlc;
 277         struct amdgpu_pfp               pfp;
 278         struct amdgpu_ce                ce;
 279         struct amdgpu_me                me;
 280         struct amdgpu_mec               mec;
 281         struct amdgpu_kiq               kiq;
 282         struct amdgpu_imu               imu;
 283         bool                            rs64_enable; /* firmware format */
 284         const struct firmware           *me_fw; /* ME firmware */
 285         uint32_t                        me_fw_version;
 286         const struct firmware           *pfp_fw; /* PFP firmware */
 287         uint32_t                        pfp_fw_version;
 288         const struct firmware           *ce_fw; /* CE firmware */
 289         uint32_t                        ce_fw_version;
 290         const struct firmware           *rlc_fw; /* RLC firmware */
 291         uint32_t                        rlc_fw_version;
 292         const struct firmware           *mec_fw; /* MEC firmware */
 293         uint32_t                        mec_fw_version;
 294         const struct firmware           *mec2_fw; /* MEC2 firmware */
 295         uint32_t                        mec2_fw_version;
 296         const struct firmware           *imu_fw; /* IMU firmware */
 297         uint32_t                        imu_fw_version;
 298         uint32_t                        me_feature_version;
 299         uint32_t                        ce_feature_version;
 300         uint32_t                        pfp_feature_version;
 301         uint32_t                        rlc_feature_version;
 302         uint32_t                        rlc_srlc_fw_version;
 303         uint32_t                        rlc_srlc_feature_version;
 304         uint32_t                        rlc_srlg_fw_version;
 305         uint32_t                        rlc_srlg_feature_version;
 306         uint32_t                        rlc_srls_fw_version;
 307         uint32_t                        rlc_srls_feature_version;
 308         uint32_t                        rlcp_ucode_version;
 309         uint32_t                        rlcp_ucode_feature_version;
 310         uint32_t                        rlcv_ucode_version;
 311         uint32_t                        rlcv_ucode_feature_version;
 312         uint32_t                        mec_feature_version;
 313         uint32_t                        mec2_feature_version;
 314         bool                            mec_fw_write_wait;
 315         bool                            me_fw_write_wait;
 316         bool                            cp_fw_write_wait;
 317         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
 318         unsigned                        num_gfx_rings;
 319         struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
 320         unsigned                        num_compute_rings;
 321         struct amdgpu_irq_src           eop_irq;
 322         struct amdgpu_irq_src           priv_reg_irq;
 323         struct amdgpu_irq_src           priv_inst_irq;
 324         struct amdgpu_irq_src           cp_ecc_error_irq;
 325         struct amdgpu_irq_src           sq_irq;
 326         struct sq_work                  sq_work;
 327
 328         /* gfx status */
 329         uint32_t                        gfx_current_status;
 330         /* ce ram size*/
 331         unsigned                        ce_ram_size;
 332         struct amdgpu_cu_info           cu_info;
 333         const struct amdgpu_gfx_funcs   *funcs;
 334
 335         /* reset mask */
 336         uint32_t                        grbm_soft_reset;
 337         uint32_t                        srbm_soft_reset;
 338
 339         /* gfx off */
 340         bool                            gfx_off_state;      /* true: enabled, false: disabled */
 341         struct mutex                    gfx_off_mutex;      /* mutex to change gfxoff state */
 342         uint32_t                        gfx_off_req_count;  /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
 343         struct delayed_work             gfx_off_delay_work; /* async work to set gfx block off */
 344         uint32_t                        gfx_off_residency;  /* last logged residency */
 345         uint64_t                        gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
 346
 347         /* pipe reservation */
 348         struct mutex                    pipe_reserve_mutex;
 349         DECLARE_BITMAP                  (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 350
 351         /*ras */
 352         struct ras_common_if            *ras_if;
 353         struct amdgpu_gfx_ras           *ras;
 354
 355         bool                            is_poweron;
 356
 357         struct amdgpu_ring              sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
 358         struct amdgpu_ring_mux          muxer;
 359 };
 360
 361 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 362 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
 363 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
 364 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
 365
 366 /**
 367  * amdgpu_gfx_create_bitmask - create a bitmask
 368  *
 369  * @bit_width: length of the mask
 370  *
 371  * create a variable length bit mask.
 372  * Returns the bitmask.
 373  */
 374 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 375 {
 376         return (u32)((1ULL << bit_width) - 1);
 377 }
 378
 379 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
 380                                  unsigned max_sh);
 381
 382 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 383                              struct amdgpu_ring *ring,
 384                              struct amdgpu_irq_src *irq);
 385
 386 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
 387
 388 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
 389 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 390                         unsigned hpd_size);
 391
 392 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 393                            unsigned mqd_size);
 394 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
 395 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
 396 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
 397
 398 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
 399 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
 400
 401 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
 402                                 int pipe, int queue);
 403 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
 404                                  int *mec, int *pipe, int *queue);
 405 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
 406                                      int pipe, int queue);
 407 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 408                                                struct amdgpu_ring *ring);
 409 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 410                                                 struct amdgpu_ring *ring);
 411 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
 412                                int pipe, int queue);
 413 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
 414                                 int *me, int *pipe, int *queue);
 415 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
 416                                     int pipe, int queue);
 417 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 418 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
 419 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 420 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
 421 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
 422 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
 423 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
 424 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 425                 void *err_data,
 426                 struct amdgpu_iv_entry *entry);
 427 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 428                                   struct amdgpu_irq_src *source,
 429                                   struct amdgpu_iv_entry *entry);
 430 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
 431 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
 432 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
 433 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
 434
 435 #endif