drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  73         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  74 };
  75
  76 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  77 {
  78         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  79         .codec_array = nv_video_codecs_encode_array,
  80 };
  81
  82 /* Navi1x */
  83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  84 {
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  91         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  92 };
  93
  94 static const struct amdgpu_video_codecs nv_video_codecs_decode =
  95 {
  96         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  97         .codec_array = nv_video_codecs_decode_array,
  98 };
  99
 100 /* Sienna Cichlid */
 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 102 {
 103         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 104         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 105         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 111 };
 112
 113 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 114 {
 115         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 116         .codec_array = sc_video_codecs_decode_array,
 117 };
 118
 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 121 {
 122         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 124 };
 125
 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
 127 {
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 130         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 131         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 132         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 133         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 134         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 135         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 136 };
 137
 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 139 {
 140         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 141         .codec_array = sriov_sc_video_codecs_encode_array,
 142 };
 143
 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
 145 {
 146         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
 147         .codec_array = sriov_sc_video_codecs_decode_array,
 148 };
 149
 150 /* Beige Goby*/
 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 152         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 153         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 154         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 155 };
 156
 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 158         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 159         .codec_array = bg_video_codecs_decode_array,
 160 };
 161
 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 163         .codec_count = 0,
 164         .codec_array = NULL,
 165 };
 166
 167 /* Yellow Carp*/
 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 169         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 170         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 171         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 172         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 173 };
 174
 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 176         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 177         .codec_array = yc_video_codecs_decode_array,
 178 };
 179
 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 181                                  const struct amdgpu_video_codecs **codecs)
 182 {
 183         switch (adev->ip_versions[UVD_HWIP][0]) {
 184         case IP_VERSION(3, 0, 0):
 185         case IP_VERSION(3, 0, 64):
 186         case IP_VERSION(3, 0, 192):
 187                 if (amdgpu_sriov_vf(adev)) {
 188                         if (encode)
 189                                 *codecs = &sriov_sc_video_codecs_encode;
 190                         else
 191                                 *codecs = &sriov_sc_video_codecs_decode;
 192                 } else {
 193                         if (encode)
 194                                 *codecs = &nv_video_codecs_encode;
 195                         else
 196                                 *codecs = &sc_video_codecs_decode;
 197                 }
 198                 return 0;
 199         case IP_VERSION(3, 0, 16):
 200         case IP_VERSION(3, 0, 2):
 201                 if (encode)
 202                         *codecs = &nv_video_codecs_encode;
 203                 else
 204                         *codecs = &sc_video_codecs_decode;
 205                 return 0;
 206         case IP_VERSION(3, 1, 1):
 207                 if (encode)
 208                         *codecs = &nv_video_codecs_encode;
 209                 else
 210                         *codecs = &yc_video_codecs_decode;
 211                 return 0;
 212         case IP_VERSION(3, 0, 33):
 213                 if (encode)
 214                         *codecs = &bg_video_codecs_encode;
 215                 else
 216                         *codecs = &bg_video_codecs_decode;
 217                 return 0;
 218         case IP_VERSION(2, 0, 0):
 219         case IP_VERSION(2, 0, 2):
 220                 if (encode)
 221                         *codecs = &nv_video_codecs_encode;
 222                 else
 223                         *codecs = &nv_video_codecs_decode;
 224                 return 0;
 225         default:
 226                 return -EINVAL;
 227         }
 228 }
 229
 230 /*
 231  * Indirect registers accessor
 232  */
 233 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 234 {
 235         unsigned long address, data;
 236         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 237         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 238
 239         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 240 }
 241
 242 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 243 {
 244         unsigned long address, data;
 245
 246         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 247         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 248
 249         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 250 }
 251
 252 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 253 {
 254         unsigned long address, data;
 255         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 256         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 257
 258         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 259 }
 260
 261 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 262 {
 263         unsigned long flags, address, data;
 264         u32 r;
 265         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 266         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 267
 268         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 269         WREG32(address, reg * 4);
 270         (void)RREG32(address);
 271         r = RREG32(data);
 272         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 273         return r;
 274 }
 275
 276 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 277 {
 278         unsigned long address, data;
 279
 280         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 281         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 282
 283         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 284 }
 285
 286 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 287 {
 288         unsigned long flags, address, data;
 289
 290         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 291         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 292
 293         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 294         WREG32(address, reg * 4);
 295         (void)RREG32(address);
 296         WREG32(data, v);
 297         (void)RREG32(data);
 298         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 299 }
 300
 301 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 302 {
 303         unsigned long flags, address, data;
 304         u32 r;
 305
 306         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 307         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 308
 309         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 310         WREG32(address, (reg));
 311         r = RREG32(data);
 312         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 313         return r;
 314 }
 315
 316 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 317 {
 318         unsigned long flags, address, data;
 319
 320         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 321         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 322
 323         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 324         WREG32(address, (reg));
 325         WREG32(data, (v));
 326         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 327 }
 328
 329 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 330 {
 331         return adev->nbio.funcs->get_memsize(adev);
 332 }
 333
 334 static u32 nv_get_xclk(struct amdgpu_device *adev)
 335 {
 336         return adev->clock.spll.reference_freq;
 337 }
 338
 339
 340 void nv_grbm_select(struct amdgpu_device *adev,
 341                      u32 me, u32 pipe, u32 queue, u32 vmid)
 342 {
 343         u32 grbm_gfx_cntl = 0;
 344         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 345         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 346         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 347         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 348
 349         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 350 }
 351
 352 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 353 {
 354         /* todo */
 355 }
 356
 357 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 358 {
 359         /* todo */
 360         return false;
 361 }
 362
 363 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 364                                   u8 *bios, u32 length_bytes)
 365 {
 366         u32 *dw_ptr;
 367         u32 i, length_dw;
 368         u32 rom_index_offset, rom_data_offset;
 369
 370         if (bios == NULL)
 371                 return false;
 372         if (length_bytes == 0)
 373                 return false;
 374         /* APU vbios image is part of sbios image */
 375         if (adev->flags & AMD_IS_APU)
 376                 return false;
 377
 378         dw_ptr = (u32 *)bios;
 379         length_dw = ALIGN(length_bytes, 4) / 4;
 380
 381         rom_index_offset =
 382                 adev->smuio.funcs->get_rom_index_offset(adev);
 383         rom_data_offset =
 384                 adev->smuio.funcs->get_rom_data_offset(adev);
 385
 386         /* set rom index to 0 */
 387         WREG32(rom_index_offset, 0);
 388         /* read out the rom data */
 389         for (i = 0; i < length_dw; i++)
 390                 dw_ptr[i] = RREG32(rom_data_offset);
 391
 392         return true;
 393 }
 394
 395 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 396         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 397         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 398         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 399         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 400         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 401         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 402         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 403         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 404         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 405         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 406         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 407         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 408         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 409         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 410         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 411         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 412         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 413         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 414         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 415 };
 416
 417 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 418                                          u32 sh_num, u32 reg_offset)
 419 {
 420         uint32_t val;
 421
 422         mutex_lock(&adev->grbm_idx_mutex);
 423         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 424                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 425
 426         val = RREG32(reg_offset);
 427
 428         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 429                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 430         mutex_unlock(&adev->grbm_idx_mutex);
 431         return val;
 432 }
 433
 434 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 435                                       bool indexed, u32 se_num,
 436                                       u32 sh_num, u32 reg_offset)
 437 {
 438         if (indexed) {
 439                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 440         } else {
 441                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 442                         return adev->gfx.config.gb_addr_config;
 443                 return RREG32(reg_offset);
 444         }
 445 }
 446
 447 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 448                             u32 sh_num, u32 reg_offset, u32 *value)
 449 {
 450         uint32_t i;
 451         struct soc15_allowed_register_entry  *en;
 452
 453         *value = 0;
 454         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 455                 en = &nv_allowed_read_registers[i];
 456                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 457                     reg_offset !=
 458                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 459                         continue;
 460
 461                 *value = nv_get_register_value(adev,
 462                                                nv_allowed_read_registers[i].grbm_indexed,
 463                                                se_num, sh_num, reg_offset);
 464                 return 0;
 465         }
 466         return -EINVAL;
 467 }
 468
 469 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 470 {
 471         u32 i;
 472         int ret = 0;
 473
 474         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 475
 476         /* disable BM */
 477         pci_clear_master(adev->pdev);
 478
 479         amdgpu_device_cache_pci_state(adev->pdev);
 480
 481         ret = amdgpu_dpm_mode2_reset(adev);
 482         if (ret)
 483                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 484
 485         amdgpu_device_load_pci_state(adev->pdev);
 486
 487         /* wait for asic to come out of reset */
 488         for (i = 0; i < adev->usec_timeout; i++) {
 489                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 490
 491                 if (memsize != 0xffffffff)
 492                         break;
 493                 udelay(1);
 494         }
 495
 496         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 497
 498         return ret;
 499 }
 500
 501 static enum amd_reset_method
 502 nv_asic_reset_method(struct amdgpu_device *adev)
 503 {
 504         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 505             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 506             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 507             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 508                 return amdgpu_reset_method;
 509
 510         if (amdgpu_reset_method != -1)
 511                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 512                                   amdgpu_reset_method);
 513
 514         switch (adev->ip_versions[MP1_HWIP][0]) {
 515         case IP_VERSION(11, 5, 0):
 516         case IP_VERSION(13, 0, 1):
 517         case IP_VERSION(13, 0, 3):
 518                 return AMD_RESET_METHOD_MODE2;
 519         case IP_VERSION(11, 0, 7):
 520         case IP_VERSION(11, 0, 11):
 521         case IP_VERSION(11, 0, 12):
 522         case IP_VERSION(11, 0, 13):
 523                 return AMD_RESET_METHOD_MODE1;
 524         default:
 525                 if (amdgpu_dpm_is_baco_supported(adev))
 526                         return AMD_RESET_METHOD_BACO;
 527                 else
 528                         return AMD_RESET_METHOD_MODE1;
 529         }
 530 }
 531
 532 static int nv_asic_reset(struct amdgpu_device *adev)
 533 {
 534         int ret = 0;
 535
 536         switch (nv_asic_reset_method(adev)) {
 537         case AMD_RESET_METHOD_PCI:
 538                 dev_info(adev->dev, "PCI reset\n");
 539                 ret = amdgpu_device_pci_reset(adev);
 540                 break;
 541         case AMD_RESET_METHOD_BACO:
 542                 dev_info(adev->dev, "BACO reset\n");
 543                 ret = amdgpu_dpm_baco_reset(adev);
 544                 break;
 545         case AMD_RESET_METHOD_MODE2:
 546                 dev_info(adev->dev, "MODE2 reset\n");
 547                 ret = nv_asic_mode2_reset(adev);
 548                 break;
 549         default:
 550                 dev_info(adev->dev, "MODE1 reset\n");
 551                 ret = amdgpu_device_mode1_reset(adev);
 552                 break;
 553         }
 554
 555         return ret;
 556 }
 557
 558 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 559 {
 560         /* todo */
 561         return 0;
 562 }
 563
 564 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 565 {
 566         /* todo */
 567         return 0;
 568 }
 569
 570 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 571 {
 572         if (pci_is_root_bus(adev->pdev->bus))
 573                 return;
 574
 575         if (amdgpu_pcie_gen2 == 0)
 576                 return;
 577
 578         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 579                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 580                 return;
 581
 582         /* todo */
 583 }
 584
 585 static void nv_program_aspm(struct amdgpu_device *adev)
 586 {
 587         if (!amdgpu_aspm)
 588                 return;
 589
 590         if (!(adev->flags & AMD_IS_APU) &&
 591             (adev->nbio.funcs->program_aspm))
 592                 adev->nbio.funcs->program_aspm(adev);
 593
 594 }
 595
 596 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 597                                         bool enable)
 598 {
 599         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 600         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 601 }
 602
 603 const struct amdgpu_ip_block_version nv_common_ip_block =
 604 {
 605         .type = AMD_IP_BLOCK_TYPE_COMMON,
 606         .major = 1,
 607         .minor = 0,
 608         .rev = 0,
 609         .funcs = &nv_common_ip_funcs,
 610 };
 611
 612 void nv_set_virt_ops(struct amdgpu_device *adev)
 613 {
 614         adev->virt.ops = &xgpu_nv_virt_ops;
 615 }
 616
 617 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 618 {
 619         return adev->nbio.funcs->get_rev_id(adev);
 620 }
 621
 622 static bool nv_need_full_reset(struct amdgpu_device *adev)
 623 {
 624         return true;
 625 }
 626
 627 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 628 {
 629         u32 sol_reg;
 630
 631         if (adev->flags & AMD_IS_APU)
 632                 return false;
 633
 634         /* Check sOS sign of life register to confirm sys driver and sOS
 635          * are already been loaded.
 636          */
 637         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 638         if (sol_reg)
 639                 return true;
 640
 641         return false;
 642 }
 643
 644 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 645 {
 646
 647         /* TODO
 648          * dummy implement for pcie_replay_count sysfs interface
 649          * */
 650
 651         return 0;
 652 }
 653
 654 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 655 {
 656         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 657         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 658         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 659         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 660         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 661         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 662         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 663         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 664         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 665         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 666         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 667         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 668         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 669         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 670         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 671         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 672         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 673         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 674         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 675         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 676         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 677         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 678         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 679         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 680         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 681
 682         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 683         adev->doorbell_index.sdma_doorbell_range = 20;
 684 }
 685
 686 static void nv_pre_asic_init(struct amdgpu_device *adev)
 687 {
 688 }
 689
 690 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 691                                        bool enter)
 692 {
 693         if (enter)
 694                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 695         else
 696                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 697
 698         if (adev->gfx.funcs->update_perfmon_mgcg)
 699                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 700
 701         if (!(adev->flags & AMD_IS_APU) &&
 702             (adev->nbio.funcs->enable_aspm))
 703                 adev->nbio.funcs->enable_aspm(adev, !enter);
 704
 705         return 0;
 706 }
 707
 708 static const struct amdgpu_asic_funcs nv_asic_funcs =
 709 {
 710         .read_disabled_bios = &nv_read_disabled_bios,
 711         .read_bios_from_rom = &nv_read_bios_from_rom,
 712         .read_register = &nv_read_register,
 713         .reset = &nv_asic_reset,
 714         .reset_method = &nv_asic_reset_method,
 715         .set_vga_state = &nv_vga_set_state,
 716         .get_xclk = &nv_get_xclk,
 717         .set_uvd_clocks = &nv_set_uvd_clocks,
 718         .set_vce_clocks = &nv_set_vce_clocks,
 719         .get_config_memsize = &nv_get_config_memsize,
 720         .init_doorbell_index = &nv_init_doorbell_index,
 721         .need_full_reset = &nv_need_full_reset,
 722         .need_reset_on_init = &nv_need_reset_on_init,
 723         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 724         .supports_baco = &amdgpu_dpm_is_baco_supported,
 725         .pre_asic_init = &nv_pre_asic_init,
 726         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 727         .query_video_codecs = &nv_query_video_codecs,
 728 };
 729
 730 static int nv_common_early_init(void *handle)
 731 {
 732 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 733         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 734
 735         if (!amdgpu_sriov_vf(adev)) {
 736                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 737                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 738         }
 739         adev->smc_rreg = NULL;
 740         adev->smc_wreg = NULL;
 741         adev->pcie_rreg = &nv_pcie_rreg;
 742         adev->pcie_wreg = &nv_pcie_wreg;
 743         adev->pcie_rreg64 = &nv_pcie_rreg64;
 744         adev->pcie_wreg64 = &nv_pcie_wreg64;
 745         adev->pciep_rreg = &nv_pcie_port_rreg;
 746         adev->pciep_wreg = &nv_pcie_port_wreg;
 747
 748         /* TODO: will add them during VCN v2 implementation */
 749         adev->uvd_ctx_rreg = NULL;
 750         adev->uvd_ctx_wreg = NULL;
 751
 752         adev->didt_rreg = &nv_didt_rreg;
 753         adev->didt_wreg = &nv_didt_wreg;
 754
 755         adev->asic_funcs = &nv_asic_funcs;
 756
 757         adev->rev_id = nv_get_rev_id(adev);
 758         adev->external_rev_id = 0xff;
 759         /* TODO: split the GC and PG flags based on the relevant IP version for which
 760          * they are relevant.
 761          */
 762         switch (adev->ip_versions[GC_HWIP][0]) {
 763         case IP_VERSION(10, 1, 10):
 764                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 765                         AMD_CG_SUPPORT_GFX_CGCG |
 766                         AMD_CG_SUPPORT_IH_CG |
 767                         AMD_CG_SUPPORT_HDP_MGCG |
 768                         AMD_CG_SUPPORT_HDP_LS |
 769                         AMD_CG_SUPPORT_SDMA_MGCG |
 770                         AMD_CG_SUPPORT_SDMA_LS |
 771                         AMD_CG_SUPPORT_MC_MGCG |
 772                         AMD_CG_SUPPORT_MC_LS |
 773                         AMD_CG_SUPPORT_ATHUB_MGCG |
 774                         AMD_CG_SUPPORT_ATHUB_LS |
 775                         AMD_CG_SUPPORT_VCN_MGCG |
 776                         AMD_CG_SUPPORT_JPEG_MGCG |
 777                         AMD_CG_SUPPORT_BIF_MGCG |
 778                         AMD_CG_SUPPORT_BIF_LS;
 779                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 780                         AMD_PG_SUPPORT_VCN_DPG |
 781                         AMD_PG_SUPPORT_JPEG |
 782                         AMD_PG_SUPPORT_ATHUB;
 783                 adev->external_rev_id = adev->rev_id + 0x1;
 784                 break;
 785         case IP_VERSION(10, 1, 1):
 786                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 787                         AMD_CG_SUPPORT_GFX_CGCG |
 788                         AMD_CG_SUPPORT_IH_CG |
 789                         AMD_CG_SUPPORT_HDP_MGCG |
 790                         AMD_CG_SUPPORT_HDP_LS |
 791                         AMD_CG_SUPPORT_SDMA_MGCG |
 792                         AMD_CG_SUPPORT_SDMA_LS |
 793                         AMD_CG_SUPPORT_MC_MGCG |
 794                         AMD_CG_SUPPORT_MC_LS |
 795                         AMD_CG_SUPPORT_ATHUB_MGCG |
 796                         AMD_CG_SUPPORT_ATHUB_LS |
 797                         AMD_CG_SUPPORT_VCN_MGCG |
 798                         AMD_CG_SUPPORT_JPEG_MGCG |
 799                         AMD_CG_SUPPORT_BIF_MGCG |
 800                         AMD_CG_SUPPORT_BIF_LS;
 801                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 802                         AMD_PG_SUPPORT_JPEG |
 803                         AMD_PG_SUPPORT_VCN_DPG;
 804                 adev->external_rev_id = adev->rev_id + 20;
 805                 break;
 806         case IP_VERSION(10, 1, 2):
 807                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 808                         AMD_CG_SUPPORT_GFX_MGLS |
 809                         AMD_CG_SUPPORT_GFX_CGCG |
 810                         AMD_CG_SUPPORT_GFX_CP_LS |
 811                         AMD_CG_SUPPORT_GFX_RLC_LS |
 812                         AMD_CG_SUPPORT_IH_CG |
 813                         AMD_CG_SUPPORT_HDP_MGCG |
 814                         AMD_CG_SUPPORT_HDP_LS |
 815                         AMD_CG_SUPPORT_SDMA_MGCG |
 816                         AMD_CG_SUPPORT_SDMA_LS |
 817                         AMD_CG_SUPPORT_MC_MGCG |
 818                         AMD_CG_SUPPORT_MC_LS |
 819                         AMD_CG_SUPPORT_ATHUB_MGCG |
 820                         AMD_CG_SUPPORT_ATHUB_LS |
 821                         AMD_CG_SUPPORT_VCN_MGCG |
 822                         AMD_CG_SUPPORT_JPEG_MGCG;
 823                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 824                         AMD_PG_SUPPORT_VCN_DPG |
 825                         AMD_PG_SUPPORT_JPEG |
 826                         AMD_PG_SUPPORT_ATHUB;
 827                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 828                  * as a consequence, the rev_id and external_rev_id are wrong.
 829                  * workaround it by hardcoding rev_id to 0 (default value).
 830                  */
 831                 if (amdgpu_sriov_vf(adev))
 832                         adev->rev_id = 0;
 833                 adev->external_rev_id = adev->rev_id + 0xa;
 834                 break;
 835         case IP_VERSION(10, 3, 0):
 836                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 837                         AMD_CG_SUPPORT_GFX_CGCG |
 838                         AMD_CG_SUPPORT_GFX_CGLS |
 839                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 840                         AMD_CG_SUPPORT_MC_MGCG |
 841                         AMD_CG_SUPPORT_VCN_MGCG |
 842                         AMD_CG_SUPPORT_JPEG_MGCG |
 843                         AMD_CG_SUPPORT_HDP_MGCG |
 844                         AMD_CG_SUPPORT_HDP_LS |
 845                         AMD_CG_SUPPORT_IH_CG |
 846                         AMD_CG_SUPPORT_MC_LS;
 847                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 848                         AMD_PG_SUPPORT_VCN_DPG |
 849                         AMD_PG_SUPPORT_JPEG |
 850                         AMD_PG_SUPPORT_ATHUB |
 851                         AMD_PG_SUPPORT_MMHUB;
 852                 if (amdgpu_sriov_vf(adev)) {
 853                         /* hypervisor control CG and PG enablement */
 854                         adev->cg_flags = 0;
 855                         adev->pg_flags = 0;
 856                 }
 857                 adev->external_rev_id = adev->rev_id + 0x28;
 858                 break;
 859         case IP_VERSION(10, 3, 2):
 860                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 861                         AMD_CG_SUPPORT_GFX_CGCG |
 862                         AMD_CG_SUPPORT_GFX_CGLS |
 863                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 864                         AMD_CG_SUPPORT_VCN_MGCG |
 865                         AMD_CG_SUPPORT_JPEG_MGCG |
 866                         AMD_CG_SUPPORT_MC_MGCG |
 867                         AMD_CG_SUPPORT_MC_LS |
 868                         AMD_CG_SUPPORT_HDP_MGCG |
 869                         AMD_CG_SUPPORT_HDP_LS |
 870                         AMD_CG_SUPPORT_IH_CG;
 871                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 872                         AMD_PG_SUPPORT_VCN_DPG |
 873                         AMD_PG_SUPPORT_JPEG |
 874                         AMD_PG_SUPPORT_ATHUB |
 875                         AMD_PG_SUPPORT_MMHUB;
 876                 adev->external_rev_id = adev->rev_id + 0x32;
 877                 break;
 878         case IP_VERSION(10, 3, 1):
 879                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 880                         AMD_CG_SUPPORT_GFX_MGLS |
 881                         AMD_CG_SUPPORT_GFX_CP_LS |
 882                         AMD_CG_SUPPORT_GFX_RLC_LS |
 883                         AMD_CG_SUPPORT_GFX_CGCG |
 884                         AMD_CG_SUPPORT_GFX_CGLS |
 885                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 886                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 887                         AMD_CG_SUPPORT_MC_MGCG |
 888                         AMD_CG_SUPPORT_MC_LS |
 889                         AMD_CG_SUPPORT_GFX_FGCG |
 890                         AMD_CG_SUPPORT_VCN_MGCG |
 891                         AMD_CG_SUPPORT_SDMA_MGCG |
 892                         AMD_CG_SUPPORT_SDMA_LS |
 893                         AMD_CG_SUPPORT_JPEG_MGCG;
 894                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 895                         AMD_PG_SUPPORT_VCN |
 896                         AMD_PG_SUPPORT_VCN_DPG |
 897                         AMD_PG_SUPPORT_JPEG;
 898                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 899                         adev->external_rev_id = adev->rev_id + 0x01;
 900                 break;
 901         case IP_VERSION(10, 3, 4):
 902                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 903                         AMD_CG_SUPPORT_GFX_CGCG |
 904                         AMD_CG_SUPPORT_GFX_CGLS |
 905                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 906                         AMD_CG_SUPPORT_VCN_MGCG |
 907                         AMD_CG_SUPPORT_JPEG_MGCG |
 908                         AMD_CG_SUPPORT_MC_MGCG |
 909                         AMD_CG_SUPPORT_MC_LS |
 910                         AMD_CG_SUPPORT_HDP_MGCG |
 911                         AMD_CG_SUPPORT_HDP_LS |
 912                         AMD_CG_SUPPORT_IH_CG;
 913                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 914                         AMD_PG_SUPPORT_VCN_DPG |
 915                         AMD_PG_SUPPORT_JPEG |
 916                         AMD_PG_SUPPORT_ATHUB |
 917                         AMD_PG_SUPPORT_MMHUB;
 918                 adev->external_rev_id = adev->rev_id + 0x3c;
 919                 break;
 920         case IP_VERSION(10, 3, 5):
 921                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 922                         AMD_CG_SUPPORT_GFX_CGCG |
 923                         AMD_CG_SUPPORT_GFX_CGLS |
 924                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 925                         AMD_CG_SUPPORT_MC_MGCG |
 926                         AMD_CG_SUPPORT_MC_LS |
 927                         AMD_CG_SUPPORT_HDP_MGCG |
 928                         AMD_CG_SUPPORT_HDP_LS |
 929                         AMD_CG_SUPPORT_IH_CG |
 930                         AMD_CG_SUPPORT_VCN_MGCG;
 931                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 932                         AMD_PG_SUPPORT_VCN_DPG |
 933                         AMD_PG_SUPPORT_ATHUB |
 934                         AMD_PG_SUPPORT_MMHUB;
 935                 adev->external_rev_id = adev->rev_id + 0x46;
 936                 break;
 937         case IP_VERSION(10, 3, 3):
 938                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 939                         AMD_CG_SUPPORT_GFX_MGLS |
 940                         AMD_CG_SUPPORT_GFX_CGCG |
 941                         AMD_CG_SUPPORT_GFX_CGLS |
 942                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 943                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 944                         AMD_CG_SUPPORT_GFX_RLC_LS |
 945                         AMD_CG_SUPPORT_GFX_CP_LS |
 946                         AMD_CG_SUPPORT_GFX_FGCG |
 947                         AMD_CG_SUPPORT_MC_MGCG |
 948                         AMD_CG_SUPPORT_MC_LS |
 949                         AMD_CG_SUPPORT_SDMA_LS |
 950                         AMD_CG_SUPPORT_HDP_MGCG |
 951                         AMD_CG_SUPPORT_HDP_LS |
 952                         AMD_CG_SUPPORT_ATHUB_MGCG |
 953                         AMD_CG_SUPPORT_ATHUB_LS |
 954                         AMD_CG_SUPPORT_IH_CG |
 955                         AMD_CG_SUPPORT_VCN_MGCG |
 956                         AMD_CG_SUPPORT_JPEG_MGCG;
 957                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 958                         AMD_PG_SUPPORT_VCN |
 959                         AMD_PG_SUPPORT_VCN_DPG |
 960                         AMD_PG_SUPPORT_JPEG;
 961                 if (adev->pdev->device == 0x1681)
 962                         adev->external_rev_id = 0x20;
 963                 else
 964                         adev->external_rev_id = adev->rev_id + 0x01;
 965                 break;
 966         case IP_VERSION(10, 1, 3):
 967                 adev->cg_flags = 0;
 968                 adev->pg_flags = 0;
 969                 adev->external_rev_id = adev->rev_id + 0x82;
 970                 break;
 971         default:
 972                 /* FIXME: not supported yet */
 973                 return -EINVAL;
 974         }
 975
 976         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
 977                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
 978                                     AMD_PG_SUPPORT_VCN_DPG |
 979                                     AMD_PG_SUPPORT_JPEG);
 980
 981         if (amdgpu_sriov_vf(adev)) {
 982                 amdgpu_virt_init_setting(adev);
 983                 xgpu_nv_mailbox_set_irq_funcs(adev);
 984         }
 985
 986         return 0;
 987 }
 988
 989 static int nv_common_late_init(void *handle)
 990 {
 991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 992
 993         if (amdgpu_sriov_vf(adev)) {
 994                 xgpu_nv_mailbox_get_irq(adev);
 995                 amdgpu_virt_update_sriov_video_codec(adev,
 996                                 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 997                                 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
 998         }
 999
1000         return 0;
1001 }
1002
1003 static int nv_common_sw_init(void *handle)
1004 {
1005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006
1007         if (amdgpu_sriov_vf(adev))
1008                 xgpu_nv_mailbox_add_irq_id(adev);
1009
1010         return 0;
1011 }
1012
1013 static int nv_common_sw_fini(void *handle)
1014 {
1015         return 0;
1016 }
1017
1018 static int nv_common_hw_init(void *handle)
1019 {
1020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021
1022         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1023                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1024
1025         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1026                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1027
1028         /* enable pcie gen2/3 link */
1029         nv_pcie_gen3_enable(adev);
1030         /* enable aspm */
1031         nv_program_aspm(adev);
1032         /* setup nbio registers */
1033         adev->nbio.funcs->init_registers(adev);
1034         /* remap HDP registers to a hole in mmio space,
1035          * for the purpose of expose those registers
1036          * to process space
1037          */
1038         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1039                 adev->nbio.funcs->remap_hdp_registers(adev);
1040         /* enable the doorbell aperture */
1041         nv_enable_doorbell_aperture(adev, true);
1042
1043         return 0;
1044 }
1045
1046 static int nv_common_hw_fini(void *handle)
1047 {
1048         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049
1050         /* disable the doorbell aperture */
1051         nv_enable_doorbell_aperture(adev, false);
1052
1053         return 0;
1054 }
1055
1056 static int nv_common_suspend(void *handle)
1057 {
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060         return nv_common_hw_fini(adev);
1061 }
1062
1063 static int nv_common_resume(void *handle)
1064 {
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         return nv_common_hw_init(adev);
1068 }
1069
1070 static bool nv_common_is_idle(void *handle)
1071 {
1072         return true;
1073 }
1074
1075 static int nv_common_wait_for_idle(void *handle)
1076 {
1077         return 0;
1078 }
1079
1080 static int nv_common_soft_reset(void *handle)
1081 {
1082         return 0;
1083 }
1084
1085 static int nv_common_set_clockgating_state(void *handle,
1086                                            enum amd_clockgating_state state)
1087 {
1088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1089
1090         if (amdgpu_sriov_vf(adev))
1091                 return 0;
1092
1093         switch (adev->ip_versions[NBIO_HWIP][0]) {
1094         case IP_VERSION(2, 3, 0):
1095         case IP_VERSION(2, 3, 1):
1096         case IP_VERSION(2, 3, 2):
1097         case IP_VERSION(3, 3, 0):
1098         case IP_VERSION(3, 3, 1):
1099         case IP_VERSION(3, 3, 2):
1100         case IP_VERSION(3, 3, 3):
1101                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1102                                 state == AMD_CG_STATE_GATE);
1103                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1104                                 state == AMD_CG_STATE_GATE);
1105                 adev->hdp.funcs->update_clock_gating(adev,
1106                                 state == AMD_CG_STATE_GATE);
1107                 adev->smuio.funcs->update_rom_clock_gating(adev,
1108                                 state == AMD_CG_STATE_GATE);
1109                 break;
1110         default:
1111                 break;
1112         }
1113         return 0;
1114 }
1115
1116 static int nv_common_set_powergating_state(void *handle,
1117                                            enum amd_powergating_state state)
1118 {
1119         /* TODO */
1120         return 0;
1121 }
1122
1123 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1124 {
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         if (amdgpu_sriov_vf(adev))
1128                 *flags = 0;
1129
1130         adev->nbio.funcs->get_clockgating_state(adev, flags);
1131
1132         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1133
1134         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1135
1136         return;
1137 }
1138
1139 static const struct amd_ip_funcs nv_common_ip_funcs = {
1140         .name = "nv_common",
1141         .early_init = nv_common_early_init,
1142         .late_init = nv_common_late_init,
1143         .sw_init = nv_common_sw_init,
1144         .sw_fini = nv_common_sw_fini,
1145         .hw_init = nv_common_hw_init,
1146         .hw_fini = nv_common_hw_fini,
1147         .suspend = nv_common_suspend,
1148         .resume = nv_common_resume,
1149         .is_idle = nv_common_is_idle,
1150         .wait_for_idle = nv_common_wait_for_idle,
1151         .soft_reset = nv_common_soft_reset,
1152         .set_clockgating_state = nv_common_set_clockgating_state,
1153         .set_powergating_state = nv_common_set_powergating_state,
1154         .get_clockgating_state = nv_common_get_clockgating_state,
1155 };