drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32 #include "vi.h"
  33 #include "vid.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "gmc/gmc_8_1_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44
  45 #include "bif/bif_5_0_d.h"
  46 #include "bif/bif_5_0_sh_mask.h"
  47
  48 #include "tonga_sdma_pkt_open.h"
  49
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51
  52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  56
  57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
  72
  73
  74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  75 {
  76         SDMA0_REGISTER_OFFSET,
  77         SDMA1_REGISTER_OFFSET
  78 };
  79
  80 static const u32 golden_settings_tonga_a11[] =
  81 {
  82         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  83         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  84         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  85         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  86         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  87         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  88         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  89         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  91         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  92 };
  93
  94 static const u32 tonga_mgcg_cgcg_init[] =
  95 {
  96         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  97         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  98 };
  99
 100 static const u32 golden_settings_fiji_a10[] =
 101 {
 102         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 103         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 104         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 105         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 106         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 108         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 109         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 110 };
 111
 112 static const u32 fiji_mgcg_cgcg_init[] =
 113 {
 114         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 115         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 116 };
 117
 118 static const u32 golden_settings_polaris11_a11[] =
 119 {
 120         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 121         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 122         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 123         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 124         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 125         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130 };
 131
 132 static const u32 golden_settings_polaris10_a11[] =
 133 {
 134         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 135         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 136         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 137         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 138         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 139         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 140         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 141         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 142         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 143         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 144 };
 145
 146 static const u32 cz_golden_settings_a11[] =
 147 {
 148         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 149         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 150         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 151         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 152         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 153         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 154         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 155         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 156         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 157         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 158         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 159         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 160 };
 161
 162 static const u32 cz_mgcg_cgcg_init[] =
 163 {
 164         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 165         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 166 };
 167
 168 static const u32 stoney_golden_settings_a11[] =
 169 {
 170         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 171         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 172         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 173         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 174 };
 175
 176 static const u32 stoney_mgcg_cgcg_init[] =
 177 {
 178         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 179 };
 180
 181 /*
 182  * sDMA - System DMA
 183  * Starting with CIK, the GPU has new asynchronous
 184  * DMA engines.  These engines are used for compute
 185  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 186  * and each one supports 1 ring buffer used for gfx
 187  * and 2 queues used for compute.
 188  *
 189  * The programming model is very similar to the CP
 190  * (ring buffer, IBs, etc.), but sDMA has it's own
 191  * packet format that is different from the PM4 format
 192  * used by the CP. sDMA supports copying data, writing
 193  * embedded data, solid fills, and a number of other
 194  * things.  It also has support for tiling/detiling of
 195  * buffers.
 196  */
 197
 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 199 {
 200         switch (adev->asic_type) {
 201         case CHIP_FIJI:
 202                 amdgpu_device_program_register_sequence(adev,
 203                                                         fiji_mgcg_cgcg_init,
 204                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 205                 amdgpu_device_program_register_sequence(adev,
 206                                                         golden_settings_fiji_a10,
 207                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 208                 break;
 209         case CHIP_TONGA:
 210                 amdgpu_device_program_register_sequence(adev,
 211                                                         tonga_mgcg_cgcg_init,
 212                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 213                 amdgpu_device_program_register_sequence(adev,
 214                                                         golden_settings_tonga_a11,
 215                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 216                 break;
 217         case CHIP_POLARIS11:
 218         case CHIP_POLARIS12:
 219         case CHIP_VEGAM:
 220                 amdgpu_device_program_register_sequence(adev,
 221                                                         golden_settings_polaris11_a11,
 222                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 223                 break;
 224         case CHIP_POLARIS10:
 225                 amdgpu_device_program_register_sequence(adev,
 226                                                         golden_settings_polaris10_a11,
 227                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 228                 break;
 229         case CHIP_CARRIZO:
 230                 amdgpu_device_program_register_sequence(adev,
 231                                                         cz_mgcg_cgcg_init,
 232                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 233                 amdgpu_device_program_register_sequence(adev,
 234                                                         cz_golden_settings_a11,
 235                                                         ARRAY_SIZE(cz_golden_settings_a11));
 236                 break;
 237         case CHIP_STONEY:
 238                 amdgpu_device_program_register_sequence(adev,
 239                                                         stoney_mgcg_cgcg_init,
 240                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 241                 amdgpu_device_program_register_sequence(adev,
 242                                                         stoney_golden_settings_a11,
 243                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 244                 break;
 245         default:
 246                 break;
 247         }
 248 }
 249
 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 251 {
 252         int i;
 253         for (i = 0; i < adev->sdma.num_instances; i++) {
 254                 release_firmware(adev->sdma.instance[i].fw);
 255                 adev->sdma.instance[i].fw = NULL;
 256         }
 257 }
 258
 259 /**
 260  * sdma_v3_0_init_microcode - load ucode images from disk
 261  *
 262  * @adev: amdgpu_device pointer
 263  *
 264  * Use the firmware interface to load the ucode images into
 265  * the driver (not loaded into hw).
 266  * Returns 0 on success, error on failure.
 267  */
 268 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 269 {
 270         const char *chip_name;
 271         char fw_name[30];
 272         int err = 0, i;
 273         struct amdgpu_firmware_info *info = NULL;
 274         const struct common_firmware_header *header = NULL;
 275         const struct sdma_firmware_header_v1_0 *hdr;
 276
 277         DRM_DEBUG("\n");
 278
 279         switch (adev->asic_type) {
 280         case CHIP_TONGA:
 281                 chip_name = "tonga";
 282                 break;
 283         case CHIP_FIJI:
 284                 chip_name = "fiji";
 285                 break;
 286         case CHIP_POLARIS10:
 287                 chip_name = "polaris10";
 288                 break;
 289         case CHIP_POLARIS11:
 290                 chip_name = "polaris11";
 291                 break;
 292         case CHIP_POLARIS12:
 293                 chip_name = "polaris12";
 294                 break;
 295         case CHIP_VEGAM:
 296                 chip_name = "vegam";
 297                 break;
 298         case CHIP_CARRIZO:
 299                 chip_name = "carrizo";
 300                 break;
 301         case CHIP_STONEY:
 302                 chip_name = "stoney";
 303                 break;
 304         default: BUG();
 305         }
 306
 307         for (i = 0; i < adev->sdma.num_instances; i++) {
 308                 if (i == 0)
 309                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 310                 else
 311                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 312                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 313                 if (err)
 314                         goto out;
 315                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 316                 if (err)
 317                         goto out;
 318                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 319                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 320                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 321                 if (adev->sdma.instance[i].feature_version >= 20)
 322                         adev->sdma.instance[i].burst_nop = true;
 323
 324                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 325                 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 326                 info->fw = adev->sdma.instance[i].fw;
 327                 header = (const struct common_firmware_header *)info->fw->data;
 328                 adev->firmware.fw_size +=
 329                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 330
 331         }
 332 out:
 333         if (err) {
 334                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 335                 for (i = 0; i < adev->sdma.num_instances; i++) {
 336                         release_firmware(adev->sdma.instance[i].fw);
 337                         adev->sdma.instance[i].fw = NULL;
 338                 }
 339         }
 340         return err;
 341 }
 342
 343 /**
 344  * sdma_v3_0_ring_get_rptr - get the current read pointer
 345  *
 346  * @ring: amdgpu ring pointer
 347  *
 348  * Get the current rptr from the hardware (VI+).
 349  */
 350 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 351 {
 352         /* XXX check if swapping is necessary on BE */
 353         return *ring->rptr_cpu_addr >> 2;
 354 }
 355
 356 /**
 357  * sdma_v3_0_ring_get_wptr - get the current write pointer
 358  *
 359  * @ring: amdgpu ring pointer
 360  *
 361  * Get the current wptr from the hardware (VI+).
 362  */
 363 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         u32 wptr;
 367
 368         if (ring->use_doorbell || ring->use_pollmem) {
 369                 /* XXX check if swapping is necessary on BE */
 370                 wptr = *ring->wptr_cpu_addr >> 2;
 371         } else {
 372                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 373         }
 374
 375         return wptr;
 376 }
 377
 378 /**
 379  * sdma_v3_0_ring_set_wptr - commit the write pointer
 380  *
 381  * @ring: amdgpu ring pointer
 382  *
 383  * Write the wptr back to the hardware (VI+).
 384  */
 385 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 386 {
 387         struct amdgpu_device *adev = ring->adev;
 388
 389         if (ring->use_doorbell) {
 390                 u32 *wb = (u32 *)ring->wptr_cpu_addr;
 391                 /* XXX check if swapping is necessary on BE */
 392                 WRITE_ONCE(*wb, ring->wptr << 2);
 393                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 394         } else if (ring->use_pollmem) {
 395                 u32 *wb = (u32 *)ring->wptr_cpu_addr;
 396
 397                 WRITE_ONCE(*wb, ring->wptr << 2);
 398         } else {
 399                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
 400         }
 401 }
 402
 403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 404 {
 405         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 406         int i;
 407
 408         for (i = 0; i < count; i++)
 409                 if (sdma && sdma->burst_nop && (i == 0))
 410                         amdgpu_ring_write(ring, ring->funcs->nop |
 411                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 412                 else
 413                         amdgpu_ring_write(ring, ring->funcs->nop);
 414 }
 415
 416 /**
 417  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 418  *
 419  * @ring: amdgpu ring pointer
 420  * @job: job to retrieve vmid from
 421  * @ib: IB object to schedule
 422  * @flags: unused
 423  *
 424  * Schedule an IB in the DMA ring (VI).
 425  */
 426 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 427                                    struct amdgpu_job *job,
 428                                    struct amdgpu_ib *ib,
 429                                    uint32_t flags)
 430 {
 431         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 432
 433         /* IB packet must end on a 8 DW boundary */
 434         sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 435
 436         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 437                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 438         /* base must be 32 byte aligned */
 439         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 440         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 441         amdgpu_ring_write(ring, ib->length_dw);
 442         amdgpu_ring_write(ring, 0);
 443         amdgpu_ring_write(ring, 0);
 444
 445 }
 446
 447 /**
 448  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 449  *
 450  * @ring: amdgpu ring pointer
 451  *
 452  * Emit an hdp flush packet on the requested DMA ring.
 453  */
 454 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 455 {
 456         u32 ref_and_mask = 0;
 457
 458         if (ring->me == 0)
 459                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 460         else
 461                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 462
 463         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 464                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 465                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 466         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 467         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 468         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 469         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 470         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 471                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 472 }
 473
 474 /**
 475  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 476  *
 477  * @ring: amdgpu ring pointer
 478  * @addr: address
 479  * @seq: sequence number
 480  * @flags: fence related flags
 481  *
 482  * Add a DMA fence packet to the ring to write
 483  * the fence seq number and DMA trap packet to generate
 484  * an interrupt if needed (VI).
 485  */
 486 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 487                                       unsigned flags)
 488 {
 489         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 490         /* write the fence */
 491         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 492         amdgpu_ring_write(ring, lower_32_bits(addr));
 493         amdgpu_ring_write(ring, upper_32_bits(addr));
 494         amdgpu_ring_write(ring, lower_32_bits(seq));
 495
 496         /* optionally write high bits as well */
 497         if (write64bit) {
 498                 addr += 4;
 499                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 500                 amdgpu_ring_write(ring, lower_32_bits(addr));
 501                 amdgpu_ring_write(ring, upper_32_bits(addr));
 502                 amdgpu_ring_write(ring, upper_32_bits(seq));
 503         }
 504
 505         /* generate an interrupt */
 506         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 507         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 508 }
 509
 510 /**
 511  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 512  *
 513  * @adev: amdgpu_device pointer
 514  *
 515  * Stop the gfx async dma ring buffers (VI).
 516  */
 517 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 518 {
 519         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 520         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 521         u32 rb_cntl, ib_cntl;
 522         int i;
 523
 524         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 525             (adev->mman.buffer_funcs_ring == sdma1))
 526                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 527
 528         for (i = 0; i < adev->sdma.num_instances; i++) {
 529                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 530                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 531                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 532                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 533                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 534                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 535         }
 536 }
 537
 538 /**
 539  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 540  *
 541  * @adev: amdgpu_device pointer
 542  *
 543  * Stop the compute async dma queues (VI).
 544  */
 545 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 546 {
 547         /* XXX todo */
 548 }
 549
 550 /**
 551  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 552  *
 553  * @adev: amdgpu_device pointer
 554  * @enable: enable/disable the DMA MEs context switch.
 555  *
 556  * Halt or unhalt the async dma engines context switch (VI).
 557  */
 558 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 559 {
 560         u32 f32_cntl, phase_quantum = 0;
 561         int i;
 562
 563         if (amdgpu_sdma_phase_quantum) {
 564                 unsigned value = amdgpu_sdma_phase_quantum;
 565                 unsigned unit = 0;
 566
 567                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 568                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 569                         value = (value + 1) >> 1;
 570                         unit++;
 571                 }
 572                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 573                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 574                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 575                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 576                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 577                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 578                         WARN_ONCE(1,
 579                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 580                                   value << unit);
 581                 }
 582                 phase_quantum =
 583                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 584                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 585         }
 586
 587         for (i = 0; i < adev->sdma.num_instances; i++) {
 588                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 589                 if (enable) {
 590                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 591                                         AUTO_CTXSW_ENABLE, 1);
 592                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 593                                         ATC_L1_ENABLE, 1);
 594                         if (amdgpu_sdma_phase_quantum) {
 595                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 596                                        phase_quantum);
 597                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 598                                        phase_quantum);
 599                         }
 600                 } else {
 601                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 602                                         AUTO_CTXSW_ENABLE, 0);
 603                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 604                                         ATC_L1_ENABLE, 1);
 605                 }
 606
 607                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 608         }
 609 }
 610
 611 /**
 612  * sdma_v3_0_enable - stop the async dma engines
 613  *
 614  * @adev: amdgpu_device pointer
 615  * @enable: enable/disable the DMA MEs.
 616  *
 617  * Halt or unhalt the async dma engines (VI).
 618  */
 619 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 620 {
 621         u32 f32_cntl;
 622         int i;
 623
 624         if (!enable) {
 625                 sdma_v3_0_gfx_stop(adev);
 626                 sdma_v3_0_rlc_stop(adev);
 627         }
 628
 629         for (i = 0; i < adev->sdma.num_instances; i++) {
 630                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 631                 if (enable)
 632                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 633                 else
 634                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 635                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 636         }
 637 }
 638
 639 /**
 640  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 641  *
 642  * @adev: amdgpu_device pointer
 643  *
 644  * Set up the gfx DMA ring buffers and enable them (VI).
 645  * Returns 0 for success, error for failure.
 646  */
 647 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 648 {
 649         struct amdgpu_ring *ring;
 650         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 651         u32 rb_bufsz;
 652         u32 doorbell;
 653         u64 wptr_gpu_addr;
 654         int i, j, r;
 655
 656         for (i = 0; i < adev->sdma.num_instances; i++) {
 657                 ring = &adev->sdma.instance[i].ring;
 658                 amdgpu_ring_clear_ring(ring);
 659
 660                 mutex_lock(&adev->srbm_mutex);
 661                 for (j = 0; j < 16; j++) {
 662                         vi_srbm_select(adev, 0, 0, 0, j);
 663                         /* SDMA GFX */
 664                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 665                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 666                 }
 667                 vi_srbm_select(adev, 0, 0, 0, 0);
 668                 mutex_unlock(&adev->srbm_mutex);
 669
 670                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 671                        adev->gfx.config.gb_addr_config & 0x70);
 672
 673                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 674
 675                 /* Set ring buffer size in dwords */
 676                 rb_bufsz = order_base_2(ring->ring_size / 4);
 677                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 678                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 679 #ifdef __BIG_ENDIAN
 680                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 681                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 682                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 683 #endif
 684                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 685
 686                 /* Initialize the ring buffer's read and write pointers */
 687                 ring->wptr = 0;
 688                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 689                 sdma_v3_0_ring_set_wptr(ring);
 690                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 691                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 692
 693                 /* set the wb address whether it's enabled or not */
 694                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 695                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 696                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 697                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 698
 699                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 700
 701                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 702                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 703
 704                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 705
 706                 if (ring->use_doorbell) {
 707                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 708                                                  OFFSET, ring->doorbell_index);
 709                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 710                 } else {
 711                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 712                 }
 713                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 714
 715                 /* setup the wptr shadow polling */
 716                 wptr_gpu_addr = ring->wptr_gpu_addr;
 717
 718                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
 719                        lower_32_bits(wptr_gpu_addr));
 720                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 721                        upper_32_bits(wptr_gpu_addr));
 722                 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
 723                 if (ring->use_pollmem) {
 724                         /*wptr polling is not enogh fast, directly clean the wptr register */
 725                         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 726                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 727                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 728                                                        ENABLE, 1);
 729                 } else {
 730                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 731                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 732                                                        ENABLE, 0);
 733                 }
 734                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 735
 736                 /* enable DMA RB */
 737                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 738                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 739
 740                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 741                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 742 #ifdef __BIG_ENDIAN
 743                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 744 #endif
 745                 /* enable DMA IBs */
 746                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 747
 748                 ring->sched.ready = true;
 749         }
 750
 751         /* unhalt the MEs */
 752         sdma_v3_0_enable(adev, true);
 753         /* enable sdma ring preemption */
 754         sdma_v3_0_ctx_switch_enable(adev, true);
 755
 756         for (i = 0; i < adev->sdma.num_instances; i++) {
 757                 ring = &adev->sdma.instance[i].ring;
 758                 r = amdgpu_ring_test_helper(ring);
 759                 if (r)
 760                         return r;
 761
 762                 if (adev->mman.buffer_funcs_ring == ring)
 763                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 764         }
 765
 766         return 0;
 767 }
 768
 769 /**
 770  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 771  *
 772  * @adev: amdgpu_device pointer
 773  *
 774  * Set up the compute DMA queues and enable them (VI).
 775  * Returns 0 for success, error for failure.
 776  */
 777 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 778 {
 779         /* XXX todo */
 780         return 0;
 781 }
 782
 783 /**
 784  * sdma_v3_0_start - setup and start the async dma engines
 785  *
 786  * @adev: amdgpu_device pointer
 787  *
 788  * Set up the DMA engines and enable them (VI).
 789  * Returns 0 for success, error for failure.
 790  */
 791 static int sdma_v3_0_start(struct amdgpu_device *adev)
 792 {
 793         int r;
 794
 795         /* disable sdma engine before programing it */
 796         sdma_v3_0_ctx_switch_enable(adev, false);
 797         sdma_v3_0_enable(adev, false);
 798
 799         /* start the gfx rings and rlc compute queues */
 800         r = sdma_v3_0_gfx_resume(adev);
 801         if (r)
 802                 return r;
 803         r = sdma_v3_0_rlc_resume(adev);
 804         if (r)
 805                 return r;
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * sdma_v3_0_ring_test_ring - simple async dma engine test
 812  *
 813  * @ring: amdgpu_ring structure holding ring information
 814  *
 815  * Test the DMA engine by writing using it to write an
 816  * value to memory. (VI).
 817  * Returns 0 for success, error for failure.
 818  */
 819 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 820 {
 821         struct amdgpu_device *adev = ring->adev;
 822         unsigned i;
 823         unsigned index;
 824         int r;
 825         u32 tmp;
 826         u64 gpu_addr;
 827
 828         r = amdgpu_device_wb_get(adev, &index);
 829         if (r)
 830                 return r;
 831
 832         gpu_addr = adev->wb.gpu_addr + (index * 4);
 833         tmp = 0xCAFEDEAD;
 834         adev->wb.wb[index] = cpu_to_le32(tmp);
 835
 836         r = amdgpu_ring_alloc(ring, 5);
 837         if (r)
 838                 goto error_free_wb;
 839
 840         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 841                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 842         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 843         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 844         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 845         amdgpu_ring_write(ring, 0xDEADBEEF);
 846         amdgpu_ring_commit(ring);
 847
 848         for (i = 0; i < adev->usec_timeout; i++) {
 849                 tmp = le32_to_cpu(adev->wb.wb[index]);
 850                 if (tmp == 0xDEADBEEF)
 851                         break;
 852                 udelay(1);
 853         }
 854
 855         if (i >= adev->usec_timeout)
 856                 r = -ETIMEDOUT;
 857
 858 error_free_wb:
 859         amdgpu_device_wb_free(adev, index);
 860         return r;
 861 }
 862
 863 /**
 864  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 865  *
 866  * @ring: amdgpu_ring structure holding ring information
 867  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 868  *
 869  * Test a simple IB in the DMA ring (VI).
 870  * Returns 0 on success, error on failure.
 871  */
 872 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 873 {
 874         struct amdgpu_device *adev = ring->adev;
 875         struct amdgpu_ib ib;
 876         struct dma_fence *f = NULL;
 877         unsigned index;
 878         u32 tmp = 0;
 879         u64 gpu_addr;
 880         long r;
 881
 882         r = amdgpu_device_wb_get(adev, &index);
 883         if (r)
 884                 return r;
 885
 886         gpu_addr = adev->wb.gpu_addr + (index * 4);
 887         tmp = 0xCAFEDEAD;
 888         adev->wb.wb[index] = cpu_to_le32(tmp);
 889         memset(&ib, 0, sizeof(ib));
 890         r = amdgpu_ib_get(adev, NULL, 256,
 891                                         AMDGPU_IB_POOL_DIRECT, &ib);
 892         if (r)
 893                 goto err0;
 894
 895         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 896                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 897         ib.ptr[1] = lower_32_bits(gpu_addr);
 898         ib.ptr[2] = upper_32_bits(gpu_addr);
 899         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 900         ib.ptr[4] = 0xDEADBEEF;
 901         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 902         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 903         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 904         ib.length_dw = 8;
 905
 906         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 907         if (r)
 908                 goto err1;
 909
 910         r = dma_fence_wait_timeout(f, false, timeout);
 911         if (r == 0) {
 912                 r = -ETIMEDOUT;
 913                 goto err1;
 914         } else if (r < 0) {
 915                 goto err1;
 916         }
 917         tmp = le32_to_cpu(adev->wb.wb[index]);
 918         if (tmp == 0xDEADBEEF)
 919                 r = 0;
 920         else
 921                 r = -EINVAL;
 922 err1:
 923         amdgpu_ib_free(adev, &ib, NULL);
 924         dma_fence_put(f);
 925 err0:
 926         amdgpu_device_wb_free(adev, index);
 927         return r;
 928 }
 929
 930 /**
 931  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 932  *
 933  * @ib: indirect buffer to fill with commands
 934  * @pe: addr of the page entry
 935  * @src: src addr to copy from
 936  * @count: number of page entries to update
 937  *
 938  * Update PTEs by copying them from the GART using sDMA (CIK).
 939  */
 940 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 941                                   uint64_t pe, uint64_t src,
 942                                   unsigned count)
 943 {
 944         unsigned bytes = count * 8;
 945
 946         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 947                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 948         ib->ptr[ib->length_dw++] = bytes;
 949         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 950         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 951         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 952         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 953         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 954 }
 955
 956 /**
 957  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 958  *
 959  * @ib: indirect buffer to fill with commands
 960  * @pe: addr of the page entry
 961  * @value: dst addr to write into pe
 962  * @count: number of page entries to update
 963  * @incr: increase next addr by incr bytes
 964  *
 965  * Update PTEs by writing them manually using sDMA (CIK).
 966  */
 967 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 968                                    uint64_t value, unsigned count,
 969                                    uint32_t incr)
 970 {
 971         unsigned ndw = count * 2;
 972
 973         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 974                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 975         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 976         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 977         ib->ptr[ib->length_dw++] = ndw;
 978         for (; ndw > 0; ndw -= 2) {
 979                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 980                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 981                 value += incr;
 982         }
 983 }
 984
 985 /**
 986  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 987  *
 988  * @ib: indirect buffer to fill with commands
 989  * @pe: addr of the page entry
 990  * @addr: dst addr to write into pe
 991  * @count: number of page entries to update
 992  * @incr: increase next addr by incr bytes
 993  * @flags: access flags
 994  *
 995  * Update the page tables using sDMA (CIK).
 996  */
 997 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 998                                      uint64_t addr, unsigned count,
 999                                      uint32_t incr, uint64_t flags)
1000 {
1001         /* for physically contiguous pages (vram) */
1002         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1003         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1004         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1005         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1006         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1007         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1008         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1009         ib->ptr[ib->length_dw++] = incr; /* increment size */
1010         ib->ptr[ib->length_dw++] = 0;
1011         ib->ptr[ib->length_dw++] = count; /* number of entries */
1012 }
1013
1014 /**
1015  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1016  *
1017  * @ring: amdgpu_ring structure holding ring information
1018  * @ib: indirect buffer to fill with padding
1019  *
1020  */
1021 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1022 {
1023         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1024         u32 pad_count;
1025         int i;
1026
1027         pad_count = (-ib->length_dw) & 7;
1028         for (i = 0; i < pad_count; i++)
1029                 if (sdma && sdma->burst_nop && (i == 0))
1030                         ib->ptr[ib->length_dw++] =
1031                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1032                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1033                 else
1034                         ib->ptr[ib->length_dw++] =
1035                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1036 }
1037
1038 /**
1039  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1040  *
1041  * @ring: amdgpu_ring pointer
1042  *
1043  * Make sure all previous operations are completed (CIK).
1044  */
1045 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1046 {
1047         uint32_t seq = ring->fence_drv.sync_seq;
1048         uint64_t addr = ring->fence_drv.gpu_addr;
1049
1050         /* wait for idle */
1051         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1052                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1053                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1054                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1055         amdgpu_ring_write(ring, addr & 0xfffffffc);
1056         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1057         amdgpu_ring_write(ring, seq); /* reference */
1058         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1059         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1060                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1061 }
1062
1063 /**
1064  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1065  *
1066  * @ring: amdgpu_ring pointer
1067  * @vmid: vmid number to use
1068  * @pd_addr: address
1069  *
1070  * Update the page table base and flush the VM TLB
1071  * using sDMA (VI).
1072  */
1073 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1074                                          unsigned vmid, uint64_t pd_addr)
1075 {
1076         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1077
1078         /* wait for flush */
1079         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1080                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1081                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1082         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1083         amdgpu_ring_write(ring, 0);
1084         amdgpu_ring_write(ring, 0); /* reference */
1085         amdgpu_ring_write(ring, 0); /* mask */
1086         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1087                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1088 }
1089
1090 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1091                                      uint32_t reg, uint32_t val)
1092 {
1093         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1094                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1095         amdgpu_ring_write(ring, reg);
1096         amdgpu_ring_write(ring, val);
1097 }
1098
1099 static int sdma_v3_0_early_init(void *handle)
1100 {
1101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102
1103         switch (adev->asic_type) {
1104         case CHIP_STONEY:
1105                 adev->sdma.num_instances = 1;
1106                 break;
1107         default:
1108                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1109                 break;
1110         }
1111
1112         sdma_v3_0_set_ring_funcs(adev);
1113         sdma_v3_0_set_buffer_funcs(adev);
1114         sdma_v3_0_set_vm_pte_funcs(adev);
1115         sdma_v3_0_set_irq_funcs(adev);
1116
1117         return 0;
1118 }
1119
1120 static int sdma_v3_0_sw_init(void *handle)
1121 {
1122         struct amdgpu_ring *ring;
1123         int r, i;
1124         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1125
1126         /* SDMA trap event */
1127         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1128                               &adev->sdma.trap_irq);
1129         if (r)
1130                 return r;
1131
1132         /* SDMA Privileged inst */
1133         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1134                               &adev->sdma.illegal_inst_irq);
1135         if (r)
1136                 return r;
1137
1138         /* SDMA Privileged inst */
1139         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1140                               &adev->sdma.illegal_inst_irq);
1141         if (r)
1142                 return r;
1143
1144         r = sdma_v3_0_init_microcode(adev);
1145         if (r) {
1146                 DRM_ERROR("Failed to load sdma firmware!\n");
1147                 return r;
1148         }
1149
1150         for (i = 0; i < adev->sdma.num_instances; i++) {
1151                 ring = &adev->sdma.instance[i].ring;
1152                 ring->ring_obj = NULL;
1153                 if (!amdgpu_sriov_vf(adev)) {
1154                         ring->use_doorbell = true;
1155                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1156                 } else {
1157                         ring->use_pollmem = true;
1158                 }
1159
1160                 sprintf(ring->name, "sdma%d", i);
1161                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1162                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1163                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1164                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1165                 if (r)
1166                         return r;
1167         }
1168
1169         return r;
1170 }
1171
1172 static int sdma_v3_0_sw_fini(void *handle)
1173 {
1174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175         int i;
1176
1177         for (i = 0; i < adev->sdma.num_instances; i++)
1178                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1179
1180         sdma_v3_0_free_microcode(adev);
1181         return 0;
1182 }
1183
1184 static int sdma_v3_0_hw_init(void *handle)
1185 {
1186         int r;
1187         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1188
1189         sdma_v3_0_init_golden_registers(adev);
1190
1191         r = sdma_v3_0_start(adev);
1192         if (r)
1193                 return r;
1194
1195         return r;
1196 }
1197
1198 static int sdma_v3_0_hw_fini(void *handle)
1199 {
1200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1201
1202         sdma_v3_0_ctx_switch_enable(adev, false);
1203         sdma_v3_0_enable(adev, false);
1204
1205         return 0;
1206 }
1207
1208 static int sdma_v3_0_suspend(void *handle)
1209 {
1210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211
1212         return sdma_v3_0_hw_fini(adev);
1213 }
1214
1215 static int sdma_v3_0_resume(void *handle)
1216 {
1217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218
1219         return sdma_v3_0_hw_init(adev);
1220 }
1221
1222 static bool sdma_v3_0_is_idle(void *handle)
1223 {
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225         u32 tmp = RREG32(mmSRBM_STATUS2);
1226
1227         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1228                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1229             return false;
1230
1231         return true;
1232 }
1233
1234 static int sdma_v3_0_wait_for_idle(void *handle)
1235 {
1236         unsigned i;
1237         u32 tmp;
1238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1239
1240         for (i = 0; i < adev->usec_timeout; i++) {
1241                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1242                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1243
1244                 if (!tmp)
1245                         return 0;
1246                 udelay(1);
1247         }
1248         return -ETIMEDOUT;
1249 }
1250
1251 static bool sdma_v3_0_check_soft_reset(void *handle)
1252 {
1253         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1254         u32 srbm_soft_reset = 0;
1255         u32 tmp = RREG32(mmSRBM_STATUS2);
1256
1257         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1258             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1259                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1260                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1261         }
1262
1263         if (srbm_soft_reset) {
1264                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1265                 return true;
1266         } else {
1267                 adev->sdma.srbm_soft_reset = 0;
1268                 return false;
1269         }
1270 }
1271
1272 static int sdma_v3_0_pre_soft_reset(void *handle)
1273 {
1274         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275         u32 srbm_soft_reset = 0;
1276
1277         if (!adev->sdma.srbm_soft_reset)
1278                 return 0;
1279
1280         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1281
1282         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1283             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1284                 sdma_v3_0_ctx_switch_enable(adev, false);
1285                 sdma_v3_0_enable(adev, false);
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int sdma_v3_0_post_soft_reset(void *handle)
1292 {
1293         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294         u32 srbm_soft_reset = 0;
1295
1296         if (!adev->sdma.srbm_soft_reset)
1297                 return 0;
1298
1299         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1300
1301         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1302             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1303                 sdma_v3_0_gfx_resume(adev);
1304                 sdma_v3_0_rlc_resume(adev);
1305         }
1306
1307         return 0;
1308 }
1309
1310 static int sdma_v3_0_soft_reset(void *handle)
1311 {
1312         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313         u32 srbm_soft_reset = 0;
1314         u32 tmp;
1315
1316         if (!adev->sdma.srbm_soft_reset)
1317                 return 0;
1318
1319         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1320
1321         if (srbm_soft_reset) {
1322                 tmp = RREG32(mmSRBM_SOFT_RESET);
1323                 tmp |= srbm_soft_reset;
1324                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1325                 WREG32(mmSRBM_SOFT_RESET, tmp);
1326                 tmp = RREG32(mmSRBM_SOFT_RESET);
1327
1328                 udelay(50);
1329
1330                 tmp &= ~srbm_soft_reset;
1331                 WREG32(mmSRBM_SOFT_RESET, tmp);
1332                 tmp = RREG32(mmSRBM_SOFT_RESET);
1333
1334                 /* Wait a little for things to settle down */
1335                 udelay(50);
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1342                                         struct amdgpu_irq_src *source,
1343                                         unsigned type,
1344                                         enum amdgpu_interrupt_state state)
1345 {
1346         u32 sdma_cntl;
1347
1348         switch (type) {
1349         case AMDGPU_SDMA_IRQ_INSTANCE0:
1350                 switch (state) {
1351                 case AMDGPU_IRQ_STATE_DISABLE:
1352                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1353                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1354                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1355                         break;
1356                 case AMDGPU_IRQ_STATE_ENABLE:
1357                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1358                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1359                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1360                         break;
1361                 default:
1362                         break;
1363                 }
1364                 break;
1365         case AMDGPU_SDMA_IRQ_INSTANCE1:
1366                 switch (state) {
1367                 case AMDGPU_IRQ_STATE_DISABLE:
1368                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1369                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1370                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1371                         break;
1372                 case AMDGPU_IRQ_STATE_ENABLE:
1373                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1374                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1375                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1376                         break;
1377                 default:
1378                         break;
1379                 }
1380                 break;
1381         default:
1382                 break;
1383         }
1384         return 0;
1385 }
1386
1387 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1388                                       struct amdgpu_irq_src *source,
1389                                       struct amdgpu_iv_entry *entry)
1390 {
1391         u8 instance_id, queue_id;
1392
1393         instance_id = (entry->ring_id & 0x3) >> 0;
1394         queue_id = (entry->ring_id & 0xc) >> 2;
1395         DRM_DEBUG("IH: SDMA trap\n");
1396         switch (instance_id) {
1397         case 0:
1398                 switch (queue_id) {
1399                 case 0:
1400                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1401                         break;
1402                 case 1:
1403                         /* XXX compute */
1404                         break;
1405                 case 2:
1406                         /* XXX compute */
1407                         break;
1408                 }
1409                 break;
1410         case 1:
1411                 switch (queue_id) {
1412                 case 0:
1413                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1414                         break;
1415                 case 1:
1416                         /* XXX compute */
1417                         break;
1418                 case 2:
1419                         /* XXX compute */
1420                         break;
1421                 }
1422                 break;
1423         }
1424         return 0;
1425 }
1426
1427 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1428                                               struct amdgpu_irq_src *source,
1429                                               struct amdgpu_iv_entry *entry)
1430 {
1431         u8 instance_id, queue_id;
1432
1433         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1434         instance_id = (entry->ring_id & 0x3) >> 0;
1435         queue_id = (entry->ring_id & 0xc) >> 2;
1436
1437         if (instance_id <= 1 && queue_id == 0)
1438                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1439         return 0;
1440 }
1441
1442 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1443                 struct amdgpu_device *adev,
1444                 bool enable)
1445 {
1446         uint32_t temp, data;
1447         int i;
1448
1449         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1450                 for (i = 0; i < adev->sdma.num_instances; i++) {
1451                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1452                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1453                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1454                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1455                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1456                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1457                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1458                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1459                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1460                         if (data != temp)
1461                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1462                 }
1463         } else {
1464                 for (i = 0; i < adev->sdma.num_instances; i++) {
1465                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1466                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1467                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1468                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1469                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1470                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1471                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1472                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1473                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1474
1475                         if (data != temp)
1476                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1477                 }
1478         }
1479 }
1480
1481 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1482                 struct amdgpu_device *adev,
1483                 bool enable)
1484 {
1485         uint32_t temp, data;
1486         int i;
1487
1488         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1489                 for (i = 0; i < adev->sdma.num_instances; i++) {
1490                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1491                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1492
1493                         if (temp != data)
1494                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1495                 }
1496         } else {
1497                 for (i = 0; i < adev->sdma.num_instances; i++) {
1498                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1499                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1500
1501                         if (temp != data)
1502                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1503                 }
1504         }
1505 }
1506
1507 static int sdma_v3_0_set_clockgating_state(void *handle,
1508                                           enum amd_clockgating_state state)
1509 {
1510         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1511
1512         if (amdgpu_sriov_vf(adev))
1513                 return 0;
1514
1515         switch (adev->asic_type) {
1516         case CHIP_FIJI:
1517         case CHIP_CARRIZO:
1518         case CHIP_STONEY:
1519                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1520                                 state == AMD_CG_STATE_GATE);
1521                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1522                                 state == AMD_CG_STATE_GATE);
1523                 break;
1524         default:
1525                 break;
1526         }
1527         return 0;
1528 }
1529
1530 static int sdma_v3_0_set_powergating_state(void *handle,
1531                                           enum amd_powergating_state state)
1532 {
1533         return 0;
1534 }
1535
1536 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)
1537 {
1538         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1539         int data;
1540
1541         if (amdgpu_sriov_vf(adev))
1542                 *flags = 0;
1543
1544         /* AMD_CG_SUPPORT_SDMA_MGCG */
1545         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1546         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1547                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1548
1549         /* AMD_CG_SUPPORT_SDMA_LS */
1550         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1551         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1552                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1553 }
1554
1555 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1556         .name = "sdma_v3_0",
1557         .early_init = sdma_v3_0_early_init,
1558         .late_init = NULL,
1559         .sw_init = sdma_v3_0_sw_init,
1560         .sw_fini = sdma_v3_0_sw_fini,
1561         .hw_init = sdma_v3_0_hw_init,
1562         .hw_fini = sdma_v3_0_hw_fini,
1563         .suspend = sdma_v3_0_suspend,
1564         .resume = sdma_v3_0_resume,
1565         .is_idle = sdma_v3_0_is_idle,
1566         .wait_for_idle = sdma_v3_0_wait_for_idle,
1567         .check_soft_reset = sdma_v3_0_check_soft_reset,
1568         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1569         .post_soft_reset = sdma_v3_0_post_soft_reset,
1570         .soft_reset = sdma_v3_0_soft_reset,
1571         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1572         .set_powergating_state = sdma_v3_0_set_powergating_state,
1573         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1574 };
1575
1576 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1577         .type = AMDGPU_RING_TYPE_SDMA,
1578         .align_mask = 0xf,
1579         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1580         .support_64bit_ptrs = false,
1581         .secure_submission_supported = true,
1582         .get_rptr = sdma_v3_0_ring_get_rptr,
1583         .get_wptr = sdma_v3_0_ring_get_wptr,
1584         .set_wptr = sdma_v3_0_ring_set_wptr,
1585         .emit_frame_size =
1586                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1587                 3 + /* hdp invalidate */
1588                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1589                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1590                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1591         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1592         .emit_ib = sdma_v3_0_ring_emit_ib,
1593         .emit_fence = sdma_v3_0_ring_emit_fence,
1594         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1595         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1596         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1597         .test_ring = sdma_v3_0_ring_test_ring,
1598         .test_ib = sdma_v3_0_ring_test_ib,
1599         .insert_nop = sdma_v3_0_ring_insert_nop,
1600         .pad_ib = sdma_v3_0_ring_pad_ib,
1601         .emit_wreg = sdma_v3_0_ring_emit_wreg,
1602 };
1603
1604 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1605 {
1606         int i;
1607
1608         for (i = 0; i < adev->sdma.num_instances; i++) {
1609                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1610                 adev->sdma.instance[i].ring.me = i;
1611         }
1612 }
1613
1614 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1615         .set = sdma_v3_0_set_trap_irq_state,
1616         .process = sdma_v3_0_process_trap_irq,
1617 };
1618
1619 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1620         .process = sdma_v3_0_process_illegal_inst_irq,
1621 };
1622
1623 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1624 {
1625         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1626         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1627         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1628 }
1629
1630 /**
1631  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1632  *
1633  * @ib: indirect buffer to copy to
1634  * @src_offset: src GPU address
1635  * @dst_offset: dst GPU address
1636  * @byte_count: number of bytes to xfer
1637  * @tmz: unused
1638  *
1639  * Copy GPU buffers using the DMA engine (VI).
1640  * Used by the amdgpu ttm implementation to move pages if
1641  * registered as the asic copy callback.
1642  */
1643 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1644                                        uint64_t src_offset,
1645                                        uint64_t dst_offset,
1646                                        uint32_t byte_count,
1647                                        bool tmz)
1648 {
1649         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1650                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1651         ib->ptr[ib->length_dw++] = byte_count;
1652         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1653         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1654         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1655         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1656         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1657 }
1658
1659 /**
1660  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1661  *
1662  * @ib: indirect buffer to copy to
1663  * @src_data: value to write to buffer
1664  * @dst_offset: dst GPU address
1665  * @byte_count: number of bytes to xfer
1666  *
1667  * Fill GPU buffers using the DMA engine (VI).
1668  */
1669 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1670                                        uint32_t src_data,
1671                                        uint64_t dst_offset,
1672                                        uint32_t byte_count)
1673 {
1674         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1675         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1676         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1677         ib->ptr[ib->length_dw++] = src_data;
1678         ib->ptr[ib->length_dw++] = byte_count;
1679 }
1680
1681 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1682         .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1683         .copy_num_dw = 7,
1684         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1685
1686         .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1687         .fill_num_dw = 5,
1688         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1689 };
1690
1691 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1692 {
1693         adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1694         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1695 }
1696
1697 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1698         .copy_pte_num_dw = 7,
1699         .copy_pte = sdma_v3_0_vm_copy_pte,
1700
1701         .write_pte = sdma_v3_0_vm_write_pte,
1702         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1703 };
1704
1705 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1706 {
1707         unsigned i;
1708
1709         adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1710         for (i = 0; i < adev->sdma.num_instances; i++) {
1711                 adev->vm_manager.vm_pte_scheds[i] =
1712                          &adev->sdma.instance[i].ring.sched;
1713         }
1714         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1715 }
1716
1717 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1718 {
1719         .type = AMD_IP_BLOCK_TYPE_SDMA,
1720         .major = 3,
1721         .minor = 0,
1722         .rev = 0,
1723         .funcs = &sdma_v3_0_ip_funcs,
1724 };
1725
1726 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1727 {
1728         .type = AMD_IP_BLOCK_TYPE_SDMA,
1729         .major = 3,
1730         .minor = 1,
1731         .rev = 0,
1732         .funcs = &sdma_v3_0_ip_funcs,
1733 };