drivers/gpu/drm/meson/meson_vclk.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <[email protected]>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <drm/drmP.h>
  23 #include "meson_drv.h"
  24 #include "meson_vclk.h"
  25
  26 /**
  27  * DOC: Video Clocks
  28  *
  29  * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
  30  * We handle the following encodings :
  31  *
  32  * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
  33  * - HDMI Pixel Clocks generation
  34  *
  35  * What is missing :
  36  *
  37  * - Genenate Pixel clocks for 2K/4K 10bit formats
  38  *
  39  * Clock generator scheme :
  40  *
  41  * .. code::
  42  *
  43  *    __________   _________            _____
  44  *   |          | |         |          |     |--ENCI
  45  *   | HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL
  46  *   |__________| |_________| \        | MUX |--ENCP
  47  *                             --VCLK2-|     |--VDAC
  48  *                                     |_____|--HDMI-TX
  49  *
  50  * Final clocks can take input for either VCLK or VCLK2, but
  51  * VCLK is the preferred path for HDMI clocking and VCLK2 is the
  52  * preferred path for CVBS VDAC clocking.
  53  *
  54  * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
  55  *
  56  * The PLL_DIV can achieve an additional fractional dividing like
  57  * 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
  58  */
  59
  60 /* HHI Registers */
  61 #define HHI_VID_PLL_CLK_DIV     0x1a0 /* 0x68 offset in data sheet */
  62 #define VID_PLL_EN              BIT(19)
  63 #define VID_PLL_BYPASS          BIT(18)
  64 #define VID_PLL_PRESET          BIT(15)
  65 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
  66 #define VCLK2_DIV_MASK          0xff
  67 #define VCLK2_DIV_EN            BIT(16)
  68 #define VCLK2_DIV_RESET         BIT(17)
  69 #define CTS_VDAC_SEL_MASK       (0xf << 28)
  70 #define CTS_VDAC_SEL_SHIFT      28
  71 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
  72 #define VCLK2_EN                BIT(19)
  73 #define VCLK2_SEL_MASK          (0x7 << 16)
  74 #define VCLK2_SEL_SHIFT         16
  75 #define VCLK2_SOFT_RESET        BIT(15)
  76 #define VCLK2_DIV1_EN           BIT(0)
  77 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
  78 #define VCLK_DIV_MASK           0xff
  79 #define VCLK_DIV_EN             BIT(16)
  80 #define VCLK_DIV_RESET          BIT(17)
  81 #define CTS_ENCP_SEL_MASK       (0xf << 24)
  82 #define CTS_ENCP_SEL_SHIFT      24
  83 #define CTS_ENCI_SEL_MASK       (0xf << 28)
  84 #define CTS_ENCI_SEL_SHIFT      28
  85 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
  86 #define VCLK_EN                 BIT(19)
  87 #define VCLK_SEL_MASK           (0x7 << 16)
  88 #define VCLK_SEL_SHIFT          16
  89 #define VCLK_SOFT_RESET         BIT(15)
  90 #define VCLK_DIV1_EN            BIT(0)
  91 #define VCLK_DIV2_EN            BIT(1)
  92 #define VCLK_DIV4_EN            BIT(2)
  93 #define VCLK_DIV6_EN            BIT(3)
  94 #define VCLK_DIV12_EN           BIT(4)
  95 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
  96 #define CTS_ENCI_EN             BIT(0)
  97 #define CTS_ENCP_EN             BIT(2)
  98 #define CTS_VDAC_EN             BIT(4)
  99 #define HDMI_TX_PIXEL_EN        BIT(5)
 100 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
 101 #define HDMI_TX_PIXEL_SEL_MASK  (0xf << 16)
 102 #define HDMI_TX_PIXEL_SEL_SHIFT 16
 103 #define CTS_HDMI_SYS_SEL_MASK   (0x7 << 9)
 104 #define CTS_HDMI_SYS_DIV_MASK   (0x7f)
 105 #define CTS_HDMI_SYS_EN         BIT(8)
 106
 107 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
 108 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
 109
 110 #define HHI_HDMI_PLL_CNTL       0x320 /* 0xc8 offset in data sheet */
 111 #define HHI_HDMI_PLL_CNTL2      0x324 /* 0xc9 offset in data sheet */
 112 #define HHI_HDMI_PLL_CNTL3      0x328 /* 0xca offset in data sheet */
 113 #define HHI_HDMI_PLL_CNTL4      0x32C /* 0xcb offset in data sheet */
 114 #define HHI_HDMI_PLL_CNTL5      0x330 /* 0xcc offset in data sheet */
 115 #define HHI_HDMI_PLL_CNTL6      0x334 /* 0xcd offset in data sheet */
 116
 117 #define HDMI_PLL_RESET          BIT(28)
 118 #define HDMI_PLL_LOCK           BIT(31)
 119
 120 /* VID PLL Dividers */
 121 enum {
 122         VID_PLL_DIV_1 = 0,
 123         VID_PLL_DIV_2,
 124         VID_PLL_DIV_2p5,
 125         VID_PLL_DIV_3,
 126         VID_PLL_DIV_3p5,
 127         VID_PLL_DIV_3p75,
 128         VID_PLL_DIV_4,
 129         VID_PLL_DIV_5,
 130         VID_PLL_DIV_6,
 131         VID_PLL_DIV_6p25,
 132         VID_PLL_DIV_7,
 133         VID_PLL_DIV_7p5,
 134         VID_PLL_DIV_12,
 135         VID_PLL_DIV_14,
 136         VID_PLL_DIV_15,
 137 };
 138
 139 void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
 140 {
 141         unsigned int shift_val = 0;
 142         unsigned int shift_sel = 0;
 143
 144         /* Disable vid_pll output clock */
 145         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
 146         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
 147
 148         switch (div) {
 149         case VID_PLL_DIV_2:
 150                 shift_val = 0x0aaa;
 151                 shift_sel = 0;
 152                 break;
 153         case VID_PLL_DIV_2p5:
 154                 shift_val = 0x5294;
 155                 shift_sel = 2;
 156                 break;
 157         case VID_PLL_DIV_3:
 158                 shift_val = 0x0db6;
 159                 shift_sel = 0;
 160                 break;
 161         case VID_PLL_DIV_3p5:
 162                 shift_val = 0x36cc;
 163                 shift_sel = 1;
 164                 break;
 165         case VID_PLL_DIV_3p75:
 166                 shift_val = 0x6666;
 167                 shift_sel = 2;
 168                 break;
 169         case VID_PLL_DIV_4:
 170                 shift_val = 0x0ccc;
 171                 shift_sel = 0;
 172                 break;
 173         case VID_PLL_DIV_5:
 174                 shift_val = 0x739c;
 175                 shift_sel = 2;
 176                 break;
 177         case VID_PLL_DIV_6:
 178                 shift_val = 0x0e38;
 179                 shift_sel = 0;
 180                 break;
 181         case VID_PLL_DIV_6p25:
 182                 shift_val = 0x0000;
 183                 shift_sel = 3;
 184                 break;
 185         case VID_PLL_DIV_7:
 186                 shift_val = 0x3c78;
 187                 shift_sel = 1;
 188                 break;
 189         case VID_PLL_DIV_7p5:
 190                 shift_val = 0x78f0;
 191                 shift_sel = 2;
 192                 break;
 193         case VID_PLL_DIV_12:
 194                 shift_val = 0x0fc0;
 195                 shift_sel = 0;
 196                 break;
 197         case VID_PLL_DIV_14:
 198                 shift_val = 0x3f80;
 199                 shift_sel = 1;
 200                 break;
 201         case VID_PLL_DIV_15:
 202                 shift_val = 0x7f80;
 203                 shift_sel = 2;
 204                 break;
 205         }
 206
 207         if (div == VID_PLL_DIV_1)
 208                 /* Enable vid_pll bypass to HDMI pll */
 209                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 210                                    VID_PLL_BYPASS, VID_PLL_BYPASS);
 211         else {
 212                 /* Disable Bypass */
 213                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 214                                    VID_PLL_BYPASS, 0);
 215                 /* Clear sel */
 216                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 217                                    3 << 16, 0);
 218                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 219                                    VID_PLL_PRESET, 0);
 220                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 221                                    0x7fff, 0);
 222
 223                 /* Setup sel and val */
 224                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 225                                    3 << 16, shift_sel << 16);
 226                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 227                                    VID_PLL_PRESET, VID_PLL_PRESET);
 228                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 229                                    0x7fff, shift_val);
 230
 231                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 232                                    VID_PLL_PRESET, 0);
 233         }
 234
 235         /* Enable the vid_pll output clock */
 236         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 237                                 VID_PLL_EN, VID_PLL_EN);
 238 }
 239
 240 /*
 241  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
 242  *
 243  * TOFIX: Refactor into table to also handle HDMI frequency and paths
 244  */
 245 static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
 246 {
 247         unsigned int val;
 248
 249         /* Setup PLL to output 1.485GHz */
 250         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 251                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
 252                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
 253                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 254                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 255                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 256                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 257                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
 258         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 259                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 260                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
 261                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
 262                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
 263                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
 264                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 265                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 266
 267                 /* Reset PLL */
 268                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 269                                         HDMI_PLL_RESET, HDMI_PLL_RESET);
 270                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 271                                         HDMI_PLL_RESET, 0);
 272         }
 273
 274         /* Poll for lock bit */
 275         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 276                                  (val & HDMI_PLL_LOCK), 10, 0);
 277
 278         /* Disable VCLK2 */
 279         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
 280
 281         /* Setup vid_pll to /1 */
 282         meson_vid_pll_set(priv, VID_PLL_DIV_1);
 283
 284         /* Setup the VCLK2 divider value to achieve 27MHz */
 285         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 286                                 VCLK2_DIV_MASK, (55 - 1));
 287
 288         /* select vid_pll for vclk2 */
 289         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 290                                 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
 291         /* enable vclk2 gate */
 292         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
 293
 294         /* select vclk_div1 for enci */
 295         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 296                                 CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
 297         /* select vclk_div1 for vdac */
 298         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 299                                 CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
 300
 301         /* release vclk2_div_reset and enable vclk2_div */
 302         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 303                                 VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
 304
 305         /* enable vclk2_div1 gate */
 306         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 307                                 VCLK2_DIV1_EN, VCLK2_DIV1_EN);
 308
 309         /* reset vclk2 */
 310         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 311                                 VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 312         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 313                                 VCLK2_SOFT_RESET, 0);
 314
 315         /* enable enci_clk */
 316         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 317                                 CTS_ENCI_EN, CTS_ENCI_EN);
 318         /* enable vdac_clk */
 319         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 320                                 CTS_VDAC_EN, CTS_VDAC_EN);
 321 }
 322
 323
 324 /* PLL  O1 O2 O3 VP DV     EN TX */
 325 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
 326 #define MESON_VCLK_HDMI_ENCI_54000      1
 327 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
 328 #define MESON_VCLK_HDMI_DDR_54000       2
 329 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 330 #define MESON_VCLK_HDMI_DDR_148500      3
 331 /* 4028 /4 /4 /1 /5 /2  => /1 /1 */
 332 #define MESON_VCLK_HDMI_25175           4
 333 /* 3200 /4 /2 /1 /5 /2  => /1 /1 */
 334 #define MESON_VCLK_HDMI_40000           5
 335 /* 5200 /4 /2 /1 /5 /2  => /1 /1 */
 336 #define MESON_VCLK_HDMI_65000           6
 337 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
 338 #define MESON_VCLK_HDMI_74250           7
 339 /* 4320 /4 /1 /1 /5 /2  => /1 /1 */
 340 #define MESON_VCLK_HDMI_108000          8
 341 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
 342 #define MESON_VCLK_HDMI_148500          9
 343 /* 3240 /2 /1 /1 /5 /2  => /1 /1 */
 344 #define MESON_VCLK_HDMI_162000          10
 345 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
 346 #define MESON_VCLK_HDMI_297000          11
 347 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
 348 #define MESON_VCLK_HDMI_594000          12
 349
 350 struct meson_vclk_params {
 351         unsigned int pll_base_freq;
 352         unsigned int pll_od1;
 353         unsigned int pll_od2;
 354         unsigned int pll_od3;
 355         unsigned int vid_pll_div;
 356         unsigned int vclk_div;
 357 } params[] = {
 358         [MESON_VCLK_HDMI_ENCI_54000] = {
 359                 .pll_base_freq = 4320000,
 360                 .pll_od1 = 4,
 361                 .pll_od2 = 4,
 362                 .pll_od3 = 1,
 363                 .vid_pll_div = VID_PLL_DIV_5,
 364                 .vclk_div = 1,
 365         },
 366         [MESON_VCLK_HDMI_DDR_54000] = {
 367                 .pll_base_freq = 4320000,
 368                 .pll_od1 = 4,
 369                 .pll_od2 = 4,
 370                 .pll_od3 = 1,
 371                 .vid_pll_div = VID_PLL_DIV_5,
 372                 .vclk_div = 1,
 373         },
 374         [MESON_VCLK_HDMI_DDR_148500] = {
 375                 .pll_base_freq = 2970000,
 376                 .pll_od1 = 4,
 377                 .pll_od2 = 1,
 378                 .pll_od3 = 1,
 379                 .vid_pll_div = VID_PLL_DIV_5,
 380                 .vclk_div = 1,
 381         },
 382         [MESON_VCLK_HDMI_74250] = {
 383                 .pll_base_freq = 2970000,
 384                 .pll_od1 = 2,
 385                 .pll_od2 = 2,
 386                 .pll_od3 = 2,
 387                 .vid_pll_div = VID_PLL_DIV_5,
 388                 .vclk_div = 1,
 389         },
 390         [MESON_VCLK_HDMI_148500] = {
 391                 .pll_base_freq = 2970000,
 392                 .pll_od1 = 1,
 393                 .pll_od2 = 2,
 394                 .pll_od3 = 2,
 395                 .vid_pll_div = VID_PLL_DIV_5,
 396                 .vclk_div = 1,
 397         },
 398         [MESON_VCLK_HDMI_297000] = {
 399                 .pll_base_freq = 2970000,
 400                 .pll_od1 = 1,
 401                 .pll_od2 = 1,
 402                 .pll_od3 = 1,
 403                 .vid_pll_div = VID_PLL_DIV_5,
 404                 .vclk_div = 2,
 405         },
 406         [MESON_VCLK_HDMI_594000] = {
 407                 .pll_base_freq = 5940000,
 408                 .pll_od1 = 1,
 409                 .pll_od2 = 1,
 410                 .pll_od3 = 2,
 411                 .vid_pll_div = VID_PLL_DIV_5,
 412                 .vclk_div = 1,
 413         },
 414         [MESON_VCLK_HDMI_25175] = {
 415                 .pll_base_freq = 4028000,
 416                 .pll_od1 = 4,
 417                 .pll_od2 = 4,
 418                 .pll_od3 = 1,
 419                 .vid_pll_div = VID_PLL_DIV_5,
 420                 .vclk_div = 2,
 421         },
 422         [MESON_VCLK_HDMI_40000] = {
 423                 .pll_base_freq = 3200000,
 424                 .pll_od1 = 4,
 425                 .pll_od2 = 2,
 426                 .pll_od3 = 1,
 427                 .vid_pll_div = VID_PLL_DIV_5,
 428                 .vclk_div = 2,
 429         },
 430         [MESON_VCLK_HDMI_65000] = {
 431                 .pll_base_freq = 5200000,
 432                 .pll_od1 = 4,
 433                 .pll_od2 = 2,
 434                 .pll_od3 = 1,
 435                 .vid_pll_div = VID_PLL_DIV_5,
 436                 .vclk_div = 2,
 437         },
 438         [MESON_VCLK_HDMI_108000] = {
 439                 .pll_base_freq = 4320000,
 440                 .pll_od1 = 4,
 441                 .pll_od2 = 1,
 442                 .pll_od3 = 1,
 443                 .vid_pll_div = VID_PLL_DIV_5,
 444                 .vclk_div = 2,
 445         },
 446         [MESON_VCLK_HDMI_162000] = {
 447                 .pll_base_freq = 3240000,
 448                 .pll_od1 = 2,
 449                 .pll_od2 = 1,
 450                 .pll_od3 = 1,
 451                 .vid_pll_div = VID_PLL_DIV_5,
 452                 .vclk_div = 2,
 453         },
 454 };
 455
 456 static inline unsigned int pll_od_to_reg(unsigned int od)
 457 {
 458         switch (od) {
 459         case 1:
 460                 return 0;
 461         case 2:
 462                 return 1;
 463         case 4:
 464                 return 2;
 465         case 8:
 466                 return 3;
 467         }
 468
 469         /* Invalid */
 470         return 0;
 471 }
 472
 473 void meson_hdmi_pll_set(struct meson_drm *priv,
 474                         unsigned int base,
 475                         unsigned int od1,
 476                         unsigned int od2,
 477                         unsigned int od3)
 478 {
 479         unsigned int val;
 480
 481         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
 482                 switch (base) {
 483                 case 2970000:
 484                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
 485                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 486                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 487                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 488                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 489                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 490
 491                         /* Enable and unreset */
 492                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 493                                                 0x7 << 28, 0x4 << 28);
 494
 495                         /* Poll for lock bit */
 496                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 497                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 498
 499                         /* div_frac */
 500                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 501                                                 0xFFFF,  0x4e00);
 502                         break;
 503
 504                 case 3200000:
 505                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000242);
 506                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 507                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 508                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 509                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 510                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 511
 512                         /* unreset */
 513                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 514                                                 BIT(28), 0);
 515
 516                         /* Poll for lock bit */
 517                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 518                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 519
 520                         /* div_frac */
 521                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 522                                                 0xFFFF,  0x4aab);
 523                         break;
 524
 525                 case 3240000:
 526                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000243);
 527                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 528                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 529                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 530                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 531                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 532
 533                         /* unreset */
 534                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 535                                                 BIT(28), 0);
 536
 537                         /* Poll for lock bit */
 538                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 539                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 540
 541                         /* div_frac */
 542                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 543                                                 0xFFFF,  0x4800);
 544                         break;
 545
 546                 case 3865000:
 547                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000250);
 548                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 549                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 550                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 551                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 552                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 553
 554                         /* unreset */
 555                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 556                                                 BIT(28), 0);
 557
 558                         /* Poll for lock bit */
 559                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 560                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 561
 562                         /* div_frac */
 563                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 564                                                 0xFFFF,  0x4855);
 565                         break;
 566
 567                 case 4028000:
 568                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000253);
 569                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 570                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 571                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 572                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 573                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 574
 575                         /* unreset */
 576                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 577                                                 BIT(28), 0);
 578
 579                         /* Poll for lock bit */
 580                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 581                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 582
 583                         /* div_frac */
 584                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 585                                                 0xFFFF,  0x4eab);
 586                         break;
 587
 588                 case 4320000:
 589                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800025a);
 590                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 591                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 592                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 593                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 594                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 595
 596                         /* unreset */
 597                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 598                                                 BIT(28), 0);
 599
 600                         /* Poll for lock bit */
 601                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 602                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 603                         break;
 604
 605                 case 5940000:
 606                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800027b);
 607                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 608                                                 0xFFFF,  0x4c00);
 609                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x135c5091);
 610                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 611                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 612                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 613
 614                         /* unreset */
 615                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 616                                                 BIT(28), 0);
 617
 618                         /* Poll for lock bit */
 619                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 620                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 621                         break;
 622
 623                 case 5200000:
 624                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800026c);
 625                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
 626                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x135c5091);
 627                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 628                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 629                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 630
 631                         /* unreset */
 632                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 633                                                 BIT(28), 0);
 634
 635                         /* Poll for lock bit */
 636                         regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 637                                         val, (val & HDMI_PLL_LOCK), 10, 0);
 638                         break;
 639                 };
 640         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 641                    meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
 642                 switch (base) {
 643                 case 2970000:
 644                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
 645                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
 646                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 647                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 648                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 649                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 650                         break;
 651
 652                 case 3200000:
 653                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000285);
 654                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb155);
 655                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 656                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 657                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 658                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 659                         break;
 660
 661                 case 3240000:
 662                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000287);
 663                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000);
 664                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 665                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 666                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 667                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 668                         break;
 669
 670                 case 3865000:
 671                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a1);
 672                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb02b);
 673                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 674                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 675                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 676                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 677                         break;
 678
 679                 case 4028000:
 680                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a7);
 681                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb355);
 682                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 683                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 684                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 685                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 686                         break;
 687
 688                 case 4320000:
 689                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002b4);
 690                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000);
 691                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 692                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 693                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 694                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 695                         break;
 696
 697                 case 5940000:
 698                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002f7);
 699                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb200);
 700                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 701                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 702                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 703                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 704                         break;
 705
 706                 case 5200000:
 707                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002d8);
 708                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb2ab);
 709                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 710                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 711                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 712                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 713                         break;
 714
 715                 };
 716
 717                 /* Reset PLL */
 718                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 719                                         HDMI_PLL_RESET, HDMI_PLL_RESET);
 720                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 721                                         HDMI_PLL_RESET, 0);
 722
 723                 /* Poll for lock bit */
 724                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 725                                 (val & HDMI_PLL_LOCK), 10, 0);
 726         };
 727
 728         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 729                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 730                                    3 << 16, pll_od_to_reg(od1) << 16);
 731         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 732                  meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 733                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 734                                    3 << 21, pll_od_to_reg(od1) << 21);
 735
 736         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 737                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 738                                    3 << 22, pll_od_to_reg(od2) << 22);
 739         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 740                  meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 741                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 742                                    3 << 23, pll_od_to_reg(od2) << 23);
 743
 744         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 745                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 746                                    3 << 18, pll_od_to_reg(od3) << 18);
 747         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 748                  meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 749                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 750                                    3 << 19, pll_od_to_reg(od3) << 19);
 751 }
 752
 753 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
 754                       unsigned int vclk_freq, unsigned int venc_freq,
 755                       unsigned int dac_freq, bool hdmi_use_enci)
 756 {
 757         unsigned int freq;
 758         unsigned int hdmi_tx_div;
 759         unsigned int venc_div;
 760
 761         if (target == MESON_VCLK_TARGET_CVBS) {
 762                 meson_venci_cvbs_clock_config(priv);
 763                 return;
 764         }
 765
 766         hdmi_tx_div = vclk_freq / dac_freq;
 767
 768         if (hdmi_tx_div == 0) {
 769                 pr_err("Fatal Error, invalid HDMI-TX freq %d\n",
 770                                 dac_freq);
 771                 return;
 772         }
 773
 774         venc_div = vclk_freq / venc_freq;
 775
 776         if (venc_div == 0) {
 777                 pr_err("Fatal Error, invalid HDMI venc freq %d\n",
 778                                 venc_freq);
 779                 return;
 780         }
 781
 782         switch (vclk_freq) {
 783         case 54000:
 784                 if (hdmi_use_enci)
 785                         freq = MESON_VCLK_HDMI_ENCI_54000;
 786                 else
 787                         freq = MESON_VCLK_HDMI_DDR_54000;
 788                 break;
 789         case 25175:
 790                 freq = MESON_VCLK_HDMI_25175;
 791                 break;
 792         case 40000:
 793                 freq = MESON_VCLK_HDMI_40000;
 794                 break;
 795         case 65000:
 796                 freq = MESON_VCLK_HDMI_65000;
 797                 break;
 798         case 74250:
 799                 freq = MESON_VCLK_HDMI_74250;
 800                 break;
 801         case 108000:
 802                 freq = MESON_VCLK_HDMI_108000;
 803                 break;
 804         case 148500:
 805                 if (dac_freq != 148500)
 806                         freq = MESON_VCLK_HDMI_DDR_148500;
 807                 else
 808                         freq = MESON_VCLK_HDMI_148500;
 809                 break;
 810         case 162000:
 811                 freq = MESON_VCLK_HDMI_162000;
 812                 break;
 813         case 297000:
 814                 freq = MESON_VCLK_HDMI_297000;
 815                 break;
 816         case 594000:
 817                 freq = MESON_VCLK_HDMI_594000;
 818                 break;
 819         default:
 820                 pr_err("Fatal Error, invalid HDMI vclk freq %d\n",
 821                         vclk_freq);
 822                 return;
 823         }
 824
 825         /* Set HDMI-TX sys clock */
 826         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 827                            CTS_HDMI_SYS_SEL_MASK, 0);
 828         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 829                            CTS_HDMI_SYS_DIV_MASK, 0);
 830         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 831                            CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
 832
 833         /* Set HDMI PLL rate */
 834         meson_hdmi_pll_set(priv, params[freq].pll_base_freq,
 835                            params[freq].pll_od1,
 836                            params[freq].pll_od2,
 837                            params[freq].pll_od3);
 838
 839         /* Setup vid_pll divider */
 840         meson_vid_pll_set(priv, params[freq].vid_pll_div);
 841
 842         /* Set VCLK div */
 843         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 844                            VCLK_SEL_MASK, 0);
 845         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 846                            VCLK_DIV_MASK, params[freq].vclk_div - 1);
 847
 848         /* Set HDMI-TX source */
 849         switch (hdmi_tx_div) {
 850         case 1:
 851                 /* enable vclk_div1 gate */
 852                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 853                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 854
 855                 /* select vclk_div1 for HDMI-TX */
 856                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 857                                    HDMI_TX_PIXEL_SEL_MASK, 0);
 858                 break;
 859         case 2:
 860                 /* enable vclk_div2 gate */
 861                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 862                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 863
 864                 /* select vclk_div2 for HDMI-TX */
 865                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 866                         HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
 867                 break;
 868         case 4:
 869                 /* enable vclk_div4 gate */
 870                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 871                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 872
 873                 /* select vclk_div4 for HDMI-TX */
 874                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 875                         HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
 876                 break;
 877         case 6:
 878                 /* enable vclk_div6 gate */
 879                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 880                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 881
 882                 /* select vclk_div6 for HDMI-TX */
 883                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 884                         HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
 885                 break;
 886         case 12:
 887                 /* enable vclk_div12 gate */
 888                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 889                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 890
 891                 /* select vclk_div12 for HDMI-TX */
 892                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 893                         HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
 894                 break;
 895         }
 896         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 897                                    HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 898
 899         /* Set ENCI/ENCP Source */
 900         switch (venc_div) {
 901         case 1:
 902                 /* enable vclk_div1 gate */
 903                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 904                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 905
 906                 if (hdmi_use_enci)
 907                         /* select vclk_div1 for enci */
 908                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 909                                            CTS_ENCI_SEL_MASK, 0);
 910                 else
 911                         /* select vclk_div1 for encp */
 912                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 913                                            CTS_ENCP_SEL_MASK, 0);
 914                 break;
 915         case 2:
 916                 /* enable vclk_div2 gate */
 917                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 918                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 919
 920                 if (hdmi_use_enci)
 921                         /* select vclk_div2 for enci */
 922                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 923                                 CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
 924                 else
 925                         /* select vclk_div2 for encp */
 926                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 927                                 CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
 928                 break;
 929         case 4:
 930                 /* enable vclk_div4 gate */
 931                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 932                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 933
 934                 if (hdmi_use_enci)
 935                         /* select vclk_div4 for enci */
 936                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 937                                 CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
 938                 else
 939                         /* select vclk_div4 for encp */
 940                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 941                                 CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
 942                 break;
 943         case 6:
 944                 /* enable vclk_div6 gate */
 945                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 946                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 947
 948                 if (hdmi_use_enci)
 949                         /* select vclk_div6 for enci */
 950                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 951                                 CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
 952                 else
 953                         /* select vclk_div6 for encp */
 954                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 955                                 CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
 956                 break;
 957         case 12:
 958                 /* enable vclk_div12 gate */
 959                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 960                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 961
 962                 if (hdmi_use_enci)
 963                         /* select vclk_div12 for enci */
 964                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 965                                 CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
 966                 else
 967                         /* select vclk_div12 for encp */
 968                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 969                                 CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
 970                 break;
 971         }
 972
 973         if (hdmi_use_enci)
 974                 /* Enable ENCI clock gate */
 975                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 976                                    CTS_ENCI_EN, CTS_ENCI_EN);
 977         else
 978                 /* Enable ENCP clock gate */
 979                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 980                                    CTS_ENCP_EN, CTS_ENCP_EN);
 981
 982         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 983 }
 984 EXPORT_SYMBOL_GPL(meson_vclk_setup);