drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_amdkfd.h"
  30 #include "amdgpu_ucode.h"
  31 #include "gfx_v8_0.h"
  32 #include "gca/gfx_8_0_sh_mask.h"
  33 #include "gca/gfx_8_0_d.h"
  34 #include "gca/gfx_8_0_enum.h"
  35 #include "oss/oss_3_0_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "vi_structs.h"
  40 #include "vid.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 struct cik_sdma_rlc_registers;
  49
  50 /*
  51  * Register access functions
  52  */
  53
  54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  55                 uint32_t sh_mem_config,
  56                 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
  57                 uint32_t sh_mem_bases);
  58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  59                 unsigned int vmid);
  60 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
  61                 uint32_t hpd_size, uint64_t hpd_gpu_addr);
  62 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
  63 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  64                         uint32_t queue_id, uint32_t __user *wptr,
  65                         uint32_t wptr_shift, uint32_t wptr_mask,
  66                         struct mm_struct *mm);
  67 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
  68 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
  69                 uint32_t pipe_id, uint32_t queue_id);
  70 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
  71 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
  72                                 enum kfd_preempt_type reset_type,
  73                                 unsigned int utimeout, uint32_t pipe_id,
  74                                 uint32_t queue_id);
  75 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
  76                                 unsigned int utimeout);
  77 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
  78 static int kgd_address_watch_disable(struct kgd_dev *kgd);
  79 static int kgd_address_watch_execute(struct kgd_dev *kgd,
  80                                         unsigned int watch_point_id,
  81                                         uint32_t cntl_val,
  82                                         uint32_t addr_hi,
  83                                         uint32_t addr_lo);
  84 static int kgd_wave_control_execute(struct kgd_dev *kgd,
  85                                         uint32_t gfx_index_val,
  86                                         uint32_t sq_cmd);
  87 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
  88                                         unsigned int watch_point_id,
  89                                         unsigned int reg_offset);
  90
  91 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
  92                 uint8_t vmid);
  93 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
  94                 uint8_t vmid);
  95 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
  96 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
  97 static void set_scratch_backing_va(struct kgd_dev *kgd,
  98                                         uint64_t va, uint32_t vmid);
  99
 100 /* Because of REG_GET_FIELD() being used, we put this function in the
 101  * asic specific file.
 102  */
 103 static int get_tile_config(struct kgd_dev *kgd,
 104                 struct tile_config *config)
 105 {
 106         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 107
 108         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 109         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 110                                 MC_ARB_RAMCFG, NOOFBANK);
 111         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 112                                 MC_ARB_RAMCFG, NOOFRANKS);
 113
 114         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 115         config->num_tile_configs =
 116                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 117         config->macro_tile_config_ptr =
 118                         adev->gfx.config.macrotile_mode_array;
 119         config->num_macro_tile_configs =
 120                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 121
 122         return 0;
 123 }
 124
 125 static const struct kfd2kgd_calls kfd2kgd = {
 126         .init_gtt_mem_allocation = alloc_gtt_mem,
 127         .free_gtt_mem = free_gtt_mem,
 128         .get_vmem_size = get_vmem_size,
 129         .get_gpu_clock_counter = get_gpu_clock_counter,
 130         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
 131         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 132         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 133         .init_pipeline = kgd_init_pipeline,
 134         .init_interrupts = kgd_init_interrupts,
 135         .hqd_load = kgd_hqd_load,
 136         .hqd_sdma_load = kgd_hqd_sdma_load,
 137         .hqd_is_occupied = kgd_hqd_is_occupied,
 138         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 139         .hqd_destroy = kgd_hqd_destroy,
 140         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 141         .address_watch_disable = kgd_address_watch_disable,
 142         .address_watch_execute = kgd_address_watch_execute,
 143         .wave_control_execute = kgd_wave_control_execute,
 144         .address_watch_get_offset = kgd_address_watch_get_offset,
 145         .get_atc_vmid_pasid_mapping_pasid =
 146                         get_atc_vmid_pasid_mapping_pasid,
 147         .get_atc_vmid_pasid_mapping_valid =
 148                         get_atc_vmid_pasid_mapping_valid,
 149         .write_vmid_invalidate_request = write_vmid_invalidate_request,
 150         .get_fw_version = get_fw_version,
 151         .set_scratch_backing_va = set_scratch_backing_va,
 152         .get_tile_config = get_tile_config,
 153 };
 154
 155 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 156 {
 157         return (struct kfd2kgd_calls *)&kfd2kgd;
 158         return (struct kfd2kgd_calls *)&kfd2kgd;
 159 }
 160
 161 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 162 {
 163         return (struct amdgpu_device *)kgd;
 164 }
 165
 166 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 167                         uint32_t queue, uint32_t vmid)
 168 {
 169         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 170         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 171
 172         mutex_lock(&adev->srbm_mutex);
 173         WREG32(mmSRBM_GFX_CNTL, value);
 174 }
 175
 176 static void unlock_srbm(struct kgd_dev *kgd)
 177 {
 178         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 179
 180         WREG32(mmSRBM_GFX_CNTL, 0);
 181         mutex_unlock(&adev->srbm_mutex);
 182 }
 183
 184 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 185                                 uint32_t queue_id)
 186 {
 187         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 188
 189         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 190         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 191
 192         lock_srbm(kgd, mec, pipe, queue_id, 0);
 193 }
 194
 195 static void release_queue(struct kgd_dev *kgd)
 196 {
 197         unlock_srbm(kgd);
 198 }
 199
 200 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 201                                         uint32_t sh_mem_config,
 202                                         uint32_t sh_mem_ape1_base,
 203                                         uint32_t sh_mem_ape1_limit,
 204                                         uint32_t sh_mem_bases)
 205 {
 206         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 207
 208         lock_srbm(kgd, 0, 0, 0, vmid);
 209
 210         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 211         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 212         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 213         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 214
 215         unlock_srbm(kgd);
 216 }
 217
 218 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 219                                         unsigned int vmid)
 220 {
 221         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 222
 223         /*
 224          * We have to assume that there is no outstanding mapping.
 225          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 226          * a mapping is in progress or because a mapping finished
 227          * and the SW cleared it.
 228          * So the protocol is to always wait & clear.
 229          */
 230         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 231                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 232
 233         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 234
 235         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 236                 cpu_relax();
 237         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 238
 239         /* Mapping vmid to pasid also for IH block */
 240         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 241
 242         return 0;
 243 }
 244
 245 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 246                                 uint32_t hpd_size, uint64_t hpd_gpu_addr)
 247 {
 248         /* amdgpu owns the per-pipe state */
 249         return 0;
 250 }
 251
 252 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 253 {
 254         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 255         uint32_t mec;
 256         uint32_t pipe;
 257
 258         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 259         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 260
 261         lock_srbm(kgd, mec, pipe, 0, 0);
 262
 263         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
 264
 265         unlock_srbm(kgd);
 266
 267         return 0;
 268 }
 269
 270 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
 271 {
 272         return 0;
 273 }
 274
 275 static inline struct vi_mqd *get_mqd(void *mqd)
 276 {
 277         return (struct vi_mqd *)mqd;
 278 }
 279
 280 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
 281 {
 282         return (struct cik_sdma_rlc_registers *)mqd;
 283 }
 284
 285 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 286                         uint32_t queue_id, uint32_t __user *wptr,
 287                         uint32_t wptr_shift, uint32_t wptr_mask,
 288                         struct mm_struct *mm)
 289 {
 290         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 291         struct vi_mqd *m;
 292         uint32_t *mqd_hqd;
 293         uint32_t reg, wptr_val, data;
 294
 295         m = get_mqd(mqd);
 296
 297         acquire_queue(kgd, pipe_id, queue_id);
 298
 299         /* HIQ is set during driver init period with vmid set to 0*/
 300         if (m->cp_hqd_vmid == 0) {
 301                 uint32_t value, mec, pipe;
 302
 303                 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 304                 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 305
 306                 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 307                         mec, pipe, queue_id);
 308                 value = RREG32(mmRLC_CP_SCHEDULERS);
 309                 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 310                         ((mec << 5) | (pipe << 3) | queue_id | 0x80));
 311                 WREG32(mmRLC_CP_SCHEDULERS, value);
 312         }
 313
 314         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
 315         mqd_hqd = &m->cp_mqd_base_addr_lo;
 316
 317         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
 318                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 319
 320         /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
 321          * This is safe since EOP RPTR==WPTR for any inactive HQD
 322          * on ASICs that do not support context-save.
 323          * EOP writes/reads can start anywhere in the ring.
 324          */
 325         if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
 326                 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
 327                 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
 328                 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
 329         }
 330
 331         for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
 332                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 333
 334         /* Copy userspace write pointer value to register.
 335          * Activate doorbell logic to monitor subsequent changes.
 336          */
 337         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 338                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 339         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 340
 341         if (read_user_wptr(mm, wptr, wptr_val))
 342                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 343
 344         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 345         WREG32(mmCP_HQD_ACTIVE, data);
 346
 347         release_queue(kgd);
 348
 349         return 0;
 350 }
 351
 352 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
 353 {
 354         return 0;
 355 }
 356
 357 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 358                                 uint32_t pipe_id, uint32_t queue_id)
 359 {
 360         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 361         uint32_t act;
 362         bool retval = false;
 363         uint32_t low, high;
 364
 365         acquire_queue(kgd, pipe_id, queue_id);
 366         act = RREG32(mmCP_HQD_ACTIVE);
 367         if (act) {
 368                 low = lower_32_bits(queue_address >> 8);
 369                 high = upper_32_bits(queue_address >> 8);
 370
 371                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 372                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 373                         retval = true;
 374         }
 375         release_queue(kgd);
 376         return retval;
 377 }
 378
 379 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 380 {
 381         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 382         struct cik_sdma_rlc_registers *m;
 383         uint32_t sdma_base_addr;
 384         uint32_t sdma_rlc_rb_cntl;
 385
 386         m = get_sdma_mqd(mqd);
 387         sdma_base_addr = get_sdma_base_addr(m);
 388
 389         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 390
 391         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 392                 return true;
 393
 394         return false;
 395 }
 396
 397 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 398                                 enum kfd_preempt_type reset_type,
 399                                 unsigned int utimeout, uint32_t pipe_id,
 400                                 uint32_t queue_id)
 401 {
 402         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 403         uint32_t temp;
 404         enum hqd_dequeue_request_type type;
 405         unsigned long flags, end_jiffies;
 406         int retry;
 407         struct vi_mqd *m = get_mqd(mqd);
 408
 409         acquire_queue(kgd, pipe_id, queue_id);
 410
 411         if (m->cp_hqd_vmid == 0)
 412                 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
 413
 414         switch (reset_type) {
 415         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 416                 type = DRAIN_PIPE;
 417                 break;
 418         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 419                 type = RESET_WAVES;
 420                 break;
 421         default:
 422                 type = DRAIN_PIPE;
 423                 break;
 424         }
 425
 426         /* Workaround: If IQ timer is active and the wait time is close to or
 427          * equal to 0, dequeueing is not safe. Wait until either the wait time
 428          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 429          * cleared before continuing. Also, ensure wait times are set to at
 430          * least 0x3.
 431          */
 432         local_irq_save(flags);
 433         preempt_disable();
 434         retry = 5000; /* wait for 500 usecs at maximum */
 435         while (true) {
 436                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 437                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 438                         pr_debug("HW is processing IQ\n");
 439                         goto loop;
 440                 }
 441                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 442                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 443                                         == 3) /* SEM-rearm is safe */
 444                                 break;
 445                         /* Wait time 3 is safe for CP, but our MMIO read/write
 446                          * time is close to 1 microsecond, so check for 10 to
 447                          * leave more buffer room
 448                          */
 449                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 450                                         >= 10)
 451                                 break;
 452                         pr_debug("IQ timer is active\n");
 453                 } else
 454                         break;
 455 loop:
 456                 if (!retry) {
 457                         pr_err("CP HQD IQ timer status time out\n");
 458                         break;
 459                 }
 460                 ndelay(100);
 461                 --retry;
 462         }
 463         retry = 1000;
 464         while (true) {
 465                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 466                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 467                         break;
 468                 pr_debug("Dequeue request is pending\n");
 469
 470                 if (!retry) {
 471                         pr_err("CP HQD dequeue request time out\n");
 472                         break;
 473                 }
 474                 ndelay(100);
 475                 --retry;
 476         }
 477         local_irq_restore(flags);
 478         preempt_enable();
 479
 480         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 481
 482         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 483         while (true) {
 484                 temp = RREG32(mmCP_HQD_ACTIVE);
 485                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 486                         break;
 487                 if (time_after(jiffies, end_jiffies)) {
 488                         pr_err("cp queue preemption time out.\n");
 489                         release_queue(kgd);
 490                         return -ETIME;
 491                 }
 492                 usleep_range(500, 1000);
 493         }
 494
 495         release_queue(kgd);
 496         return 0;
 497 }
 498
 499 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 500                                 unsigned int utimeout)
 501 {
 502         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 503         struct cik_sdma_rlc_registers *m;
 504         uint32_t sdma_base_addr;
 505         uint32_t temp;
 506         int timeout = utimeout;
 507
 508         m = get_sdma_mqd(mqd);
 509         sdma_base_addr = get_sdma_base_addr(m);
 510
 511         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 512         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 513         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 514
 515         while (true) {
 516                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 517                 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
 518                         break;
 519                 if (timeout <= 0)
 520                         return -ETIME;
 521                 msleep(20);
 522                 timeout -= 20;
 523         }
 524
 525         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 526         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
 527         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
 528         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
 529
 530         return 0;
 531 }
 532
 533 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 534                                                         uint8_t vmid)
 535 {
 536         uint32_t reg;
 537         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 538
 539         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 540         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 541 }
 542
 543 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 544                                                                 uint8_t vmid)
 545 {
 546         uint32_t reg;
 547         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 548
 549         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 550         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 551 }
 552
 553 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
 554 {
 555         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 556
 557         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 558 }
 559
 560 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 561 {
 562         return 0;
 563 }
 564
 565 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 566                                         unsigned int watch_point_id,
 567                                         uint32_t cntl_val,
 568                                         uint32_t addr_hi,
 569                                         uint32_t addr_lo)
 570 {
 571         return 0;
 572 }
 573
 574 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 575                                         uint32_t gfx_index_val,
 576                                         uint32_t sq_cmd)
 577 {
 578         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 579         uint32_t data = 0;
 580
 581         mutex_lock(&adev->grbm_idx_mutex);
 582
 583         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 584         WREG32(mmSQ_CMD, sq_cmd);
 585
 586         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 587                 INSTANCE_BROADCAST_WRITES, 1);
 588         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 589                 SH_BROADCAST_WRITES, 1);
 590         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 591                 SE_BROADCAST_WRITES, 1);
 592
 593         WREG32(mmGRBM_GFX_INDEX, data);
 594         mutex_unlock(&adev->grbm_idx_mutex);
 595
 596         return 0;
 597 }
 598
 599 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 600                                         unsigned int watch_point_id,
 601                                         unsigned int reg_offset)
 602 {
 603         return 0;
 604 }
 605
 606 static void set_scratch_backing_va(struct kgd_dev *kgd,
 607                                         uint64_t va, uint32_t vmid)
 608 {
 609         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 610
 611         lock_srbm(kgd, 0, 0, 0, vmid);
 612         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 613         unlock_srbm(kgd);
 614 }
 615
 616 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 617 {
 618         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 619         const union amdgpu_firmware_header *hdr;
 620
 621         BUG_ON(kgd == NULL);
 622
 623         switch (type) {
 624         case KGD_ENGINE_PFP:
 625                 hdr = (const union amdgpu_firmware_header *)
 626                                                 adev->gfx.pfp_fw->data;
 627                 break;
 628
 629         case KGD_ENGINE_ME:
 630                 hdr = (const union amdgpu_firmware_header *)
 631                                                 adev->gfx.me_fw->data;
 632                 break;
 633
 634         case KGD_ENGINE_CE:
 635                 hdr = (const union amdgpu_firmware_header *)
 636                                                 adev->gfx.ce_fw->data;
 637                 break;
 638
 639         case KGD_ENGINE_MEC1:
 640                 hdr = (const union amdgpu_firmware_header *)
 641                                                 adev->gfx.mec_fw->data;
 642                 break;
 643
 644         case KGD_ENGINE_MEC2:
 645                 hdr = (const union amdgpu_firmware_header *)
 646                                                 adev->gfx.mec2_fw->data;
 647                 break;
 648
 649         case KGD_ENGINE_RLC:
 650                 hdr = (const union amdgpu_firmware_header *)
 651                                                 adev->gfx.rlc_fw->data;
 652                 break;
 653
 654         case KGD_ENGINE_SDMA1:
 655                 hdr = (const union amdgpu_firmware_header *)
 656                                                 adev->sdma.instance[0].fw->data;
 657                 break;
 658
 659         case KGD_ENGINE_SDMA2:
 660                 hdr = (const union amdgpu_firmware_header *)
 661                                                 adev->sdma.instance[1].fw->data;
 662                 break;
 663
 664         default:
 665                 return 0;
 666         }
 667
 668         if (hdr == NULL)
 669                 return 0;
 670
 671         /* Only 12 bit in use*/
 672         return hdr->common.ucode_version;
 673 }