drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_xgmi.h"
  27 #include "amdgpu_ras.h"
  28 #include "soc15.h"
  29 #include "df/df_3_6_offset.h"
  30 #include "xgmi/xgmi_4_0_0_smn.h"
  31 #include "xgmi/xgmi_4_0_0_sh_mask.h"
  32 #include "xgmi/xgmi_6_1_0_sh_mask.h"
  33 #include "wafl/wafl2_4_0_0_smn.h"
  34 #include "wafl/wafl2_4_0_0_sh_mask.h"
  35
  36 #include "amdgpu_reset.h"
  37
  38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
  39 #define smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK   0x11a00218
  40 #define smnPCS_GOPX1_PCS_ERROR_STATUS    0x12200210
  41 #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK      0x12200218
  42
  43 static DEFINE_MUTEX(xgmi_mutex);
  44
  45 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE         4
  46
  47 static LIST_HEAD(xgmi_hive_list);
  48
  49 static const int xgmi_pcs_err_status_reg_vg20[] = {
  50         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  51         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  52 };
  53
  54 static const int wafl_pcs_err_status_reg_vg20[] = {
  55         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  56         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  57 };
  58
  59 static const int xgmi_pcs_err_status_reg_arct[] = {
  60         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  61         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  62         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
  63         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
  64         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
  65         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
  66 };
  67
  68 /* same as vg20*/
  69 static const int wafl_pcs_err_status_reg_arct[] = {
  70         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  71         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  72 };
  73
  74 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = {
  75         smnPCS_XGMI3X16_PCS_ERROR_STATUS,
  76         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000,
  77         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000,
  78         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000,
  79         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000,
  80         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000,
  81         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000,
  82         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000
  83 };
  84
  85 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[] = {
  86         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK,
  87         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000,
  88         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x200000,
  89         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x300000,
  90         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x400000,
  91         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x500000,
  92         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x600000,
  93         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x700000
  94 };
  95
  96 static const int walf_pcs_err_status_reg_aldebaran[] = {
  97         smnPCS_GOPX1_PCS_ERROR_STATUS,
  98         smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000
  99 };
 100
 101 static const int walf_pcs_err_noncorrectable_mask_reg_aldebaran[] = {
 102         smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK,
 103         smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000
 104 };
 105
 106 static const int xgmi3x16_pcs_err_status_reg_v6_4[] = {
 107         smnPCS_XGMI3X16_PCS_ERROR_STATUS,
 108         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000
 109 };
 110
 111 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[] = {
 112         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK,
 113         smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000
 114 };
 115
 116 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
 117         {"XGMI PCS DataLossErr",
 118          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
 119         {"XGMI PCS TrainingErr",
 120          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
 121         {"XGMI PCS CRCErr",
 122          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
 123         {"XGMI PCS BERExceededErr",
 124          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
 125         {"XGMI PCS TxMetaDataErr",
 126          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
 127         {"XGMI PCS ReplayBufParityErr",
 128          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
 129         {"XGMI PCS DataParityErr",
 130          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
 131         {"XGMI PCS ReplayFifoOverflowErr",
 132          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 133         {"XGMI PCS ReplayFifoUnderflowErr",
 134          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 135         {"XGMI PCS ElasticFifoOverflowErr",
 136          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 137         {"XGMI PCS DeskewErr",
 138          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
 139         {"XGMI PCS DataStartupLimitErr",
 140          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
 141         {"XGMI PCS FCInitTimeoutErr",
 142          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 143         {"XGMI PCS RecoveryTimeoutErr",
 144          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 145         {"XGMI PCS ReadySerialTimeoutErr",
 146          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 147         {"XGMI PCS ReadySerialAttemptErr",
 148          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 149         {"XGMI PCS RecoveryAttemptErr",
 150          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 151         {"XGMI PCS RecoveryRelockAttemptErr",
 152          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 153 };
 154
 155 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
 156         {"WAFL PCS DataLossErr",
 157          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
 158         {"WAFL PCS TrainingErr",
 159          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
 160         {"WAFL PCS CRCErr",
 161          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
 162         {"WAFL PCS BERExceededErr",
 163          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
 164         {"WAFL PCS TxMetaDataErr",
 165          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
 166         {"WAFL PCS ReplayBufParityErr",
 167          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
 168         {"WAFL PCS DataParityErr",
 169          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
 170         {"WAFL PCS ReplayFifoOverflowErr",
 171          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 172         {"WAFL PCS ReplayFifoUnderflowErr",
 173          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 174         {"WAFL PCS ElasticFifoOverflowErr",
 175          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 176         {"WAFL PCS DeskewErr",
 177          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
 178         {"WAFL PCS DataStartupLimitErr",
 179          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
 180         {"WAFL PCS FCInitTimeoutErr",
 181          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 182         {"WAFL PCS RecoveryTimeoutErr",
 183          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 184         {"WAFL PCS ReadySerialTimeoutErr",
 185          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 186         {"WAFL PCS ReadySerialAttemptErr",
 187          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 188         {"WAFL PCS RecoveryAttemptErr",
 189          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 190         {"WAFL PCS RecoveryRelockAttemptErr",
 191          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 192 };
 193
 194 static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = {
 195         {"XGMI3X16 PCS DataLossErr",
 196          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataLossErr)},
 197         {"XGMI3X16 PCS TrainingErr",
 198          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TrainingErr)},
 199         {"XGMI3X16 PCS FlowCtrlAckErr",
 200          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlAckErr)},
 201         {"XGMI3X16 PCS RxFifoUnderflowErr",
 202          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoUnderflowErr)},
 203         {"XGMI3X16 PCS RxFifoOverflowErr",
 204          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoOverflowErr)},
 205         {"XGMI3X16 PCS CRCErr",
 206          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, CRCErr)},
 207         {"XGMI3X16 PCS BERExceededErr",
 208          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, BERExceededErr)},
 209         {"XGMI3X16 PCS TxVcidDataErr",
 210          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxVcidDataErr)},
 211         {"XGMI3X16 PCS ReplayBufParityErr",
 212          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayBufParityErr)},
 213         {"XGMI3X16 PCS DataParityErr",
 214          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataParityErr)},
 215         {"XGMI3X16 PCS ReplayFifoOverflowErr",
 216          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 217         {"XGMI3X16 PCS ReplayFifoUnderflowErr",
 218          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 219         {"XGMI3X16 PCS ElasticFifoOverflowErr",
 220          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 221         {"XGMI3X16 PCS DeskewErr",
 222          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DeskewErr)},
 223         {"XGMI3X16 PCS FlowCtrlCRCErr",
 224          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlCRCErr)},
 225         {"XGMI3X16 PCS DataStartupLimitErr",
 226          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataStartupLimitErr)},
 227         {"XGMI3X16 PCS FCInitTimeoutErr",
 228          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 229         {"XGMI3X16 PCS RecoveryTimeoutErr",
 230          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 231         {"XGMI3X16 PCS ReadySerialTimeoutErr",
 232          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 233         {"XGMI3X16 PCS ReadySerialAttemptErr",
 234          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 235         {"XGMI3X16 PCS RecoveryAttemptErr",
 236          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 237         {"XGMI3X16 PCS RecoveryRelockAttemptErr",
 238          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 239         {"XGMI3X16 PCS ReplayAttemptErr",
 240          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayAttemptErr)},
 241         {"XGMI3X16 PCS SyncHdrErr",
 242          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, SyncHdrErr)},
 243         {"XGMI3X16 PCS TxReplayTimeoutErr",
 244          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxReplayTimeoutErr)},
 245         {"XGMI3X16 PCS RxReplayTimeoutErr",
 246          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxReplayTimeoutErr)},
 247         {"XGMI3X16 PCS LinkSubTxTimeoutErr",
 248          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubTxTimeoutErr)},
 249         {"XGMI3X16 PCS LinkSubRxTimeoutErr",
 250          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubRxTimeoutErr)},
 251         {"XGMI3X16 PCS RxCMDPktErr",
 252          SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)},
 253 };
 254
 255 /**
 256  * DOC: AMDGPU XGMI Support
 257  *
 258  * XGMI is a high speed interconnect that joins multiple GPU cards
 259  * into a homogeneous memory space that is organized by a collective
 260  * hive ID and individual node IDs, both of which are 64-bit numbers.
 261  *
 262  * The file xgmi_device_id contains the unique per GPU device ID and
 263  * is stored in the /sys/class/drm/card${cardno}/device/ directory.
 264  *
 265  * Inside the device directory a sub-directory 'xgmi_hive_info' is
 266  * created which contains the hive ID and the list of nodes.
 267  *
 268  * The hive ID is stored in:
 269  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
 270  *
 271  * The node information is stored in numbered directories:
 272  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
 273  *
 274  * Each device has their own xgmi_hive_info direction with a mirror
 275  * set of node sub-directories.
 276  *
 277  * The XGMI memory space is built by contiguously adding the power of
 278  * two padded VRAM space from each node to each other.
 279  *
 280  */
 281
 282 static struct attribute amdgpu_xgmi_hive_id = {
 283         .name = "xgmi_hive_id",
 284         .mode = S_IRUGO
 285 };
 286
 287 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
 288         &amdgpu_xgmi_hive_id,
 289         NULL
 290 };
 291 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive);
 292
 293 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
 294         struct attribute *attr, char *buf)
 295 {
 296         struct amdgpu_hive_info *hive = container_of(
 297                 kobj, struct amdgpu_hive_info, kobj);
 298
 299         if (attr == &amdgpu_xgmi_hive_id)
 300                 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
 301
 302         return 0;
 303 }
 304
 305 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
 306 {
 307         struct amdgpu_hive_info *hive = container_of(
 308                 kobj, struct amdgpu_hive_info, kobj);
 309
 310         amdgpu_reset_put_reset_domain(hive->reset_domain);
 311         hive->reset_domain = NULL;
 312
 313         mutex_destroy(&hive->hive_lock);
 314         kfree(hive);
 315 }
 316
 317 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
 318         .show = amdgpu_xgmi_show_attrs,
 319 };
 320
 321 static const struct kobj_type amdgpu_xgmi_hive_type = {
 322         .release = amdgpu_xgmi_hive_release,
 323         .sysfs_ops = &amdgpu_xgmi_hive_ops,
 324         .default_groups = amdgpu_xgmi_hive_groups,
 325 };
 326
 327 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
 328                                      struct device_attribute *attr,
 329                                      char *buf)
 330 {
 331         struct drm_device *ddev = dev_get_drvdata(dev);
 332         struct amdgpu_device *adev = drm_to_adev(ddev);
 333
 334         return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id);
 335
 336 }
 337
 338 static ssize_t amdgpu_xgmi_show_physical_id(struct device *dev,
 339                                      struct device_attribute *attr,
 340                                      char *buf)
 341 {
 342         struct drm_device *ddev = dev_get_drvdata(dev);
 343         struct amdgpu_device *adev = drm_to_adev(ddev);
 344
 345         return sysfs_emit(buf, "%u\n", adev->gmc.xgmi.physical_node_id);
 346
 347 }
 348
 349 static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev,
 350                                         struct device_attribute *attr,
 351                                         char *buf)
 352 {
 353         struct drm_device *ddev = dev_get_drvdata(dev);
 354         struct amdgpu_device *adev = drm_to_adev(ddev);
 355         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 356         int i;
 357
 358         for (i = 0; i < top->num_nodes; i++)
 359                 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops);
 360
 361         return sysfs_emit(buf, "%s\n", buf);
 362 }
 363
 364 static ssize_t amdgpu_xgmi_show_num_links(struct device *dev,
 365                                         struct device_attribute *attr,
 366                                         char *buf)
 367 {
 368         struct drm_device *ddev = dev_get_drvdata(dev);
 369         struct amdgpu_device *adev = drm_to_adev(ddev);
 370         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 371         int i;
 372
 373         for (i = 0; i < top->num_nodes; i++)
 374                 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links);
 375
 376         return sysfs_emit(buf, "%s\n", buf);
 377 }
 378
 379 #define AMDGPU_XGMI_SET_FICAA(o)        ((o) | 0x456801)
 380 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
 381                                       struct device_attribute *attr,
 382                                       char *buf)
 383 {
 384         struct drm_device *ddev = dev_get_drvdata(dev);
 385         struct amdgpu_device *adev = drm_to_adev(ddev);
 386         uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
 387         uint64_t fica_out;
 388         unsigned int error_count = 0;
 389
 390         ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
 391         ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
 392
 393         if ((!adev->df.funcs) ||
 394             (!adev->df.funcs->get_fica) ||
 395             (!adev->df.funcs->set_fica))
 396                 return -EINVAL;
 397
 398         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
 399         if (fica_out != 0x1f)
 400                 pr_err("xGMI error counters not enabled!\n");
 401
 402         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
 403
 404         if ((fica_out & 0xffff) == 2)
 405                 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
 406
 407         adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
 408
 409         return sysfs_emit(buf, "%u\n", error_count);
 410 }
 411
 412
 413 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
 414 static DEVICE_ATTR(xgmi_physical_id, 0444, amdgpu_xgmi_show_physical_id, NULL);
 415 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
 416 static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL);
 417 static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL);
 418
 419 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
 420                                          struct amdgpu_hive_info *hive)
 421 {
 422         int ret = 0;
 423         char node[10] = { 0 };
 424
 425         /* Create xgmi device id file */
 426         ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
 427         if (ret) {
 428                 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
 429                 return ret;
 430         }
 431
 432         ret = device_create_file(adev->dev, &dev_attr_xgmi_physical_id);
 433         if (ret) {
 434                 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_physical_id\n");
 435                 return ret;
 436         }
 437
 438         /* Create xgmi error file */
 439         ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
 440         if (ret)
 441                 pr_err("failed to create xgmi_error\n");
 442
 443         /* Create xgmi num hops file */
 444         ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops);
 445         if (ret)
 446                 pr_err("failed to create xgmi_num_hops\n");
 447
 448         /* Create xgmi num links file */
 449         ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links);
 450         if (ret)
 451                 pr_err("failed to create xgmi_num_links\n");
 452
 453         /* Create sysfs link to hive info folder on the first device */
 454         if (hive->kobj.parent != (&adev->dev->kobj)) {
 455                 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
 456                                         "xgmi_hive_info");
 457                 if (ret) {
 458                         dev_err(adev->dev, "XGMI: Failed to create link to hive info");
 459                         goto remove_file;
 460                 }
 461         }
 462
 463         sprintf(node, "node%d", atomic_read(&hive->number_devices));
 464         /* Create sysfs link form the hive folder to yourself */
 465         ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
 466         if (ret) {
 467                 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
 468                 goto remove_link;
 469         }
 470
 471         goto success;
 472
 473
 474 remove_link:
 475         sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
 476
 477 remove_file:
 478         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 479         device_remove_file(adev->dev, &dev_attr_xgmi_physical_id);
 480         device_remove_file(adev->dev, &dev_attr_xgmi_error);
 481         device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
 482         device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
 483
 484 success:
 485         return ret;
 486 }
 487
 488 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
 489                                           struct amdgpu_hive_info *hive)
 490 {
 491         char node[10];
 492         memset(node, 0, sizeof(node));
 493
 494         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 495         device_remove_file(adev->dev, &dev_attr_xgmi_physical_id);
 496         device_remove_file(adev->dev, &dev_attr_xgmi_error);
 497         device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
 498         device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
 499
 500         if (hive->kobj.parent != (&adev->dev->kobj))
 501                 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
 502
 503         sprintf(node, "node%d", atomic_read(&hive->number_devices));
 504         sysfs_remove_link(&hive->kobj, node);
 505
 506 }
 507
 508
 509
 510 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
 511 {
 512         struct amdgpu_hive_info *hive = NULL;
 513         int ret;
 514
 515         if (!adev->gmc.xgmi.hive_id)
 516                 return NULL;
 517
 518         if (adev->hive) {
 519                 kobject_get(&adev->hive->kobj);
 520                 return adev->hive;
 521         }
 522
 523         mutex_lock(&xgmi_mutex);
 524
 525         list_for_each_entry(hive, &xgmi_hive_list, node)  {
 526                 if (hive->hive_id == adev->gmc.xgmi.hive_id)
 527                         goto pro_end;
 528         }
 529
 530         hive = kzalloc(sizeof(*hive), GFP_KERNEL);
 531         if (!hive) {
 532                 dev_err(adev->dev, "XGMI: allocation failed\n");
 533                 ret = -ENOMEM;
 534                 hive = NULL;
 535                 goto pro_end;
 536         }
 537
 538         /* initialize new hive if not exist */
 539         ret = kobject_init_and_add(&hive->kobj,
 540                         &amdgpu_xgmi_hive_type,
 541                         &adev->dev->kobj,
 542                         "%s", "xgmi_hive_info");
 543         if (ret) {
 544                 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
 545                 kobject_put(&hive->kobj);
 546                 hive = NULL;
 547                 goto pro_end;
 548         }
 549
 550         /**
 551          * Only init hive->reset_domain for none SRIOV configuration. For SRIOV,
 552          * Host driver decide how to reset the GPU either through FLR or chain reset.
 553          * Guest side will get individual notifications from the host for the FLR
 554          * if necessary.
 555          */
 556         if (!amdgpu_sriov_vf(adev)) {
 557         /**
 558          * Avoid recreating reset domain when hive is reconstructed for the case
 559          * of reset the devices in the XGMI hive during probe for passthrough GPU
 560          * See https://www.spinics.net/lists/amd-gfx/msg58836.html
 561          */
 562                 if (adev->reset_domain->type != XGMI_HIVE) {
 563                         hive->reset_domain =
 564                                 amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
 565                         if (!hive->reset_domain) {
 566                                 dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n");
 567                                 ret = -ENOMEM;
 568                                 kobject_put(&hive->kobj);
 569                                 hive = NULL;
 570                                 goto pro_end;
 571                         }
 572                 } else {
 573                         amdgpu_reset_get_reset_domain(adev->reset_domain);
 574                         hive->reset_domain = adev->reset_domain;
 575                 }
 576         }
 577
 578         hive->hive_id = adev->gmc.xgmi.hive_id;
 579         INIT_LIST_HEAD(&hive->device_list);
 580         INIT_LIST_HEAD(&hive->node);
 581         mutex_init(&hive->hive_lock);
 582         atomic_set(&hive->number_devices, 0);
 583         task_barrier_init(&hive->tb);
 584         hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
 585         hive->hi_req_gpu = NULL;
 586
 587         /*
 588          * hive pstate on boot is high in vega20 so we have to go to low
 589          * pstate on after boot.
 590          */
 591         hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
 592         list_add_tail(&hive->node, &xgmi_hive_list);
 593
 594 pro_end:
 595         if (hive)
 596                 kobject_get(&hive->kobj);
 597         mutex_unlock(&xgmi_mutex);
 598         return hive;
 599 }
 600
 601 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
 602 {
 603         if (hive)
 604                 kobject_put(&hive->kobj);
 605 }
 606
 607 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
 608 {
 609         int ret = 0;
 610         struct amdgpu_hive_info *hive;
 611         struct amdgpu_device *request_adev;
 612         bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
 613         bool init_low;
 614
 615         hive = amdgpu_get_xgmi_hive(adev);
 616         if (!hive)
 617                 return 0;
 618
 619         request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev;
 620         init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
 621         amdgpu_put_xgmi_hive(hive);
 622         /* fw bug so temporarily disable pstate switching */
 623         return 0;
 624
 625         if (!hive || adev->asic_type != CHIP_VEGA20)
 626                 return 0;
 627
 628         mutex_lock(&hive->hive_lock);
 629
 630         if (is_hi_req)
 631                 hive->hi_req_count++;
 632         else
 633                 hive->hi_req_count--;
 634
 635         /*
 636          * Vega20 only needs single peer to request pstate high for the hive to
 637          * go high but all peers must request pstate low for the hive to go low
 638          */
 639         if (hive->pstate == pstate ||
 640                         (!is_hi_req && hive->hi_req_count && !init_low))
 641                 goto out;
 642
 643         dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
 644
 645         ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
 646         if (ret) {
 647                 dev_err(request_adev->dev,
 648                         "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
 649                         request_adev->gmc.xgmi.node_id,
 650                         request_adev->gmc.xgmi.hive_id, ret);
 651                 goto out;
 652         }
 653
 654         if (init_low)
 655                 hive->pstate = hive->hi_req_count ?
 656                                         hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
 657         else {
 658                 hive->pstate = pstate;
 659                 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
 660                                                         adev : NULL;
 661         }
 662 out:
 663         mutex_unlock(&hive->hive_lock);
 664         return ret;
 665 }
 666
 667 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
 668 {
 669         int ret;
 670
 671         if (amdgpu_sriov_vf(adev))
 672                 return 0;
 673
 674         /* Each psp need to set the latest topology */
 675         ret = psp_xgmi_set_topology_info(&adev->psp,
 676                                          atomic_read(&hive->number_devices),
 677                                          &adev->psp.xgmi_context.top_info);
 678         if (ret)
 679                 dev_err(adev->dev,
 680                         "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
 681                         adev->gmc.xgmi.node_id,
 682                         adev->gmc.xgmi.hive_id, ret);
 683
 684         return ret;
 685 }
 686
 687
 688 /*
 689  * NOTE psp_xgmi_node_info.num_hops layout is as follows:
 690  * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved)
 691  * num_hops[5:3] = reserved
 692  * num_hops[2:0] = number of hops
 693  */
 694 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
 695                 struct amdgpu_device *peer_adev)
 696 {
 697         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 698         uint8_t num_hops_mask = 0x7;
 699         int i;
 700
 701         for (i = 0 ; i < top->num_nodes; ++i)
 702                 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
 703                         return top->nodes[i].num_hops & num_hops_mask;
 704         return  -EINVAL;
 705 }
 706
 707 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
 708                 struct amdgpu_device *peer_adev)
 709 {
 710         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 711         int i;
 712
 713         for (i = 0 ; i < top->num_nodes; ++i)
 714                 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
 715                         return top->nodes[i].num_links;
 716         return  -EINVAL;
 717 }
 718
 719 /*
 720  * Devices that support extended data require the entire hive to initialize with
 721  * the shared memory buffer flag set.
 722  *
 723  * Hive locks and conditions apply - see amdgpu_xgmi_add_device
 724  */
 725 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive,
 726                                                         bool set_extended_data)
 727 {
 728         struct amdgpu_device *tmp_adev;
 729         int ret;
 730
 731         list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 732                 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false);
 733                 if (ret) {
 734                         dev_err(tmp_adev->dev,
 735                                 "XGMI: Failed to initialize xgmi session for data partition %i\n",
 736                                 set_extended_data);
 737                         return ret;
 738                 }
 739
 740         }
 741
 742         return 0;
 743 }
 744
 745 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
 746 {
 747         struct psp_xgmi_topology_info *top_info;
 748         struct amdgpu_hive_info *hive;
 749         struct amdgpu_xgmi      *entry;
 750         struct amdgpu_device *tmp_adev = NULL;
 751
 752         int count = 0, ret = 0;
 753
 754         if (!adev->gmc.xgmi.supported)
 755                 return 0;
 756
 757         if (!adev->gmc.xgmi.pending_reset &&
 758             amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 759                 ret = psp_xgmi_initialize(&adev->psp, false, true);
 760                 if (ret) {
 761                         dev_err(adev->dev,
 762                                 "XGMI: Failed to initialize xgmi session\n");
 763                         return ret;
 764                 }
 765
 766                 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
 767                 if (ret) {
 768                         dev_err(adev->dev,
 769                                 "XGMI: Failed to get hive id\n");
 770                         return ret;
 771                 }
 772
 773                 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
 774                 if (ret) {
 775                         dev_err(adev->dev,
 776                                 "XGMI: Failed to get node id\n");
 777                         return ret;
 778                 }
 779         } else {
 780                 adev->gmc.xgmi.hive_id = 16;
 781                 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
 782         }
 783
 784         hive = amdgpu_get_xgmi_hive(adev);
 785         if (!hive) {
 786                 ret = -EINVAL;
 787                 dev_err(adev->dev,
 788                         "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
 789                         adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
 790                 goto exit;
 791         }
 792         mutex_lock(&hive->hive_lock);
 793
 794         top_info = &adev->psp.xgmi_context.top_info;
 795
 796         list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
 797         list_for_each_entry(entry, &hive->device_list, head)
 798                 top_info->nodes[count++].node_id = entry->node_id;
 799         top_info->num_nodes = count;
 800         atomic_set(&hive->number_devices, count);
 801
 802         task_barrier_add_task(&hive->tb);
 803
 804         if (!adev->gmc.xgmi.pending_reset &&
 805             amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 806                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 807                         /* update node list for other device in the hive */
 808                         if (tmp_adev != adev) {
 809                                 top_info = &tmp_adev->psp.xgmi_context.top_info;
 810                                 top_info->nodes[count - 1].node_id =
 811                                         adev->gmc.xgmi.node_id;
 812                                 top_info->num_nodes = count;
 813                         }
 814                         ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
 815                         if (ret)
 816                                 goto exit_unlock;
 817                 }
 818
 819                 /* get latest topology info for each device from psp */
 820                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 821                         ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
 822                                         &tmp_adev->psp.xgmi_context.top_info, false);
 823                         if (ret) {
 824                                 dev_err(tmp_adev->dev,
 825                                         "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
 826                                         tmp_adev->gmc.xgmi.node_id,
 827                                         tmp_adev->gmc.xgmi.hive_id, ret);
 828                                 /* To do : continue with some node failed or disable the whole hive */
 829                                 goto exit_unlock;
 830                         }
 831                 }
 832
 833                 /* get topology again for hives that support extended data */
 834                 if (adev->psp.xgmi_context.supports_extended_data) {
 835
 836                         /* initialize the hive to get extended data.  */
 837                         ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true);
 838                         if (ret)
 839                                 goto exit_unlock;
 840
 841                         /* get the extended data. */
 842                         list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 843                                 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
 844                                                 &tmp_adev->psp.xgmi_context.top_info, true);
 845                                 if (ret) {
 846                                         dev_err(tmp_adev->dev,
 847                                                 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d",
 848                                                 tmp_adev->gmc.xgmi.node_id,
 849                                                 tmp_adev->gmc.xgmi.hive_id, ret);
 850                                         goto exit_unlock;
 851                                 }
 852                         }
 853
 854                         /* initialize the hive to get non-extended data for the next round. */
 855                         ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false);
 856                         if (ret)
 857                                 goto exit_unlock;
 858
 859                 }
 860         }
 861
 862         if (!ret && !adev->gmc.xgmi.pending_reset)
 863                 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
 864
 865 exit_unlock:
 866         mutex_unlock(&hive->hive_lock);
 867 exit:
 868         if (!ret) {
 869                 adev->hive = hive;
 870                 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
 871                          adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
 872         } else {
 873                 amdgpu_put_xgmi_hive(hive);
 874                 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
 875                         adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
 876                         ret);
 877         }
 878
 879         return ret;
 880 }
 881
 882 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
 883 {
 884         struct amdgpu_hive_info *hive = adev->hive;
 885
 886         if (!adev->gmc.xgmi.supported)
 887                 return -EINVAL;
 888
 889         if (!hive)
 890                 return -EINVAL;
 891
 892         mutex_lock(&hive->hive_lock);
 893         task_barrier_rem_task(&hive->tb);
 894         amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
 895         if (hive->hi_req_gpu == adev)
 896                 hive->hi_req_gpu = NULL;
 897         list_del(&adev->gmc.xgmi.head);
 898         mutex_unlock(&hive->hive_lock);
 899
 900         amdgpu_put_xgmi_hive(hive);
 901         adev->hive = NULL;
 902
 903         if (atomic_dec_return(&hive->number_devices) == 0) {
 904                 /* Remove the hive from global hive list */
 905                 mutex_lock(&xgmi_mutex);
 906                 list_del(&hive->node);
 907                 mutex_unlock(&xgmi_mutex);
 908
 909                 amdgpu_put_xgmi_hive(hive);
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 916 {
 917         if (!adev->gmc.xgmi.supported ||
 918             adev->gmc.xgmi.num_physical_nodes == 0)
 919                 return 0;
 920
 921         amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);
 922
 923         return amdgpu_ras_block_late_init(adev, ras_block);
 924 }
 925
 926 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
 927                                            uint64_t addr)
 928 {
 929         struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
 930         return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
 931 }
 932
 933 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
 934 {
 935         WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
 936         WREG32_PCIE(pcs_status_reg, 0);
 937 }
 938
 939 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
 940 {
 941         uint32_t i;
 942
 943         switch (adev->asic_type) {
 944         case CHIP_ARCTURUS:
 945                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
 946                         pcs_clear_status(adev,
 947                                          xgmi_pcs_err_status_reg_arct[i]);
 948                 break;
 949         case CHIP_VEGA20:
 950                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
 951                         pcs_clear_status(adev,
 952                                          xgmi_pcs_err_status_reg_vg20[i]);
 953                 break;
 954         case CHIP_ALDEBARAN:
 955                 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)
 956                         pcs_clear_status(adev,
 957                                          xgmi3x16_pcs_err_status_reg_aldebaran[i]);
 958                 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++)
 959                         pcs_clear_status(adev,
 960                                          walf_pcs_err_status_reg_aldebaran[i]);
 961                 break;
 962         default:
 963                 break;
 964         }
 965
 966         switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {
 967         case IP_VERSION(6, 4, 0):
 968                 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++)
 969                         pcs_clear_status(adev,
 970                                         xgmi3x16_pcs_err_status_reg_v6_4[i]);
 971                 break;
 972         default:
 973                 break;
 974         }
 975 }
 976
 977 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
 978                                               uint32_t value,
 979                                                   uint32_t mask_value,
 980                                               uint32_t *ue_count,
 981                                               uint32_t *ce_count,
 982                                               bool is_xgmi_pcs,
 983                                                   bool check_mask)
 984 {
 985         int i;
 986         int ue_cnt = 0;
 987         const struct amdgpu_pcs_ras_field *pcs_ras_fields = NULL;
 988         uint32_t field_array_size = 0;
 989
 990         if (is_xgmi_pcs) {
 991                 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) ==
 992                     IP_VERSION(6, 1, 0) ||
 993                     amdgpu_ip_version(adev, XGMI_HWIP, 0) ==
 994                     IP_VERSION(6, 4, 0)) {
 995                         pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0];
 996                         field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields);
 997                 } else {
 998                         pcs_ras_fields = &xgmi_pcs_ras_fields[0];
 999                         field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields);
1000                 }
1001         } else {
1002                 pcs_ras_fields = &wafl_pcs_ras_fields[0];
1003                 field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields);
1004         }
1005
1006         if (check_mask)
1007                 value = value & ~mask_value;
1008
1009         /* query xgmi/walf pcs error status,
1010          * only ue is supported */
1011         for (i = 0; value && i < field_array_size; i++) {
1012                 ue_cnt = (value &
1013                                 pcs_ras_fields[i].pcs_err_mask) >>
1014                                 pcs_ras_fields[i].pcs_err_shift;
1015                 if (ue_cnt) {
1016                         dev_info(adev->dev, "%s detected\n",
1017                                  pcs_ras_fields[i].err_name);
1018                         *ue_count += ue_cnt;
1019                 }
1020
1021                 /* reset bit value if the bit is checked */
1022                 value &= ~(pcs_ras_fields[i].pcs_err_mask);
1023         }
1024
1025         return 0;
1026 }
1027
1028 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
1029                                              void *ras_error_status)
1030 {
1031         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1032         int i, supported = 1;
1033         uint32_t data, mask_data = 0;
1034         uint32_t ue_cnt = 0, ce_cnt = 0;
1035
1036         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
1037                 return ;
1038
1039         err_data->ue_count = 0;
1040         err_data->ce_count = 0;
1041
1042         switch (adev->asic_type) {
1043         case CHIP_ARCTURUS:
1044                 /* check xgmi pcs error */
1045                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
1046                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
1047                         if (data)
1048                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1049                                                 mask_data, &ue_cnt, &ce_cnt, true, false);
1050                 }
1051                 /* check wafl pcs error */
1052                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
1053                         data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
1054                         if (data)
1055                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1056                                                 mask_data, &ue_cnt, &ce_cnt, false, false);
1057                 }
1058                 break;
1059         case CHIP_VEGA20:
1060                 /* check xgmi pcs error */
1061                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
1062                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
1063                         if (data)
1064                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1065                                                 mask_data, &ue_cnt, &ce_cnt, true, false);
1066                 }
1067                 /* check wafl pcs error */
1068                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
1069                         data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
1070                         if (data)
1071                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1072                                                 mask_data, &ue_cnt, &ce_cnt, false, false);
1073                 }
1074                 break;
1075         case CHIP_ALDEBARAN:
1076                 /* check xgmi3x16 pcs error */
1077                 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {
1078                         data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);
1079                         mask_data =
1080                                 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
1081                         if (data)
1082                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1083                                                 mask_data, &ue_cnt, &ce_cnt, true, true);
1084                 }
1085                 /* check wafl pcs error */
1086                 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) {
1087                         data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]);
1088                         mask_data =
1089                                 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
1090                         if (data)
1091                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1092                                                 mask_data, &ue_cnt, &ce_cnt, false, true);
1093                 }
1094                 break;
1095         default:
1096                 supported = 0;
1097                 break;
1098         }
1099
1100         switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {
1101         case IP_VERSION(6, 4, 0):
1102                 /* check xgmi3x16 pcs error */
1103                 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) {
1104                         data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]);
1105                         mask_data =
1106                                 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[i]);
1107                         if (data)
1108                                 amdgpu_xgmi_query_pcs_error_status(adev, data,
1109                                                 mask_data, &ue_cnt, &ce_cnt, true, true);
1110                 }
1111                 break;
1112         default:
1113                 if (!supported)
1114                         dev_warn(adev->dev, "XGMI RAS error query not supported");
1115                 break;
1116         }
1117
1118         amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL);
1119
1120         err_data->ue_count += ue_cnt;
1121         err_data->ce_count += ce_cnt;
1122 }
1123
1124 /* Trigger XGMI/WAFL error */
1125 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
1126                         void *inject_if, uint32_t instance_mask)
1127 {
1128         int ret1, ret2;
1129         struct ta_ras_trigger_error_input *block_info =
1130                                 (struct ta_ras_trigger_error_input *)inject_if;
1131
1132         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
1133                 dev_warn(adev->dev, "Failed to disallow df cstate");
1134
1135         ret1 = amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DISALLOW);
1136         if (ret1 && ret1 != -EOPNOTSUPP)
1137                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
1138
1139         ret2 = psp_ras_trigger_error(&adev->psp, block_info, instance_mask);
1140
1141         if (amdgpu_ras_intr_triggered())
1142                 return ret2;
1143
1144         ret1 = amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DEFAULT);
1145         if (ret1 && ret1 != -EOPNOTSUPP)
1146                 dev_warn(adev->dev, "Failed to allow XGMI power down");
1147
1148         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
1149                 dev_warn(adev->dev, "Failed to allow df cstate");
1150
1151         return ret2;
1152 }
1153
1154 struct amdgpu_ras_block_hw_ops  xgmi_ras_hw_ops = {
1155         .query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
1156         .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
1157         .ras_error_inject = amdgpu_ras_error_inject_xgmi,
1158 };
1159
1160 struct amdgpu_xgmi_ras xgmi_ras = {
1161         .ras_block = {
1162                 .hw_ops = &xgmi_ras_hw_ops,
1163                 .ras_late_init = amdgpu_xgmi_ras_late_init,
1164         },
1165 };
1166
1167 int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev)
1168 {
1169         int err;
1170         struct amdgpu_xgmi_ras *ras;
1171
1172         if (!adev->gmc.xgmi.ras)
1173                 return 0;
1174
1175         ras = adev->gmc.xgmi.ras;
1176         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1177         if (err) {
1178                 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n");
1179                 return err;
1180         }
1181
1182         strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl");
1183         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
1184         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1185         adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm;
1186
1187         return 0;
1188 }