drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 if (robj->gem_base.import_attach)
  40                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  41                 amdgpu_mn_unregister(robj);
  42                 amdgpu_bo_unref(&robj);
  43         }
  44 }
  45
  46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  47                                 int alignment, u32 initial_domain,
  48                                 u64 flags, bool kernel,
  49                                 struct drm_gem_object **obj)
  50 {
  51         struct amdgpu_bo *robj;
  52         unsigned long max_size;
  53         int r;
  54
  55         *obj = NULL;
  56         /* At least align on page size */
  57         if (alignment < PAGE_SIZE) {
  58                 alignment = PAGE_SIZE;
  59         }
  60
  61         if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
  62                 /* Maximum bo size is the unpinned gtt size since we use the gtt to
  63                  * handle vram to system pool migrations.
  64                  */
  65                 max_size = adev->mc.gtt_size - adev->gart_pin_size;
  66                 if (size > max_size) {
  67                         DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  68                                   size >> 20, max_size >> 20);
  69                         return -ENOMEM;
  70                 }
  71         }
  72 retry:
  73         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  74                              flags, NULL, NULL, &robj);
  75         if (r) {
  76                 if (r != -ERESTARTSYS) {
  77                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  78                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  79                                 goto retry;
  80                         }
  81                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  82                                   size, initial_domain, alignment, r);
  83                 }
  84                 return r;
  85         }
  86         *obj = &robj->gem_base;
  87
  88         return 0;
  89 }
  90
  91 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  92 {
  93         struct drm_device *ddev = adev->ddev;
  94         struct drm_file *file;
  95
  96         mutex_lock(&ddev->filelist_mutex);
  97
  98         list_for_each_entry(file, &ddev->filelist, lhead) {
  99                 struct drm_gem_object *gobj;
 100                 int handle;
 101
 102                 WARN_ONCE(1, "Still active user space clients!\n");
 103                 spin_lock(&file->table_lock);
 104                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 105                         WARN_ONCE(1, "And also active allocations!\n");
 106                         drm_gem_object_unreference_unlocked(gobj);
 107                 }
 108                 idr_destroy(&file->object_idr);
 109                 spin_unlock(&file->table_lock);
 110         }
 111
 112         mutex_unlock(&ddev->filelist_mutex);
 113 }
 114
 115 /*
 116  * Call from drm_gem_handle_create which appear in both new and open ioctl
 117  * case.
 118  */
 119 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
 120 {
 121         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 122         struct amdgpu_device *adev = abo->adev;
 123         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 124         struct amdgpu_vm *vm = &fpriv->vm;
 125         struct amdgpu_bo_va *bo_va;
 126         int r;
 127         r = amdgpu_bo_reserve(abo, false);
 128         if (r)
 129                 return r;
 130
 131         bo_va = amdgpu_vm_bo_find(vm, abo);
 132         if (!bo_va) {
 133                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 134         } else {
 135                 ++bo_va->ref_count;
 136         }
 137         amdgpu_bo_unreserve(abo);
 138         return 0;
 139 }
 140
 141 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 142                              struct drm_file *file_priv)
 143 {
 144         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 145         struct amdgpu_device *adev = bo->adev;
 146         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 147         struct amdgpu_vm *vm = &fpriv->vm;
 148
 149         struct amdgpu_bo_list_entry vm_pd;
 150         struct list_head list, duplicates;
 151         struct ttm_validate_buffer tv;
 152         struct ww_acquire_ctx ticket;
 153         struct amdgpu_bo_va *bo_va;
 154         int r;
 155
 156         INIT_LIST_HEAD(&list);
 157         INIT_LIST_HEAD(&duplicates);
 158
 159         tv.bo = &bo->tbo;
 160         tv.shared = true;
 161         list_add(&tv.head, &list);
 162
 163         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 164
 165         r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
 166         if (r) {
 167                 dev_err(adev->dev, "leaking bo va because "
 168                         "we fail to reserve bo (%d)\n", r);
 169                 return;
 170         }
 171         bo_va = amdgpu_vm_bo_find(vm, bo);
 172         if (bo_va) {
 173                 if (--bo_va->ref_count == 0) {
 174                         amdgpu_vm_bo_rmv(adev, bo_va);
 175                 }
 176         }
 177         ttm_eu_backoff_reservation(&ticket, &list);
 178 }
 179
 180 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
 181 {
 182         if (r == -EDEADLK) {
 183                 r = amdgpu_gpu_reset(adev);
 184                 if (!r)
 185                         r = -EAGAIN;
 186         }
 187         return r;
 188 }
 189
 190 /*
 191  * GEM ioctls.
 192  */
 193 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 194                             struct drm_file *filp)
 195 {
 196         struct amdgpu_device *adev = dev->dev_private;
 197         union drm_amdgpu_gem_create *args = data;
 198         uint64_t size = args->in.bo_size;
 199         struct drm_gem_object *gobj;
 200         uint32_t handle;
 201         bool kernel = false;
 202         int r;
 203
 204         /* create a gem object to contain this object in */
 205         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 206             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 207                 kernel = true;
 208                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 209                         size = size << AMDGPU_GDS_SHIFT;
 210                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 211                         size = size << AMDGPU_GWS_SHIFT;
 212                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 213                         size = size << AMDGPU_OA_SHIFT;
 214                 else {
 215                         r = -EINVAL;
 216                         goto error_unlock;
 217                 }
 218         }
 219         size = roundup(size, PAGE_SIZE);
 220
 221         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 222                                      (u32)(0xffffffff & args->in.domains),
 223                                      args->in.domain_flags,
 224                                      kernel, &gobj);
 225         if (r)
 226                 goto error_unlock;
 227
 228         r = drm_gem_handle_create(filp, gobj, &handle);
 229         /* drop reference from allocate - handle holds it now */
 230         drm_gem_object_unreference_unlocked(gobj);
 231         if (r)
 232                 goto error_unlock;
 233
 234         memset(args, 0, sizeof(*args));
 235         args->out.handle = handle;
 236         return 0;
 237
 238 error_unlock:
 239         r = amdgpu_gem_handle_lockup(adev, r);
 240         return r;
 241 }
 242
 243 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 244                              struct drm_file *filp)
 245 {
 246         struct amdgpu_device *adev = dev->dev_private;
 247         struct drm_amdgpu_gem_userptr *args = data;
 248         struct drm_gem_object *gobj;
 249         struct amdgpu_bo *bo;
 250         uint32_t handle;
 251         int r;
 252
 253         if (offset_in_page(args->addr | args->size))
 254                 return -EINVAL;
 255
 256         /* reject unknown flag values */
 257         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 258             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 259             AMDGPU_GEM_USERPTR_REGISTER))
 260                 return -EINVAL;
 261
 262         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 263              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 264
 265                 /* if we want to write to it we must install a MMU notifier */
 266                 return -EACCES;
 267         }
 268
 269         /* create a gem object to contain this object in */
 270         r = amdgpu_gem_object_create(adev, args->size, 0,
 271                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 272                                      0, &gobj);
 273         if (r)
 274                 goto handle_lockup;
 275
 276         bo = gem_to_amdgpu_bo(gobj);
 277         bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
 278         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 279         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 280         if (r)
 281                 goto release_object;
 282
 283         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 284                 r = amdgpu_mn_register(bo, args->addr);
 285                 if (r)
 286                         goto release_object;
 287         }
 288
 289         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 290                 down_read(&current->mm->mmap_sem);
 291
 292                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 293                                                  bo->tbo.ttm->pages);
 294                 if (r)
 295                         goto unlock_mmap_sem;
 296
 297                 r = amdgpu_bo_reserve(bo, true);
 298                 if (r)
 299                         goto free_pages;
 300
 301                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 302                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 303                 amdgpu_bo_unreserve(bo);
 304                 if (r)
 305                         goto free_pages;
 306
 307                 up_read(&current->mm->mmap_sem);
 308         }
 309
 310         r = drm_gem_handle_create(filp, gobj, &handle);
 311         /* drop reference from allocate - handle holds it now */
 312         drm_gem_object_unreference_unlocked(gobj);
 313         if (r)
 314                 goto handle_lockup;
 315
 316         args->handle = handle;
 317         return 0;
 318
 319 free_pages:
 320         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
 321
 322 unlock_mmap_sem:
 323         up_read(&current->mm->mmap_sem);
 324
 325 release_object:
 326         drm_gem_object_unreference_unlocked(gobj);
 327
 328 handle_lockup:
 329         r = amdgpu_gem_handle_lockup(adev, r);
 330
 331         return r;
 332 }
 333
 334 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 335                           struct drm_device *dev,
 336                           uint32_t handle, uint64_t *offset_p)
 337 {
 338         struct drm_gem_object *gobj;
 339         struct amdgpu_bo *robj;
 340
 341         gobj = drm_gem_object_lookup(filp, handle);
 342         if (gobj == NULL) {
 343                 return -ENOENT;
 344         }
 345         robj = gem_to_amdgpu_bo(gobj);
 346         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 347             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 348                 drm_gem_object_unreference_unlocked(gobj);
 349                 return -EPERM;
 350         }
 351         *offset_p = amdgpu_bo_mmap_offset(robj);
 352         drm_gem_object_unreference_unlocked(gobj);
 353         return 0;
 354 }
 355
 356 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 357                           struct drm_file *filp)
 358 {
 359         union drm_amdgpu_gem_mmap *args = data;
 360         uint32_t handle = args->in.handle;
 361         memset(args, 0, sizeof(*args));
 362         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 363 }
 364
 365 /**
 366  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 367  *
 368  * @timeout_ns: timeout in ns
 369  *
 370  * Calculate the timeout in jiffies from an absolute timeout in ns.
 371  */
 372 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 373 {
 374         unsigned long timeout_jiffies;
 375         ktime_t timeout;
 376
 377         /* clamp timeout if it's to large */
 378         if (((int64_t)timeout_ns) < 0)
 379                 return MAX_SCHEDULE_TIMEOUT;
 380
 381         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 382         if (ktime_to_ns(timeout) < 0)
 383                 return 0;
 384
 385         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 386         /*  clamp timeout to avoid unsigned-> signed overflow */
 387         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 388                 return MAX_SCHEDULE_TIMEOUT - 1;
 389
 390         return timeout_jiffies;
 391 }
 392
 393 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 394                               struct drm_file *filp)
 395 {
 396         struct amdgpu_device *adev = dev->dev_private;
 397         union drm_amdgpu_gem_wait_idle *args = data;
 398         struct drm_gem_object *gobj;
 399         struct amdgpu_bo *robj;
 400         uint32_t handle = args->in.handle;
 401         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 402         int r = 0;
 403         long ret;
 404
 405         gobj = drm_gem_object_lookup(filp, handle);
 406         if (gobj == NULL) {
 407                 return -ENOENT;
 408         }
 409         robj = gem_to_amdgpu_bo(gobj);
 410         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 411                                                   timeout);
 412
 413         /* ret == 0 means not signaled,
 414          * ret > 0 means signaled
 415          * ret < 0 means interrupted before timeout
 416          */
 417         if (ret >= 0) {
 418                 memset(args, 0, sizeof(*args));
 419                 args->out.status = (ret == 0);
 420         } else
 421                 r = ret;
 422
 423         drm_gem_object_unreference_unlocked(gobj);
 424         r = amdgpu_gem_handle_lockup(adev, r);
 425         return r;
 426 }
 427
 428 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 429                                 struct drm_file *filp)
 430 {
 431         struct drm_amdgpu_gem_metadata *args = data;
 432         struct drm_gem_object *gobj;
 433         struct amdgpu_bo *robj;
 434         int r = -1;
 435
 436         DRM_DEBUG("%d \n", args->handle);
 437         gobj = drm_gem_object_lookup(filp, args->handle);
 438         if (gobj == NULL)
 439                 return -ENOENT;
 440         robj = gem_to_amdgpu_bo(gobj);
 441
 442         r = amdgpu_bo_reserve(robj, false);
 443         if (unlikely(r != 0))
 444                 goto out;
 445
 446         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 447                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 448                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 449                                            sizeof(args->data.data),
 450                                            &args->data.data_size_bytes,
 451                                            &args->data.flags);
 452         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 453                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 454                         r = -EINVAL;
 455                         goto unreserve;
 456                 }
 457                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 458                 if (!r)
 459                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 460                                                    args->data.data_size_bytes,
 461                                                    args->data.flags);
 462         }
 463
 464 unreserve:
 465         amdgpu_bo_unreserve(robj);
 466 out:
 467         drm_gem_object_unreference_unlocked(gobj);
 468         return r;
 469 }
 470
 471 /**
 472  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 473  *
 474  * @adev: amdgpu_device pointer
 475  * @bo_va: bo_va to update
 476  *
 477  * Update the bo_va directly after setting it's address. Errors are not
 478  * vital here, so they are not reported back to userspace.
 479  */
 480 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 481                                     struct amdgpu_bo_va *bo_va, uint32_t operation)
 482 {
 483         struct ttm_validate_buffer tv, *entry;
 484         struct amdgpu_bo_list_entry vm_pd;
 485         struct ww_acquire_ctx ticket;
 486         struct list_head list, duplicates;
 487         unsigned domain;
 488         int r;
 489
 490         INIT_LIST_HEAD(&list);
 491         INIT_LIST_HEAD(&duplicates);
 492
 493         tv.bo = &bo_va->bo->tbo;
 494         tv.shared = true;
 495         list_add(&tv.head, &list);
 496
 497         amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
 498
 499         /* Provide duplicates to avoid -EALREADY */
 500         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 501         if (r)
 502                 goto error_print;
 503
 504         amdgpu_vm_get_pt_bos(adev, bo_va->vm, &duplicates);
 505         list_for_each_entry(entry, &list, head) {
 506                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 507                 /* if anything is swapped out don't swap it in here,
 508                    just abort and wait for the next CS */
 509                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 510                         goto error_unreserve;
 511         }
 512         list_for_each_entry(entry, &duplicates, head) {
 513                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 514                 /* if anything is swapped out don't swap it in here,
 515                    just abort and wait for the next CS */
 516                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 517                         goto error_unreserve;
 518         }
 519
 520         r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
 521         if (r)
 522                 goto error_unreserve;
 523
 524         r = amdgpu_vm_clear_freed(adev, bo_va->vm);
 525         if (r)
 526                 goto error_unreserve;
 527
 528         if (operation == AMDGPU_VA_OP_MAP)
 529                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 530
 531 error_unreserve:
 532         ttm_eu_backoff_reservation(&ticket, &list);
 533
 534 error_print:
 535         if (r && r != -ERESTARTSYS)
 536                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 537 }
 538
 539
 540
 541 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 542                           struct drm_file *filp)
 543 {
 544         struct drm_amdgpu_gem_va *args = data;
 545         struct drm_gem_object *gobj;
 546         struct amdgpu_device *adev = dev->dev_private;
 547         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 548         struct amdgpu_bo *abo;
 549         struct amdgpu_bo_va *bo_va;
 550         struct ttm_validate_buffer tv, tv_pd;
 551         struct ww_acquire_ctx ticket;
 552         struct list_head list, duplicates;
 553         uint32_t invalid_flags, va_flags = 0;
 554         int r = 0;
 555
 556         if (!adev->vm_manager.enabled)
 557                 return -ENOTTY;
 558
 559         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 560                 dev_err(&dev->pdev->dev,
 561                         "va_address 0x%lX is in reserved area 0x%X\n",
 562                         (unsigned long)args->va_address,
 563                         AMDGPU_VA_RESERVED_SIZE);
 564                 return -EINVAL;
 565         }
 566
 567         invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
 568                         AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
 569         if ((args->flags & invalid_flags)) {
 570                 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
 571                         args->flags, invalid_flags);
 572                 return -EINVAL;
 573         }
 574
 575         switch (args->operation) {
 576         case AMDGPU_VA_OP_MAP:
 577         case AMDGPU_VA_OP_UNMAP:
 578                 break;
 579         default:
 580                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 581                         args->operation);
 582                 return -EINVAL;
 583         }
 584
 585         gobj = drm_gem_object_lookup(filp, args->handle);
 586         if (gobj == NULL)
 587                 return -ENOENT;
 588         abo = gem_to_amdgpu_bo(gobj);
 589         INIT_LIST_HEAD(&list);
 590         INIT_LIST_HEAD(&duplicates);
 591         tv.bo = &abo->tbo;
 592         tv.shared = true;
 593         list_add(&tv.head, &list);
 594
 595         tv_pd.bo = &fpriv->vm.page_directory->tbo;
 596         tv_pd.shared = true;
 597         list_add(&tv_pd.head, &list);
 598
 599         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 600         if (r) {
 601                 drm_gem_object_unreference_unlocked(gobj);
 602                 return r;
 603         }
 604
 605         bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 606         if (!bo_va) {
 607                 ttm_eu_backoff_reservation(&ticket, &list);
 608                 drm_gem_object_unreference_unlocked(gobj);
 609                 return -ENOENT;
 610         }
 611
 612         switch (args->operation) {
 613         case AMDGPU_VA_OP_MAP:
 614                 if (args->flags & AMDGPU_VM_PAGE_READABLE)
 615                         va_flags |= AMDGPU_PTE_READABLE;
 616                 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
 617                         va_flags |= AMDGPU_PTE_WRITEABLE;
 618                 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
 619                         va_flags |= AMDGPU_PTE_EXECUTABLE;
 620                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 621                                      args->offset_in_bo, args->map_size,
 622                                      va_flags);
 623                 break;
 624         case AMDGPU_VA_OP_UNMAP:
 625                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 626                 break;
 627         default:
 628                 break;
 629         }
 630         ttm_eu_backoff_reservation(&ticket, &list);
 631         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
 632             !amdgpu_vm_debug)
 633                 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
 634
 635         drm_gem_object_unreference_unlocked(gobj);
 636         return r;
 637 }
 638
 639 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 640                         struct drm_file *filp)
 641 {
 642         struct drm_amdgpu_gem_op *args = data;
 643         struct drm_gem_object *gobj;
 644         struct amdgpu_bo *robj;
 645         int r;
 646
 647         gobj = drm_gem_object_lookup(filp, args->handle);
 648         if (gobj == NULL) {
 649                 return -ENOENT;
 650         }
 651         robj = gem_to_amdgpu_bo(gobj);
 652
 653         r = amdgpu_bo_reserve(robj, false);
 654         if (unlikely(r))
 655                 goto out;
 656
 657         switch (args->op) {
 658         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 659                 struct drm_amdgpu_gem_create_in info;
 660                 void __user *out = (void __user *)(long)args->value;
 661
 662                 info.bo_size = robj->gem_base.size;
 663                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 664                 info.domains = robj->prefered_domains;
 665                 info.domain_flags = robj->flags;
 666                 amdgpu_bo_unreserve(robj);
 667                 if (copy_to_user(out, &info, sizeof(info)))
 668                         r = -EFAULT;
 669                 break;
 670         }
 671         case AMDGPU_GEM_OP_SET_PLACEMENT:
 672                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 673                         r = -EPERM;
 674                         amdgpu_bo_unreserve(robj);
 675                         break;
 676                 }
 677                 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 678                                                         AMDGPU_GEM_DOMAIN_GTT |
 679                                                         AMDGPU_GEM_DOMAIN_CPU);
 680                 robj->allowed_domains = robj->prefered_domains;
 681                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 682                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 683
 684                 amdgpu_bo_unreserve(robj);
 685                 break;
 686         default:
 687                 amdgpu_bo_unreserve(robj);
 688                 r = -EINVAL;
 689         }
 690
 691 out:
 692         drm_gem_object_unreference_unlocked(gobj);
 693         return r;
 694 }
 695
 696 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 697                             struct drm_device *dev,
 698                             struct drm_mode_create_dumb *args)
 699 {
 700         struct amdgpu_device *adev = dev->dev_private;
 701         struct drm_gem_object *gobj;
 702         uint32_t handle;
 703         int r;
 704
 705         args->pitch = amdgpu_align_pitch(adev, args->width,
 706                                          DIV_ROUND_UP(args->bpp, 8), 0);
 707         args->size = (u64)args->pitch * args->height;
 708         args->size = ALIGN(args->size, PAGE_SIZE);
 709
 710         r = amdgpu_gem_object_create(adev, args->size, 0,
 711                                      AMDGPU_GEM_DOMAIN_VRAM,
 712                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 713                                      ttm_bo_type_device,
 714                                      &gobj);
 715         if (r)
 716                 return -ENOMEM;
 717
 718         r = drm_gem_handle_create(file_priv, gobj, &handle);
 719         /* drop reference from allocate - handle holds it now */
 720         drm_gem_object_unreference_unlocked(gobj);
 721         if (r) {
 722                 return r;
 723         }
 724         args->handle = handle;
 725         return 0;
 726 }
 727
 728 #if defined(CONFIG_DEBUG_FS)
 729 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 730 {
 731         struct drm_gem_object *gobj = ptr;
 732         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 733         struct seq_file *m = data;
 734
 735         unsigned domain;
 736         const char *placement;
 737         unsigned pin_count;
 738
 739         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 740         switch (domain) {
 741         case AMDGPU_GEM_DOMAIN_VRAM:
 742                 placement = "VRAM";
 743                 break;
 744         case AMDGPU_GEM_DOMAIN_GTT:
 745                 placement = " GTT";
 746                 break;
 747         case AMDGPU_GEM_DOMAIN_CPU:
 748         default:
 749                 placement = " CPU";
 750                 break;
 751         }
 752         seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
 753                    id, amdgpu_bo_size(bo), placement,
 754                    amdgpu_bo_gpu_offset(bo));
 755
 756         pin_count = ACCESS_ONCE(bo->pin_count);
 757         if (pin_count)
 758                 seq_printf(m, " pin count %d", pin_count);
 759         seq_printf(m, "\n");
 760
 761         return 0;
 762 }
 763
 764 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 765 {
 766         struct drm_info_node *node = (struct drm_info_node *)m->private;
 767         struct drm_device *dev = node->minor->dev;
 768         struct drm_file *file;
 769         int r;
 770
 771         r = mutex_lock_interruptible(&dev->filelist_mutex);
 772         if (r)
 773                 return r;
 774
 775         list_for_each_entry(file, &dev->filelist, lhead) {
 776                 struct task_struct *task;
 777
 778                 /*
 779                  * Although we have a valid reference on file->pid, that does
 780                  * not guarantee that the task_struct who called get_pid() is
 781                  * still alive (e.g. get_pid(current) => fork() => exit()).
 782                  * Therefore, we need to protect this ->comm access using RCU.
 783                  */
 784                 rcu_read_lock();
 785                 task = pid_task(file->pid, PIDTYPE_PID);
 786                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 787                            task ? task->comm : "<unknown>");
 788                 rcu_read_unlock();
 789
 790                 spin_lock(&file->table_lock);
 791                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 792                 spin_unlock(&file->table_lock);
 793         }
 794
 795         mutex_unlock(&dev->filelist_mutex);
 796         return 0;
 797 }
 798
 799 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 800         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 801 };
 802 #endif
 803
 804 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 805 {
 806 #if defined(CONFIG_DEBUG_FS)
 807         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 808 #endif
 809         return 0;
 810 }