2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/cec.h>
33 #include <linux/hdmi.h>
34 #include <linux/i2c.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
41 #include <drm/drm_displayid.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_encoder.h>
45 #include <drm/drm_print.h>
47 #include "drm_crtc_internal.h"
49 static int oui(u8 first, u8 second, u8 third)
51 return (first << 16) | (second << 8) | third;
54 #define EDID_EST_TIMINGS 16
55 #define EDID_STD_TIMINGS 8
56 #define EDID_DETAILED_TIMINGS 4
59 * EDID blocks out in the wild have a variety of bugs, try to collect
60 * them here (note that userspace may work around broken monitors first,
61 * but fixes should make their way here so that the kernel "just works"
62 * on as many displays as possible).
65 /* First detailed mode wrong, use largest 60Hz mode */
66 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
67 /* Reported 135MHz pixel clock is too high, needs adjustment */
68 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
69 /* Prefer the largest mode at 75 Hz */
70 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
71 /* Detail timing is in cm not mm */
72 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
73 /* Detailed timing descriptors have bogus size values, so just take the
74 * maximum size and use that.
76 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
77 /* use +hsync +vsync for detailed mode */
78 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
79 /* Force reduced-blanking timings for detailed modes */
80 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
82 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
84 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
86 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
88 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
89 /* Non desktop display (i.e. HMD) */
90 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 /* Cap the DSC target bitrate to 15bpp */
92 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
94 #define MICROSOFT_IEEE_OUI 0xca125c
96 struct detailed_mode_closure {
97 struct drm_connector *connector;
98 const struct drm_edid *drm_edid;
108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
115 static const struct edid_quirk {
118 } edid_quirk_list[] = {
120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
127 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
128 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
130 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
131 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
133 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
134 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
136 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
137 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
139 /* Belinea 10 15 55 */
140 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
141 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
143 /* Envision Peripherals, Inc. EN-7100e */
144 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
145 /* Envision EN2028 */
146 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
148 /* Funai Electronics PM36B */
149 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
150 EDID_QUIRK_DETAILED_IN_CM),
153 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
156 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
158 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
159 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
161 /* LG Philips LCD LP154W01-A5 */
162 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
163 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
165 /* Samsung SyncMaster 205BW. Note: irony */
166 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
167 /* Samsung SyncMaster 22[5-6]BW */
168 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
169 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
171 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
172 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
174 /* ViewSonic VA2026w */
175 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
177 /* Medion MD 30217 PG */
178 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
181 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
183 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
184 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
186 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
187 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
189 /* Valve Index Headset */
190 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
208 /* HTC Vive and Vive Pro VR Headsets */
209 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
212 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
213 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
218 /* Windows Mixed Reality Headsets */
219 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
226 /* Sony PlayStation VR Headset */
227 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
229 /* Sensics VR Headsets */
230 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
232 /* OSVR HDK and HDK2 VR Headsets */
233 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
234 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
238 * Autogenerated from the DMT spec.
239 * This table is copied from xfree86/modes/xf86EdidModes.c.
241 static const struct drm_display_mode drm_dmt_modes[] = {
242 /* 0x01 - 640x350@85Hz */
243 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 350, 382, 385, 445, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
246 /* 0x02 - 640x400@85Hz */
247 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
248 736, 832, 0, 400, 401, 404, 445, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x03 - 720x400@85Hz */
251 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
252 828, 936, 0, 400, 401, 404, 446, 0,
253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
254 /* 0x04 - 640x480@60Hz */
255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
256 752, 800, 0, 480, 490, 492, 525, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 0x05 - 640x480@72Hz */
259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
260 704, 832, 0, 480, 489, 492, 520, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x06 - 640x480@75Hz */
263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
264 720, 840, 0, 480, 481, 484, 500, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
266 /* 0x07 - 640x480@85Hz */
267 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
268 752, 832, 0, 480, 481, 484, 509, 0,
269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x08 - 800x600@56Hz */
271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
272 896, 1024, 0, 600, 601, 603, 625, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x09 - 800x600@60Hz */
275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
276 968, 1056, 0, 600, 601, 605, 628, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x0a - 800x600@72Hz */
279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
280 976, 1040, 0, 600, 637, 643, 666, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x0b - 800x600@75Hz */
283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
284 896, 1056, 0, 600, 601, 604, 625, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x0c - 800x600@85Hz */
287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
288 896, 1048, 0, 600, 601, 604, 631, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 0x0d - 800x600@120Hz RB */
291 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
292 880, 960, 0, 600, 603, 607, 636, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
294 /* 0x0e - 848x480@60Hz */
295 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
296 976, 1088, 0, 480, 486, 494, 517, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x0f - 1024x768@43Hz, interlace */
299 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
300 1208, 1264, 0, 768, 768, 776, 817, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
302 DRM_MODE_FLAG_INTERLACE) },
303 /* 0x10 - 1024x768@60Hz */
304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
305 1184, 1344, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
307 /* 0x11 - 1024x768@70Hz */
308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
309 1184, 1328, 0, 768, 771, 777, 806, 0,
310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x12 - 1024x768@75Hz */
312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
313 1136, 1312, 0, 768, 769, 772, 800, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x13 - 1024x768@85Hz */
316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
317 1168, 1376, 0, 768, 769, 772, 808, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x14 - 1024x768@120Hz RB */
320 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
321 1104, 1184, 0, 768, 771, 775, 813, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
323 /* 0x15 - 1152x864@75Hz */
324 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
325 1344, 1600, 0, 864, 865, 868, 900, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x55 - 1280x720@60Hz */
328 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
329 1430, 1650, 0, 720, 725, 730, 750, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x16 - 1280x768@60Hz RB */
332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
333 1360, 1440, 0, 768, 771, 778, 790, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
335 /* 0x17 - 1280x768@60Hz */
336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
337 1472, 1664, 0, 768, 771, 778, 798, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x18 - 1280x768@75Hz */
340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
341 1488, 1696, 0, 768, 771, 778, 805, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x19 - 1280x768@85Hz */
344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
345 1496, 1712, 0, 768, 771, 778, 809, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
347 /* 0x1a - 1280x768@120Hz RB */
348 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
349 1360, 1440, 0, 768, 771, 778, 813, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
351 /* 0x1b - 1280x800@60Hz RB */
352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
353 1360, 1440, 0, 800, 803, 809, 823, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
355 /* 0x1c - 1280x800@60Hz */
356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
357 1480, 1680, 0, 800, 803, 809, 831, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x1d - 1280x800@75Hz */
360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
361 1488, 1696, 0, 800, 803, 809, 838, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x1e - 1280x800@85Hz */
364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
365 1496, 1712, 0, 800, 803, 809, 843, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x1f - 1280x800@120Hz RB */
368 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
369 1360, 1440, 0, 800, 803, 809, 847, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
371 /* 0x20 - 1280x960@60Hz */
372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
373 1488, 1800, 0, 960, 961, 964, 1000, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x21 - 1280x960@85Hz */
376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
377 1504, 1728, 0, 960, 961, 964, 1011, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x22 - 1280x960@120Hz RB */
380 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
381 1360, 1440, 0, 960, 963, 967, 1017, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
383 /* 0x23 - 1280x1024@60Hz */
384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x24 - 1280x1024@75Hz */
388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
389 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x25 - 1280x1024@85Hz */
392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
393 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
395 /* 0x26 - 1280x1024@120Hz RB */
396 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
397 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
399 /* 0x27 - 1360x768@60Hz */
400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
401 1536, 1792, 0, 768, 771, 777, 795, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x28 - 1360x768@120Hz RB */
404 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
405 1440, 1520, 0, 768, 771, 776, 813, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
407 /* 0x51 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
409 1579, 1792, 0, 768, 771, 774, 798, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x56 - 1366x768@60Hz */
412 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
413 1436, 1500, 0, 768, 769, 772, 800, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x29 - 1400x1050@60Hz RB */
416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
417 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
419 /* 0x2a - 1400x1050@60Hz */
420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
421 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x2b - 1400x1050@75Hz */
424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
425 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x2c - 1400x1050@85Hz */
428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
429 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x2d - 1400x1050@120Hz RB */
432 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
433 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x2e - 1440x900@60Hz RB */
436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
437 1520, 1600, 0, 900, 903, 909, 926, 0,
438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
439 /* 0x2f - 1440x900@60Hz */
440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
441 1672, 1904, 0, 900, 903, 909, 934, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x30 - 1440x900@75Hz */
444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
445 1688, 1936, 0, 900, 903, 909, 942, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x31 - 1440x900@85Hz */
448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
449 1696, 1952, 0, 900, 903, 909, 948, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x32 - 1440x900@120Hz RB */
452 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
453 1520, 1600, 0, 900, 903, 909, 953, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 0x53 - 1600x900@60Hz */
456 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
457 1704, 1800, 0, 900, 901, 904, 1000, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x33 - 1600x1200@60Hz */
460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x34 - 1600x1200@65Hz */
464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x35 - 1600x1200@70Hz */
468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x36 - 1600x1200@75Hz */
472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x37 - 1600x1200@85Hz */
476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
477 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x38 - 1600x1200@120Hz RB */
480 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
481 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x39 - 1680x1050@60Hz RB */
484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
485 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
487 /* 0x3a - 1680x1050@60Hz */
488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
489 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x3b - 1680x1050@75Hz */
492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
493 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x3c - 1680x1050@85Hz */
496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
497 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x3d - 1680x1050@120Hz RB */
500 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
501 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x3e - 1792x1344@60Hz */
504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
505 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
507 /* 0x3f - 1792x1344@75Hz */
508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
509 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
510 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
511 /* 0x40 - 1792x1344@120Hz RB */
512 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
513 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
515 /* 0x41 - 1856x1392@60Hz */
516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
517 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x42 - 1856x1392@75Hz */
520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
521 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 0x43 - 1856x1392@120Hz RB */
524 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
525 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x52 - 1920x1080@60Hz */
528 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
529 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 /* 0x44 - 1920x1200@60Hz RB */
532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
533 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
535 /* 0x45 - 1920x1200@60Hz */
536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
537 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
539 /* 0x46 - 1920x1200@75Hz */
540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
541 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 0x47 - 1920x1200@85Hz */
544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
545 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
547 /* 0x48 - 1920x1200@120Hz RB */
548 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
549 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
551 /* 0x49 - 1920x1440@60Hz */
552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
553 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 0x4a - 1920x1440@75Hz */
556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
557 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
559 /* 0x4b - 1920x1440@120Hz RB */
560 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
561 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
563 /* 0x54 - 2048x1152@60Hz */
564 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
565 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
567 /* 0x4c - 2560x1600@60Hz RB */
568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
569 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
571 /* 0x4d - 2560x1600@60Hz */
572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
573 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
575 /* 0x4e - 2560x1600@75Hz */
576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
579 /* 0x4f - 2560x1600@85Hz */
580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
581 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
583 /* 0x50 - 2560x1600@120Hz RB */
584 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
585 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x57 - 4096x2160@60Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
592 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
593 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
598 * These more or less come from the DMT spec. The 720x400 modes are
599 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
600 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
601 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
604 * The DMT modes have been fact-checked; the rest are mild guesses.
606 static const struct drm_display_mode edid_est_modes[] = {
607 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
608 968, 1056, 0, 600, 601, 605, 628, 0,
609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
611 896, 1024, 0, 600, 601, 603, 625, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
614 720, 840, 0, 480, 481, 484, 500, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
616 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
617 704, 832, 0, 480, 489, 492, 520, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
619 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
620 768, 864, 0, 480, 483, 486, 525, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
622 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
623 752, 800, 0, 480, 490, 492, 525, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
625 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
626 846, 900, 0, 400, 421, 423, 449, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
628 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
629 846, 900, 0, 400, 412, 414, 449, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
631 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
632 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
634 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
635 1136, 1312, 0, 768, 769, 772, 800, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
637 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
638 1184, 1328, 0, 768, 771, 777, 806, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
640 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
641 1184, 1344, 0, 768, 771, 777, 806, 0,
642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
643 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
644 1208, 1264, 0, 768, 768, 776, 817, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
646 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
647 928, 1152, 0, 624, 625, 628, 667, 0,
648 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
649 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
650 896, 1056, 0, 600, 601, 604, 625, 0,
651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
652 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
653 976, 1040, 0, 600, 637, 643, 666, 0,
654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
655 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
656 1344, 1600, 0, 864, 865, 868, 900, 0,
657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
667 static const struct minimode est3_modes[] = {
675 { 1024, 768, 85, 0 },
676 { 1152, 864, 75, 0 },
678 { 1280, 768, 60, 1 },
679 { 1280, 768, 60, 0 },
680 { 1280, 768, 75, 0 },
681 { 1280, 768, 85, 0 },
682 { 1280, 960, 60, 0 },
683 { 1280, 960, 85, 0 },
684 { 1280, 1024, 60, 0 },
685 { 1280, 1024, 85, 0 },
687 { 1360, 768, 60, 0 },
688 { 1440, 900, 60, 1 },
689 { 1440, 900, 60, 0 },
690 { 1440, 900, 75, 0 },
691 { 1440, 900, 85, 0 },
692 { 1400, 1050, 60, 1 },
693 { 1400, 1050, 60, 0 },
694 { 1400, 1050, 75, 0 },
696 { 1400, 1050, 85, 0 },
697 { 1680, 1050, 60, 1 },
698 { 1680, 1050, 60, 0 },
699 { 1680, 1050, 75, 0 },
700 { 1680, 1050, 85, 0 },
701 { 1600, 1200, 60, 0 },
702 { 1600, 1200, 65, 0 },
703 { 1600, 1200, 70, 0 },
705 { 1600, 1200, 75, 0 },
706 { 1600, 1200, 85, 0 },
707 { 1792, 1344, 60, 0 },
708 { 1792, 1344, 75, 0 },
709 { 1856, 1392, 60, 0 },
710 { 1856, 1392, 75, 0 },
711 { 1920, 1200, 60, 1 },
712 { 1920, 1200, 60, 0 },
714 { 1920, 1200, 75, 0 },
715 { 1920, 1200, 85, 0 },
716 { 1920, 1440, 60, 0 },
717 { 1920, 1440, 75, 0 },
720 static const struct minimode extra_modes[] = {
721 { 1024, 576, 60, 0 },
722 { 1366, 768, 60, 0 },
723 { 1600, 900, 60, 0 },
724 { 1680, 945, 60, 0 },
725 { 1920, 1080, 60, 0 },
726 { 2048, 1152, 60, 0 },
727 { 2048, 1536, 60, 0 },
731 * From CEA/CTA-861 spec.
733 * Do not access directly, instead always use cea_mode_for_vic().
735 static const struct drm_display_mode edid_cea_modes_1[] = {
736 /* 1 - 640x480@60Hz 4:3 */
737 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
738 752, 800, 0, 480, 490, 492, 525, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
741 /* 2 - 720x480@60Hz 4:3 */
742 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
743 798, 858, 0, 480, 489, 495, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 3 - 720x480@60Hz 16:9 */
747 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
748 798, 858, 0, 480, 489, 495, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 4 - 1280x720@60Hz 16:9 */
752 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
753 1430, 1650, 0, 720, 725, 730, 750, 0,
754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 5 - 1920x1080i@60Hz 16:9 */
757 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
758 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
760 DRM_MODE_FLAG_INTERLACE),
761 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
762 /* 6 - 720(1440)x480i@60Hz 4:3 */
763 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 480, 488, 494, 525, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
767 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
768 /* 7 - 720(1440)x480i@60Hz 16:9 */
769 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
770 801, 858, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
773 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 8 - 720(1440)x240@60Hz 4:3 */
775 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
776 801, 858, 0, 240, 244, 247, 262, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_DBLCLK),
779 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
780 /* 9 - 720(1440)x240@60Hz 16:9 */
781 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
782 801, 858, 0, 240, 244, 247, 262, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
784 DRM_MODE_FLAG_DBLCLK),
785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
786 /* 10 - 2880x480i@60Hz 4:3 */
787 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 480, 488, 494, 525, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
790 DRM_MODE_FLAG_INTERLACE),
791 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 11 - 2880x480i@60Hz 16:9 */
793 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
794 3204, 3432, 0, 480, 488, 494, 525, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
796 DRM_MODE_FLAG_INTERLACE),
797 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798 /* 12 - 2880x240@60Hz 4:3 */
799 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
800 3204, 3432, 0, 240, 244, 247, 262, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
803 /* 13 - 2880x240@60Hz 16:9 */
804 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
805 3204, 3432, 0, 240, 244, 247, 262, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 14 - 1440x480@60Hz 4:3 */
809 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
810 1596, 1716, 0, 480, 489, 495, 525, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
813 /* 15 - 1440x480@60Hz 16:9 */
814 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
815 1596, 1716, 0, 480, 489, 495, 525, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
818 /* 16 - 1920x1080@60Hz 16:9 */
819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
820 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 17 - 720x576@50Hz 4:3 */
824 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
825 796, 864, 0, 576, 581, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828 /* 18 - 720x576@50Hz 16:9 */
829 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
830 796, 864, 0, 576, 581, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 19 - 1280x720@50Hz 16:9 */
834 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
835 1760, 1980, 0, 720, 725, 730, 750, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 20 - 1920x1080i@50Hz 16:9 */
839 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
840 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
842 DRM_MODE_FLAG_INTERLACE),
843 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
844 /* 21 - 720(1440)x576i@50Hz 4:3 */
845 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 576, 580, 586, 625, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
849 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
850 /* 22 - 720(1440)x576i@50Hz 16:9 */
851 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
852 795, 864, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
854 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
855 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
856 /* 23 - 720(1440)x288@50Hz 4:3 */
857 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
858 795, 864, 0, 288, 290, 293, 312, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
860 DRM_MODE_FLAG_DBLCLK),
861 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
862 /* 24 - 720(1440)x288@50Hz 16:9 */
863 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
864 795, 864, 0, 288, 290, 293, 312, 0,
865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
866 DRM_MODE_FLAG_DBLCLK),
867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 25 - 2880x576i@50Hz 4:3 */
869 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 576, 580, 586, 625, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
872 DRM_MODE_FLAG_INTERLACE),
873 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
874 /* 26 - 2880x576i@50Hz 16:9 */
875 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
876 3180, 3456, 0, 576, 580, 586, 625, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
878 DRM_MODE_FLAG_INTERLACE),
879 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 27 - 2880x288@50Hz 4:3 */
881 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
882 3180, 3456, 0, 288, 290, 293, 312, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
885 /* 28 - 2880x288@50Hz 16:9 */
886 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
887 3180, 3456, 0, 288, 290, 293, 312, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 29 - 1440x576@50Hz 4:3 */
891 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
892 1592, 1728, 0, 576, 581, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
895 /* 30 - 1440x576@50Hz 16:9 */
896 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
897 1592, 1728, 0, 576, 581, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 31 - 1920x1080@50Hz 16:9 */
901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
902 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 32 - 1920x1080@24Hz 16:9 */
906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
907 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 33 - 1920x1080@25Hz 16:9 */
911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
912 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 34 - 1920x1080@30Hz 16:9 */
916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
917 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 35 - 2880x480@60Hz 4:3 */
921 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
922 3192, 3432, 0, 480, 489, 495, 525, 0,
923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
925 /* 36 - 2880x480@60Hz 16:9 */
926 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
927 3192, 3432, 0, 480, 489, 495, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930 /* 37 - 2880x576@50Hz 4:3 */
931 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
932 3184, 3456, 0, 576, 581, 586, 625, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
935 /* 38 - 2880x576@50Hz 16:9 */
936 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
937 3184, 3456, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 39 - 1920x1080i@50Hz 16:9 */
941 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
942 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
944 DRM_MODE_FLAG_INTERLACE),
945 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
946 /* 40 - 1920x1080i@100Hz 16:9 */
947 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
948 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
950 DRM_MODE_FLAG_INTERLACE),
951 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
952 /* 41 - 1280x720@100Hz 16:9 */
953 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
954 1760, 1980, 0, 720, 725, 730, 750, 0,
955 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 42 - 720x576@100Hz 4:3 */
958 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
959 796, 864, 0, 576, 581, 586, 625, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
962 /* 43 - 720x576@100Hz 16:9 */
963 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
964 796, 864, 0, 576, 581, 586, 625, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 44 - 720(1440)x576i@100Hz 4:3 */
968 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
969 795, 864, 0, 576, 580, 586, 625, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
971 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
973 /* 45 - 720(1440)x576i@100Hz 16:9 */
974 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
975 795, 864, 0, 576, 580, 586, 625, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
977 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
978 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 46 - 1920x1080i@120Hz 16:9 */
980 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
981 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
983 DRM_MODE_FLAG_INTERLACE),
984 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 47 - 1280x720@120Hz 16:9 */
986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
987 1430, 1650, 0, 720, 725, 730, 750, 0,
988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 48 - 720x480@120Hz 4:3 */
991 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
992 798, 858, 0, 480, 489, 495, 525, 0,
993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
995 /* 49 - 720x480@120Hz 16:9 */
996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
997 798, 858, 0, 480, 489, 495, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1000 /* 50 - 720(1440)x480i@120Hz 4:3 */
1001 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1002 801, 858, 0, 480, 488, 494, 525, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1004 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1005 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1006 /* 51 - 720(1440)x480i@120Hz 16:9 */
1007 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1008 801, 858, 0, 480, 488, 494, 525, 0,
1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1010 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1012 /* 52 - 720x576@200Hz 4:3 */
1013 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1014 796, 864, 0, 576, 581, 586, 625, 0,
1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1017 /* 53 - 720x576@200Hz 16:9 */
1018 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1019 796, 864, 0, 576, 581, 586, 625, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1022 /* 54 - 720(1440)x576i@200Hz 4:3 */
1023 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1024 795, 864, 0, 576, 580, 586, 625, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1026 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1028 /* 55 - 720(1440)x576i@200Hz 16:9 */
1029 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1030 795, 864, 0, 576, 580, 586, 625, 0,
1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1034 /* 56 - 720x480@240Hz 4:3 */
1035 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1036 798, 858, 0, 480, 489, 495, 525, 0,
1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1039 /* 57 - 720x480@240Hz 16:9 */
1040 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1041 798, 858, 0, 480, 489, 495, 525, 0,
1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044 /* 58 - 720(1440)x480i@240Hz 4:3 */
1045 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1046 801, 858, 0, 480, 488, 494, 525, 0,
1047 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1048 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1050 /* 59 - 720(1440)x480i@240Hz 16:9 */
1051 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1052 801, 858, 0, 480, 488, 494, 525, 0,
1053 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1054 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1055 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1056 /* 60 - 1280x720@24Hz 16:9 */
1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1058 3080, 3300, 0, 720, 725, 730, 750, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 61 - 1280x720@25Hz 16:9 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1063 3740, 3960, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 62 - 1280x720@30Hz 16:9 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1068 3080, 3300, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071 /* 63 - 1920x1080@120Hz 16:9 */
1072 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1073 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1076 /* 64 - 1920x1080@100Hz 16:9 */
1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1078 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1081 /* 65 - 1280x720@24Hz 64:27 */
1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1083 3080, 3300, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 66 - 1280x720@25Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1088 3740, 3960, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 67 - 1280x720@30Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1093 3080, 3300, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 68 - 1280x720@50Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1098 1760, 1980, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 69 - 1280x720@60Hz 64:27 */
1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1103 1430, 1650, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 70 - 1280x720@100Hz 64:27 */
1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1108 1760, 1980, 0, 720, 725, 730, 750, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 71 - 1280x720@120Hz 64:27 */
1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1113 1430, 1650, 0, 720, 725, 730, 750, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 72 - 1920x1080@24Hz 64:27 */
1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1118 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 73 - 1920x1080@25Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1123 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 74 - 1920x1080@30Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1128 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 75 - 1920x1080@50Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1133 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 76 - 1920x1080@60Hz 64:27 */
1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1138 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 77 - 1920x1080@100Hz 64:27 */
1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1143 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 78 - 1920x1080@120Hz 64:27 */
1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1148 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 79 - 1680x720@24Hz 64:27 */
1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1153 3080, 3300, 0, 720, 725, 730, 750, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 80 - 1680x720@25Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1158 2948, 3168, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 81 - 1680x720@30Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1163 2420, 2640, 0, 720, 725, 730, 750, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 82 - 1680x720@50Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1168 1980, 2200, 0, 720, 725, 730, 750, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 83 - 1680x720@60Hz 64:27 */
1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1173 1980, 2200, 0, 720, 725, 730, 750, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 84 - 1680x720@100Hz 64:27 */
1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1178 1780, 2000, 0, 720, 725, 730, 825, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 85 - 1680x720@120Hz 64:27 */
1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1183 1780, 2000, 0, 720, 725, 730, 825, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 86 - 2560x1080@24Hz 64:27 */
1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1188 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 87 - 2560x1080@25Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1193 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 88 - 2560x1080@30Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1198 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 89 - 2560x1080@50Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1203 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 90 - 2560x1080@60Hz 64:27 */
1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1208 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 91 - 2560x1080@100Hz 64:27 */
1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1213 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 92 - 2560x1080@120Hz 64:27 */
1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1218 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221 /* 93 - 3840x2160@24Hz 16:9 */
1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1223 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1226 /* 94 - 3840x2160@25Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1228 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 95 - 3840x2160@30Hz 16:9 */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1233 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236 /* 96 - 3840x2160@50Hz 16:9 */
1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1238 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1241 /* 97 - 3840x2160@60Hz 16:9 */
1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1243 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1246 /* 98 - 4096x2160@24Hz 256:135 */
1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1248 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1251 /* 99 - 4096x2160@25Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1253 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 100 - 4096x2160@30Hz 256:135 */
1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1258 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261 /* 101 - 4096x2160@50Hz 256:135 */
1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1263 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1266 /* 102 - 4096x2160@60Hz 256:135 */
1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1268 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1271 /* 103 - 3840x2160@24Hz 64:27 */
1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1273 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1276 /* 104 - 3840x2160@25Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1278 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 /* 105 - 3840x2160@30Hz 64:27 */
1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1283 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286 /* 106 - 3840x2160@50Hz 64:27 */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1288 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1291 /* 107 - 3840x2160@60Hz 64:27 */
1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1293 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1296 /* 108 - 1280x720@48Hz 16:9 */
1297 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1298 2280, 2500, 0, 720, 725, 730, 750, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1301 /* 109 - 1280x720@48Hz 64:27 */
1302 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1303 2280, 2500, 0, 720, 725, 730, 750, 0,
1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1306 /* 110 - 1680x720@48Hz 64:27 */
1307 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1308 2530, 2750, 0, 720, 725, 730, 750, 0,
1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311 /* 111 - 1920x1080@48Hz 16:9 */
1312 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1313 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1316 /* 112 - 1920x1080@48Hz 64:27 */
1317 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1318 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1321 /* 113 - 2560x1080@48Hz 64:27 */
1322 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1323 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1326 /* 114 - 3840x2160@48Hz 16:9 */
1327 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1328 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1331 /* 115 - 4096x2160@48Hz 256:135 */
1332 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1336 /* 116 - 3840x2160@48Hz 64:27 */
1337 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1338 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1341 /* 117 - 3840x2160@100Hz 16:9 */
1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1343 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1346 /* 118 - 3840x2160@120Hz 16:9 */
1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1348 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1351 /* 119 - 3840x2160@100Hz 64:27 */
1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1353 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1356 /* 120 - 3840x2160@120Hz 64:27 */
1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1358 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361 /* 121 - 5120x2160@24Hz 64:27 */
1362 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1363 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366 /* 122 - 5120x2160@25Hz 64:27 */
1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1368 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371 /* 123 - 5120x2160@30Hz 64:27 */
1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1373 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376 /* 124 - 5120x2160@48Hz 64:27 */
1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1378 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 /* 125 - 5120x2160@50Hz 64:27 */
1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1383 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386 /* 126 - 5120x2160@60Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 127 - 5120x2160@100Hz 64:27 */
1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1393 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1399 * From CEA/CTA-861 spec.
1401 * Do not access directly, instead always use cea_mode_for_vic().
1403 static const struct drm_display_mode edid_cea_modes_193[] = {
1404 /* 193 - 5120x2160@120Hz 64:27 */
1405 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1406 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1408 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1409 /* 194 - 7680x4320@24Hz 16:9 */
1410 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1411 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1414 /* 195 - 7680x4320@25Hz 16:9 */
1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1416 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419 /* 196 - 7680x4320@30Hz 16:9 */
1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1421 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424 /* 197 - 7680x4320@48Hz 16:9 */
1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1426 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429 /* 198 - 7680x4320@50Hz 16:9 */
1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1431 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434 /* 199 - 7680x4320@60Hz 16:9 */
1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1436 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439 /* 200 - 7680x4320@100Hz 16:9 */
1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1441 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444 /* 201 - 7680x4320@120Hz 16:9 */
1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1446 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1449 /* 202 - 7680x4320@24Hz 64:27 */
1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1451 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1454 /* 203 - 7680x4320@25Hz 64:27 */
1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1456 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459 /* 204 - 7680x4320@30Hz 64:27 */
1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1461 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464 /* 205 - 7680x4320@48Hz 64:27 */
1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1466 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469 /* 206 - 7680x4320@50Hz 64:27 */
1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1471 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474 /* 207 - 7680x4320@60Hz 64:27 */
1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1476 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479 /* 208 - 7680x4320@100Hz 64:27 */
1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1481 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484 /* 209 - 7680x4320@120Hz 64:27 */
1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1486 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489 /* 210 - 10240x4320@24Hz 64:27 */
1490 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1491 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494 /* 211 - 10240x4320@25Hz 64:27 */
1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1496 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499 /* 212 - 10240x4320@30Hz 64:27 */
1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1501 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504 /* 213 - 10240x4320@48Hz 64:27 */
1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1506 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509 /* 214 - 10240x4320@50Hz 64:27 */
1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1511 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514 /* 215 - 10240x4320@60Hz 64:27 */
1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1516 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519 /* 216 - 10240x4320@100Hz 64:27 */
1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1521 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524 /* 217 - 10240x4320@120Hz 64:27 */
1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1526 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1529 /* 218 - 4096x2160@100Hz 256:135 */
1530 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1531 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1534 /* 219 - 4096x2160@120Hz 256:135 */
1535 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1536 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1542 * HDMI 1.4 4k modes. Index using the VIC.
1544 static const struct drm_display_mode edid_4k_modes[] = {
1545 /* 0 - dummy, VICs start at 1 */
1547 /* 1 - 3840x2160@30Hz */
1548 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1549 3840, 4016, 4104, 4400, 0,
1550 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1553 /* 2 - 3840x2160@25Hz */
1554 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1555 3840, 4896, 4984, 5280, 0,
1556 2160, 2168, 2178, 2250, 0,
1557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1558 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1559 /* 3 - 3840x2160@24Hz */
1560 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1561 3840, 5116, 5204, 5500, 0,
1562 2160, 2168, 2178, 2250, 0,
1563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1564 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1565 /* 4 - 4096x2160@24Hz (SMPTE) */
1566 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1567 4096, 5116, 5204, 5500, 0,
1568 2160, 2168, 2178, 2250, 0,
1569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1570 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1573 /*** DDC fetch and block validation ***/
1576 * The opaque EDID type, internal to drm_edid.c.
1579 /* Size allocated for edid */
1581 const struct edid *edid;
1584 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1586 static int edid_hfeeodb_block_count(const struct edid *edid)
1588 int eeodb = edid_hfeeodb_extension_block_count(edid);
1590 return eeodb ? eeodb + 1 : 0;
1593 static int edid_extension_block_count(const struct edid *edid)
1595 return edid->extensions;
1598 static int edid_block_count(const struct edid *edid)
1600 return edid_extension_block_count(edid) + 1;
1603 static int edid_size_by_blocks(int num_blocks)
1605 return num_blocks * EDID_LENGTH;
1608 static int edid_size(const struct edid *edid)
1610 return edid_size_by_blocks(edid_block_count(edid));
1613 static const void *edid_block_data(const struct edid *edid, int index)
1615 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1617 return edid + index;
1620 static const void *edid_extension_block_data(const struct edid *edid, int index)
1622 return edid_block_data(edid, index + 1);
1625 /* EDID block count indicated in EDID, may exceed allocated size */
1626 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1630 /* Starting point */
1631 num_blocks = edid_block_count(drm_edid->edid);
1633 /* HF-EEODB override */
1634 if (drm_edid->size >= edid_size_by_blocks(2)) {
1638 * Note: HF-EEODB may specify a smaller extension count than the
1639 * regular one. Unlike in buffer allocation, here we can use it.
1641 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1649 /* EDID block count, limited by allocated size */
1650 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1652 /* Limit by allocated size */
1653 return min(__drm_edid_block_count(drm_edid),
1654 (int)drm_edid->size / EDID_LENGTH);
1657 /* EDID extension block count, limited by allocated size */
1658 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1660 return drm_edid_block_count(drm_edid) - 1;
1663 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1665 return edid_block_data(drm_edid->edid, index);
1668 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1671 return edid_extension_block_data(drm_edid->edid, index);
1675 * Initializer helper for legacy interfaces, where we have no choice but to
1676 * trust edid size. Not for general purpose use.
1678 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1679 const struct edid *edid)
1684 memset(drm_edid, 0, sizeof(*drm_edid));
1686 drm_edid->edid = edid;
1687 drm_edid->size = edid_size(edid);
1693 * EDID base and extension block iterator.
1695 * struct drm_edid_iter iter;
1698 * drm_edid_iter_begin(drm_edid, &iter);
1699 * drm_edid_iter_for_each(block, &iter) {
1700 * // do stuff with block
1702 * drm_edid_iter_end(&iter);
1704 struct drm_edid_iter {
1705 const struct drm_edid *drm_edid;
1707 /* Current block index. */
1711 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1712 struct drm_edid_iter *iter)
1714 memset(iter, 0, sizeof(*iter));
1716 iter->drm_edid = drm_edid;
1719 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1721 const void *block = NULL;
1723 if (!iter->drm_edid)
1726 if (iter->index < drm_edid_block_count(iter->drm_edid))
1727 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1732 #define drm_edid_iter_for_each(__block, __iter) \
1733 while (((__block) = __drm_edid_iter_next(__iter)))
1735 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1737 memset(iter, 0, sizeof(*iter));
1740 static const u8 edid_header[] = {
1741 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1744 static void edid_header_fix(void *edid)
1746 memcpy(edid, edid_header, sizeof(edid_header));
1750 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1751 * @_edid: pointer to raw base EDID block
1753 * Sanity check the header of the base EDID block.
1755 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1757 int drm_edid_header_is_valid(const void *_edid)
1759 const struct edid *edid = _edid;
1762 for (i = 0; i < sizeof(edid_header); i++) {
1763 if (edid->header[i] == edid_header[i])
1769 EXPORT_SYMBOL(drm_edid_header_is_valid);
1771 static int edid_fixup __read_mostly = 6;
1772 module_param_named(edid_fixup, edid_fixup, int, 0400);
1773 MODULE_PARM_DESC(edid_fixup,
1774 "Minimum number of valid EDID header bytes (0-8, default 6)");
1776 static int edid_block_compute_checksum(const void *_block)
1778 const u8 *block = _block;
1780 u8 csum = 0, crc = 0;
1782 for (i = 0; i < EDID_LENGTH - 1; i++)
1790 static int edid_block_get_checksum(const void *_block)
1792 const struct edid *block = _block;
1794 return block->checksum;
1797 static int edid_block_tag(const void *_block)
1799 const u8 *block = _block;
1804 static bool edid_block_is_zero(const void *edid)
1806 return !memchr_inv(edid, 0, EDID_LENGTH);
1810 * drm_edid_are_equal - compare two edid blobs.
1811 * @edid1: pointer to first blob
1812 * @edid2: pointer to second blob
1813 * This helper can be used during probing to determine if
1816 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1818 int edid1_len, edid2_len;
1819 bool edid1_present = edid1 != NULL;
1820 bool edid2_present = edid2 != NULL;
1822 if (edid1_present != edid2_present)
1826 edid1_len = edid_size(edid1);
1827 edid2_len = edid_size(edid2);
1829 if (edid1_len != edid2_len)
1832 if (memcmp(edid1, edid2, edid1_len))
1838 EXPORT_SYMBOL(drm_edid_are_equal);
1840 enum edid_block_status {
1842 EDID_BLOCK_READ_FAIL,
1845 EDID_BLOCK_HEADER_CORRUPT,
1846 EDID_BLOCK_HEADER_REPAIR,
1847 EDID_BLOCK_HEADER_FIXED,
1848 EDID_BLOCK_CHECKSUM,
1852 static enum edid_block_status edid_block_check(const void *_block,
1855 const struct edid *block = _block;
1858 return EDID_BLOCK_NULL;
1860 if (is_base_block) {
1861 int score = drm_edid_header_is_valid(block);
1863 if (score < clamp(edid_fixup, 0, 8)) {
1864 if (edid_block_is_zero(block))
1865 return EDID_BLOCK_ZERO;
1867 return EDID_BLOCK_HEADER_CORRUPT;
1871 return EDID_BLOCK_HEADER_REPAIR;
1874 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1875 if (edid_block_is_zero(block))
1876 return EDID_BLOCK_ZERO;
1878 return EDID_BLOCK_CHECKSUM;
1881 if (is_base_block) {
1882 if (block->version != 1)
1883 return EDID_BLOCK_VERSION;
1886 return EDID_BLOCK_OK;
1889 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1891 return status == EDID_BLOCK_OK ||
1892 status == EDID_BLOCK_HEADER_FIXED ||
1893 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1896 static bool edid_block_valid(const void *block, bool base)
1898 return edid_block_status_valid(edid_block_check(block, base),
1899 edid_block_tag(block));
1902 static void edid_block_status_print(enum edid_block_status status,
1903 const struct edid *block,
1909 case EDID_BLOCK_READ_FAIL:
1910 pr_debug("EDID block %d read failed\n", block_num);
1912 case EDID_BLOCK_NULL:
1913 pr_debug("EDID block %d pointer is NULL\n", block_num);
1915 case EDID_BLOCK_ZERO:
1916 pr_notice("EDID block %d is all zeroes\n", block_num);
1918 case EDID_BLOCK_HEADER_CORRUPT:
1919 pr_notice("EDID has corrupt header\n");
1921 case EDID_BLOCK_HEADER_REPAIR:
1922 pr_debug("EDID corrupt header needs repair\n");
1924 case EDID_BLOCK_HEADER_FIXED:
1925 pr_debug("EDID corrupt header fixed\n");
1927 case EDID_BLOCK_CHECKSUM:
1928 if (edid_block_status_valid(status, edid_block_tag(block))) {
1929 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1930 block_num, edid_block_tag(block),
1931 edid_block_compute_checksum(block));
1933 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1934 block_num, edid_block_tag(block),
1935 edid_block_compute_checksum(block));
1938 case EDID_BLOCK_VERSION:
1939 pr_notice("EDID has major version %d, instead of 1\n",
1943 WARN(1, "EDID block %d unknown edid block status code %d\n",
1949 static void edid_block_dump(const char *level, const void *block, int block_num)
1951 enum edid_block_status status;
1954 status = edid_block_check(block, block_num == 0);
1955 if (status == EDID_BLOCK_ZERO)
1956 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1957 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1958 sprintf(prefix, "\t[%02x] BAD ", block_num);
1960 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1962 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1963 block, EDID_LENGTH, false);
1967 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1968 * @_block: pointer to raw EDID block
1969 * @block_num: type of block to validate (0 for base, extension otherwise)
1970 * @print_bad_edid: if true, dump bad EDID blocks to the console
1971 * @edid_corrupt: if true, the header or checksum is invalid
1973 * Validate a base or extension EDID block and optionally dump bad blocks to
1976 * Return: True if the block is valid, false otherwise.
1978 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1981 struct edid *block = (struct edid *)_block;
1982 enum edid_block_status status;
1983 bool is_base_block = block_num == 0;
1986 if (WARN_ON(!block))
1989 status = edid_block_check(block, is_base_block);
1990 if (status == EDID_BLOCK_HEADER_REPAIR) {
1991 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1992 edid_header_fix(block);
1994 /* Retry with fixed header, update status if that worked. */
1995 status = edid_block_check(block, is_base_block);
1996 if (status == EDID_BLOCK_OK)
1997 status = EDID_BLOCK_HEADER_FIXED;
2002 * Unknown major version isn't corrupt but we can't use it. Only
2003 * the base block can reset edid_corrupt to false.
2005 if (is_base_block &&
2006 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2007 *edid_corrupt = false;
2008 else if (status != EDID_BLOCK_OK)
2009 *edid_corrupt = true;
2012 edid_block_status_print(status, block, block_num);
2014 /* Determine whether we can use this block with this status. */
2015 valid = edid_block_status_valid(status, edid_block_tag(block));
2017 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2018 pr_notice("Raw EDID:\n");
2019 edid_block_dump(KERN_NOTICE, block, block_num);
2024 EXPORT_SYMBOL(drm_edid_block_valid);
2027 * drm_edid_is_valid - sanity check EDID data
2030 * Sanity-check an entire EDID record (including extensions)
2032 * Return: True if the EDID data is valid, false otherwise.
2034 bool drm_edid_is_valid(struct edid *edid)
2041 for (i = 0; i < edid_block_count(edid); i++) {
2042 void *block = (void *)edid_block_data(edid, i);
2044 if (!drm_edid_block_valid(block, i, true, NULL))
2050 EXPORT_SYMBOL(drm_edid_is_valid);
2053 * drm_edid_valid - sanity check EDID data
2054 * @drm_edid: EDID data
2056 * Sanity check an EDID. Cross check block count against allocated size and
2057 * checksum the blocks.
2059 * Return: True if the EDID data is valid, false otherwise.
2061 bool drm_edid_valid(const struct drm_edid *drm_edid)
2068 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2071 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2072 const void *block = drm_edid_block_data(drm_edid, i);
2074 if (!edid_block_valid(block, i == 0))
2080 EXPORT_SYMBOL(drm_edid_valid);
2082 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2086 int i, valid_blocks = 0;
2089 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2090 * back to regular extension count here. We don't want to start
2091 * modifying the HF-EEODB extension too.
2093 for (i = 0; i < edid_block_count(edid); i++) {
2094 const void *src_block = edid_block_data(edid, i);
2096 if (edid_block_valid(src_block, i == 0)) {
2097 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2099 memmove(dst_block, src_block, EDID_LENGTH);
2104 /* We already trusted the base block to be valid here... */
2105 if (WARN_ON(!valid_blocks)) {
2110 edid->extensions = valid_blocks - 1;
2111 edid->checksum = edid_block_compute_checksum(edid);
2113 *alloc_size = edid_size_by_blocks(valid_blocks);
2115 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2122 #define DDC_SEGMENT_ADDR 0x30
2124 * drm_do_probe_ddc_edid() - get EDID information via I2C
2125 * @data: I2C device adapter
2126 * @buf: EDID data buffer to be filled
2127 * @block: 128 byte EDID block to start fetching from
2128 * @len: EDID data buffer length to fetch
2130 * Try to fetch EDID information by calling I2C driver functions.
2132 * Return: 0 on success or -1 on failure.
2135 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2137 struct i2c_adapter *adapter = data;
2138 unsigned char start = block * EDID_LENGTH;
2139 unsigned char segment = block >> 1;
2140 unsigned char xfers = segment ? 3 : 2;
2141 int ret, retries = 5;
2144 * The core I2C driver will automatically retry the transfer if the
2145 * adapter reports EAGAIN. However, we find that bit-banging transfers
2146 * are susceptible to errors under a heavily loaded machine and
2147 * generate spurious NAKs and timeouts. Retrying the transfer
2148 * of the individual block a few times seems to overcome this.
2151 struct i2c_msg msgs[] = {
2153 .addr = DDC_SEGMENT_ADDR,
2171 * Avoid sending the segment addr to not upset non-compliant
2174 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2176 if (ret == -ENXIO) {
2177 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2181 } while (ret != xfers && --retries);
2183 return ret == xfers ? 0 : -1;
2186 static void connector_bad_edid(struct drm_connector *connector,
2187 const struct edid *edid, int num_blocks)
2193 * 0x7e in the EDID is the number of extension blocks. The EDID
2194 * is 1 (base block) + num_ext_blocks big. That means we can think
2195 * of 0x7e in the EDID of the _index_ of the last block in the
2196 * combined chunk of memory.
2198 last_block = edid->extensions;
2200 /* Calculate real checksum for the last edid extension block data */
2201 if (last_block < num_blocks)
2202 connector->real_edid_checksum =
2203 edid_block_compute_checksum(edid + last_block);
2205 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2208 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2209 connector->base.id, connector->name);
2210 for (i = 0; i < num_blocks; i++)
2211 edid_block_dump(KERN_DEBUG, edid + i, i);
2214 /* Get override or firmware EDID */
2215 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2217 const struct drm_edid *override = NULL;
2219 mutex_lock(&connector->edid_override_mutex);
2221 if (connector->edid_override)
2222 override = drm_edid_dup(connector->edid_override);
2224 mutex_unlock(&connector->edid_override_mutex);
2227 override = drm_edid_load_firmware(connector);
2229 return IS_ERR(override) ? NULL : override;
2232 /* For debugfs edid_override implementation */
2233 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2235 const struct drm_edid *drm_edid;
2237 mutex_lock(&connector->edid_override_mutex);
2239 drm_edid = connector->edid_override;
2241 seq_write(m, drm_edid->edid, drm_edid->size);
2243 mutex_unlock(&connector->edid_override_mutex);
2248 /* For debugfs edid_override implementation */
2249 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2252 const struct drm_edid *drm_edid;
2254 drm_edid = drm_edid_alloc(edid, size);
2255 if (!drm_edid_valid(drm_edid)) {
2256 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2257 connector->base.id, connector->name);
2258 drm_edid_free(drm_edid);
2262 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2263 connector->base.id, connector->name);
2265 mutex_lock(&connector->edid_override_mutex);
2267 drm_edid_free(connector->edid_override);
2268 connector->edid_override = drm_edid;
2270 mutex_unlock(&connector->edid_override_mutex);
2275 /* For debugfs edid_override implementation */
2276 int drm_edid_override_reset(struct drm_connector *connector)
2278 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2279 connector->base.id, connector->name);
2281 mutex_lock(&connector->edid_override_mutex);
2283 drm_edid_free(connector->edid_override);
2284 connector->edid_override = NULL;
2286 mutex_unlock(&connector->edid_override_mutex);
2292 * drm_edid_override_connector_update - add modes from override/firmware EDID
2293 * @connector: connector we're probing
2295 * Add modes from the override/firmware EDID, if available. Only to be used from
2296 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2297 * failed during drm_get_edid() and caused the override/firmware EDID to be
2300 * Return: The number of modes added or 0 if we couldn't find any.
2302 int drm_edid_override_connector_update(struct drm_connector *connector)
2304 const struct drm_edid *override;
2307 override = drm_edid_override_get(connector);
2309 num_modes = drm_edid_connector_update(connector, override);
2311 drm_edid_free(override);
2313 drm_dbg_kms(connector->dev,
2314 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2315 connector->base.id, connector->name, num_modes);
2320 EXPORT_SYMBOL(drm_edid_override_connector_update);
2322 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2324 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2325 read_block_fn read_block,
2328 enum edid_block_status status;
2329 bool is_base_block = block_num == 0;
2332 for (try = 0; try < 4; try++) {
2333 if (read_block(context, block, block_num, EDID_LENGTH))
2334 return EDID_BLOCK_READ_FAIL;
2336 status = edid_block_check(block, is_base_block);
2337 if (status == EDID_BLOCK_HEADER_REPAIR) {
2338 edid_header_fix(block);
2340 /* Retry with fixed header, update status if that worked. */
2341 status = edid_block_check(block, is_base_block);
2342 if (status == EDID_BLOCK_OK)
2343 status = EDID_BLOCK_HEADER_FIXED;
2346 if (edid_block_status_valid(status, edid_block_tag(block)))
2349 /* Fail early for unrepairable base block all zeros. */
2350 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2357 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2358 read_block_fn read_block, void *context,
2361 enum edid_block_status status;
2362 int i, num_blocks, invalid_blocks = 0;
2363 const struct drm_edid *override;
2364 struct edid *edid, *new;
2365 size_t alloc_size = EDID_LENGTH;
2367 override = drm_edid_override_get(connector);
2369 alloc_size = override->size;
2370 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2371 drm_edid_free(override);
2377 edid = kmalloc(alloc_size, GFP_KERNEL);
2381 status = edid_block_read(edid, 0, read_block, context);
2383 edid_block_status_print(status, edid, 0);
2385 if (status == EDID_BLOCK_READ_FAIL)
2388 /* FIXME: Clarify what a corrupt EDID actually means. */
2389 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2390 connector->edid_corrupt = false;
2392 connector->edid_corrupt = true;
2394 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2395 if (status == EDID_BLOCK_ZERO)
2396 connector->null_edid_counter++;
2398 connector_bad_edid(connector, edid, 1);
2402 if (!edid_extension_block_count(edid))
2405 alloc_size = edid_size(edid);
2406 new = krealloc(edid, alloc_size, GFP_KERNEL);
2411 num_blocks = edid_block_count(edid);
2412 for (i = 1; i < num_blocks; i++) {
2413 void *block = (void *)edid_block_data(edid, i);
2415 status = edid_block_read(block, i, read_block, context);
2417 edid_block_status_print(status, block, i);
2419 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2420 if (status == EDID_BLOCK_READ_FAIL)
2423 } else if (i == 1) {
2425 * If the first EDID extension is a CTA extension, and
2426 * the first Data Block is HF-EEODB, override the
2427 * extension block count.
2429 * Note: HF-EEODB could specify a smaller extension
2430 * count too, but we can't risk allocating a smaller
2433 int eeodb = edid_hfeeodb_block_count(edid);
2435 if (eeodb > num_blocks) {
2437 alloc_size = edid_size_by_blocks(num_blocks);
2438 new = krealloc(edid, alloc_size, GFP_KERNEL);
2446 if (invalid_blocks) {
2447 connector_bad_edid(connector, edid, num_blocks);
2449 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2464 * drm_do_get_edid - get EDID data using a custom EDID block read function
2465 * @connector: connector we're probing
2466 * @read_block: EDID block read function
2467 * @context: private data passed to the block read function
2469 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2470 * exposes a different interface to read EDID blocks this function can be used
2471 * to get EDID data using a custom block read function.
2473 * As in the general case the DDC bus is accessible by the kernel at the I2C
2474 * level, drivers must make all reasonable efforts to expose it as an I2C
2475 * adapter and use drm_get_edid() instead of abusing this function.
2477 * The EDID may be overridden using debugfs override_edid or firmware EDID
2478 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2479 * order. Having either of them bypasses actual EDID reads.
2481 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2483 struct edid *drm_do_get_edid(struct drm_connector *connector,
2484 read_block_fn read_block,
2487 return _drm_do_get_edid(connector, read_block, context, NULL);
2489 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2492 * drm_edid_raw - Get a pointer to the raw EDID data.
2493 * @drm_edid: drm_edid container
2495 * Get a pointer to the raw EDID data.
2497 * This is for transition only. Avoid using this like the plague.
2499 * Return: Pointer to raw EDID data.
2501 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2503 if (!drm_edid || !drm_edid->size)
2507 * Do not return pointers where relying on EDID extension count would
2508 * lead to buffer overflow.
2510 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2513 return drm_edid->edid;
2515 EXPORT_SYMBOL(drm_edid_raw);
2517 /* Allocate struct drm_edid container *without* duplicating the edid data */
2518 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2520 struct drm_edid *drm_edid;
2522 if (!edid || !size || size < EDID_LENGTH)
2525 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2527 drm_edid->edid = edid;
2528 drm_edid->size = size;
2535 * drm_edid_alloc - Allocate a new drm_edid container
2536 * @edid: Pointer to raw EDID data
2537 * @size: Size of memory allocated for EDID
2539 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2540 * the actual size that has been allocated for the data. There is no validation
2541 * of the raw EDID data against the size, but at least the EDID base block must
2542 * fit in the buffer.
2544 * The returned pointer must be freed using drm_edid_free().
2546 * Return: drm_edid container, or NULL on errors
2548 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2550 const struct drm_edid *drm_edid;
2552 if (!edid || !size || size < EDID_LENGTH)
2555 edid = kmemdup(edid, size, GFP_KERNEL);
2559 drm_edid = _drm_edid_alloc(edid, size);
2565 EXPORT_SYMBOL(drm_edid_alloc);
2568 * drm_edid_dup - Duplicate a drm_edid container
2569 * @drm_edid: EDID to duplicate
2571 * The returned pointer must be freed using drm_edid_free().
2573 * Returns: drm_edid container copy, or NULL on errors
2575 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2580 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2582 EXPORT_SYMBOL(drm_edid_dup);
2585 * drm_edid_free - Free the drm_edid container
2586 * @drm_edid: EDID to free
2588 void drm_edid_free(const struct drm_edid *drm_edid)
2593 kfree(drm_edid->edid);
2596 EXPORT_SYMBOL(drm_edid_free);
2599 * drm_probe_ddc() - probe DDC presence
2600 * @adapter: I2C adapter to probe
2602 * Return: True on success, false on failure.
2605 drm_probe_ddc(struct i2c_adapter *adapter)
2609 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2611 EXPORT_SYMBOL(drm_probe_ddc);
2614 * drm_get_edid - get EDID data, if available
2615 * @connector: connector we're probing
2616 * @adapter: I2C adapter to use for DDC
2618 * Poke the given I2C channel to grab EDID data if possible. If found,
2619 * attach it to the connector.
2621 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2623 struct edid *drm_get_edid(struct drm_connector *connector,
2624 struct i2c_adapter *adapter)
2628 if (connector->force == DRM_FORCE_OFF)
2631 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2634 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2635 drm_connector_update_edid_property(connector, edid);
2638 EXPORT_SYMBOL(drm_get_edid);
2641 * drm_edid_read_custom - Read EDID data using given EDID block read function
2642 * @connector: Connector to use
2643 * @read_block: EDID block read function
2644 * @context: Private data passed to the block read function
2646 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2647 * exposes a different interface to read EDID blocks this function can be used
2648 * to get EDID data using a custom block read function.
2650 * As in the general case the DDC bus is accessible by the kernel at the I2C
2651 * level, drivers must make all reasonable efforts to expose it as an I2C
2652 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2655 * The EDID may be overridden using debugfs override_edid or firmware EDID
2656 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2657 * order. Having either of them bypasses actual EDID reads.
2659 * The returned pointer must be freed using drm_edid_free().
2661 * Return: Pointer to EDID, or NULL if probe/read failed.
2663 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2664 read_block_fn read_block,
2667 const struct drm_edid *drm_edid;
2671 edid = _drm_do_get_edid(connector, read_block, context, &size);
2675 /* Sanity check for now */
2676 drm_WARN_ON(connector->dev, !size);
2678 drm_edid = _drm_edid_alloc(edid, size);
2684 EXPORT_SYMBOL(drm_edid_read_custom);
2687 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2688 * @connector: Connector to use
2689 * @adapter: I2C adapter to use for DDC
2691 * Read EDID using the given I2C adapter.
2693 * The EDID may be overridden using debugfs override_edid or firmware EDID
2694 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2695 * order. Having either of them bypasses actual EDID reads.
2697 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2698 * using drm_edid_read() instead of this function.
2700 * The returned pointer must be freed using drm_edid_free().
2702 * Return: Pointer to EDID, or NULL if probe/read failed.
2704 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2705 struct i2c_adapter *adapter)
2707 const struct drm_edid *drm_edid;
2709 if (connector->force == DRM_FORCE_OFF)
2712 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2715 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2717 /* Note: Do *not* call connector updates here. */
2721 EXPORT_SYMBOL(drm_edid_read_ddc);
2724 * drm_edid_read - Read EDID data using connector's I2C adapter
2725 * @connector: Connector to use
2727 * Read EDID using the connector's I2C adapter.
2729 * The EDID may be overridden using debugfs override_edid or firmware EDID
2730 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2731 * order. Having either of them bypasses actual EDID reads.
2733 * The returned pointer must be freed using drm_edid_free().
2735 * Return: Pointer to EDID, or NULL if probe/read failed.
2737 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2739 if (drm_WARN_ON(connector->dev, !connector->ddc))
2742 return drm_edid_read_ddc(connector, connector->ddc);
2744 EXPORT_SYMBOL(drm_edid_read);
2746 static u32 edid_extract_panel_id(const struct edid *edid)
2749 * We represent the ID as a 32-bit number so it can easily be compared
2752 * NOTE that we deal with endianness differently for the top half
2753 * of this ID than for the bottom half. The bottom half (the product
2754 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2755 * that's how everyone seems to interpret it. The top half (the mfg_id)
2756 * gets stored as big endian because that makes
2757 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2758 * to write (it's easier to extract the ASCII). It doesn't really
2759 * matter, though, as long as the number here is unique.
2761 return (u32)edid->mfg_id[0] << 24 |
2762 (u32)edid->mfg_id[1] << 16 |
2763 (u32)EDID_PRODUCT_ID(edid);
2767 * drm_edid_get_panel_id - Get a panel's ID through DDC
2768 * @adapter: I2C adapter to use for DDC
2770 * This function reads the first block of the EDID of a panel and (assuming
2771 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2772 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2773 * supposed to be different for each different modem of panel.
2775 * This function is intended to be used during early probing on devices where
2776 * more than one panel might be present. Because of its intended use it must
2777 * assume that the EDID of the panel is correct, at least as far as the ID
2778 * is concerned (in other words, we don't process any overrides here).
2780 * NOTE: it's expected that this function and drm_do_get_edid() will both
2781 * be read the EDID, but there is no caching between them. Since we're only
2782 * reading the first block, hopefully this extra overhead won't be too big.
2784 * Return: A 32-bit ID that should be different for each make/model of panel.
2785 * See the functions drm_edid_encode_panel_id() and
2786 * drm_edid_decode_panel_id() for some details on the structure of this
2790 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2792 enum edid_block_status status;
2797 * There are no manufacturer IDs of 0, so if there is a problem reading
2798 * the EDID then we'll just return 0.
2801 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2805 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2807 edid_block_status_print(status, base_block, 0);
2809 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2810 panel_id = edid_extract_panel_id(base_block);
2812 edid_block_dump(KERN_NOTICE, base_block, 0);
2818 EXPORT_SYMBOL(drm_edid_get_panel_id);
2821 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2822 * @connector: connector we're probing
2823 * @adapter: I2C adapter to use for DDC
2825 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2826 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2827 * switch DDC to the GPU which is retrieving EDID.
2829 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2831 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2832 struct i2c_adapter *adapter)
2834 struct drm_device *dev = connector->dev;
2835 struct pci_dev *pdev = to_pci_dev(dev->dev);
2838 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2841 vga_switcheroo_lock_ddc(pdev);
2842 edid = drm_get_edid(connector, adapter);
2843 vga_switcheroo_unlock_ddc(pdev);
2847 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2850 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2851 * @connector: connector we're probing
2852 * @adapter: I2C adapter to use for DDC
2854 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2855 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2856 * temporarily switch DDC to the GPU which is retrieving EDID.
2858 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2860 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2861 struct i2c_adapter *adapter)
2863 struct drm_device *dev = connector->dev;
2864 struct pci_dev *pdev = to_pci_dev(dev->dev);
2865 const struct drm_edid *drm_edid;
2867 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2870 vga_switcheroo_lock_ddc(pdev);
2871 drm_edid = drm_edid_read_ddc(connector, adapter);
2872 vga_switcheroo_unlock_ddc(pdev);
2876 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2879 * drm_edid_duplicate - duplicate an EDID and the extensions
2880 * @edid: EDID to duplicate
2882 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2884 struct edid *drm_edid_duplicate(const struct edid *edid)
2889 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2891 EXPORT_SYMBOL(drm_edid_duplicate);
2893 /*** EDID parsing ***/
2896 * edid_get_quirks - return quirk flags for a given EDID
2897 * @drm_edid: EDID to process
2899 * This tells subsequent routines what fixes they need to apply.
2901 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2903 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2904 const struct edid_quirk *quirk;
2907 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2908 quirk = &edid_quirk_list[i];
2909 if (quirk->panel_id == panel_id)
2910 return quirk->quirks;
2916 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2917 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2920 * Walk the mode list for connector, clearing the preferred status on existing
2921 * modes and setting it anew for the right mode ala quirks.
2923 static void edid_fixup_preferred(struct drm_connector *connector)
2925 const struct drm_display_info *info = &connector->display_info;
2926 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2927 int target_refresh = 0;
2928 int cur_vrefresh, preferred_vrefresh;
2930 if (list_empty(&connector->probed_modes))
2933 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2934 target_refresh = 60;
2935 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2936 target_refresh = 75;
2938 preferred_mode = list_first_entry(&connector->probed_modes,
2939 struct drm_display_mode, head);
2941 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2942 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2944 if (cur_mode == preferred_mode)
2947 /* Largest mode is preferred */
2948 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2949 preferred_mode = cur_mode;
2951 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2952 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2953 /* At a given size, try to get closest to target refresh */
2954 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2955 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2956 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2957 preferred_mode = cur_mode;
2961 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2965 mode_is_rb(const struct drm_display_mode *mode)
2967 return (mode->htotal - mode->hdisplay == 160) &&
2968 (mode->hsync_end - mode->hdisplay == 80) &&
2969 (mode->hsync_end - mode->hsync_start == 32) &&
2970 (mode->vsync_start - mode->vdisplay == 3);
2974 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2975 * @dev: Device to duplicate against
2976 * @hsize: Mode width
2977 * @vsize: Mode height
2978 * @fresh: Mode refresh rate
2979 * @rb: Mode reduced-blanking-ness
2981 * Walk the DMT mode list looking for a match for the given parameters.
2983 * Return: A newly allocated copy of the mode, or NULL if not found.
2985 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2986 int hsize, int vsize, int fresh,
2991 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2992 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2994 if (hsize != ptr->hdisplay)
2996 if (vsize != ptr->vdisplay)
2998 if (fresh != drm_mode_vrefresh(ptr))
3000 if (rb != mode_is_rb(ptr))
3003 return drm_mode_duplicate(dev, ptr);
3008 EXPORT_SYMBOL(drm_mode_find_dmt);
3010 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3012 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3014 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3016 return descriptor->pixel_clock == 0 &&
3017 descriptor->data.other_data.pad1 == 0 &&
3018 descriptor->data.other_data.type == type;
3021 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3023 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3025 return descriptor->pixel_clock != 0;
3028 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3031 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3035 const u8 *det_base = ext + d;
3037 if (d < 4 || d > 127)
3041 for (i = 0; i < n; i++)
3042 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3046 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3048 unsigned int i, n = min((int)ext[0x02], 6);
3049 const u8 *det_base = ext + 5;
3052 return; /* unknown version */
3054 for (i = 0; i < n; i++)
3055 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3058 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3059 detailed_cb *cb, void *closure)
3061 struct drm_edid_iter edid_iter;
3068 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3069 cb(&drm_edid->edid->detailed_timings[i], closure);
3071 drm_edid_iter_begin(drm_edid, &edid_iter);
3072 drm_edid_iter_for_each(ext, &edid_iter) {
3075 cea_for_each_detailed_block(ext, cb, closure);
3078 vtb_for_each_detailed_block(ext, cb, closure);
3084 drm_edid_iter_end(&edid_iter);
3088 is_rb(const struct detailed_timing *descriptor, void *data)
3092 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3095 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3096 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3098 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3099 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3103 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3105 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3107 if (drm_edid->edid->revision >= 4) {
3110 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3114 return drm_edid_is_digital(drm_edid);
3118 find_gtf2(const struct detailed_timing *descriptor, void *data)
3120 const struct detailed_timing **res = data;
3122 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3125 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3127 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3131 /* Secondary GTF curve kicks in above some break frequency */
3133 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3135 const struct detailed_timing *descriptor = NULL;
3137 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3139 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3141 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3145 drm_gtf2_2c(const struct drm_edid *drm_edid)
3147 const struct detailed_timing *descriptor = NULL;
3149 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3151 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3153 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3157 drm_gtf2_m(const struct drm_edid *drm_edid)
3159 const struct detailed_timing *descriptor = NULL;
3161 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3163 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3165 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3169 drm_gtf2_k(const struct drm_edid *drm_edid)
3171 const struct detailed_timing *descriptor = NULL;
3173 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3175 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3177 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3181 drm_gtf2_2j(const struct drm_edid *drm_edid)
3183 const struct detailed_timing *descriptor = NULL;
3185 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3187 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3189 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3193 get_timing_level(const struct detailed_timing *descriptor, void *data)
3197 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3200 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3202 switch (descriptor->data.other_data.data.range.flags) {
3203 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3206 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3209 case DRM_EDID_CVT_SUPPORT_FLAG:
3217 /* Get standard timing level (CVT/GTF/DMT). */
3218 static int standard_timing_level(const struct drm_edid *drm_edid)
3220 const struct edid *edid = drm_edid->edid;
3222 if (edid->revision >= 4) {
3224 * If the range descriptor doesn't
3225 * indicate otherwise default to CVT
3227 int ret = LEVEL_CVT;
3229 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3232 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3234 } else if (edid->revision >= 2) {
3242 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3243 * monitors fill with ascii space (0x20) instead.
3246 bad_std_timing(u8 a, u8 b)
3248 return (a == 0x00 && b == 0x00) ||
3249 (a == 0x01 && b == 0x01) ||
3250 (a == 0x20 && b == 0x20);
3253 static int drm_mode_hsync(const struct drm_display_mode *mode)
3255 if (mode->htotal <= 0)
3258 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3261 static struct drm_display_mode *
3262 drm_gtf2_mode(struct drm_device *dev,
3263 const struct drm_edid *drm_edid,
3264 int hsize, int vsize, int vrefresh_rate)
3266 struct drm_display_mode *mode;
3269 * This is potentially wrong if there's ever a monitor with
3270 * more than one ranges section, each claiming a different
3271 * secondary GTF curve. Please don't do that.
3273 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3277 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3278 drm_mode_destroy(dev, mode);
3279 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3280 vrefresh_rate, 0, 0,
3281 drm_gtf2_m(drm_edid),
3282 drm_gtf2_2c(drm_edid),
3283 drm_gtf2_k(drm_edid),
3284 drm_gtf2_2j(drm_edid));
3291 * Take the standard timing params (in this case width, aspect, and refresh)
3292 * and convert them into a real mode using CVT/GTF/DMT.
3294 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3295 const struct drm_edid *drm_edid,
3296 const struct std_timing *t)
3298 struct drm_device *dev = connector->dev;
3299 struct drm_display_mode *m, *mode = NULL;
3302 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3303 >> EDID_TIMING_ASPECT_SHIFT;
3304 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3305 >> EDID_TIMING_VFREQ_SHIFT;
3306 int timing_level = standard_timing_level(drm_edid);
3308 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3311 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3312 hsize = t->hsize * 8 + 248;
3313 /* vrefresh_rate = vfreq + 60 */
3314 vrefresh_rate = vfreq + 60;
3315 /* the vdisplay is calculated based on the aspect ratio */
3316 if (aspect_ratio == 0) {
3317 if (drm_edid->edid->revision < 3)
3320 vsize = (hsize * 10) / 16;
3321 } else if (aspect_ratio == 1)
3322 vsize = (hsize * 3) / 4;
3323 else if (aspect_ratio == 2)
3324 vsize = (hsize * 4) / 5;
3326 vsize = (hsize * 9) / 16;
3328 /* HDTV hack, part 1 */
3329 if (vrefresh_rate == 60 &&
3330 ((hsize == 1360 && vsize == 765) ||
3331 (hsize == 1368 && vsize == 769))) {
3337 * If this connector already has a mode for this size and refresh
3338 * rate (because it came from detailed or CVT info), use that
3339 * instead. This way we don't have to guess at interlace or
3342 list_for_each_entry(m, &connector->probed_modes, head)
3343 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3344 drm_mode_vrefresh(m) == vrefresh_rate)
3347 /* HDTV hack, part 2 */
3348 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3349 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3353 mode->hdisplay = 1366;
3354 mode->hsync_start = mode->hsync_start - 1;
3355 mode->hsync_end = mode->hsync_end - 1;
3359 /* check whether it can be found in default mode table */
3360 if (drm_monitor_supports_rb(drm_edid)) {
3361 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3366 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3370 /* okay, generate it */
3371 switch (timing_level) {
3375 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3378 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3381 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3389 * EDID is delightfully ambiguous about how interlaced modes are to be
3390 * encoded. Our internal representation is of frame height, but some
3391 * HDTV detailed timings are encoded as field height.
3393 * The format list here is from CEA, in frame size. Technically we
3394 * should be checking refresh rate too. Whatever.
3397 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3398 const struct detailed_pixel_timing *pt)
3401 static const struct {
3403 } cea_interlaced[] = {
3413 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3416 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3417 if ((mode->hdisplay == cea_interlaced[i].w) &&
3418 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3419 mode->vdisplay *= 2;
3420 mode->vsync_start *= 2;
3421 mode->vsync_end *= 2;
3427 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3431 * Create a new mode from an EDID detailed timing section. An EDID detailed
3432 * timing block contains enough info for us to create and return a new struct
3435 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3436 const struct drm_edid *drm_edid,
3437 const struct detailed_timing *timing)
3439 const struct drm_display_info *info = &connector->display_info;
3440 struct drm_device *dev = connector->dev;
3441 struct drm_display_mode *mode;
3442 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3443 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3444 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3445 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3446 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3447 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3448 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3449 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3450 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3452 /* ignore tiny modes */
3453 if (hactive < 64 || vactive < 64)
3456 if (pt->misc & DRM_EDID_PT_STEREO) {
3457 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3458 connector->base.id, connector->name);
3461 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3462 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3463 connector->base.id, connector->name);
3466 /* it is incorrect if hsync/vsync width is zero */
3467 if (!hsync_pulse_width || !vsync_pulse_width) {
3468 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3469 connector->base.id, connector->name);
3473 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3474 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3481 mode = drm_mode_create(dev);
3485 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3486 mode->clock = 1088 * 10;
3488 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3490 mode->hdisplay = hactive;
3491 mode->hsync_start = mode->hdisplay + hsync_offset;
3492 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3493 mode->htotal = mode->hdisplay + hblank;
3495 mode->vdisplay = vactive;
3496 mode->vsync_start = mode->vdisplay + vsync_offset;
3497 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3498 mode->vtotal = mode->vdisplay + vblank;
3500 /* Some EDIDs have bogus h/vsync_end values */
3501 if (mode->hsync_end > mode->htotal) {
3502 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3503 connector->base.id, connector->name,
3504 mode->hsync_end, mode->htotal);
3505 mode->hsync_end = mode->htotal;
3507 if (mode->vsync_end > mode->vtotal) {
3508 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3509 connector->base.id, connector->name,
3510 mode->vsync_end, mode->vtotal);
3511 mode->vsync_end = mode->vtotal;
3514 drm_mode_do_interlace_quirk(mode, pt);
3516 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3517 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3519 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3520 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3521 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3522 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3526 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3527 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3529 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3530 mode->width_mm *= 10;
3531 mode->height_mm *= 10;
3534 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3535 mode->width_mm = drm_edid->edid->width_cm * 10;
3536 mode->height_mm = drm_edid->edid->height_cm * 10;
3539 mode->type = DRM_MODE_TYPE_DRIVER;
3540 drm_mode_set_name(mode);
3546 mode_in_hsync_range(const struct drm_display_mode *mode,
3547 const struct edid *edid, const u8 *t)
3549 int hsync, hmin, hmax;
3552 if (edid->revision >= 4)
3553 hmin += ((t[4] & 0x04) ? 255 : 0);
3555 if (edid->revision >= 4)
3556 hmax += ((t[4] & 0x08) ? 255 : 0);
3557 hsync = drm_mode_hsync(mode);
3559 return (hsync <= hmax && hsync >= hmin);
3563 mode_in_vsync_range(const struct drm_display_mode *mode,
3564 const struct edid *edid, const u8 *t)
3566 int vsync, vmin, vmax;
3569 if (edid->revision >= 4)
3570 vmin += ((t[4] & 0x01) ? 255 : 0);
3572 if (edid->revision >= 4)
3573 vmax += ((t[4] & 0x02) ? 255 : 0);
3574 vsync = drm_mode_vrefresh(mode);
3576 return (vsync <= vmax && vsync >= vmin);
3580 range_pixel_clock(const struct edid *edid, const u8 *t)
3583 if (t[9] == 0 || t[9] == 255)
3586 /* 1.4 with CVT support gives us real precision, yay */
3587 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3588 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3590 /* 1.3 is pathetic, so fuzz up a bit */
3591 return t[9] * 10000 + 5001;
3594 static bool mode_in_range(const struct drm_display_mode *mode,
3595 const struct drm_edid *drm_edid,
3596 const struct detailed_timing *timing)
3598 const struct edid *edid = drm_edid->edid;
3600 const u8 *t = (const u8 *)timing;
3602 if (!mode_in_hsync_range(mode, edid, t))
3605 if (!mode_in_vsync_range(mode, edid, t))
3608 if ((max_clock = range_pixel_clock(edid, t)))
3609 if (mode->clock > max_clock)
3612 /* 1.4 max horizontal check */
3613 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3614 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3617 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3623 static bool valid_inferred_mode(const struct drm_connector *connector,
3624 const struct drm_display_mode *mode)
3626 const struct drm_display_mode *m;
3629 list_for_each_entry(m, &connector->probed_modes, head) {
3630 if (mode->hdisplay == m->hdisplay &&
3631 mode->vdisplay == m->vdisplay &&
3632 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3633 return false; /* duplicated */
3634 if (mode->hdisplay <= m->hdisplay &&
3635 mode->vdisplay <= m->vdisplay)
3641 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3642 const struct drm_edid *drm_edid,
3643 const struct detailed_timing *timing)
3646 struct drm_display_mode *newmode;
3647 struct drm_device *dev = connector->dev;
3649 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3650 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3651 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3652 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3654 drm_mode_probed_add(connector, newmode);
3663 /* fix up 1366x768 mode from 1368x768;
3664 * GFT/CVT can't express 1366 width which isn't dividable by 8
3666 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3668 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3669 mode->hdisplay = 1366;
3670 mode->hsync_start--;
3672 drm_mode_set_name(mode);
3676 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3677 const struct drm_edid *drm_edid,
3678 const struct detailed_timing *timing)
3681 struct drm_display_mode *newmode;
3682 struct drm_device *dev = connector->dev;
3684 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3685 const struct minimode *m = &extra_modes[i];
3687 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3691 drm_mode_fixup_1366x768(newmode);
3692 if (!mode_in_range(newmode, drm_edid, timing) ||
3693 !valid_inferred_mode(connector, newmode)) {
3694 drm_mode_destroy(dev, newmode);
3698 drm_mode_probed_add(connector, newmode);
3705 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3706 const struct drm_edid *drm_edid,
3707 const struct detailed_timing *timing)
3710 struct drm_display_mode *newmode;
3711 struct drm_device *dev = connector->dev;
3713 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3714 const struct minimode *m = &extra_modes[i];
3716 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3720 drm_mode_fixup_1366x768(newmode);
3721 if (!mode_in_range(newmode, drm_edid, timing) ||
3722 !valid_inferred_mode(connector, newmode)) {
3723 drm_mode_destroy(dev, newmode);
3727 drm_mode_probed_add(connector, newmode);
3734 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3735 const struct drm_edid *drm_edid,
3736 const struct detailed_timing *timing)
3739 struct drm_display_mode *newmode;
3740 struct drm_device *dev = connector->dev;
3741 bool rb = drm_monitor_supports_rb(drm_edid);
3743 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3744 const struct minimode *m = &extra_modes[i];
3746 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3750 drm_mode_fixup_1366x768(newmode);
3751 if (!mode_in_range(newmode, drm_edid, timing) ||
3752 !valid_inferred_mode(connector, newmode)) {
3753 drm_mode_destroy(dev, newmode);
3757 drm_mode_probed_add(connector, newmode);
3765 do_inferred_modes(const struct detailed_timing *timing, void *c)
3767 struct detailed_mode_closure *closure = c;
3768 const struct detailed_non_pixel *data = &timing->data.other_data;
3769 const struct detailed_data_monitor_range *range = &data->data.range;
3771 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3774 closure->modes += drm_dmt_modes_for_range(closure->connector,
3778 if (closure->drm_edid->edid->revision < 2)
3779 return; /* GTF not defined yet */
3781 switch (range->flags) {
3782 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3783 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3787 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3788 closure->modes += drm_gtf_modes_for_range(closure->connector,
3792 case DRM_EDID_CVT_SUPPORT_FLAG:
3793 if (closure->drm_edid->edid->revision < 4)
3796 closure->modes += drm_cvt_modes_for_range(closure->connector,
3800 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3806 static int add_inferred_modes(struct drm_connector *connector,
3807 const struct drm_edid *drm_edid)
3809 struct detailed_mode_closure closure = {
3810 .connector = connector,
3811 .drm_edid = drm_edid,
3814 if (drm_edid->edid->revision >= 1)
3815 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3817 return closure.modes;
3821 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3823 int i, j, m, modes = 0;
3824 struct drm_display_mode *mode;
3825 const u8 *est = ((const u8 *)timing) + 6;
3827 for (i = 0; i < 6; i++) {
3828 for (j = 7; j >= 0; j--) {
3829 m = (i * 8) + (7 - j);
3830 if (m >= ARRAY_SIZE(est3_modes))
3832 if (est[i] & (1 << j)) {
3833 mode = drm_mode_find_dmt(connector->dev,
3839 drm_mode_probed_add(connector, mode);
3850 do_established_modes(const struct detailed_timing *timing, void *c)
3852 struct detailed_mode_closure *closure = c;
3854 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3857 closure->modes += drm_est3_modes(closure->connector, timing);
3861 * Get established modes from EDID and add them. Each EDID block contains a
3862 * bitmap of the supported "established modes" list (defined above). Tease them
3863 * out and add them to the global modes list.
3865 static int add_established_modes(struct drm_connector *connector,
3866 const struct drm_edid *drm_edid)
3868 struct drm_device *dev = connector->dev;
3869 const struct edid *edid = drm_edid->edid;
3870 unsigned long est_bits = edid->established_timings.t1 |
3871 (edid->established_timings.t2 << 8) |
3872 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3874 struct detailed_mode_closure closure = {
3875 .connector = connector,
3876 .drm_edid = drm_edid,
3879 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3880 if (est_bits & (1<<i)) {
3881 struct drm_display_mode *newmode;
3883 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3885 drm_mode_probed_add(connector, newmode);
3891 if (edid->revision >= 1)
3892 drm_for_each_detailed_block(drm_edid, do_established_modes,
3895 return modes + closure.modes;
3899 do_standard_modes(const struct detailed_timing *timing, void *c)
3901 struct detailed_mode_closure *closure = c;
3902 const struct detailed_non_pixel *data = &timing->data.other_data;
3903 struct drm_connector *connector = closure->connector;
3906 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3909 for (i = 0; i < 6; i++) {
3910 const struct std_timing *std = &data->data.timings[i];
3911 struct drm_display_mode *newmode;
3913 newmode = drm_mode_std(connector, closure->drm_edid, std);
3915 drm_mode_probed_add(connector, newmode);
3922 * Get standard modes from EDID and add them. Standard modes can be calculated
3923 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3924 * add them to the list.
3926 static int add_standard_modes(struct drm_connector *connector,
3927 const struct drm_edid *drm_edid)
3930 struct detailed_mode_closure closure = {
3931 .connector = connector,
3932 .drm_edid = drm_edid,
3935 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3936 struct drm_display_mode *newmode;
3938 newmode = drm_mode_std(connector, drm_edid,
3939 &drm_edid->edid->standard_timings[i]);
3941 drm_mode_probed_add(connector, newmode);
3946 if (drm_edid->edid->revision >= 1)
3947 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3950 /* XXX should also look for standard codes in VTB blocks */
3952 return modes + closure.modes;
3955 static int drm_cvt_modes(struct drm_connector *connector,
3956 const struct detailed_timing *timing)
3958 int i, j, modes = 0;
3959 struct drm_display_mode *newmode;
3960 struct drm_device *dev = connector->dev;
3961 const struct cvt_timing *cvt;
3962 static const int rates[] = { 60, 85, 75, 60, 50 };
3963 const u8 empty[3] = { 0, 0, 0 };
3965 for (i = 0; i < 4; i++) {
3968 cvt = &(timing->data.other_data.data.cvt[i]);
3970 if (!memcmp(cvt->code, empty, 3))
3973 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3974 switch (cvt->code[1] & 0x0c) {
3975 /* default - because compiler doesn't see that we've enumerated all cases */
3978 width = height * 4 / 3;
3981 width = height * 16 / 9;
3984 width = height * 16 / 10;
3987 width = height * 15 / 9;
3991 for (j = 1; j < 5; j++) {
3992 if (cvt->code[2] & (1 << j)) {
3993 newmode = drm_cvt_mode(dev, width, height,
3997 drm_mode_probed_add(connector, newmode);
4008 do_cvt_mode(const struct detailed_timing *timing, void *c)
4010 struct detailed_mode_closure *closure = c;
4012 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4015 closure->modes += drm_cvt_modes(closure->connector, timing);
4019 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4021 struct detailed_mode_closure closure = {
4022 .connector = connector,
4023 .drm_edid = drm_edid,
4026 if (drm_edid->edid->revision >= 3)
4027 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4029 /* XXX should also look for CVT codes in VTB blocks */
4031 return closure.modes;
4034 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4035 struct drm_display_mode *mode);
4038 do_detailed_mode(const struct detailed_timing *timing, void *c)
4040 struct detailed_mode_closure *closure = c;
4041 struct drm_display_mode *newmode;
4043 if (!is_detailed_timing_descriptor(timing))
4046 newmode = drm_mode_detailed(closure->connector,
4047 closure->drm_edid, timing);
4051 if (closure->preferred)
4052 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4055 * Detailed modes are limited to 10kHz pixel clock resolution,
4056 * so fix up anything that looks like CEA/HDMI mode, but the clock
4057 * is just slightly off.
4059 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4061 drm_mode_probed_add(closure->connector, newmode);
4063 closure->preferred = false;
4067 * add_detailed_modes - Add modes from detailed timings
4068 * @connector: attached connector
4069 * @drm_edid: EDID block to scan
4071 static int add_detailed_modes(struct drm_connector *connector,
4072 const struct drm_edid *drm_edid)
4074 struct detailed_mode_closure closure = {
4075 .connector = connector,
4076 .drm_edid = drm_edid,
4079 if (drm_edid->edid->revision >= 4)
4080 closure.preferred = true; /* first detailed timing is always preferred */
4083 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4085 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4087 return closure.modes;
4090 /* CTA-861-H Table 60 - CTA Tag Codes */
4091 #define CTA_DB_AUDIO 1
4092 #define CTA_DB_VIDEO 2
4093 #define CTA_DB_VENDOR 3
4094 #define CTA_DB_SPEAKER 4
4095 #define CTA_DB_EXTENDED_TAG 7
4097 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4098 #define CTA_EXT_DB_VIDEO_CAP 0
4099 #define CTA_EXT_DB_VENDOR 1
4100 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4101 #define CTA_EXT_DB_420_VIDEO_DATA 14
4102 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4103 #define CTA_EXT_DB_HF_EEODB 0x78
4104 #define CTA_EXT_DB_HF_SCDB 0x79
4106 #define EDID_BASIC_AUDIO (1 << 6)
4107 #define EDID_CEA_YCRCB444 (1 << 5)
4108 #define EDID_CEA_YCRCB422 (1 << 4)
4109 #define EDID_CEA_VCDB_QS (1 << 6)
4112 * Search EDID for CEA extension block.
4114 * FIXME: Prefer not returning pointers to raw EDID data.
4116 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4117 int ext_id, int *ext_index)
4119 const u8 *edid_ext = NULL;
4122 /* No EDID or EDID extensions */
4123 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4126 /* Find CEA extension */
4127 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4128 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4129 if (edid_block_tag(edid_ext) == ext_id)
4133 if (i >= drm_edid_extension_block_count(drm_edid))
4141 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4142 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4144 const struct displayid_block *block;
4145 struct displayid_iter iter;
4149 /* Look for a top level CEA extension block */
4150 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4153 /* CEA blocks can also be found embedded in a DisplayID block */
4154 displayid_iter_edid_begin(drm_edid, &iter);
4155 displayid_iter_for_each(block, &iter) {
4156 if (block->tag == DATA_BLOCK_CTA) {
4161 displayid_iter_end(&iter);
4166 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4168 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4169 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4171 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4172 return &edid_cea_modes_1[vic - 1];
4173 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4174 return &edid_cea_modes_193[vic - 193];
4178 static u8 cea_num_vics(void)
4180 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4183 static u8 cea_next_vic(u8 vic)
4185 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4191 * Calculate the alternate clock for the CEA mode
4192 * (60Hz vs. 59.94Hz etc.)
4195 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4197 unsigned int clock = cea_mode->clock;
4199 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4203 * edid_cea_modes contains the 59.94Hz
4204 * variant for 240 and 480 line modes,
4205 * and the 60Hz variant otherwise.
4207 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4208 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4210 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4216 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4219 * For certain VICs the spec allows the vertical
4220 * front porch to vary by one or two lines.
4222 * cea_modes[] stores the variant with the shortest
4223 * vertical front porch. We can adjust the mode to
4224 * get the other variants by simply increasing the
4225 * vertical front porch length.
4227 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4228 cea_mode_for_vic(9)->vtotal != 262 ||
4229 cea_mode_for_vic(12)->vtotal != 262 ||
4230 cea_mode_for_vic(13)->vtotal != 262 ||
4231 cea_mode_for_vic(23)->vtotal != 312 ||
4232 cea_mode_for_vic(24)->vtotal != 312 ||
4233 cea_mode_for_vic(27)->vtotal != 312 ||
4234 cea_mode_for_vic(28)->vtotal != 312);
4236 if (((vic == 8 || vic == 9 ||
4237 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4238 ((vic == 23 || vic == 24 ||
4239 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4240 mode->vsync_start++;
4250 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4251 unsigned int clock_tolerance)
4253 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4256 if (!to_match->clock)
4259 if (to_match->picture_aspect_ratio)
4260 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4262 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4263 struct drm_display_mode cea_mode;
4264 unsigned int clock1, clock2;
4266 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4268 /* Check both 60Hz and 59.94Hz */
4269 clock1 = cea_mode.clock;
4270 clock2 = cea_mode_alternate_clock(&cea_mode);
4272 if (abs(to_match->clock - clock1) > clock_tolerance &&
4273 abs(to_match->clock - clock2) > clock_tolerance)
4277 if (drm_mode_match(to_match, &cea_mode, match_flags))
4279 } while (cea_mode_alternate_timings(vic, &cea_mode));
4286 * drm_match_cea_mode - look for a CEA mode matching given mode
4287 * @to_match: display mode
4289 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4292 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4294 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4297 if (!to_match->clock)
4300 if (to_match->picture_aspect_ratio)
4301 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4303 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4304 struct drm_display_mode cea_mode;
4305 unsigned int clock1, clock2;
4307 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4309 /* Check both 60Hz and 59.94Hz */
4310 clock1 = cea_mode.clock;
4311 clock2 = cea_mode_alternate_clock(&cea_mode);
4313 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4314 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4318 if (drm_mode_match(to_match, &cea_mode, match_flags))
4320 } while (cea_mode_alternate_timings(vic, &cea_mode));
4325 EXPORT_SYMBOL(drm_match_cea_mode);
4327 static bool drm_valid_cea_vic(u8 vic)
4329 return cea_mode_for_vic(vic) != NULL;
4332 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4334 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4337 return mode->picture_aspect_ratio;
4339 return HDMI_PICTURE_ASPECT_NONE;
4342 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4344 return edid_4k_modes[video_code].picture_aspect_ratio;
4348 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4352 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4354 return cea_mode_alternate_clock(hdmi_mode);
4357 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4358 unsigned int clock_tolerance)
4360 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4363 if (!to_match->clock)
4366 if (to_match->picture_aspect_ratio)
4367 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4369 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4370 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4371 unsigned int clock1, clock2;
4373 /* Make sure to also match alternate clocks */
4374 clock1 = hdmi_mode->clock;
4375 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4377 if (abs(to_match->clock - clock1) > clock_tolerance &&
4378 abs(to_match->clock - clock2) > clock_tolerance)
4381 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4389 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4390 * @to_match: display mode
4392 * An HDMI mode is one defined in the HDMI vendor specific block.
4394 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4396 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4398 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4401 if (!to_match->clock)
4404 if (to_match->picture_aspect_ratio)
4405 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4407 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4408 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4409 unsigned int clock1, clock2;
4411 /* Make sure to also match alternate clocks */
4412 clock1 = hdmi_mode->clock;
4413 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4415 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4416 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4417 drm_mode_match(to_match, hdmi_mode, match_flags))
4423 static bool drm_valid_hdmi_vic(u8 vic)
4425 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4428 static int add_alternate_cea_modes(struct drm_connector *connector,
4429 const struct drm_edid *drm_edid)
4431 struct drm_device *dev = connector->dev;
4432 struct drm_display_mode *mode, *tmp;
4436 /* Don't add CTA modes if the CTA extension block is missing */
4437 if (!drm_edid_has_cta_extension(drm_edid))
4441 * Go through all probed modes and create a new mode
4442 * with the alternate clock for certain CEA modes.
4444 list_for_each_entry(mode, &connector->probed_modes, head) {
4445 const struct drm_display_mode *cea_mode = NULL;
4446 struct drm_display_mode *newmode;
4447 u8 vic = drm_match_cea_mode(mode);
4448 unsigned int clock1, clock2;
4450 if (drm_valid_cea_vic(vic)) {
4451 cea_mode = cea_mode_for_vic(vic);
4452 clock2 = cea_mode_alternate_clock(cea_mode);
4454 vic = drm_match_hdmi_mode(mode);
4455 if (drm_valid_hdmi_vic(vic)) {
4456 cea_mode = &edid_4k_modes[vic];
4457 clock2 = hdmi_mode_alternate_clock(cea_mode);
4464 clock1 = cea_mode->clock;
4466 if (clock1 == clock2)
4469 if (mode->clock != clock1 && mode->clock != clock2)
4472 newmode = drm_mode_duplicate(dev, cea_mode);
4476 /* Carry over the stereo flags */
4477 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4480 * The current mode could be either variant. Make
4481 * sure to pick the "other" clock for the new mode.
4483 if (mode->clock != clock1)
4484 newmode->clock = clock1;
4486 newmode->clock = clock2;
4488 list_add_tail(&newmode->head, &list);
4491 list_for_each_entry_safe(mode, tmp, &list, head) {
4492 list_del(&mode->head);
4493 drm_mode_probed_add(connector, mode);
4500 static u8 svd_to_vic(u8 svd)
4502 /* 0-6 bit vic, 7th bit native mode indicator */
4503 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4510 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4511 * the EDID, or NULL on errors.
4513 static struct drm_display_mode *
4514 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4516 const struct drm_display_info *info = &connector->display_info;
4517 struct drm_device *dev = connector->dev;
4519 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4522 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4526 * do_y420vdb_modes - Parse YCBCR 420 only modes
4527 * @connector: connector corresponding to the HDMI sink
4528 * @svds: start of the data block of CEA YCBCR 420 VDB
4529 * @len: length of the CEA YCBCR 420 VDB
4531 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4532 * which contains modes which can be supported in YCBCR 420
4533 * output format only.
4535 static int do_y420vdb_modes(struct drm_connector *connector,
4536 const u8 *svds, u8 svds_len)
4538 struct drm_device *dev = connector->dev;
4541 for (i = 0; i < svds_len; i++) {
4542 u8 vic = svd_to_vic(svds[i]);
4543 struct drm_display_mode *newmode;
4545 if (!drm_valid_cea_vic(vic))
4548 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4551 drm_mode_probed_add(connector, newmode);
4559 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4561 * @video_code: CEA VIC of the mode
4563 * Creates a new mode matching the specified CEA VIC.
4565 * Returns: A new drm_display_mode on success or NULL on failure
4567 struct drm_display_mode *
4568 drm_display_mode_from_cea_vic(struct drm_device *dev,
4571 const struct drm_display_mode *cea_mode;
4572 struct drm_display_mode *newmode;
4574 cea_mode = cea_mode_for_vic(video_code);
4578 newmode = drm_mode_duplicate(dev, cea_mode);
4584 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4586 /* Add modes based on VICs parsed in parse_cta_vdb() */
4587 static int add_cta_vdb_modes(struct drm_connector *connector)
4589 const struct drm_display_info *info = &connector->display_info;
4595 for (i = 0; i < info->vics_len; i++) {
4596 struct drm_display_mode *mode;
4598 mode = drm_display_mode_from_vic_index(connector, i);
4600 drm_mode_probed_add(connector, mode);
4608 struct stereo_mandatory_mode {
4609 int width, height, vrefresh;
4613 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4614 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4615 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4617 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4619 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4620 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4621 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4622 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4623 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4627 stereo_match_mandatory(const struct drm_display_mode *mode,
4628 const struct stereo_mandatory_mode *stereo_mode)
4630 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4632 return mode->hdisplay == stereo_mode->width &&
4633 mode->vdisplay == stereo_mode->height &&
4634 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4635 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4638 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4640 struct drm_device *dev = connector->dev;
4641 const struct drm_display_mode *mode;
4642 struct list_head stereo_modes;
4645 INIT_LIST_HEAD(&stereo_modes);
4647 list_for_each_entry(mode, &connector->probed_modes, head) {
4648 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4649 const struct stereo_mandatory_mode *mandatory;
4650 struct drm_display_mode *new_mode;
4652 if (!stereo_match_mandatory(mode,
4653 &stereo_mandatory_modes[i]))
4656 mandatory = &stereo_mandatory_modes[i];
4657 new_mode = drm_mode_duplicate(dev, mode);
4661 new_mode->flags |= mandatory->flags;
4662 list_add_tail(&new_mode->head, &stereo_modes);
4667 list_splice_tail(&stereo_modes, &connector->probed_modes);
4672 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4674 struct drm_device *dev = connector->dev;
4675 struct drm_display_mode *newmode;
4677 if (!drm_valid_hdmi_vic(vic)) {
4678 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4679 connector->base.id, connector->name, vic);
4683 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4687 drm_mode_probed_add(connector, newmode);
4692 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4695 struct drm_display_mode *newmode;
4698 if (structure & (1 << 0)) {
4699 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4701 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4702 drm_mode_probed_add(connector, newmode);
4706 if (structure & (1 << 6)) {
4707 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4709 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4710 drm_mode_probed_add(connector, newmode);
4714 if (structure & (1 << 8)) {
4715 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4717 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4718 drm_mode_probed_add(connector, newmode);
4726 static bool hdmi_vsdb_latency_present(const u8 *db)
4728 return db[8] & BIT(7);
4731 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4733 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4736 static int hdmi_vsdb_latency_length(const u8 *db)
4738 if (hdmi_vsdb_i_latency_present(db))
4740 else if (hdmi_vsdb_latency_present(db))
4747 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4748 * @connector: connector corresponding to the HDMI sink
4749 * @db: start of the CEA vendor specific block
4750 * @len: length of the CEA block payload, ie. one can access up to db[len]
4752 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4753 * also adds the stereo 3d modes when applicable.
4756 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4758 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4759 u8 vic_len, hdmi_3d_len = 0;
4766 /* no HDMI_Video_Present */
4767 if (!(db[8] & (1 << 5)))
4770 offset += hdmi_vsdb_latency_length(db);
4772 /* the declared length is not long enough for the 2 first bytes
4773 * of additional video format capabilities */
4774 if (len < (8 + offset + 2))
4779 if (db[8 + offset] & (1 << 7)) {
4780 modes += add_hdmi_mandatory_stereo_modes(connector);
4782 /* 3D_Multi_present */
4783 multi_present = (db[8 + offset] & 0x60) >> 5;
4787 vic_len = db[8 + offset] >> 5;
4788 hdmi_3d_len = db[8 + offset] & 0x1f;
4790 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4793 vic = db[9 + offset + i];
4794 modes += add_hdmi_mode(connector, vic);
4796 offset += 1 + vic_len;
4798 if (multi_present == 1)
4800 else if (multi_present == 2)
4805 if (len < (8 + offset + hdmi_3d_len - 1))
4808 if (hdmi_3d_len < multi_len)
4811 if (multi_present == 1 || multi_present == 2) {
4812 /* 3D_Structure_ALL */
4813 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4815 /* check if 3D_MASK is present */
4816 if (multi_present == 2)
4817 mask = (db[10 + offset] << 8) | db[11 + offset];
4821 for (i = 0; i < 16; i++) {
4822 if (mask & (1 << i))
4823 modes += add_3d_struct_modes(connector,
4828 offset += multi_len;
4830 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4832 struct drm_display_mode *newmode = NULL;
4833 unsigned int newflag = 0;
4834 bool detail_present;
4836 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4838 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4841 /* 2D_VIC_order_X */
4842 vic_index = db[8 + offset + i] >> 4;
4844 /* 3D_Structure_X */
4845 switch (db[8 + offset + i] & 0x0f) {
4847 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4850 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4854 if ((db[9 + offset + i] >> 4) == 1)
4855 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4860 newmode = drm_display_mode_from_vic_index(connector,
4864 newmode->flags |= newflag;
4865 drm_mode_probed_add(connector, newmode);
4879 cea_revision(const u8 *cea)
4882 * FIXME is this correct for the DispID variant?
4883 * The DispID spec doesn't really specify whether
4884 * this is the revision of the CEA extension or
4885 * the DispID CEA data block. And the only value
4886 * given as an example is 0.
4892 * CTA Data Block iterator.
4894 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4897 * struct cea_db *db:
4898 * struct cea_db_iter iter;
4900 * cea_db_iter_edid_begin(edid, &iter);
4901 * cea_db_iter_for_each(db, &iter) {
4902 * // do stuff with db
4904 * cea_db_iter_end(&iter);
4906 struct cea_db_iter {
4907 struct drm_edid_iter edid_iter;
4908 struct displayid_iter displayid_iter;
4910 /* Current Data Block Collection. */
4911 const u8 *collection;
4913 /* Current Data Block index in current collection. */
4916 /* End index in current collection. */
4920 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4926 static int cea_db_tag(const struct cea_db *db)
4928 return db->tag_length >> 5;
4931 static int cea_db_payload_len(const void *_db)
4933 /* FIXME: Transition to passing struct cea_db * everywhere. */
4934 const struct cea_db *db = _db;
4936 return db->tag_length & 0x1f;
4939 static const void *cea_db_data(const struct cea_db *db)
4944 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4946 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4947 cea_db_payload_len(db) >= 1 &&
4951 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4953 const u8 *data = cea_db_data(db);
4955 return cea_db_tag(db) == CTA_DB_VENDOR &&
4956 cea_db_payload_len(db) >= 3 &&
4957 oui(data[2], data[1], data[0]) == vendor_oui;
4960 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4961 struct cea_db_iter *iter)
4963 memset(iter, 0, sizeof(*iter));
4965 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4966 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4969 static const struct cea_db *
4970 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4972 const struct cea_db *db;
4974 if (!iter->collection)
4977 db = (const struct cea_db *)&iter->collection[iter->index];
4979 if (iter->index + sizeof(*db) <= iter->end &&
4980 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4988 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4990 static int cea_db_collection_size(const u8 *cta)
4994 if (d < 4 || d > 127)
5002 * - VESA E-EDID v1.4
5003 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5005 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5009 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5012 /* Only support CTA Extension revision 3+ */
5013 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5016 size = cea_db_collection_size(ext);
5021 iter->end = iter->index + size;
5031 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5032 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5034 * Note that the above do not specify any connection between DisplayID Data
5035 * Block revision and CTA Extension versions.
5037 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5039 const struct displayid_block *block;
5041 displayid_iter_for_each(block, &iter->displayid_iter) {
5042 if (block->tag != DATA_BLOCK_CTA)
5046 * The displayid iterator has already verified the block bounds
5047 * in displayid_iter_block().
5049 iter->index = sizeof(*block);
5050 iter->end = iter->index + block->num_bytes;
5058 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5060 const struct cea_db *db;
5062 if (iter->collection) {
5063 /* Current collection should always be valid. */
5064 db = __cea_db_iter_current_block(iter);
5066 iter->collection = NULL;
5070 /* Next block in CTA Data Block Collection */
5071 iter->index += sizeof(*db) + cea_db_payload_len(db);
5073 db = __cea_db_iter_current_block(iter);
5080 * Find the next CTA Data Block Collection. First iterate all
5081 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5083 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5084 * Extension, it's recommended that DisplayID extensions are
5085 * exposed after all of the CTA Extensions.
5087 iter->collection = __cea_db_iter_edid_next(iter);
5088 if (!iter->collection)
5089 iter->collection = __cea_db_iter_displayid_next(iter);
5091 if (!iter->collection)
5094 db = __cea_db_iter_current_block(iter);
5100 #define cea_db_iter_for_each(__db, __iter) \
5101 while (((__db) = __cea_db_iter_next(__iter)))
5103 static void cea_db_iter_end(struct cea_db_iter *iter)
5105 displayid_iter_end(&iter->displayid_iter);
5106 drm_edid_iter_end(&iter->edid_iter);
5108 memset(iter, 0, sizeof(*iter));
5111 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5113 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5114 cea_db_payload_len(db) >= 5;
5117 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5119 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5120 cea_db_payload_len(db) >= 7;
5123 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5125 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5126 cea_db_payload_len(db) >= 2;
5129 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5131 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5132 cea_db_payload_len(db) == 21;
5135 static bool cea_db_is_vcdb(const struct cea_db *db)
5137 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5138 cea_db_payload_len(db) == 2;
5141 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5143 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5144 cea_db_payload_len(db) >= 7;
5147 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5149 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5152 static bool cea_db_is_y420vdb(const struct cea_db *db)
5154 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5157 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5159 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5160 cea_db_payload_len(db) >= 3;
5164 * Get the HF-EEODB override extension block count from EDID.
5166 * The passed in EDID may be partially read, as long as it has at least two
5167 * blocks (base block and one extension block) if EDID extension count is > 0.
5169 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5170 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5171 * iterators instead.
5174 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5176 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5180 /* No extensions according to base block, no HF-EEODB. */
5181 if (!edid_extension_block_count(edid))
5184 /* HF-EEODB is always in the first EDID extension block only */
5185 cta = edid_extension_block_data(edid, 0);
5186 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5189 /* Need to have the data block collection, and at least 3 bytes. */
5190 if (cea_db_collection_size(cta) < 3)
5194 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5195 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5196 * through 6 of Block 1 of the E-EDID.
5198 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5205 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5207 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5208 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5209 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5210 * support YCBCR420 output too.
5212 static void parse_cta_y420cmdb(struct drm_connector *connector,
5213 const struct cea_db *db, u64 *y420cmdb_map)
5215 struct drm_display_info *info = &connector->display_info;
5216 int i, map_len = cea_db_payload_len(db) - 1;
5217 const u8 *data = cea_db_data(db) + 1;
5221 /* All CEA modes support ycbcr420 sampling also.*/
5227 * This map indicates which of the existing CEA block modes
5228 * from VDB can support YCBCR420 output too. So if bit=0 is
5229 * set, first mode from VDB can support YCBCR420 output too.
5230 * We will parse and keep this map, before parsing VDB itself
5231 * to avoid going through the same block again and again.
5233 * Spec is not clear about max possible size of this block.
5234 * Clamping max bitmap block size at 8 bytes. Every byte can
5235 * address 8 CEA modes, in this way this map can address
5236 * 8*8 = first 64 SVDs.
5238 if (WARN_ON_ONCE(map_len > 8))
5241 for (i = 0; i < map_len; i++)
5242 map |= (u64)data[i] << (8 * i);
5246 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5248 *y420cmdb_map = map;
5251 static int add_cea_modes(struct drm_connector *connector,
5252 const struct drm_edid *drm_edid)
5254 const struct cea_db *db;
5255 struct cea_db_iter iter;
5258 /* CTA VDB block VICs parsed earlier */
5259 modes = add_cta_vdb_modes(connector);
5261 cea_db_iter_edid_begin(drm_edid, &iter);
5262 cea_db_iter_for_each(db, &iter) {
5263 if (cea_db_is_hdmi_vsdb(db)) {
5264 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5265 cea_db_payload_len(db));
5266 } else if (cea_db_is_y420vdb(db)) {
5267 const u8 *vdb420 = cea_db_data(db) + 1;
5269 /* Add 4:2:0(only) modes present in EDID */
5270 modes += do_y420vdb_modes(connector, vdb420,
5271 cea_db_payload_len(db) - 1);
5274 cea_db_iter_end(&iter);
5279 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5280 struct drm_display_mode *mode)
5282 const struct drm_display_mode *cea_mode;
5283 int clock1, clock2, clock;
5288 * allow 5kHz clock difference either way to account for
5289 * the 10kHz clock resolution limit of detailed timings.
5291 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5292 if (drm_valid_cea_vic(vic)) {
5294 cea_mode = cea_mode_for_vic(vic);
5295 clock1 = cea_mode->clock;
5296 clock2 = cea_mode_alternate_clock(cea_mode);
5298 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5299 if (drm_valid_hdmi_vic(vic)) {
5301 cea_mode = &edid_4k_modes[vic];
5302 clock1 = cea_mode->clock;
5303 clock2 = hdmi_mode_alternate_clock(cea_mode);
5309 /* pick whichever is closest */
5310 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5315 if (mode->clock == clock)
5318 drm_dbg_kms(connector->dev,
5319 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5320 connector->base.id, connector->name,
5321 type, vic, mode->clock, clock);
5322 mode->clock = clock;
5325 static void drm_calculate_luminance_range(struct drm_connector *connector)
5327 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5328 struct drm_luminance_range_info *luminance_range =
5329 &connector->display_info.luminance_range;
5330 static const u8 pre_computed_values[] = {
5331 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5332 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5334 u32 max_avg, min_cll, max, min, q, r;
5336 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5339 max_avg = hdr_metadata->max_fall;
5340 min_cll = hdr_metadata->min_cll;
5343 * From the specification (CTA-861-G), for calculating the maximum
5344 * luminance we need to use:
5345 * Luminance = 50*2**(CV/32)
5346 * Where CV is a one-byte value.
5347 * For calculating this expression we may need float point precision;
5348 * to avoid this complexity level, we take advantage that CV is divided
5349 * by a constant. From the Euclids division algorithm, we know that CV
5350 * can be written as: CV = 32*q + r. Next, we replace CV in the
5351 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5352 * need to pre-compute the value of r/32. For pre-computing the values
5353 * We just used the following Ruby line:
5354 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5355 * The results of the above expressions can be verified at
5356 * pre_computed_values.
5360 max = (1 << q) * pre_computed_values[r];
5362 /* min luminance: maxLum * (CV/255)^2 / 100 */
5363 q = DIV_ROUND_CLOSEST(min_cll, 255);
5364 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5366 luminance_range->min_luminance = min;
5367 luminance_range->max_luminance = max;
5370 static uint8_t eotf_supported(const u8 *edid_ext)
5372 return edid_ext[2] &
5373 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5374 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5375 BIT(HDMI_EOTF_SMPTE_ST2084) |
5376 BIT(HDMI_EOTF_BT_2100_HLG));
5379 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5381 return edid_ext[3] &
5382 BIT(HDMI_STATIC_METADATA_TYPE1);
5386 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5390 len = cea_db_payload_len(db);
5392 connector->hdr_sink_metadata.hdmi_type1.eotf =
5394 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5395 hdr_metadata_type(db);
5398 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5400 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5402 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5404 /* Calculate only when all values are available */
5405 drm_calculate_luminance_range(connector);
5409 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5411 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5413 u8 len = cea_db_payload_len(db);
5415 if (len >= 6 && (db[6] & (1 << 7)))
5416 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5418 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5419 connector->latency_present[0] = true;
5420 connector->video_latency[0] = db[9];
5421 connector->audio_latency[0] = db[10];
5424 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5425 connector->latency_present[1] = true;
5426 connector->video_latency[1] = db[11];
5427 connector->audio_latency[1] = db[12];
5430 drm_dbg_kms(connector->dev,
5431 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5432 connector->base.id, connector->name,
5433 connector->latency_present[0], connector->latency_present[1],
5434 connector->video_latency[0], connector->video_latency[1],
5435 connector->audio_latency[0], connector->audio_latency[1]);
5439 monitor_name(const struct detailed_timing *timing, void *data)
5441 const char **res = data;
5443 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5446 *res = timing->data.other_data.data.str.str;
5449 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5451 const char *edid_name = NULL;
5454 if (!drm_edid || !name)
5457 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5458 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5459 if (edid_name[mnl] == 0x0a)
5462 name[mnl] = edid_name[mnl];
5469 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5470 * @edid: monitor EDID information
5471 * @name: pointer to a character array to hold the name of the monitor
5472 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5475 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5477 int name_length = 0;
5484 struct drm_edid drm_edid = {
5486 .size = edid_size(edid),
5489 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5490 memcpy(name, buf, name_length);
5493 name[name_length] = '\0';
5495 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5497 static void clear_eld(struct drm_connector *connector)
5499 memset(connector->eld, 0, sizeof(connector->eld));
5501 connector->latency_present[0] = false;
5502 connector->latency_present[1] = false;
5503 connector->video_latency[0] = 0;
5504 connector->audio_latency[0] = 0;
5505 connector->video_latency[1] = 0;
5506 connector->audio_latency[1] = 0;
5510 * drm_edid_to_eld - build ELD from EDID
5511 * @connector: connector corresponding to the HDMI/DP sink
5512 * @drm_edid: EDID to parse
5514 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5515 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5517 static void drm_edid_to_eld(struct drm_connector *connector,
5518 const struct drm_edid *drm_edid)
5520 const struct drm_display_info *info = &connector->display_info;
5521 const struct cea_db *db;
5522 struct cea_db_iter iter;
5523 uint8_t *eld = connector->eld;
5524 int total_sad_count = 0;
5530 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5531 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5532 connector->base.id, connector->name,
5533 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5535 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5536 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5538 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5540 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5541 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5542 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5543 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5545 cea_db_iter_edid_begin(drm_edid, &iter);
5546 cea_db_iter_for_each(db, &iter) {
5547 const u8 *data = cea_db_data(db);
5548 int len = cea_db_payload_len(db);
5551 switch (cea_db_tag(db)) {
5553 /* Audio Data Block, contains SADs */
5554 sad_count = min(len / 3, 15 - total_sad_count);
5556 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5557 data, sad_count * 3);
5558 total_sad_count += sad_count;
5560 case CTA_DB_SPEAKER:
5561 /* Speaker Allocation Data Block */
5563 eld[DRM_ELD_SPEAKER] = data[0];
5566 /* HDMI Vendor-Specific Data Block */
5567 if (cea_db_is_hdmi_vsdb(db))
5568 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5574 cea_db_iter_end(&iter);
5576 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5578 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5579 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5580 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5582 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5584 eld[DRM_ELD_BASELINE_ELD_LEN] =
5585 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5587 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5588 connector->base.id, connector->name,
5589 drm_eld_size(eld), total_sad_count);
5592 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5593 struct cea_sad **sads)
5595 const struct cea_db *db;
5596 struct cea_db_iter iter;
5599 cea_db_iter_edid_begin(drm_edid, &iter);
5600 cea_db_iter_for_each(db, &iter) {
5601 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5604 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5605 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5608 for (j = 0; j < count; j++) {
5609 const u8 *sad = &db->data[j * 3];
5611 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5612 (*sads)[j].channels = sad[0] & 0x7;
5613 (*sads)[j].freq = sad[1] & 0x7F;
5614 (*sads)[j].byte2 = sad[2];
5619 cea_db_iter_end(&iter);
5621 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5627 * drm_edid_to_sad - extracts SADs from EDID
5628 * @edid: EDID to parse
5629 * @sads: pointer that will be set to the extracted SADs
5631 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5633 * Note: The returned pointer needs to be freed using kfree().
5635 * Return: The number of found SADs or negative number on error.
5637 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5639 struct drm_edid drm_edid;
5641 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5643 EXPORT_SYMBOL(drm_edid_to_sad);
5645 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5648 const struct cea_db *db;
5649 struct cea_db_iter iter;
5652 cea_db_iter_edid_begin(drm_edid, &iter);
5653 cea_db_iter_for_each(db, &iter) {
5654 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5655 cea_db_payload_len(db) == 3) {
5656 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5660 count = cea_db_payload_len(db);
5664 cea_db_iter_end(&iter);
5666 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5672 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5673 * @edid: EDID to parse
5674 * @sadb: pointer to the speaker block
5676 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5678 * Note: The returned pointer needs to be freed using kfree().
5680 * Return: The number of found Speaker Allocation Blocks or negative number on
5683 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5685 struct drm_edid drm_edid;
5687 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5690 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5693 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5694 * @connector: connector associated with the HDMI/DP sink
5695 * @mode: the display mode
5697 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5698 * the sink doesn't support audio or video.
5700 int drm_av_sync_delay(struct drm_connector *connector,
5701 const struct drm_display_mode *mode)
5703 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5706 if (!connector->latency_present[0])
5708 if (!connector->latency_present[1])
5711 a = connector->audio_latency[i];
5712 v = connector->video_latency[i];
5715 * HDMI/DP sink doesn't support audio or video?
5717 if (a == 255 || v == 255)
5721 * Convert raw EDID values to millisecond.
5722 * Treat unknown latency as 0ms.
5725 a = min(2 * (a - 1), 500);
5727 v = min(2 * (v - 1), 500);
5729 return max(v - a, 0);
5731 EXPORT_SYMBOL(drm_av_sync_delay);
5733 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5735 const struct cea_db *db;
5736 struct cea_db_iter iter;
5740 * Because HDMI identifier is in Vendor Specific Block,
5741 * search it from all data blocks of CEA extension.
5743 cea_db_iter_edid_begin(drm_edid, &iter);
5744 cea_db_iter_for_each(db, &iter) {
5745 if (cea_db_is_hdmi_vsdb(db)) {
5750 cea_db_iter_end(&iter);
5756 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5757 * @edid: monitor EDID information
5759 * Parse the CEA extension according to CEA-861-B.
5761 * Drivers that have added the modes parsed from EDID to drm_display_info
5762 * should use &drm_display_info.is_hdmi instead of calling this function.
5764 * Return: True if the monitor is HDMI, false if not or unknown.
5766 bool drm_detect_hdmi_monitor(const struct edid *edid)
5768 struct drm_edid drm_edid;
5770 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5772 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5774 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5776 struct drm_edid_iter edid_iter;
5777 const struct cea_db *db;
5778 struct cea_db_iter iter;
5780 bool has_audio = false;
5782 drm_edid_iter_begin(drm_edid, &edid_iter);
5783 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5784 if (edid_ext[0] == CEA_EXT) {
5785 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5790 drm_edid_iter_end(&edid_iter);
5793 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5797 cea_db_iter_edid_begin(drm_edid, &iter);
5798 cea_db_iter_for_each(db, &iter) {
5799 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5800 const u8 *data = cea_db_data(db);
5803 for (i = 0; i < cea_db_payload_len(db); i += 3)
5804 DRM_DEBUG_KMS("CEA audio format %d\n",
5805 (data[i] >> 3) & 0xf);
5810 cea_db_iter_end(&iter);
5817 * drm_detect_monitor_audio - check monitor audio capability
5818 * @edid: EDID block to scan
5820 * Monitor should have CEA extension block.
5821 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5822 * audio' only. If there is any audio extension block and supported
5823 * audio format, assume at least 'basic audio' support, even if 'basic
5824 * audio' is not defined in EDID.
5826 * Return: True if the monitor supports audio, false otherwise.
5828 bool drm_detect_monitor_audio(const struct edid *edid)
5830 struct drm_edid drm_edid;
5832 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5834 EXPORT_SYMBOL(drm_detect_monitor_audio);
5838 * drm_default_rgb_quant_range - default RGB quantization range
5839 * @mode: display mode
5841 * Determine the default RGB quantization range for the mode,
5842 * as specified in CEA-861.
5844 * Return: The default RGB quantization range for the mode
5846 enum hdmi_quantization_range
5847 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5849 /* All CEA modes other than VIC 1 use limited quantization range. */
5850 return drm_match_cea_mode(mode) > 1 ?
5851 HDMI_QUANTIZATION_RANGE_LIMITED :
5852 HDMI_QUANTIZATION_RANGE_FULL;
5854 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5856 /* CTA-861 Video Data Block (CTA VDB) */
5857 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5859 struct drm_display_info *info = &connector->display_info;
5860 int i, vic_index, len = cea_db_payload_len(db);
5861 const u8 *svds = cea_db_data(db);
5867 /* Gracefully handle multiple VDBs, however unlikely that is */
5868 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5872 vic_index = info->vics_len;
5873 info->vics_len += len;
5876 for (i = 0; i < len; i++) {
5877 u8 vic = svd_to_vic(svds[i]);
5879 if (!drm_valid_cea_vic(vic))
5882 info->vics[vic_index++] = vic;
5887 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5889 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5890 * using the VICs themselves.
5892 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5894 struct drm_display_info *info = &connector->display_info;
5895 struct drm_hdmi_info *hdmi = &info->hdmi;
5896 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5898 for (i = 0; i < len; i++) {
5899 u8 vic = info->vics[i];
5901 if (vic && y420cmdb_map & BIT_ULL(i))
5902 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5906 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5908 const struct drm_display_info *info = &connector->display_info;
5911 if (!vic || !info->vics)
5914 for (i = 0; i < info->vics_len; i++) {
5915 if (info->vics[i] == vic)
5922 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5923 static void parse_cta_y420vdb(struct drm_connector *connector,
5924 const struct cea_db *db)
5926 struct drm_display_info *info = &connector->display_info;
5927 struct drm_hdmi_info *hdmi = &info->hdmi;
5928 const u8 *svds = cea_db_data(db) + 1;
5931 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5932 u8 vic = svd_to_vic(svds[i]);
5934 if (!drm_valid_cea_vic(vic))
5937 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5938 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5942 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5944 struct drm_display_info *info = &connector->display_info;
5946 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5947 connector->base.id, connector->name, db[2]);
5949 if (db[2] & EDID_CEA_VCDB_QS)
5950 info->rgb_quant_range_selectable = true;
5954 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5956 switch (max_frl_rate) {
5959 *max_rate_per_lane = 3;
5963 *max_rate_per_lane = 6;
5967 *max_rate_per_lane = 6;
5971 *max_rate_per_lane = 8;
5975 *max_rate_per_lane = 10;
5979 *max_rate_per_lane = 12;
5984 *max_rate_per_lane = 0;
5988 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5992 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5994 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5995 hdmi->y420_dc_modes = dc_mask;
5998 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6001 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6003 if (!hdmi_dsc->v_1p2)
6006 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6007 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6009 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6010 hdmi_dsc->bpc_supported = 16;
6011 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6012 hdmi_dsc->bpc_supported = 12;
6013 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6014 hdmi_dsc->bpc_supported = 10;
6016 /* Supports min 8 BPC if DSC 1.2 is supported*/
6017 hdmi_dsc->bpc_supported = 8;
6019 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6021 u8 dsc_max_frl_rate;
6023 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6024 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6025 &hdmi_dsc->max_frl_rate_per_lane);
6027 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6029 switch (dsc_max_slices) {
6031 hdmi_dsc->max_slices = 1;
6032 hdmi_dsc->clk_per_slice = 340;
6035 hdmi_dsc->max_slices = 2;
6036 hdmi_dsc->clk_per_slice = 340;
6039 hdmi_dsc->max_slices = 4;
6040 hdmi_dsc->clk_per_slice = 340;
6043 hdmi_dsc->max_slices = 8;
6044 hdmi_dsc->clk_per_slice = 340;
6047 hdmi_dsc->max_slices = 8;
6048 hdmi_dsc->clk_per_slice = 400;
6051 hdmi_dsc->max_slices = 12;
6052 hdmi_dsc->clk_per_slice = 400;
6055 hdmi_dsc->max_slices = 16;
6056 hdmi_dsc->clk_per_slice = 400;
6060 hdmi_dsc->max_slices = 0;
6061 hdmi_dsc->clk_per_slice = 0;
6065 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6066 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6069 /* Sink Capability Data Structure */
6070 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6073 struct drm_display_info *info = &connector->display_info;
6074 struct drm_hdmi_info *hdmi = &info->hdmi;
6075 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6076 int max_tmds_clock = 0;
6077 u8 max_frl_rate = 0;
6078 bool dsc_support = false;
6080 info->has_hdmi_infoframe = true;
6082 if (hf_scds[6] & 0x80) {
6083 hdmi->scdc.supported = true;
6084 if (hf_scds[6] & 0x40)
6085 hdmi->scdc.read_request = true;
6089 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6090 * And as per the spec, three factors confirm this:
6091 * * Availability of a HF-VSDB block in EDID (check)
6092 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6093 * * SCDC support available (let's check)
6094 * Lets check it out.
6098 struct drm_scdc *scdc = &hdmi->scdc;
6100 /* max clock is 5000 KHz times block value */
6101 max_tmds_clock = hf_scds[5] * 5000;
6103 if (max_tmds_clock > 340000) {
6104 info->max_tmds_clock = max_tmds_clock;
6107 if (scdc->supported) {
6108 scdc->scrambling.supported = true;
6110 /* Few sinks support scrambling for clocks < 340M */
6111 if ((hf_scds[6] & 0x8))
6112 scdc->scrambling.low_rates = true;
6117 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6118 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6119 &hdmi->max_frl_rate_per_lane);
6122 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6124 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6125 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6129 drm_dbg_kms(connector->dev,
6130 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6131 connector->base.id, connector->name,
6132 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6135 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6138 struct drm_display_info *info = &connector->display_info;
6139 unsigned int dc_bpc = 0;
6141 /* HDMI supports at least 8 bpc */
6144 if (cea_db_payload_len(hdmi) < 6)
6147 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6149 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6150 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6151 connector->base.id, connector->name);
6154 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6156 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6157 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6158 connector->base.id, connector->name);
6161 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6163 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6164 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6165 connector->base.id, connector->name);
6169 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6170 connector->base.id, connector->name);
6174 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6175 connector->base.id, connector->name, dc_bpc);
6178 /* YCRCB444 is optional according to spec. */
6179 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6180 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6181 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6182 connector->base.id, connector->name);
6186 * Spec says that if any deep color mode is supported at all,
6187 * then deep color 36 bit must be supported.
6189 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6190 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6191 connector->base.id, connector->name);
6195 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6197 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6199 struct drm_display_info *info = &connector->display_info;
6200 u8 len = cea_db_payload_len(db);
6202 info->is_hdmi = true;
6204 info->source_physical_address = (db[4] << 8) | db[5];
6207 info->dvi_dual = db[6] & 1;
6209 info->max_tmds_clock = db[7] * 5000;
6212 * Try to infer whether the sink supports HDMI infoframes.
6214 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6215 * supports infoframes if HDMI_Video_present is set.
6217 if (len >= 8 && db[8] & BIT(5))
6218 info->has_hdmi_infoframe = true;
6220 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6221 connector->base.id, connector->name,
6222 info->dvi_dual, info->max_tmds_clock);
6224 drm_parse_hdmi_deep_color_info(connector, db);
6228 * See EDID extension for head-mounted and specialized monitors, specified at:
6229 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6231 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6234 struct drm_display_info *info = &connector->display_info;
6236 bool desktop_usage = db[5] & BIT(6);
6238 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6239 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6240 info->non_desktop = true;
6242 drm_dbg_kms(connector->dev,
6243 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6244 connector->base.id, connector->name, version, db[5]);
6247 static void drm_parse_cea_ext(struct drm_connector *connector,
6248 const struct drm_edid *drm_edid)
6250 struct drm_display_info *info = &connector->display_info;
6251 struct drm_edid_iter edid_iter;
6252 const struct cea_db *db;
6253 struct cea_db_iter iter;
6255 u64 y420cmdb_map = 0;
6257 drm_edid_iter_begin(drm_edid, &edid_iter);
6258 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6259 if (edid_ext[0] != CEA_EXT)
6263 info->cea_rev = edid_ext[1];
6265 if (info->cea_rev != edid_ext[1])
6266 drm_dbg_kms(connector->dev,
6267 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6268 connector->base.id, connector->name,
6269 info->cea_rev, edid_ext[1]);
6271 /* The existence of a CTA extension should imply RGB support */
6272 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6273 if (edid_ext[3] & EDID_CEA_YCRCB444)
6274 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6275 if (edid_ext[3] & EDID_CEA_YCRCB422)
6276 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6277 if (edid_ext[3] & EDID_BASIC_AUDIO)
6278 info->has_audio = true;
6281 drm_edid_iter_end(&edid_iter);
6283 cea_db_iter_edid_begin(drm_edid, &iter);
6284 cea_db_iter_for_each(db, &iter) {
6285 /* FIXME: convert parsers to use struct cea_db */
6286 const u8 *data = (const u8 *)db;
6288 if (cea_db_is_hdmi_vsdb(db))
6289 drm_parse_hdmi_vsdb_video(connector, data);
6290 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6291 cea_db_is_hdmi_forum_scdb(db))
6292 drm_parse_hdmi_forum_scds(connector, data);
6293 else if (cea_db_is_microsoft_vsdb(db))
6294 drm_parse_microsoft_vsdb(connector, data);
6295 else if (cea_db_is_y420cmdb(db))
6296 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6297 else if (cea_db_is_y420vdb(db))
6298 parse_cta_y420vdb(connector, db);
6299 else if (cea_db_is_vcdb(db))
6300 drm_parse_vcdb(connector, data);
6301 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6302 drm_parse_hdr_metadata_block(connector, data);
6303 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6304 parse_cta_vdb(connector, db);
6305 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6306 info->has_audio = true;
6308 cea_db_iter_end(&iter);
6311 update_cta_y420cmdb(connector, y420cmdb_map);
6315 void get_monitor_range(const struct detailed_timing *timing, void *c)
6317 struct detailed_mode_closure *closure = c;
6318 struct drm_display_info *info = &closure->connector->display_info;
6319 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6320 const struct detailed_non_pixel *data = &timing->data.other_data;
6321 const struct detailed_data_monitor_range *range = &data->data.range;
6322 const struct edid *edid = closure->drm_edid->edid;
6324 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6328 * These limits are used to determine the VRR refresh
6329 * rate range. Only the "range limits only" variant
6330 * of the range descriptor seems to guarantee that
6331 * any and all timings are accepted by the sink, as
6332 * opposed to just timings conforming to the indicated
6333 * formula (GTF/GTF2/CVT). Thus other variants of the
6334 * range descriptor are not accepted here.
6336 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6339 monitor_range->min_vfreq = range->min_vfreq;
6340 monitor_range->max_vfreq = range->max_vfreq;
6342 if (edid->revision >= 4) {
6343 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6344 monitor_range->min_vfreq += 255;
6345 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6346 monitor_range->max_vfreq += 255;
6350 static void drm_get_monitor_range(struct drm_connector *connector,
6351 const struct drm_edid *drm_edid)
6353 const struct drm_display_info *info = &connector->display_info;
6354 struct detailed_mode_closure closure = {
6355 .connector = connector,
6356 .drm_edid = drm_edid,
6359 if (drm_edid->edid->revision < 4)
6362 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6365 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6367 drm_dbg_kms(connector->dev,
6368 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6369 connector->base.id, connector->name,
6370 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6373 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6374 const struct displayid_block *block)
6376 struct displayid_vesa_vendor_specific_block *vesa =
6377 (struct displayid_vesa_vendor_specific_block *)block;
6378 struct drm_display_info *info = &connector->display_info;
6380 if (block->num_bytes < 3) {
6381 drm_dbg_kms(connector->dev,
6382 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6383 connector->base.id, connector->name, block->num_bytes);
6387 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6390 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6391 drm_dbg_kms(connector->dev,
6392 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6393 connector->base.id, connector->name);
6397 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6399 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6400 connector->base.id, connector->name);
6403 info->mso_stream_count = 0;
6406 info->mso_stream_count = 2; /* 2 or 4 links */
6409 info->mso_stream_count = 4; /* 4 links */
6413 if (!info->mso_stream_count) {
6414 info->mso_pixel_overlap = 0;
6418 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6419 if (info->mso_pixel_overlap > 8) {
6420 drm_dbg_kms(connector->dev,
6421 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6422 connector->base.id, connector->name,
6423 info->mso_pixel_overlap);
6424 info->mso_pixel_overlap = 8;
6427 drm_dbg_kms(connector->dev,
6428 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6429 connector->base.id, connector->name,
6430 info->mso_stream_count, info->mso_pixel_overlap);
6433 static void drm_update_mso(struct drm_connector *connector,
6434 const struct drm_edid *drm_edid)
6436 const struct displayid_block *block;
6437 struct displayid_iter iter;
6439 displayid_iter_edid_begin(drm_edid, &iter);
6440 displayid_iter_for_each(block, &iter) {
6441 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6442 drm_parse_vesa_mso_data(connector, block);
6444 displayid_iter_end(&iter);
6447 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6448 * all of the values which would have been set from EDID
6450 static void drm_reset_display_info(struct drm_connector *connector)
6452 struct drm_display_info *info = &connector->display_info;
6455 info->height_mm = 0;
6458 info->color_formats = 0;
6460 info->max_tmds_clock = 0;
6461 info->dvi_dual = false;
6462 info->is_hdmi = false;
6463 info->has_audio = false;
6464 info->has_hdmi_infoframe = false;
6465 info->rgb_quant_range_selectable = false;
6466 memset(&info->hdmi, 0, sizeof(info->hdmi));
6468 info->edid_hdmi_rgb444_dc_modes = 0;
6469 info->edid_hdmi_ycbcr444_dc_modes = 0;
6471 info->non_desktop = 0;
6472 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6473 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6475 info->mso_stream_count = 0;
6476 info->mso_pixel_overlap = 0;
6477 info->max_dsc_bpp = 0;
6485 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6488 static void update_displayid_info(struct drm_connector *connector,
6489 const struct drm_edid *drm_edid)
6491 struct drm_display_info *info = &connector->display_info;
6492 const struct displayid_block *block;
6493 struct displayid_iter iter;
6495 displayid_iter_edid_begin(drm_edid, &iter);
6496 displayid_iter_for_each(block, &iter) {
6497 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6498 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6499 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6500 info->non_desktop = true;
6503 * We're only interested in the base section here, no need to
6508 displayid_iter_end(&iter);
6511 static void update_display_info(struct drm_connector *connector,
6512 const struct drm_edid *drm_edid)
6514 struct drm_display_info *info = &connector->display_info;
6515 const struct edid *edid;
6517 drm_reset_display_info(connector);
6518 clear_eld(connector);
6523 edid = drm_edid->edid;
6525 info->quirks = edid_get_quirks(drm_edid);
6527 info->width_mm = edid->width_cm * 10;
6528 info->height_mm = edid->height_cm * 10;
6530 drm_get_monitor_range(connector, drm_edid);
6532 if (edid->revision < 3)
6535 if (!drm_edid_is_digital(drm_edid))
6538 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6539 drm_parse_cea_ext(connector, drm_edid);
6541 update_displayid_info(connector, drm_edid);
6544 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6546 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6547 * tells us to assume 8 bpc color depth if the EDID doesn't have
6548 * extensions which tell otherwise.
6550 if (info->bpc == 0 && edid->revision == 3 &&
6551 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6553 drm_dbg_kms(connector->dev,
6554 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6555 connector->base.id, connector->name, info->bpc);
6558 /* Only defined for 1.4 with digital displays */
6559 if (edid->revision < 4)
6562 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6563 case DRM_EDID_DIGITAL_DEPTH_6:
6566 case DRM_EDID_DIGITAL_DEPTH_8:
6569 case DRM_EDID_DIGITAL_DEPTH_10:
6572 case DRM_EDID_DIGITAL_DEPTH_12:
6575 case DRM_EDID_DIGITAL_DEPTH_14:
6578 case DRM_EDID_DIGITAL_DEPTH_16:
6581 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6587 drm_dbg_kms(connector->dev,
6588 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6589 connector->base.id, connector->name, info->bpc);
6591 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6592 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6593 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6594 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6596 drm_update_mso(connector, drm_edid);
6599 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6600 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6601 connector->base.id, connector->name,
6602 info->non_desktop ? " (redundant quirk)" : "");
6603 info->non_desktop = true;
6606 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6607 info->max_dsc_bpp = 15;
6609 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6612 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6615 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6618 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6621 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6622 drm_edid_to_eld(connector, drm_edid);
6625 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6626 struct displayid_detailed_timings_1 *timings,
6629 struct drm_display_mode *mode;
6630 unsigned pixel_clock = (timings->pixel_clock[0] |
6631 (timings->pixel_clock[1] << 8) |
6632 (timings->pixel_clock[2] << 16)) + 1;
6633 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6634 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6635 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6636 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6637 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6638 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6639 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6640 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6641 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6642 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6644 mode = drm_mode_create(dev);
6648 /* resolution is kHz for type VII, and 10 kHz for type I */
6649 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6650 mode->hdisplay = hactive;
6651 mode->hsync_start = mode->hdisplay + hsync;
6652 mode->hsync_end = mode->hsync_start + hsync_width;
6653 mode->htotal = mode->hdisplay + hblank;
6655 mode->vdisplay = vactive;
6656 mode->vsync_start = mode->vdisplay + vsync;
6657 mode->vsync_end = mode->vsync_start + vsync_width;
6658 mode->vtotal = mode->vdisplay + vblank;
6661 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6662 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6663 mode->type = DRM_MODE_TYPE_DRIVER;
6665 if (timings->flags & 0x80)
6666 mode->type |= DRM_MODE_TYPE_PREFERRED;
6667 drm_mode_set_name(mode);
6672 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6673 const struct displayid_block *block)
6675 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6678 struct drm_display_mode *newmode;
6680 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6681 /* blocks must be multiple of 20 bytes length */
6682 if (block->num_bytes % 20)
6685 num_timings = block->num_bytes / 20;
6686 for (i = 0; i < num_timings; i++) {
6687 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6689 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6693 drm_mode_probed_add(connector, newmode);
6699 static int add_displayid_detailed_modes(struct drm_connector *connector,
6700 const struct drm_edid *drm_edid)
6702 const struct displayid_block *block;
6703 struct displayid_iter iter;
6706 displayid_iter_edid_begin(drm_edid, &iter);
6707 displayid_iter_for_each(block, &iter) {
6708 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6709 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6710 num_modes += add_displayid_detailed_1_modes(connector, block);
6712 displayid_iter_end(&iter);
6717 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6718 const struct drm_edid *drm_edid)
6720 const struct drm_display_info *info = &connector->display_info;
6727 * EDID spec says modes should be preferred in this order:
6728 * - preferred detailed mode
6729 * - other detailed modes from base block
6730 * - detailed modes from extension blocks
6731 * - CVT 3-byte code modes
6732 * - standard timing codes
6733 * - established timing codes
6734 * - modes inferred from GTF or CVT range information
6736 * We get this pretty much right.
6738 * XXX order for additional mode types in extension blocks?
6740 num_modes += add_detailed_modes(connector, drm_edid);
6741 num_modes += add_cvt_modes(connector, drm_edid);
6742 num_modes += add_standard_modes(connector, drm_edid);
6743 num_modes += add_established_modes(connector, drm_edid);
6744 num_modes += add_cea_modes(connector, drm_edid);
6745 num_modes += add_alternate_cea_modes(connector, drm_edid);
6746 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6747 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6748 num_modes += add_inferred_modes(connector, drm_edid);
6750 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6751 edid_fixup_preferred(connector);
6756 static void _drm_update_tile_info(struct drm_connector *connector,
6757 const struct drm_edid *drm_edid);
6759 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6760 const struct drm_edid *drm_edid)
6762 struct drm_device *dev = connector->dev;
6765 if (connector->edid_blob_ptr) {
6766 const struct edid *old_edid = connector->edid_blob_ptr->data;
6769 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6770 connector->epoch_counter++;
6771 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6772 connector->base.id, connector->name,
6773 connector->epoch_counter);
6778 ret = drm_property_replace_global_blob(dev,
6779 &connector->edid_blob_ptr,
6780 drm_edid ? drm_edid->size : 0,
6781 drm_edid ? drm_edid->edid : NULL,
6783 dev->mode_config.edid_property);
6785 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6786 connector->base.id, connector->name, ret);
6790 ret = drm_object_property_set_value(&connector->base,
6791 dev->mode_config.non_desktop_property,
6792 connector->display_info.non_desktop);
6794 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6795 connector->base.id, connector->name, ret);
6799 ret = drm_connector_set_tile_property(connector);
6801 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6802 connector->base.id, connector->name, ret);
6811 * drm_edid_connector_update - Update connector information from EDID
6812 * @connector: Connector
6815 * Update the connector display info, ELD, HDR metadata, relevant properties,
6816 * etc. from the passed in EDID.
6818 * If EDID is NULL, reset the information.
6820 * Must be called before calling drm_edid_connector_add_modes().
6822 * Return: 0 on success, negative error on errors.
6824 int drm_edid_connector_update(struct drm_connector *connector,
6825 const struct drm_edid *drm_edid)
6827 update_display_info(connector, drm_edid);
6829 _drm_update_tile_info(connector, drm_edid);
6831 return _drm_edid_connector_property_update(connector, drm_edid);
6833 EXPORT_SYMBOL(drm_edid_connector_update);
6836 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6837 * @connector: Connector
6839 * Add the modes from the previously updated EDID property to the connector
6840 * probed modes list.
6842 * drm_edid_connector_update() must have been called before this to update the
6845 * Return: The number of modes added, or 0 if we couldn't find any.
6847 int drm_edid_connector_add_modes(struct drm_connector *connector)
6849 const struct drm_edid *drm_edid = NULL;
6852 if (connector->edid_blob_ptr)
6853 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6854 connector->edid_blob_ptr->length);
6856 count = _drm_edid_connector_add_modes(connector, drm_edid);
6858 drm_edid_free(drm_edid);
6862 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6865 * drm_connector_update_edid_property - update the edid property of a connector
6866 * @connector: drm connector
6867 * @edid: new value of the edid property
6869 * This function creates a new blob modeset object and assigns its id to the
6870 * connector's edid property.
6871 * Since we also parse tile information from EDID's displayID block, we also
6872 * set the connector's tile property here. See drm_connector_set_tile_property()
6875 * This function is deprecated. Use drm_edid_connector_update() instead.
6878 * Zero on success, negative errno on failure.
6880 int drm_connector_update_edid_property(struct drm_connector *connector,
6881 const struct edid *edid)
6883 struct drm_edid drm_edid;
6885 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6887 EXPORT_SYMBOL(drm_connector_update_edid_property);
6890 * drm_add_edid_modes - add modes from EDID data, if available
6891 * @connector: connector we're probing
6894 * Add the specified modes to the connector's mode list. Also fills out the
6895 * &drm_display_info structure and ELD in @connector with any information which
6896 * can be derived from the edid.
6898 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6900 * Return: The number of modes added or 0 if we couldn't find any.
6902 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6904 struct drm_edid _drm_edid;
6905 const struct drm_edid *drm_edid;
6907 if (edid && !drm_edid_is_valid(edid)) {
6908 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6909 connector->base.id, connector->name);
6913 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6915 update_display_info(connector, drm_edid);
6917 return _drm_edid_connector_add_modes(connector, drm_edid);
6919 EXPORT_SYMBOL(drm_add_edid_modes);
6922 * drm_add_modes_noedid - add modes for the connectors without EDID
6923 * @connector: connector we're probing
6924 * @hdisplay: the horizontal display limit
6925 * @vdisplay: the vertical display limit
6927 * Add the specified modes to the connector's mode list. Only when the
6928 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6930 * Return: The number of modes added or 0 if we couldn't find any.
6932 int drm_add_modes_noedid(struct drm_connector *connector,
6933 int hdisplay, int vdisplay)
6935 int i, count, num_modes = 0;
6936 struct drm_display_mode *mode;
6937 struct drm_device *dev = connector->dev;
6939 count = ARRAY_SIZE(drm_dmt_modes);
6945 for (i = 0; i < count; i++) {
6946 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6948 if (hdisplay && vdisplay) {
6950 * Only when two are valid, they will be used to check
6951 * whether the mode should be added to the mode list of
6954 if (ptr->hdisplay > hdisplay ||
6955 ptr->vdisplay > vdisplay)
6958 if (drm_mode_vrefresh(ptr) > 61)
6960 mode = drm_mode_duplicate(dev, ptr);
6962 drm_mode_probed_add(connector, mode);
6968 EXPORT_SYMBOL(drm_add_modes_noedid);
6971 * drm_set_preferred_mode - Sets the preferred mode of a connector
6972 * @connector: connector whose mode list should be processed
6973 * @hpref: horizontal resolution of preferred mode
6974 * @vpref: vertical resolution of preferred mode
6976 * Marks a mode as preferred if it matches the resolution specified by @hpref
6979 void drm_set_preferred_mode(struct drm_connector *connector,
6980 int hpref, int vpref)
6982 struct drm_display_mode *mode;
6984 list_for_each_entry(mode, &connector->probed_modes, head) {
6985 if (mode->hdisplay == hpref &&
6986 mode->vdisplay == vpref)
6987 mode->type |= DRM_MODE_TYPE_PREFERRED;
6990 EXPORT_SYMBOL(drm_set_preferred_mode);
6992 static bool is_hdmi2_sink(const struct drm_connector *connector)
6995 * FIXME: sil-sii8620 doesn't have a connector around when
6996 * we need one, so we have to be prepared for a NULL connector.
7001 return connector->display_info.hdmi.scdc.supported ||
7002 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7005 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7006 const struct drm_display_mode *mode)
7008 bool has_hdmi_infoframe = connector ?
7009 connector->display_info.has_hdmi_infoframe : false;
7011 if (!has_hdmi_infoframe)
7014 /* No HDMI VIC when signalling 3D video format */
7015 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7018 return drm_match_hdmi_mode(mode);
7021 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7022 const struct drm_display_mode *mode)
7025 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7026 * we should send its VIC in vendor infoframes, else send the
7027 * VIC in AVI infoframes. Lets check if this mode is present in
7028 * HDMI 1.4b 4K modes
7030 if (drm_mode_hdmi_vic(connector, mode))
7033 return drm_match_cea_mode(mode);
7037 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7038 * conform to HDMI 1.4.
7040 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7041 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7043 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7046 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7048 if (!is_hdmi2_sink(connector) && vic > 64 &&
7049 !cta_vdb_has_vic(connector, vic))
7056 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7057 * data from a DRM display mode
7058 * @frame: HDMI AVI infoframe
7059 * @connector: the connector
7060 * @mode: DRM display mode
7062 * Return: 0 on success or a negative error code on failure.
7065 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7066 const struct drm_connector *connector,
7067 const struct drm_display_mode *mode)
7069 enum hdmi_picture_aspect picture_aspect;
7072 if (!frame || !mode)
7075 hdmi_avi_infoframe_init(frame);
7077 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7078 frame->pixel_repeat = 1;
7080 vic = drm_mode_cea_vic(connector, mode);
7081 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7083 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7086 * As some drivers don't support atomic, we can't use connector state.
7087 * So just initialize the frame with default values, just the same way
7088 * as it's done with other properties here.
7090 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7094 * Populate picture aspect ratio from either
7095 * user input (if specified) or from the CEA/HDMI mode lists.
7097 picture_aspect = mode->picture_aspect_ratio;
7098 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7100 picture_aspect = drm_get_cea_aspect_ratio(vic);
7102 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7106 * The infoframe can't convey anything but none, 4:3
7107 * and 16:9, so if the user has asked for anything else
7108 * we can only satisfy it by specifying the right VIC.
7110 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7112 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7114 } else if (hdmi_vic) {
7115 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7121 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7124 frame->video_code = vic_for_avi_infoframe(connector, vic);
7125 frame->picture_aspect = picture_aspect;
7126 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7127 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7131 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7134 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7135 * quantization range information
7136 * @frame: HDMI AVI infoframe
7137 * @connector: the connector
7138 * @mode: DRM display mode
7139 * @rgb_quant_range: RGB quantization range (Q)
7142 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7143 const struct drm_connector *connector,
7144 const struct drm_display_mode *mode,
7145 enum hdmi_quantization_range rgb_quant_range)
7147 const struct drm_display_info *info = &connector->display_info;
7151 * "A Source shall not send a non-zero Q value that does not correspond
7152 * to the default RGB Quantization Range for the transmitted Picture
7153 * unless the Sink indicates support for the Q bit in a Video
7154 * Capabilities Data Block."
7156 * HDMI 2.0 recommends sending non-zero Q when it does match the
7157 * default RGB quantization range for the mode, even when QS=0.
7159 if (info->rgb_quant_range_selectable ||
7160 rgb_quant_range == drm_default_rgb_quant_range(mode))
7161 frame->quantization_range = rgb_quant_range;
7163 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7167 * "When transmitting any RGB colorimetry, the Source should set the
7168 * YQ-field to match the RGB Quantization Range being transmitted
7169 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7170 * set YQ=1) and the Sink shall ignore the YQ-field."
7172 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7173 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7174 * good way to tell which version of CEA-861 the sink supports, so
7175 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7178 if (!is_hdmi2_sink(connector) ||
7179 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7180 frame->ycc_quantization_range =
7181 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7183 frame->ycc_quantization_range =
7184 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7186 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7188 static enum hdmi_3d_structure
7189 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7191 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7194 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7195 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7196 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7197 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7198 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7199 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7200 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7201 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7202 case DRM_MODE_FLAG_3D_L_DEPTH:
7203 return HDMI_3D_STRUCTURE_L_DEPTH;
7204 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7205 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7206 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7207 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7208 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7209 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7211 return HDMI_3D_STRUCTURE_INVALID;
7216 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7217 * data from a DRM display mode
7218 * @frame: HDMI vendor infoframe
7219 * @connector: the connector
7220 * @mode: DRM display mode
7222 * Note that there's is a need to send HDMI vendor infoframes only when using a
7223 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7224 * function will return -EINVAL, error that can be safely ignored.
7226 * Return: 0 on success or a negative error code on failure.
7229 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7230 const struct drm_connector *connector,
7231 const struct drm_display_mode *mode)
7234 * FIXME: sil-sii8620 doesn't have a connector around when
7235 * we need one, so we have to be prepared for a NULL connector.
7237 bool has_hdmi_infoframe = connector ?
7238 connector->display_info.has_hdmi_infoframe : false;
7241 if (!frame || !mode)
7244 if (!has_hdmi_infoframe)
7247 err = hdmi_vendor_infoframe_init(frame);
7252 * Even if it's not absolutely necessary to send the infoframe
7253 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7254 * know that the sink can handle it. This is based on a
7255 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7256 * have trouble realizing that they should switch from 3D to 2D
7257 * mode if the source simply stops sending the infoframe when
7258 * it wants to switch from 3D to 2D.
7260 frame->vic = drm_mode_hdmi_vic(connector, mode);
7261 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7265 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7267 static void drm_parse_tiled_block(struct drm_connector *connector,
7268 const struct displayid_block *block)
7270 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7272 u8 tile_v_loc, tile_h_loc;
7273 u8 num_v_tile, num_h_tile;
7274 struct drm_tile_group *tg;
7276 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7277 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7279 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7280 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7281 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7282 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7284 connector->has_tile = true;
7285 if (tile->tile_cap & 0x80)
7286 connector->tile_is_single_monitor = true;
7288 connector->num_h_tile = num_h_tile + 1;
7289 connector->num_v_tile = num_v_tile + 1;
7290 connector->tile_h_loc = tile_h_loc;
7291 connector->tile_v_loc = tile_v_loc;
7292 connector->tile_h_size = w + 1;
7293 connector->tile_v_size = h + 1;
7295 drm_dbg_kms(connector->dev,
7296 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7297 connector->base.id, connector->name,
7299 connector->tile_h_size, connector->tile_v_size,
7300 connector->num_h_tile, connector->num_v_tile,
7301 connector->tile_h_loc, connector->tile_v_loc,
7302 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7304 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7306 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7310 if (connector->tile_group != tg) {
7311 /* if we haven't got a pointer,
7312 take the reference, drop ref to old tile group */
7313 if (connector->tile_group)
7314 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7315 connector->tile_group = tg;
7317 /* if same tile group, then release the ref we just took. */
7318 drm_mode_put_tile_group(connector->dev, tg);
7322 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7323 const struct displayid_block *block)
7325 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7326 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7327 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7328 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7331 static void _drm_update_tile_info(struct drm_connector *connector,
7332 const struct drm_edid *drm_edid)
7334 const struct displayid_block *block;
7335 struct displayid_iter iter;
7337 connector->has_tile = false;
7339 displayid_iter_edid_begin(drm_edid, &iter);
7340 displayid_iter_for_each(block, &iter) {
7341 if (displayid_is_tiled_block(&iter, block))
7342 drm_parse_tiled_block(connector, block);
7344 displayid_iter_end(&iter);
7346 if (!connector->has_tile && connector->tile_group) {
7347 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7348 connector->tile_group = NULL;
7353 * drm_edid_is_digital - is digital?
7354 * @drm_edid: The EDID
7356 * Return true if input is digital.
7358 bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7360 return drm_edid && drm_edid->edid &&
7361 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7363 EXPORT_SYMBOL(drm_edid_is_digital);
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