drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* Compliance test status bits  */
  48 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  49 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52
  53 struct dp_link_dpll {
  54         int clock;
  55         struct dpll dpll;
  56 };
  57
  58 static const struct dp_link_dpll gen4_dpll[] = {
  59         { 162000,
  60                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  61         { 270000,
  62                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  63 };
  64
  65 static const struct dp_link_dpll pch_dpll[] = {
  66         { 162000,
  67                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  68         { 270000,
  69                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  70 };
  71
  72 static const struct dp_link_dpll vlv_dpll[] = {
  73         { 162000,
  74                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  75         { 270000,
  76                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  77 };
  78
  79 /*
  80  * CHV supports eDP 1.4 that have  more link rates.
  81  * Below only provides the fixed rate but exclude variable rate.
  82  */
  83 static const struct dp_link_dpll chv_dpll[] = {
  84         /*
  85          * CHV requires to program fractional division for m2.
  86          * m2 is stored in fixed point format using formula below
  87          * (m2_int << 22) | m2_fraction
  88          */
  89         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  90                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  91         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  92                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  93         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  95 };
  96
  97 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  98                                   324000, 432000, 540000 };
  99 static const int skl_rates[] = { 162000, 216000, 270000,
 100                                   324000, 432000, 540000 };
 101 static const int cnl_rates[] = { 162000, 216000, 270000,
 102                                  324000, 432000, 540000,
 103                                  648000, 810000 };
 104 static const int default_rates[] = { 162000, 270000, 540000 };
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  */
 113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 116
 117         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 118 }
 119
 120 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 121 {
 122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 123
 124         return intel_dig_port->base.base.dev;
 125 }
 126
 127 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 128 {
 129         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 130 }
 131
 132 static void intel_dp_link_down(struct intel_dp *intel_dp);
 133 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 134 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 135 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 136 static void vlv_steal_power_sequencer(struct drm_device *dev,
 137                                       enum pipe pipe);
 138 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 139
 140 /* update sink rates from dpcd */
 141 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 142 {
 143         int i, max_rate;
 144
 145         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 146
 147         for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
 148                 if (default_rates[i] > max_rate)
 149                         break;
 150                 intel_dp->sink_rates[i] = default_rates[i];
 151         }
 152
 153         intel_dp->num_sink_rates = i;
 154 }
 155
 156 /* Theoretical max between source and sink */
 157 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 158 {
 159         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 160 }
 161
 162 /* Theoretical max between source and sink */
 163 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 164 {
 165         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 166         int source_max = intel_dig_port->max_lanes;
 167         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 168
 169         return min(source_max, sink_max);
 170 }
 171
 172 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 173 {
 174         return intel_dp->max_link_lane_count;
 175 }
 176
 177 int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 181         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 182 }
 183
 184 int
 185 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 186 {
 187         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 188          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 189          * is transmitted every LS_Clk per lane, there is no need to account for
 190          * the channel encoding that is done in the PHY layer here.
 191          */
 192
 193         return max_link_clock * max_lanes;
 194 }
 195
 196 static int
 197 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 198 {
 199         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 200         struct intel_encoder *encoder = &intel_dig_port->base;
 201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 202         int max_dotclk = dev_priv->max_dotclk_freq;
 203         int ds_max_dotclk;
 204
 205         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 206
 207         if (type != DP_DS_PORT_TYPE_VGA)
 208                 return max_dotclk;
 209
 210         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 211                                                     intel_dp->downstream_ports);
 212
 213         if (ds_max_dotclk != 0)
 214                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 215
 216         return max_dotclk;
 217 }
 218
 219 static void
 220 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 221 {
 222         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 223         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 224         enum port port = dig_port->port;
 225         const int *source_rates;
 226         int size;
 227         u32 voltage;
 228
 229         /* This should only be done once */
 230         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 231
 232         if (IS_GEN9_LP(dev_priv)) {
 233                 source_rates = bxt_rates;
 234                 size = ARRAY_SIZE(bxt_rates);
 235         } else if (IS_CANNONLAKE(dev_priv)) {
 236                 source_rates = cnl_rates;
 237                 size = ARRAY_SIZE(cnl_rates);
 238                 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 239                 if (port == PORT_A || port == PORT_D ||
 240                     voltage == VOLTAGE_INFO_0_85V)
 241                         size -= 2;
 242         } else if (IS_GEN9_BC(dev_priv)) {
 243                 source_rates = skl_rates;
 244                 size = ARRAY_SIZE(skl_rates);
 245         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 246                    IS_BROADWELL(dev_priv)) {
 247                 source_rates = default_rates;
 248                 size = ARRAY_SIZE(default_rates);
 249         } else {
 250                 source_rates = default_rates;
 251                 size = ARRAY_SIZE(default_rates) - 1;
 252         }
 253
 254         intel_dp->source_rates = source_rates;
 255         intel_dp->num_source_rates = size;
 256 }
 257
 258 static int intersect_rates(const int *source_rates, int source_len,
 259                            const int *sink_rates, int sink_len,
 260                            int *common_rates)
 261 {
 262         int i = 0, j = 0, k = 0;
 263
 264         while (i < source_len && j < sink_len) {
 265                 if (source_rates[i] == sink_rates[j]) {
 266                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 267                                 return k;
 268                         common_rates[k] = source_rates[i];
 269                         ++k;
 270                         ++i;
 271                         ++j;
 272                 } else if (source_rates[i] < sink_rates[j]) {
 273                         ++i;
 274                 } else {
 275                         ++j;
 276                 }
 277         }
 278         return k;
 279 }
 280
 281 /* return index of rate in rates array, or -1 if not found */
 282 static int intel_dp_rate_index(const int *rates, int len, int rate)
 283 {
 284         int i;
 285
 286         for (i = 0; i < len; i++)
 287                 if (rate == rates[i])
 288                         return i;
 289
 290         return -1;
 291 }
 292
 293 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 294 {
 295         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 296
 297         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 298                                                      intel_dp->num_source_rates,
 299                                                      intel_dp->sink_rates,
 300                                                      intel_dp->num_sink_rates,
 301                                                      intel_dp->common_rates);
 302
 303         /* Paranoia, there should always be something in common. */
 304         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 305                 intel_dp->common_rates[0] = default_rates[0];
 306                 intel_dp->num_common_rates = 1;
 307         }
 308 }
 309
 310 /* get length of common rates potentially limited by max_rate */
 311 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 312                                           int max_rate)
 313 {
 314         const int *common_rates = intel_dp->common_rates;
 315         int i, common_len = intel_dp->num_common_rates;
 316
 317         /* Limit results by potentially reduced max rate */
 318         for (i = 0; i < common_len; i++) {
 319                 if (common_rates[common_len - i - 1] <= max_rate)
 320                         return common_len - i;
 321         }
 322
 323         return 0;
 324 }
 325
 326 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 327                                        uint8_t lane_count)
 328 {
 329         /*
 330          * FIXME: we need to synchronize the current link parameters with
 331          * hardware readout. Currently fast link training doesn't work on
 332          * boot-up.
 333          */
 334         if (link_rate == 0 ||
 335             link_rate > intel_dp->max_link_rate)
 336                 return false;
 337
 338         if (lane_count == 0 ||
 339             lane_count > intel_dp_max_lane_count(intel_dp))
 340                 return false;
 341
 342         return true;
 343 }
 344
 345 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 346                                             int link_rate, uint8_t lane_count)
 347 {
 348         int index;
 349
 350         index = intel_dp_rate_index(intel_dp->common_rates,
 351                                     intel_dp->num_common_rates,
 352                                     link_rate);
 353         if (index > 0) {
 354                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 355                 intel_dp->max_link_lane_count = lane_count;
 356         } else if (lane_count > 1) {
 357                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 358                 intel_dp->max_link_lane_count = lane_count >> 1;
 359         } else {
 360                 DRM_ERROR("Link Training Unsuccessful\n");
 361                 return -1;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static enum drm_mode_status
 368 intel_dp_mode_valid(struct drm_connector *connector,
 369                     struct drm_display_mode *mode)
 370 {
 371         struct intel_dp *intel_dp = intel_attached_dp(connector);
 372         struct intel_connector *intel_connector = to_intel_connector(connector);
 373         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 374         int target_clock = mode->clock;
 375         int max_rate, mode_rate, max_lanes, max_link_clock;
 376         int max_dotclk;
 377
 378         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 379
 380         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 381                 if (mode->hdisplay > fixed_mode->hdisplay)
 382                         return MODE_PANEL;
 383
 384                 if (mode->vdisplay > fixed_mode->vdisplay)
 385                         return MODE_PANEL;
 386
 387                 target_clock = fixed_mode->clock;
 388         }
 389
 390         max_link_clock = intel_dp_max_link_rate(intel_dp);
 391         max_lanes = intel_dp_max_lane_count(intel_dp);
 392
 393         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 394         mode_rate = intel_dp_link_required(target_clock, 18);
 395
 396         if (mode_rate > max_rate || target_clock > max_dotclk)
 397                 return MODE_CLOCK_HIGH;
 398
 399         if (mode->clock < 10000)
 400                 return MODE_CLOCK_LOW;
 401
 402         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 403                 return MODE_H_ILLEGAL;
 404
 405         return MODE_OK;
 406 }
 407
 408 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 409 {
 410         int     i;
 411         uint32_t v = 0;
 412
 413         if (src_bytes > 4)
 414                 src_bytes = 4;
 415         for (i = 0; i < src_bytes; i++)
 416                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 417         return v;
 418 }
 419
 420 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 421 {
 422         int i;
 423         if (dst_bytes > 4)
 424                 dst_bytes = 4;
 425         for (i = 0; i < dst_bytes; i++)
 426                 dst[i] = src >> ((3-i) * 8);
 427 }
 428
 429 static void
 430 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 431                                     struct intel_dp *intel_dp);
 432 static void
 433 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 434                                               struct intel_dp *intel_dp,
 435                                               bool force_disable_vdd);
 436 static void
 437 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 438
 439 static void pps_lock(struct intel_dp *intel_dp)
 440 {
 441         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 442         struct intel_encoder *encoder = &intel_dig_port->base;
 443         struct drm_device *dev = encoder->base.dev;
 444         struct drm_i915_private *dev_priv = to_i915(dev);
 445
 446         /*
 447          * See vlv_power_sequencer_reset() why we need
 448          * a power domain reference here.
 449          */
 450         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 451
 452         mutex_lock(&dev_priv->pps_mutex);
 453 }
 454
 455 static void pps_unlock(struct intel_dp *intel_dp)
 456 {
 457         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 458         struct intel_encoder *encoder = &intel_dig_port->base;
 459         struct drm_device *dev = encoder->base.dev;
 460         struct drm_i915_private *dev_priv = to_i915(dev);
 461
 462         mutex_unlock(&dev_priv->pps_mutex);
 463
 464         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 465 }
 466
 467 static void
 468 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 469 {
 470         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 471         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 472         enum pipe pipe = intel_dp->pps_pipe;
 473         bool pll_enabled, release_cl_override = false;
 474         enum dpio_phy phy = DPIO_PHY(pipe);
 475         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 476         uint32_t DP;
 477
 478         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 479                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 480                  pipe_name(pipe), port_name(intel_dig_port->port)))
 481                 return;
 482
 483         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 484                       pipe_name(pipe), port_name(intel_dig_port->port));
 485
 486         /* Preserve the BIOS-computed detected bit. This is
 487          * supposed to be read-only.
 488          */
 489         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 490         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 491         DP |= DP_PORT_WIDTH(1);
 492         DP |= DP_LINK_TRAIN_PAT_1;
 493
 494         if (IS_CHERRYVIEW(dev_priv))
 495                 DP |= DP_PIPE_SELECT_CHV(pipe);
 496         else if (pipe == PIPE_B)
 497                 DP |= DP_PIPEB_SELECT;
 498
 499         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 500
 501         /*
 502          * The DPLL for the pipe must be enabled for this to work.
 503          * So enable temporarily it if it's not already enabled.
 504          */
 505         if (!pll_enabled) {
 506                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 507                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 508
 509                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 510                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 511                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 512                                   pipe_name(pipe));
 513                         return;
 514                 }
 515         }
 516
 517         /*
 518          * Similar magic as in intel_dp_enable_port().
 519          * We _must_ do this port enable + disable trick
 520          * to make this power seqeuencer lock onto the port.
 521          * Otherwise even VDD force bit won't work.
 522          */
 523         I915_WRITE(intel_dp->output_reg, DP);
 524         POSTING_READ(intel_dp->output_reg);
 525
 526         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 527         POSTING_READ(intel_dp->output_reg);
 528
 529         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 530         POSTING_READ(intel_dp->output_reg);
 531
 532         if (!pll_enabled) {
 533                 vlv_force_pll_off(dev_priv, pipe);
 534
 535                 if (release_cl_override)
 536                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 537         }
 538 }
 539
 540 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 541 {
 542         struct intel_encoder *encoder;
 543         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 544
 545         /*
 546          * We don't have power sequencer currently.
 547          * Pick one that's not used by other ports.
 548          */
 549         for_each_intel_encoder(&dev_priv->drm, encoder) {
 550                 struct intel_dp *intel_dp;
 551
 552                 if (encoder->type != INTEL_OUTPUT_DP &&
 553                     encoder->type != INTEL_OUTPUT_EDP)
 554                         continue;
 555
 556                 intel_dp = enc_to_intel_dp(&encoder->base);
 557
 558                 if (encoder->type == INTEL_OUTPUT_EDP) {
 559                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 560                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 561
 562                         if (intel_dp->pps_pipe != INVALID_PIPE)
 563                                 pipes &= ~(1 << intel_dp->pps_pipe);
 564                 } else {
 565                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 566
 567                         if (intel_dp->active_pipe != INVALID_PIPE)
 568                                 pipes &= ~(1 << intel_dp->active_pipe);
 569                 }
 570         }
 571
 572         if (pipes == 0)
 573                 return INVALID_PIPE;
 574
 575         return ffs(pipes) - 1;
 576 }
 577
 578 static enum pipe
 579 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 580 {
 581         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 582         struct drm_device *dev = intel_dig_port->base.base.dev;
 583         struct drm_i915_private *dev_priv = to_i915(dev);
 584         enum pipe pipe;
 585
 586         lockdep_assert_held(&dev_priv->pps_mutex);
 587
 588         /* We should never land here with regular DP ports */
 589         WARN_ON(!intel_dp_is_edp(intel_dp));
 590
 591         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 592                 intel_dp->active_pipe != intel_dp->pps_pipe);
 593
 594         if (intel_dp->pps_pipe != INVALID_PIPE)
 595                 return intel_dp->pps_pipe;
 596
 597         pipe = vlv_find_free_pps(dev_priv);
 598
 599         /*
 600          * Didn't find one. This should not happen since there
 601          * are two power sequencers and up to two eDP ports.
 602          */
 603         if (WARN_ON(pipe == INVALID_PIPE))
 604                 pipe = PIPE_A;
 605
 606         vlv_steal_power_sequencer(dev, pipe);
 607         intel_dp->pps_pipe = pipe;
 608
 609         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 610                       pipe_name(intel_dp->pps_pipe),
 611                       port_name(intel_dig_port->port));
 612
 613         /* init power sequencer on this pipe and port */
 614         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 615         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 616
 617         /*
 618          * Even vdd force doesn't work until we've made
 619          * the power sequencer lock in on the port.
 620          */
 621         vlv_power_sequencer_kick(intel_dp);
 622
 623         return intel_dp->pps_pipe;
 624 }
 625
 626 static int
 627 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 628 {
 629         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 630         struct drm_device *dev = intel_dig_port->base.base.dev;
 631         struct drm_i915_private *dev_priv = to_i915(dev);
 632
 633         lockdep_assert_held(&dev_priv->pps_mutex);
 634
 635         /* We should never land here with regular DP ports */
 636         WARN_ON(!intel_dp_is_edp(intel_dp));
 637
 638         /*
 639          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 640          * mapping needs to be retrieved from VBT, for now just hard-code to
 641          * use instance #0 always.
 642          */
 643         if (!intel_dp->pps_reset)
 644                 return 0;
 645
 646         intel_dp->pps_reset = false;
 647
 648         /*
 649          * Only the HW needs to be reprogrammed, the SW state is fixed and
 650          * has been setup during connector init.
 651          */
 652         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 653
 654         return 0;
 655 }
 656
 657 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 658                                enum pipe pipe);
 659
 660 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 661                                enum pipe pipe)
 662 {
 663         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 664 }
 665
 666 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 667                                 enum pipe pipe)
 668 {
 669         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 670 }
 671
 672 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 673                          enum pipe pipe)
 674 {
 675         return true;
 676 }
 677
 678 static enum pipe
 679 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 680                      enum port port,
 681                      vlv_pipe_check pipe_check)
 682 {
 683         enum pipe pipe;
 684
 685         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 686                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 687                         PANEL_PORT_SELECT_MASK;
 688
 689                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 690                         continue;
 691
 692                 if (!pipe_check(dev_priv, pipe))
 693                         continue;
 694
 695                 return pipe;
 696         }
 697
 698         return INVALID_PIPE;
 699 }
 700
 701 static void
 702 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 703 {
 704         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 705         struct drm_device *dev = intel_dig_port->base.base.dev;
 706         struct drm_i915_private *dev_priv = to_i915(dev);
 707         enum port port = intel_dig_port->port;
 708
 709         lockdep_assert_held(&dev_priv->pps_mutex);
 710
 711         /* try to find a pipe with this port selected */
 712         /* first pick one where the panel is on */
 713         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 714                                                   vlv_pipe_has_pp_on);
 715         /* didn't find one? pick one where vdd is on */
 716         if (intel_dp->pps_pipe == INVALID_PIPE)
 717                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 718                                                           vlv_pipe_has_vdd_on);
 719         /* didn't find one? pick one with just the correct port */
 720         if (intel_dp->pps_pipe == INVALID_PIPE)
 721                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 722                                                           vlv_pipe_any);
 723
 724         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 725         if (intel_dp->pps_pipe == INVALID_PIPE) {
 726                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 727                               port_name(port));
 728                 return;
 729         }
 730
 731         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 732                       port_name(port), pipe_name(intel_dp->pps_pipe));
 733
 734         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 735         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 736 }
 737
 738 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 739 {
 740         struct drm_device *dev = &dev_priv->drm;
 741         struct intel_encoder *encoder;
 742
 743         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 744                     !IS_GEN9_LP(dev_priv)))
 745                 return;
 746
 747         /*
 748          * We can't grab pps_mutex here due to deadlock with power_domain
 749          * mutex when power_domain functions are called while holding pps_mutex.
 750          * That also means that in order to use pps_pipe the code needs to
 751          * hold both a power domain reference and pps_mutex, and the power domain
 752          * reference get/put must be done while _not_ holding pps_mutex.
 753          * pps_{lock,unlock}() do these steps in the correct order, so one
 754          * should use them always.
 755          */
 756
 757         for_each_intel_encoder(dev, encoder) {
 758                 struct intel_dp *intel_dp;
 759
 760                 if (encoder->type != INTEL_OUTPUT_DP &&
 761                     encoder->type != INTEL_OUTPUT_EDP)
 762                         continue;
 763
 764                 intel_dp = enc_to_intel_dp(&encoder->base);
 765
 766                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 767
 768                 if (encoder->type != INTEL_OUTPUT_EDP)
 769                         continue;
 770
 771                 if (IS_GEN9_LP(dev_priv))
 772                         intel_dp->pps_reset = true;
 773                 else
 774                         intel_dp->pps_pipe = INVALID_PIPE;
 775         }
 776 }
 777
 778 struct pps_registers {
 779         i915_reg_t pp_ctrl;
 780         i915_reg_t pp_stat;
 781         i915_reg_t pp_on;
 782         i915_reg_t pp_off;
 783         i915_reg_t pp_div;
 784 };
 785
 786 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 787                                     struct intel_dp *intel_dp,
 788                                     struct pps_registers *regs)
 789 {
 790         int pps_idx = 0;
 791
 792         memset(regs, 0, sizeof(*regs));
 793
 794         if (IS_GEN9_LP(dev_priv))
 795                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 796         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 797                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 798
 799         regs->pp_ctrl = PP_CONTROL(pps_idx);
 800         regs->pp_stat = PP_STATUS(pps_idx);
 801         regs->pp_on = PP_ON_DELAYS(pps_idx);
 802         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 803         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 804                 regs->pp_div = PP_DIVISOR(pps_idx);
 805 }
 806
 807 static i915_reg_t
 808 _pp_ctrl_reg(struct intel_dp *intel_dp)
 809 {
 810         struct pps_registers regs;
 811
 812         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 813                                 &regs);
 814
 815         return regs.pp_ctrl;
 816 }
 817
 818 static i915_reg_t
 819 _pp_stat_reg(struct intel_dp *intel_dp)
 820 {
 821         struct pps_registers regs;
 822
 823         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 824                                 &regs);
 825
 826         return regs.pp_stat;
 827 }
 828
 829 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 830    This function only applicable when panel PM state is not to be tracked */
 831 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 832                               void *unused)
 833 {
 834         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 835                                                  edp_notifier);
 836         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 837         struct drm_i915_private *dev_priv = to_i915(dev);
 838
 839         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 840                 return 0;
 841
 842         pps_lock(intel_dp);
 843
 844         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 845                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 846                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 847                 u32 pp_div;
 848
 849                 pp_ctrl_reg = PP_CONTROL(pipe);
 850                 pp_div_reg  = PP_DIVISOR(pipe);
 851                 pp_div = I915_READ(pp_div_reg);
 852                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 853
 854                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 855                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 856                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 857                 msleep(intel_dp->panel_power_cycle_delay);
 858         }
 859
 860         pps_unlock(intel_dp);
 861
 862         return 0;
 863 }
 864
 865 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 866 {
 867         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 868         struct drm_i915_private *dev_priv = to_i915(dev);
 869
 870         lockdep_assert_held(&dev_priv->pps_mutex);
 871
 872         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 873             intel_dp->pps_pipe == INVALID_PIPE)
 874                 return false;
 875
 876         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 877 }
 878
 879 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 880 {
 881         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 882         struct drm_i915_private *dev_priv = to_i915(dev);
 883
 884         lockdep_assert_held(&dev_priv->pps_mutex);
 885
 886         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 887             intel_dp->pps_pipe == INVALID_PIPE)
 888                 return false;
 889
 890         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 891 }
 892
 893 static void
 894 intel_dp_check_edp(struct intel_dp *intel_dp)
 895 {
 896         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 897         struct drm_i915_private *dev_priv = to_i915(dev);
 898
 899         if (!intel_dp_is_edp(intel_dp))
 900                 return;
 901
 902         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 903                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 904                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 905                               I915_READ(_pp_stat_reg(intel_dp)),
 906                               I915_READ(_pp_ctrl_reg(intel_dp)));
 907         }
 908 }
 909
 910 static uint32_t
 911 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 912 {
 913         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 914         struct drm_device *dev = intel_dig_port->base.base.dev;
 915         struct drm_i915_private *dev_priv = to_i915(dev);
 916         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 917         uint32_t status;
 918         bool done;
 919
 920 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 921         if (has_aux_irq)
 922                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 923                                           msecs_to_jiffies_timeout(10));
 924         else
 925                 done = wait_for(C, 10) == 0;
 926         if (!done)
 927                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 928                           has_aux_irq);
 929 #undef C
 930
 931         return status;
 932 }
 933
 934 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 935 {
 936         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 937         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 938
 939         if (index)
 940                 return 0;
 941
 942         /*
 943          * The clock divider is based off the hrawclk, and would like to run at
 944          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 945          */
 946         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 947 }
 948
 949 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 950 {
 951         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 952         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 953
 954         if (index)
 955                 return 0;
 956
 957         /*
 958          * The clock divider is based off the cdclk or PCH rawclk, and would
 959          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 960          * divide by 2000 and use that
 961          */
 962         if (intel_dig_port->port == PORT_A)
 963                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 964         else
 965                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 966 }
 967
 968 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 969 {
 970         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 971         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 972
 973         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 974                 /* Workaround for non-ULT HSW */
 975                 switch (index) {
 976                 case 0: return 63;
 977                 case 1: return 72;
 978                 default: return 0;
 979                 }
 980         }
 981
 982         return ilk_get_aux_clock_divider(intel_dp, index);
 983 }
 984
 985 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 986 {
 987         /*
 988          * SKL doesn't need us to program the AUX clock divider (Hardware will
 989          * derive the clock from CDCLK automatically). We still implement the
 990          * get_aux_clock_divider vfunc to plug-in into the existing code.
 991          */
 992         return index ? 0 : 1;
 993 }
 994
 995 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 996                                      bool has_aux_irq,
 997                                      int send_bytes,
 998                                      uint32_t aux_clock_divider)
 999 {
1000         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1001         struct drm_i915_private *dev_priv =
1002                         to_i915(intel_dig_port->base.base.dev);
1003         uint32_t precharge, timeout;
1004
1005         if (IS_GEN6(dev_priv))
1006                 precharge = 3;
1007         else
1008                 precharge = 5;
1009
1010         if (IS_BROADWELL(dev_priv))
1011                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1012         else
1013                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1014
1015         return DP_AUX_CH_CTL_SEND_BUSY |
1016                DP_AUX_CH_CTL_DONE |
1017                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1018                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1019                timeout |
1020                DP_AUX_CH_CTL_RECEIVE_ERROR |
1021                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1022                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1023                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1024 }
1025
1026 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1027                                       bool has_aux_irq,
1028                                       int send_bytes,
1029                                       uint32_t unused)
1030 {
1031         return DP_AUX_CH_CTL_SEND_BUSY |
1032                DP_AUX_CH_CTL_DONE |
1033                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1034                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1035                DP_AUX_CH_CTL_TIME_OUT_MAX |
1036                DP_AUX_CH_CTL_RECEIVE_ERROR |
1037                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1038                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1039                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1040 }
1041
1042 static int
1043 intel_dp_aux_ch(struct intel_dp *intel_dp,
1044                 const uint8_t *send, int send_bytes,
1045                 uint8_t *recv, int recv_size)
1046 {
1047         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1048         struct drm_i915_private *dev_priv =
1049                         to_i915(intel_dig_port->base.base.dev);
1050         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1051         uint32_t aux_clock_divider;
1052         int i, ret, recv_bytes;
1053         uint32_t status;
1054         int try, clock = 0;
1055         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1056         bool vdd;
1057
1058         pps_lock(intel_dp);
1059
1060         /*
1061          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1062          * In such cases we want to leave VDD enabled and it's up to upper layers
1063          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1064          * ourselves.
1065          */
1066         vdd = edp_panel_vdd_on(intel_dp);
1067
1068         /* dp aux is extremely sensitive to irq latency, hence request the
1069          * lowest possible wakeup latency and so prevent the cpu from going into
1070          * deep sleep states.
1071          */
1072         pm_qos_update_request(&dev_priv->pm_qos, 0);
1073
1074         intel_dp_check_edp(intel_dp);
1075
1076         /* Try to wait for any previous AUX channel activity */
1077         for (try = 0; try < 3; try++) {
1078                 status = I915_READ_NOTRACE(ch_ctl);
1079                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1080                         break;
1081                 msleep(1);
1082         }
1083
1084         if (try == 3) {
1085                 static u32 last_status = -1;
1086                 const u32 status = I915_READ(ch_ctl);
1087
1088                 if (status != last_status) {
1089                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1090                              status);
1091                         last_status = status;
1092                 }
1093
1094                 ret = -EBUSY;
1095                 goto out;
1096         }
1097
1098         /* Only 5 data registers! */
1099         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1100                 ret = -E2BIG;
1101                 goto out;
1102         }
1103
1104         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1105                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1106                                                           has_aux_irq,
1107                                                           send_bytes,
1108                                                           aux_clock_divider);
1109
1110                 /* Must try at least 3 times according to DP spec */
1111                 for (try = 0; try < 5; try++) {
1112                         /* Load the send data into the aux channel data registers */
1113                         for (i = 0; i < send_bytes; i += 4)
1114                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1115                                            intel_dp_pack_aux(send + i,
1116                                                              send_bytes - i));
1117
1118                         /* Send the command and wait for it to complete */
1119                         I915_WRITE(ch_ctl, send_ctl);
1120
1121                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1122
1123                         /* Clear done status and any errors */
1124                         I915_WRITE(ch_ctl,
1125                                    status |
1126                                    DP_AUX_CH_CTL_DONE |
1127                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1128                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1129
1130                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1131                                 continue;
1132
1133                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1134                          *   400us delay required for errors and timeouts
1135                          *   Timeout errors from the HW already meet this
1136                          *   requirement so skip to next iteration
1137                          */
1138                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1139                                 usleep_range(400, 500);
1140                                 continue;
1141                         }
1142                         if (status & DP_AUX_CH_CTL_DONE)
1143                                 goto done;
1144                 }
1145         }
1146
1147         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1148                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1149                 ret = -EBUSY;
1150                 goto out;
1151         }
1152
1153 done:
1154         /* Check for timeout or receive error.
1155          * Timeouts occur when the sink is not connected
1156          */
1157         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1158                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1159                 ret = -EIO;
1160                 goto out;
1161         }
1162
1163         /* Timeouts occur when the device isn't connected, so they're
1164          * "normal" -- don't fill the kernel log with these */
1165         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1166                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1167                 ret = -ETIMEDOUT;
1168                 goto out;
1169         }
1170
1171         /* Unload any bytes sent back from the other side */
1172         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1173                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1174
1175         /*
1176          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1177          * We have no idea of what happened so we return -EBUSY so
1178          * drm layer takes care for the necessary retries.
1179          */
1180         if (recv_bytes == 0 || recv_bytes > 20) {
1181                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1182                               recv_bytes);
1183                 /*
1184                  * FIXME: This patch was created on top of a series that
1185                  * organize the retries at drm level. There EBUSY should
1186                  * also take care for 1ms wait before retrying.
1187                  * That aux retries re-org is still needed and after that is
1188                  * merged we remove this sleep from here.
1189                  */
1190                 usleep_range(1000, 1500);
1191                 ret = -EBUSY;
1192                 goto out;
1193         }
1194
1195         if (recv_bytes > recv_size)
1196                 recv_bytes = recv_size;
1197
1198         for (i = 0; i < recv_bytes; i += 4)
1199                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1200                                     recv + i, recv_bytes - i);
1201
1202         ret = recv_bytes;
1203 out:
1204         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1205
1206         if (vdd)
1207                 edp_panel_vdd_off(intel_dp, false);
1208
1209         pps_unlock(intel_dp);
1210
1211         return ret;
1212 }
1213
1214 #define BARE_ADDRESS_SIZE       3
1215 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1216 static ssize_t
1217 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1218 {
1219         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1220         uint8_t txbuf[20], rxbuf[20];
1221         size_t txsize, rxsize;
1222         int ret;
1223
1224         txbuf[0] = (msg->request << 4) |
1225                 ((msg->address >> 16) & 0xf);
1226         txbuf[1] = (msg->address >> 8) & 0xff;
1227         txbuf[2] = msg->address & 0xff;
1228         txbuf[3] = msg->size - 1;
1229
1230         switch (msg->request & ~DP_AUX_I2C_MOT) {
1231         case DP_AUX_NATIVE_WRITE:
1232         case DP_AUX_I2C_WRITE:
1233         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1234                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1235                 rxsize = 2; /* 0 or 1 data bytes */
1236
1237                 if (WARN_ON(txsize > 20))
1238                         return -E2BIG;
1239
1240                 WARN_ON(!msg->buffer != !msg->size);
1241
1242                 if (msg->buffer)
1243                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1244
1245                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1246                 if (ret > 0) {
1247                         msg->reply = rxbuf[0] >> 4;
1248
1249                         if (ret > 1) {
1250                                 /* Number of bytes written in a short write. */
1251                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1252                         } else {
1253                                 /* Return payload size. */
1254                                 ret = msg->size;
1255                         }
1256                 }
1257                 break;
1258
1259         case DP_AUX_NATIVE_READ:
1260         case DP_AUX_I2C_READ:
1261                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1262                 rxsize = msg->size + 1;
1263
1264                 if (WARN_ON(rxsize > 20))
1265                         return -E2BIG;
1266
1267                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1268                 if (ret > 0) {
1269                         msg->reply = rxbuf[0] >> 4;
1270                         /*
1271                          * Assume happy day, and copy the data. The caller is
1272                          * expected to check msg->reply before touching it.
1273                          *
1274                          * Return payload size.
1275                          */
1276                         ret--;
1277                         memcpy(msg->buffer, rxbuf + 1, ret);
1278                 }
1279                 break;
1280
1281         default:
1282                 ret = -EINVAL;
1283                 break;
1284         }
1285
1286         return ret;
1287 }
1288
1289 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1290                                 enum port port)
1291 {
1292         const struct ddi_vbt_port_info *info =
1293                 &dev_priv->vbt.ddi_port_info[port];
1294         enum port aux_port;
1295
1296         if (!info->alternate_aux_channel) {
1297                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1298                               port_name(port), port_name(port));
1299                 return port;
1300         }
1301
1302         switch (info->alternate_aux_channel) {
1303         case DP_AUX_A:
1304                 aux_port = PORT_A;
1305                 break;
1306         case DP_AUX_B:
1307                 aux_port = PORT_B;
1308                 break;
1309         case DP_AUX_C:
1310                 aux_port = PORT_C;
1311                 break;
1312         case DP_AUX_D:
1313                 aux_port = PORT_D;
1314                 break;
1315         default:
1316                 MISSING_CASE(info->alternate_aux_channel);
1317                 aux_port = PORT_A;
1318                 break;
1319         }
1320
1321         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1322                       port_name(aux_port), port_name(port));
1323
1324         return aux_port;
1325 }
1326
1327 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1328                                   enum port port)
1329 {
1330         switch (port) {
1331         case PORT_B:
1332         case PORT_C:
1333         case PORT_D:
1334                 return DP_AUX_CH_CTL(port);
1335         default:
1336                 MISSING_CASE(port);
1337                 return DP_AUX_CH_CTL(PORT_B);
1338         }
1339 }
1340
1341 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1342                                    enum port port, int index)
1343 {
1344         switch (port) {
1345         case PORT_B:
1346         case PORT_C:
1347         case PORT_D:
1348                 return DP_AUX_CH_DATA(port, index);
1349         default:
1350                 MISSING_CASE(port);
1351                 return DP_AUX_CH_DATA(PORT_B, index);
1352         }
1353 }
1354
1355 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1356                                   enum port port)
1357 {
1358         switch (port) {
1359         case PORT_A:
1360                 return DP_AUX_CH_CTL(port);
1361         case PORT_B:
1362         case PORT_C:
1363         case PORT_D:
1364                 return PCH_DP_AUX_CH_CTL(port);
1365         default:
1366                 MISSING_CASE(port);
1367                 return DP_AUX_CH_CTL(PORT_A);
1368         }
1369 }
1370
1371 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1372                                    enum port port, int index)
1373 {
1374         switch (port) {
1375         case PORT_A:
1376                 return DP_AUX_CH_DATA(port, index);
1377         case PORT_B:
1378         case PORT_C:
1379         case PORT_D:
1380                 return PCH_DP_AUX_CH_DATA(port, index);
1381         default:
1382                 MISSING_CASE(port);
1383                 return DP_AUX_CH_DATA(PORT_A, index);
1384         }
1385 }
1386
1387 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1388                                   enum port port)
1389 {
1390         switch (port) {
1391         case PORT_A:
1392         case PORT_B:
1393         case PORT_C:
1394         case PORT_D:
1395                 return DP_AUX_CH_CTL(port);
1396         default:
1397                 MISSING_CASE(port);
1398                 return DP_AUX_CH_CTL(PORT_A);
1399         }
1400 }
1401
1402 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1403                                    enum port port, int index)
1404 {
1405         switch (port) {
1406         case PORT_A:
1407         case PORT_B:
1408         case PORT_C:
1409         case PORT_D:
1410                 return DP_AUX_CH_DATA(port, index);
1411         default:
1412                 MISSING_CASE(port);
1413                 return DP_AUX_CH_DATA(PORT_A, index);
1414         }
1415 }
1416
1417 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1418                                     enum port port)
1419 {
1420         if (INTEL_INFO(dev_priv)->gen >= 9)
1421                 return skl_aux_ctl_reg(dev_priv, port);
1422         else if (HAS_PCH_SPLIT(dev_priv))
1423                 return ilk_aux_ctl_reg(dev_priv, port);
1424         else
1425                 return g4x_aux_ctl_reg(dev_priv, port);
1426 }
1427
1428 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1429                                      enum port port, int index)
1430 {
1431         if (INTEL_INFO(dev_priv)->gen >= 9)
1432                 return skl_aux_data_reg(dev_priv, port, index);
1433         else if (HAS_PCH_SPLIT(dev_priv))
1434                 return ilk_aux_data_reg(dev_priv, port, index);
1435         else
1436                 return g4x_aux_data_reg(dev_priv, port, index);
1437 }
1438
1439 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1442         enum port port = intel_aux_port(dev_priv,
1443                                         dp_to_dig_port(intel_dp)->port);
1444         int i;
1445
1446         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1447         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1448                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1449 }
1450
1451 static void
1452 intel_dp_aux_fini(struct intel_dp *intel_dp)
1453 {
1454         kfree(intel_dp->aux.name);
1455 }
1456
1457 static void
1458 intel_dp_aux_init(struct intel_dp *intel_dp)
1459 {
1460         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1461         enum port port = intel_dig_port->port;
1462
1463         intel_aux_reg_init(intel_dp);
1464         drm_dp_aux_init(&intel_dp->aux);
1465
1466         /* Failure to allocate our preferred name is not critical */
1467         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1468         intel_dp->aux.transfer = intel_dp_aux_transfer;
1469 }
1470
1471 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1472 {
1473         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1474
1475         return max_rate >= 540000;
1476 }
1477
1478 static void
1479 intel_dp_set_clock(struct intel_encoder *encoder,
1480                    struct intel_crtc_state *pipe_config)
1481 {
1482         struct drm_device *dev = encoder->base.dev;
1483         struct drm_i915_private *dev_priv = to_i915(dev);
1484         const struct dp_link_dpll *divisor = NULL;
1485         int i, count = 0;
1486
1487         if (IS_G4X(dev_priv)) {
1488                 divisor = gen4_dpll;
1489                 count = ARRAY_SIZE(gen4_dpll);
1490         } else if (HAS_PCH_SPLIT(dev_priv)) {
1491                 divisor = pch_dpll;
1492                 count = ARRAY_SIZE(pch_dpll);
1493         } else if (IS_CHERRYVIEW(dev_priv)) {
1494                 divisor = chv_dpll;
1495                 count = ARRAY_SIZE(chv_dpll);
1496         } else if (IS_VALLEYVIEW(dev_priv)) {
1497                 divisor = vlv_dpll;
1498                 count = ARRAY_SIZE(vlv_dpll);
1499         }
1500
1501         if (divisor && count) {
1502                 for (i = 0; i < count; i++) {
1503                         if (pipe_config->port_clock == divisor[i].clock) {
1504                                 pipe_config->dpll = divisor[i].dpll;
1505                                 pipe_config->clock_set = true;
1506                                 break;
1507                         }
1508                 }
1509         }
1510 }
1511
1512 static void snprintf_int_array(char *str, size_t len,
1513                                const int *array, int nelem)
1514 {
1515         int i;
1516
1517         str[0] = '\0';
1518
1519         for (i = 0; i < nelem; i++) {
1520                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1521                 if (r >= len)
1522                         return;
1523                 str += r;
1524                 len -= r;
1525         }
1526 }
1527
1528 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1529 {
1530         char str[128]; /* FIXME: too big for stack? */
1531
1532         if ((drm_debug & DRM_UT_KMS) == 0)
1533                 return;
1534
1535         snprintf_int_array(str, sizeof(str),
1536                            intel_dp->source_rates, intel_dp->num_source_rates);
1537         DRM_DEBUG_KMS("source rates: %s\n", str);
1538
1539         snprintf_int_array(str, sizeof(str),
1540                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1541         DRM_DEBUG_KMS("sink rates: %s\n", str);
1542
1543         snprintf_int_array(str, sizeof(str),
1544                            intel_dp->common_rates, intel_dp->num_common_rates);
1545         DRM_DEBUG_KMS("common rates: %s\n", str);
1546 }
1547
1548 int
1549 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1550 {
1551         int len;
1552
1553         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1554         if (WARN_ON(len <= 0))
1555                 return 162000;
1556
1557         return intel_dp->common_rates[len - 1];
1558 }
1559
1560 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1561 {
1562         int i = intel_dp_rate_index(intel_dp->sink_rates,
1563                                     intel_dp->num_sink_rates, rate);
1564
1565         if (WARN_ON(i < 0))
1566                 i = 0;
1567
1568         return i;
1569 }
1570
1571 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1572                            uint8_t *link_bw, uint8_t *rate_select)
1573 {
1574         /* eDP 1.4 rate select method. */
1575         if (intel_dp->use_rate_select) {
1576                 *link_bw = 0;
1577                 *rate_select =
1578                         intel_dp_rate_select(intel_dp, port_clock);
1579         } else {
1580                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1581                 *rate_select = 0;
1582         }
1583 }
1584
1585 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1586                                 struct intel_crtc_state *pipe_config)
1587 {
1588         int bpp, bpc;
1589
1590         bpp = pipe_config->pipe_bpp;
1591         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1592
1593         if (bpc > 0)
1594                 bpp = min(bpp, 3*bpc);
1595
1596         /* For DP Compliance we override the computed bpp for the pipe */
1597         if (intel_dp->compliance.test_data.bpc != 0) {
1598                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1599                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1600                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1601                               pipe_config->pipe_bpp);
1602         }
1603         return bpp;
1604 }
1605
1606 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1607                                        struct drm_display_mode *m2)
1608 {
1609         bool bres = false;
1610
1611         if (m1 && m2)
1612                 bres = (m1->hdisplay == m2->hdisplay &&
1613                         m1->hsync_start == m2->hsync_start &&
1614                         m1->hsync_end == m2->hsync_end &&
1615                         m1->htotal == m2->htotal &&
1616                         m1->vdisplay == m2->vdisplay &&
1617                         m1->vsync_start == m2->vsync_start &&
1618                         m1->vsync_end == m2->vsync_end &&
1619                         m1->vtotal == m2->vtotal);
1620         return bres;
1621 }
1622
1623 bool
1624 intel_dp_compute_config(struct intel_encoder *encoder,
1625                         struct intel_crtc_state *pipe_config,
1626                         struct drm_connector_state *conn_state)
1627 {
1628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1629         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1630         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1631         enum port port = dp_to_dig_port(intel_dp)->port;
1632         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1633         struct intel_connector *intel_connector = intel_dp->attached_connector;
1634         struct intel_digital_connector_state *intel_conn_state =
1635                 to_intel_digital_connector_state(conn_state);
1636         int lane_count, clock;
1637         int min_lane_count = 1;
1638         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1639         /* Conveniently, the link BW constants become indices with a shift...*/
1640         int min_clock = 0;
1641         int max_clock;
1642         int bpp, mode_rate;
1643         int link_avail, link_clock;
1644         int common_len;
1645         uint8_t link_bw, rate_select;
1646         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1647                                            DP_DPCD_QUIRK_LIMITED_M_N);
1648
1649         common_len = intel_dp_common_len_rate_limit(intel_dp,
1650                                                     intel_dp->max_link_rate);
1651
1652         /* No common link rates between source and sink */
1653         WARN_ON(common_len <= 0);
1654
1655         max_clock = common_len - 1;
1656
1657         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1658                 pipe_config->has_pch_encoder = true;
1659
1660         pipe_config->has_drrs = false;
1661         if (port == PORT_A)
1662                 pipe_config->has_audio = false;
1663         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1664                 pipe_config->has_audio = intel_dp->has_audio;
1665         else
1666                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1667
1668         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1669                 struct drm_display_mode *panel_mode =
1670                         intel_connector->panel.alt_fixed_mode;
1671                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1672
1673                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1674                         panel_mode = intel_connector->panel.fixed_mode;
1675
1676                 drm_mode_debug_printmodeline(panel_mode);
1677
1678                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1679
1680                 if (INTEL_GEN(dev_priv) >= 9) {
1681                         int ret;
1682                         ret = skl_update_scaler_crtc(pipe_config);
1683                         if (ret)
1684                                 return ret;
1685                 }
1686
1687                 if (HAS_GMCH_DISPLAY(dev_priv))
1688                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1689                                                  conn_state->scaling_mode);
1690                 else
1691                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1692                                                 conn_state->scaling_mode);
1693         }
1694
1695         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1696                 return false;
1697
1698         /* Use values requested by Compliance Test Request */
1699         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1700                 int index;
1701
1702                 /* Validate the compliance test data since max values
1703                  * might have changed due to link train fallback.
1704                  */
1705                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1706                                                intel_dp->compliance.test_lane_count)) {
1707                         index = intel_dp_rate_index(intel_dp->common_rates,
1708                                                     intel_dp->num_common_rates,
1709                                                     intel_dp->compliance.test_link_rate);
1710                         if (index >= 0)
1711                                 min_clock = max_clock = index;
1712                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1713                 }
1714         }
1715         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1716                       "max bw %d pixel clock %iKHz\n",
1717                       max_lane_count, intel_dp->common_rates[max_clock],
1718                       adjusted_mode->crtc_clock);
1719
1720         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1721          * bpc in between. */
1722         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1723         if (intel_dp_is_edp(intel_dp)) {
1724
1725                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1726                 if (intel_connector->base.display_info.bpc == 0 &&
1727                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1728                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1729                                       dev_priv->vbt.edp.bpp);
1730                         bpp = dev_priv->vbt.edp.bpp;
1731                 }
1732
1733                 /*
1734                  * Use the maximum clock and number of lanes the eDP panel
1735                  * advertizes being capable of. The panels are generally
1736                  * designed to support only a single clock and lane
1737                  * configuration, and typically these values correspond to the
1738                  * native resolution of the panel.
1739                  */
1740                 min_lane_count = max_lane_count;
1741                 min_clock = max_clock;
1742         }
1743
1744         for (; bpp >= 6*3; bpp -= 2*3) {
1745                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1746                                                    bpp);
1747
1748                 for (clock = min_clock; clock <= max_clock; clock++) {
1749                         for (lane_count = min_lane_count;
1750                                 lane_count <= max_lane_count;
1751                                 lane_count <<= 1) {
1752
1753                                 link_clock = intel_dp->common_rates[clock];
1754                                 link_avail = intel_dp_max_data_rate(link_clock,
1755                                                                     lane_count);
1756
1757                                 if (mode_rate <= link_avail) {
1758                                         goto found;
1759                                 }
1760                         }
1761                 }
1762         }
1763
1764         return false;
1765
1766 found:
1767         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1768                 /*
1769                  * See:
1770                  * CEA-861-E - 5.1 Default Encoding Parameters
1771                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1772                  */
1773                 pipe_config->limited_color_range =
1774                         bpp != 18 &&
1775                         drm_default_rgb_quant_range(adjusted_mode) ==
1776                         HDMI_QUANTIZATION_RANGE_LIMITED;
1777         } else {
1778                 pipe_config->limited_color_range =
1779                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1780         }
1781
1782         pipe_config->lane_count = lane_count;
1783
1784         pipe_config->pipe_bpp = bpp;
1785         pipe_config->port_clock = intel_dp->common_rates[clock];
1786
1787         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1788                               &link_bw, &rate_select);
1789
1790         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1791                       link_bw, rate_select, pipe_config->lane_count,
1792                       pipe_config->port_clock, bpp);
1793         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1794                       mode_rate, link_avail);
1795
1796         intel_link_compute_m_n(bpp, lane_count,
1797                                adjusted_mode->crtc_clock,
1798                                pipe_config->port_clock,
1799                                &pipe_config->dp_m_n,
1800                                reduce_m_n);
1801
1802         if (intel_connector->panel.downclock_mode != NULL &&
1803                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1804                         pipe_config->has_drrs = true;
1805                         intel_link_compute_m_n(bpp, lane_count,
1806                                 intel_connector->panel.downclock_mode->clock,
1807                                 pipe_config->port_clock,
1808                                 &pipe_config->dp_m2_n2,
1809                                 reduce_m_n);
1810         }
1811
1812         /*
1813          * DPLL0 VCO may need to be adjusted to get the correct
1814          * clock for eDP. This will affect cdclk as well.
1815          */
1816         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1817                 int vco;
1818
1819                 switch (pipe_config->port_clock / 2) {
1820                 case 108000:
1821                 case 216000:
1822                         vco = 8640000;
1823                         break;
1824                 default:
1825                         vco = 8100000;
1826                         break;
1827                 }
1828
1829                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1830         }
1831
1832         if (!HAS_DDI(dev_priv))
1833                 intel_dp_set_clock(encoder, pipe_config);
1834
1835         intel_psr_compute_config(intel_dp, pipe_config);
1836
1837         return true;
1838 }
1839
1840 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1841                               int link_rate, uint8_t lane_count,
1842                               bool link_mst)
1843 {
1844         intel_dp->link_rate = link_rate;
1845         intel_dp->lane_count = lane_count;
1846         intel_dp->link_mst = link_mst;
1847 }
1848
1849 static void intel_dp_prepare(struct intel_encoder *encoder,
1850                              const struct intel_crtc_state *pipe_config)
1851 {
1852         struct drm_device *dev = encoder->base.dev;
1853         struct drm_i915_private *dev_priv = to_i915(dev);
1854         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1855         enum port port = dp_to_dig_port(intel_dp)->port;
1856         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1857         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1858
1859         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1860                                  pipe_config->lane_count,
1861                                  intel_crtc_has_type(pipe_config,
1862                                                      INTEL_OUTPUT_DP_MST));
1863
1864         /*
1865          * There are four kinds of DP registers:
1866          *
1867          *      IBX PCH
1868          *      SNB CPU
1869          *      IVB CPU
1870          *      CPT PCH
1871          *
1872          * IBX PCH and CPU are the same for almost everything,
1873          * except that the CPU DP PLL is configured in this
1874          * register
1875          *
1876          * CPT PCH is quite different, having many bits moved
1877          * to the TRANS_DP_CTL register instead. That
1878          * configuration happens (oddly) in ironlake_pch_enable
1879          */
1880
1881         /* Preserve the BIOS-computed detected bit. This is
1882          * supposed to be read-only.
1883          */
1884         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1885
1886         /* Handle DP bits in common between all three register formats */
1887         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1888         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1889
1890         /* Split out the IBX/CPU vs CPT settings */
1891
1892         if (IS_GEN7(dev_priv) && port == PORT_A) {
1893                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1894                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1895                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1896                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1897                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1898
1899                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1900                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1901
1902                 intel_dp->DP |= crtc->pipe << 29;
1903         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1904                 u32 trans_dp;
1905
1906                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1907
1908                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1909                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1910                         trans_dp |= TRANS_DP_ENH_FRAMING;
1911                 else
1912                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1913                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1914         } else {
1915                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1916                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1917
1918                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1919                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1920                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1921                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1922                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1923
1924                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1925                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1926
1927                 if (IS_CHERRYVIEW(dev_priv))
1928                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1929                 else if (crtc->pipe == PIPE_B)
1930                         intel_dp->DP |= DP_PIPEB_SELECT;
1931         }
1932 }
1933
1934 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1935 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1936
1937 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1938 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1939
1940 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1941 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1942
1943 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1944                                    struct intel_dp *intel_dp);
1945
1946 static void wait_panel_status(struct intel_dp *intel_dp,
1947                                        u32 mask,
1948                                        u32 value)
1949 {
1950         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1953
1954         lockdep_assert_held(&dev_priv->pps_mutex);
1955
1956         intel_pps_verify_state(dev_priv, intel_dp);
1957
1958         pp_stat_reg = _pp_stat_reg(intel_dp);
1959         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1960
1961         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1962                         mask, value,
1963                         I915_READ(pp_stat_reg),
1964                         I915_READ(pp_ctrl_reg));
1965
1966         if (intel_wait_for_register(dev_priv,
1967                                     pp_stat_reg, mask, value,
1968                                     5000))
1969                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1970                                 I915_READ(pp_stat_reg),
1971                                 I915_READ(pp_ctrl_reg));
1972
1973         DRM_DEBUG_KMS("Wait complete\n");
1974 }
1975
1976 static void wait_panel_on(struct intel_dp *intel_dp)
1977 {
1978         DRM_DEBUG_KMS("Wait for panel power on\n");
1979         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1980 }
1981
1982 static void wait_panel_off(struct intel_dp *intel_dp)
1983 {
1984         DRM_DEBUG_KMS("Wait for panel power off time\n");
1985         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1986 }
1987
1988 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1989 {
1990         ktime_t panel_power_on_time;
1991         s64 panel_power_off_duration;
1992
1993         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1994
1995         /* take the difference of currrent time and panel power off time
1996          * and then make panel wait for t11_t12 if needed. */
1997         panel_power_on_time = ktime_get_boottime();
1998         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1999
2000         /* When we disable the VDD override bit last we have to do the manual
2001          * wait. */
2002         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2003                 wait_remaining_ms_from_jiffies(jiffies,
2004                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2005
2006         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2007 }
2008
2009 static void wait_backlight_on(struct intel_dp *intel_dp)
2010 {
2011         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2012                                        intel_dp->backlight_on_delay);
2013 }
2014
2015 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2016 {
2017         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2018                                        intel_dp->backlight_off_delay);
2019 }
2020
2021 /* Read the current pp_control value, unlocking the register if it
2022  * is locked
2023  */
2024
2025 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2026 {
2027         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2028         struct drm_i915_private *dev_priv = to_i915(dev);
2029         u32 control;
2030
2031         lockdep_assert_held(&dev_priv->pps_mutex);
2032
2033         control = I915_READ(_pp_ctrl_reg(intel_dp));
2034         if (WARN_ON(!HAS_DDI(dev_priv) &&
2035                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2036                 control &= ~PANEL_UNLOCK_MASK;
2037                 control |= PANEL_UNLOCK_REGS;
2038         }
2039         return control;
2040 }
2041
2042 /*
2043  * Must be paired with edp_panel_vdd_off().
2044  * Must hold pps_mutex around the whole on/off sequence.
2045  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2046  */
2047 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2048 {
2049         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2050         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2051         struct drm_i915_private *dev_priv = to_i915(dev);
2052         u32 pp;
2053         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2054         bool need_to_disable = !intel_dp->want_panel_vdd;
2055
2056         lockdep_assert_held(&dev_priv->pps_mutex);
2057
2058         if (!intel_dp_is_edp(intel_dp))
2059                 return false;
2060
2061         cancel_delayed_work(&intel_dp->panel_vdd_work);
2062         intel_dp->want_panel_vdd = true;
2063
2064         if (edp_have_panel_vdd(intel_dp))
2065                 return need_to_disable;
2066
2067         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2068
2069         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2070                       port_name(intel_dig_port->port));
2071
2072         if (!edp_have_panel_power(intel_dp))
2073                 wait_panel_power_cycle(intel_dp);
2074
2075         pp = ironlake_get_pp_control(intel_dp);
2076         pp |= EDP_FORCE_VDD;
2077
2078         pp_stat_reg = _pp_stat_reg(intel_dp);
2079         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2080
2081         I915_WRITE(pp_ctrl_reg, pp);
2082         POSTING_READ(pp_ctrl_reg);
2083         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2084                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2085         /*
2086          * If the panel wasn't on, delay before accessing aux channel
2087          */
2088         if (!edp_have_panel_power(intel_dp)) {
2089                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2090                               port_name(intel_dig_port->port));
2091                 msleep(intel_dp->panel_power_up_delay);
2092         }
2093
2094         return need_to_disable;
2095 }
2096
2097 /*
2098  * Must be paired with intel_edp_panel_vdd_off() or
2099  * intel_edp_panel_off().
2100  * Nested calls to these functions are not allowed since
2101  * we drop the lock. Caller must use some higher level
2102  * locking to prevent nested calls from other threads.
2103  */
2104 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2105 {
2106         bool vdd;
2107
2108         if (!intel_dp_is_edp(intel_dp))
2109                 return;
2110
2111         pps_lock(intel_dp);
2112         vdd = edp_panel_vdd_on(intel_dp);
2113         pps_unlock(intel_dp);
2114
2115         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2116              port_name(dp_to_dig_port(intel_dp)->port));
2117 }
2118
2119 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2120 {
2121         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2122         struct drm_i915_private *dev_priv = to_i915(dev);
2123         struct intel_digital_port *intel_dig_port =
2124                 dp_to_dig_port(intel_dp);
2125         u32 pp;
2126         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2127
2128         lockdep_assert_held(&dev_priv->pps_mutex);
2129
2130         WARN_ON(intel_dp->want_panel_vdd);
2131
2132         if (!edp_have_panel_vdd(intel_dp))
2133                 return;
2134
2135         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2136                       port_name(intel_dig_port->port));
2137
2138         pp = ironlake_get_pp_control(intel_dp);
2139         pp &= ~EDP_FORCE_VDD;
2140
2141         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2142         pp_stat_reg = _pp_stat_reg(intel_dp);
2143
2144         I915_WRITE(pp_ctrl_reg, pp);
2145         POSTING_READ(pp_ctrl_reg);
2146
2147         /* Make sure sequencer is idle before allowing subsequent activity */
2148         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2149         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2150
2151         if ((pp & PANEL_POWER_ON) == 0)
2152                 intel_dp->panel_power_off_time = ktime_get_boottime();
2153
2154         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2155 }
2156
2157 static void edp_panel_vdd_work(struct work_struct *__work)
2158 {
2159         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2160                                                  struct intel_dp, panel_vdd_work);
2161
2162         pps_lock(intel_dp);
2163         if (!intel_dp->want_panel_vdd)
2164                 edp_panel_vdd_off_sync(intel_dp);
2165         pps_unlock(intel_dp);
2166 }
2167
2168 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2169 {
2170         unsigned long delay;
2171
2172         /*
2173          * Queue the timer to fire a long time from now (relative to the power
2174          * down delay) to keep the panel power up across a sequence of
2175          * operations.
2176          */
2177         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2178         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2179 }
2180
2181 /*
2182  * Must be paired with edp_panel_vdd_on().
2183  * Must hold pps_mutex around the whole on/off sequence.
2184  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2185  */
2186 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2187 {
2188         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2189
2190         lockdep_assert_held(&dev_priv->pps_mutex);
2191
2192         if (!intel_dp_is_edp(intel_dp))
2193                 return;
2194
2195         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2196              port_name(dp_to_dig_port(intel_dp)->port));
2197
2198         intel_dp->want_panel_vdd = false;
2199
2200         if (sync)
2201                 edp_panel_vdd_off_sync(intel_dp);
2202         else
2203                 edp_panel_vdd_schedule_off(intel_dp);
2204 }
2205
2206 static void edp_panel_on(struct intel_dp *intel_dp)
2207 {
2208         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2209         struct drm_i915_private *dev_priv = to_i915(dev);
2210         u32 pp;
2211         i915_reg_t pp_ctrl_reg;
2212
2213         lockdep_assert_held(&dev_priv->pps_mutex);
2214
2215         if (!intel_dp_is_edp(intel_dp))
2216                 return;
2217
2218         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2219                       port_name(dp_to_dig_port(intel_dp)->port));
2220
2221         if (WARN(edp_have_panel_power(intel_dp),
2222                  "eDP port %c panel power already on\n",
2223                  port_name(dp_to_dig_port(intel_dp)->port)))
2224                 return;
2225
2226         wait_panel_power_cycle(intel_dp);
2227
2228         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2229         pp = ironlake_get_pp_control(intel_dp);
2230         if (IS_GEN5(dev_priv)) {
2231                 /* ILK workaround: disable reset around power sequence */
2232                 pp &= ~PANEL_POWER_RESET;
2233                 I915_WRITE(pp_ctrl_reg, pp);
2234                 POSTING_READ(pp_ctrl_reg);
2235         }
2236
2237         pp |= PANEL_POWER_ON;
2238         if (!IS_GEN5(dev_priv))
2239                 pp |= PANEL_POWER_RESET;
2240
2241         I915_WRITE(pp_ctrl_reg, pp);
2242         POSTING_READ(pp_ctrl_reg);
2243
2244         wait_panel_on(intel_dp);
2245         intel_dp->last_power_on = jiffies;
2246
2247         if (IS_GEN5(dev_priv)) {
2248                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2249                 I915_WRITE(pp_ctrl_reg, pp);
2250                 POSTING_READ(pp_ctrl_reg);
2251         }
2252 }
2253
2254 void intel_edp_panel_on(struct intel_dp *intel_dp)
2255 {
2256         if (!intel_dp_is_edp(intel_dp))
2257                 return;
2258
2259         pps_lock(intel_dp);
2260         edp_panel_on(intel_dp);
2261         pps_unlock(intel_dp);
2262 }
2263
2264
2265 static void edp_panel_off(struct intel_dp *intel_dp)
2266 {
2267         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2268         struct drm_i915_private *dev_priv = to_i915(dev);
2269         u32 pp;
2270         i915_reg_t pp_ctrl_reg;
2271
2272         lockdep_assert_held(&dev_priv->pps_mutex);
2273
2274         if (!intel_dp_is_edp(intel_dp))
2275                 return;
2276
2277         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2278                       port_name(dp_to_dig_port(intel_dp)->port));
2279
2280         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2281              port_name(dp_to_dig_port(intel_dp)->port));
2282
2283         pp = ironlake_get_pp_control(intel_dp);
2284         /* We need to switch off panel power _and_ force vdd, for otherwise some
2285          * panels get very unhappy and cease to work. */
2286         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2287                 EDP_BLC_ENABLE);
2288
2289         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2290
2291         intel_dp->want_panel_vdd = false;
2292
2293         I915_WRITE(pp_ctrl_reg, pp);
2294         POSTING_READ(pp_ctrl_reg);
2295
2296         wait_panel_off(intel_dp);
2297         intel_dp->panel_power_off_time = ktime_get_boottime();
2298
2299         /* We got a reference when we enabled the VDD. */
2300         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2301 }
2302
2303 void intel_edp_panel_off(struct intel_dp *intel_dp)
2304 {
2305         if (!intel_dp_is_edp(intel_dp))
2306                 return;
2307
2308         pps_lock(intel_dp);
2309         edp_panel_off(intel_dp);
2310         pps_unlock(intel_dp);
2311 }
2312
2313 /* Enable backlight in the panel power control. */
2314 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2315 {
2316         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2317         struct drm_device *dev = intel_dig_port->base.base.dev;
2318         struct drm_i915_private *dev_priv = to_i915(dev);
2319         u32 pp;
2320         i915_reg_t pp_ctrl_reg;
2321
2322         /*
2323          * If we enable the backlight right away following a panel power
2324          * on, we may see slight flicker as the panel syncs with the eDP
2325          * link.  So delay a bit to make sure the image is solid before
2326          * allowing it to appear.
2327          */
2328         wait_backlight_on(intel_dp);
2329
2330         pps_lock(intel_dp);
2331
2332         pp = ironlake_get_pp_control(intel_dp);
2333         pp |= EDP_BLC_ENABLE;
2334
2335         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2336
2337         I915_WRITE(pp_ctrl_reg, pp);
2338         POSTING_READ(pp_ctrl_reg);
2339
2340         pps_unlock(intel_dp);
2341 }
2342
2343 /* Enable backlight PWM and backlight PP control. */
2344 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2345                             const struct drm_connector_state *conn_state)
2346 {
2347         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2348
2349         if (!intel_dp_is_edp(intel_dp))
2350                 return;
2351
2352         DRM_DEBUG_KMS("\n");
2353
2354         intel_panel_enable_backlight(crtc_state, conn_state);
2355         _intel_edp_backlight_on(intel_dp);
2356 }
2357
2358 /* Disable backlight in the panel power control. */
2359 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2360 {
2361         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2362         struct drm_i915_private *dev_priv = to_i915(dev);
2363         u32 pp;
2364         i915_reg_t pp_ctrl_reg;
2365
2366         if (!intel_dp_is_edp(intel_dp))
2367                 return;
2368
2369         pps_lock(intel_dp);
2370
2371         pp = ironlake_get_pp_control(intel_dp);
2372         pp &= ~EDP_BLC_ENABLE;
2373
2374         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2375
2376         I915_WRITE(pp_ctrl_reg, pp);
2377         POSTING_READ(pp_ctrl_reg);
2378
2379         pps_unlock(intel_dp);
2380
2381         intel_dp->last_backlight_off = jiffies;
2382         edp_wait_backlight_off(intel_dp);
2383 }
2384
2385 /* Disable backlight PP control and backlight PWM. */
2386 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2387 {
2388         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2389
2390         if (!intel_dp_is_edp(intel_dp))
2391                 return;
2392
2393         DRM_DEBUG_KMS("\n");
2394
2395         _intel_edp_backlight_off(intel_dp);
2396         intel_panel_disable_backlight(old_conn_state);
2397 }
2398
2399 /*
2400  * Hook for controlling the panel power control backlight through the bl_power
2401  * sysfs attribute. Take care to handle multiple calls.
2402  */
2403 static void intel_edp_backlight_power(struct intel_connector *connector,
2404                                       bool enable)
2405 {
2406         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2407         bool is_enabled;
2408
2409         pps_lock(intel_dp);
2410         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2411         pps_unlock(intel_dp);
2412
2413         if (is_enabled == enable)
2414                 return;
2415
2416         DRM_DEBUG_KMS("panel power control backlight %s\n",
2417                       enable ? "enable" : "disable");
2418
2419         if (enable)
2420                 _intel_edp_backlight_on(intel_dp);
2421         else
2422                 _intel_edp_backlight_off(intel_dp);
2423 }
2424
2425 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2426 {
2427         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2428         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2429         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2430
2431         I915_STATE_WARN(cur_state != state,
2432                         "DP port %c state assertion failure (expected %s, current %s)\n",
2433                         port_name(dig_port->port),
2434                         onoff(state), onoff(cur_state));
2435 }
2436 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2437
2438 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2439 {
2440         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2441
2442         I915_STATE_WARN(cur_state != state,
2443                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2444                         onoff(state), onoff(cur_state));
2445 }
2446 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2447 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2448
2449 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2450                                 const struct intel_crtc_state *pipe_config)
2451 {
2452         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2454
2455         assert_pipe_disabled(dev_priv, crtc->pipe);
2456         assert_dp_port_disabled(intel_dp);
2457         assert_edp_pll_disabled(dev_priv);
2458
2459         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2460                       pipe_config->port_clock);
2461
2462         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2463
2464         if (pipe_config->port_clock == 162000)
2465                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2466         else
2467                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2468
2469         I915_WRITE(DP_A, intel_dp->DP);
2470         POSTING_READ(DP_A);
2471         udelay(500);
2472
2473         /*
2474          * [DevILK] Work around required when enabling DP PLL
2475          * while a pipe is enabled going to FDI:
2476          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2477          * 2. Program DP PLL enable
2478          */
2479         if (IS_GEN5(dev_priv))
2480                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2481
2482         intel_dp->DP |= DP_PLL_ENABLE;
2483
2484         I915_WRITE(DP_A, intel_dp->DP);
2485         POSTING_READ(DP_A);
2486         udelay(200);
2487 }
2488
2489 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2490 {
2491         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2492         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2493         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2494
2495         assert_pipe_disabled(dev_priv, crtc->pipe);
2496         assert_dp_port_disabled(intel_dp);
2497         assert_edp_pll_enabled(dev_priv);
2498
2499         DRM_DEBUG_KMS("disabling eDP PLL\n");
2500
2501         intel_dp->DP &= ~DP_PLL_ENABLE;
2502
2503         I915_WRITE(DP_A, intel_dp->DP);
2504         POSTING_READ(DP_A);
2505         udelay(200);
2506 }
2507
2508 /* If the sink supports it, try to set the power state appropriately */
2509 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2510 {
2511         int ret, i;
2512
2513         /* Should have a valid DPCD by this point */
2514         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2515                 return;
2516
2517         if (mode != DRM_MODE_DPMS_ON) {
2518                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2519                                          DP_SET_POWER_D3);
2520         } else {
2521                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2522
2523                 /*
2524                  * When turning on, we need to retry for 1ms to give the sink
2525                  * time to wake up.
2526                  */
2527                 for (i = 0; i < 3; i++) {
2528                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2529                                                  DP_SET_POWER_D0);
2530                         if (ret == 1)
2531                                 break;
2532                         msleep(1);
2533                 }
2534
2535                 if (ret == 1 && lspcon->active)
2536                         lspcon_wait_pcon_mode(lspcon);
2537         }
2538
2539         if (ret != 1)
2540                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2541                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2542 }
2543
2544 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2545                                   enum pipe *pipe)
2546 {
2547         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2548         enum port port = dp_to_dig_port(intel_dp)->port;
2549         struct drm_device *dev = encoder->base.dev;
2550         struct drm_i915_private *dev_priv = to_i915(dev);
2551         u32 tmp;
2552         bool ret;
2553
2554         if (!intel_display_power_get_if_enabled(dev_priv,
2555                                                 encoder->power_domain))
2556                 return false;
2557
2558         ret = false;
2559
2560         tmp = I915_READ(intel_dp->output_reg);
2561
2562         if (!(tmp & DP_PORT_EN))
2563                 goto out;
2564
2565         if (IS_GEN7(dev_priv) && port == PORT_A) {
2566                 *pipe = PORT_TO_PIPE_CPT(tmp);
2567         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2568                 enum pipe p;
2569
2570                 for_each_pipe(dev_priv, p) {
2571                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2572                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2573                                 *pipe = p;
2574                                 ret = true;
2575
2576                                 goto out;
2577                         }
2578                 }
2579
2580                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2581                               i915_mmio_reg_offset(intel_dp->output_reg));
2582         } else if (IS_CHERRYVIEW(dev_priv)) {
2583                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2584         } else {
2585                 *pipe = PORT_TO_PIPE(tmp);
2586         }
2587
2588         ret = true;
2589
2590 out:
2591         intel_display_power_put(dev_priv, encoder->power_domain);
2592
2593         return ret;
2594 }
2595
2596 static void intel_dp_get_config(struct intel_encoder *encoder,
2597                                 struct intel_crtc_state *pipe_config)
2598 {
2599         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2600         u32 tmp, flags = 0;
2601         struct drm_device *dev = encoder->base.dev;
2602         struct drm_i915_private *dev_priv = to_i915(dev);
2603         enum port port = dp_to_dig_port(intel_dp)->port;
2604         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2605
2606         tmp = I915_READ(intel_dp->output_reg);
2607
2608         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2609
2610         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2611                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2612
2613                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2614                         flags |= DRM_MODE_FLAG_PHSYNC;
2615                 else
2616                         flags |= DRM_MODE_FLAG_NHSYNC;
2617
2618                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2619                         flags |= DRM_MODE_FLAG_PVSYNC;
2620                 else
2621                         flags |= DRM_MODE_FLAG_NVSYNC;
2622         } else {
2623                 if (tmp & DP_SYNC_HS_HIGH)
2624                         flags |= DRM_MODE_FLAG_PHSYNC;
2625                 else
2626                         flags |= DRM_MODE_FLAG_NHSYNC;
2627
2628                 if (tmp & DP_SYNC_VS_HIGH)
2629                         flags |= DRM_MODE_FLAG_PVSYNC;
2630                 else
2631                         flags |= DRM_MODE_FLAG_NVSYNC;
2632         }
2633
2634         pipe_config->base.adjusted_mode.flags |= flags;
2635
2636         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2637                 pipe_config->limited_color_range = true;
2638
2639         pipe_config->lane_count =
2640                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2641
2642         intel_dp_get_m_n(crtc, pipe_config);
2643
2644         if (port == PORT_A) {
2645                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2646                         pipe_config->port_clock = 162000;
2647                 else
2648                         pipe_config->port_clock = 270000;
2649         }
2650
2651         pipe_config->base.adjusted_mode.crtc_clock =
2652                 intel_dotclock_calculate(pipe_config->port_clock,
2653                                          &pipe_config->dp_m_n);
2654
2655         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2656             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2657                 /*
2658                  * This is a big fat ugly hack.
2659                  *
2660                  * Some machines in UEFI boot mode provide us a VBT that has 18
2661                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2662                  * unknown we fail to light up. Yet the same BIOS boots up with
2663                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2664                  * max, not what it tells us to use.
2665                  *
2666                  * Note: This will still be broken if the eDP panel is not lit
2667                  * up by the BIOS, and thus we can't get the mode at module
2668                  * load.
2669                  */
2670                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2671                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2672                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2673         }
2674 }
2675
2676 static void intel_disable_dp(struct intel_encoder *encoder,
2677                              const struct intel_crtc_state *old_crtc_state,
2678                              const struct drm_connector_state *old_conn_state)
2679 {
2680         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2681
2682         if (old_crtc_state->has_audio)
2683                 intel_audio_codec_disable(encoder);
2684
2685         /* Make sure the panel is off before trying to change the mode. But also
2686          * ensure that we have vdd while we switch off the panel. */
2687         intel_edp_panel_vdd_on(intel_dp);
2688         intel_edp_backlight_off(old_conn_state);
2689         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2690         intel_edp_panel_off(intel_dp);
2691 }
2692
2693 static void g4x_disable_dp(struct intel_encoder *encoder,
2694                            const struct intel_crtc_state *old_crtc_state,
2695                            const struct drm_connector_state *old_conn_state)
2696 {
2697         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2698
2699         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2700
2701         /* disable the port before the pipe on g4x */
2702         intel_dp_link_down(intel_dp);
2703 }
2704
2705 static void ilk_disable_dp(struct intel_encoder *encoder,
2706                            const struct intel_crtc_state *old_crtc_state,
2707                            const struct drm_connector_state *old_conn_state)
2708 {
2709         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2710 }
2711
2712 static void vlv_disable_dp(struct intel_encoder *encoder,
2713                            const struct intel_crtc_state *old_crtc_state,
2714                            const struct drm_connector_state *old_conn_state)
2715 {
2716         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2717
2718         intel_psr_disable(intel_dp, old_crtc_state);
2719
2720         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2721 }
2722
2723 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2724                                 const struct intel_crtc_state *old_crtc_state,
2725                                 const struct drm_connector_state *old_conn_state)
2726 {
2727         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2728         enum port port = dp_to_dig_port(intel_dp)->port;
2729
2730         intel_dp_link_down(intel_dp);
2731
2732         /* Only ilk+ has port A */
2733         if (port == PORT_A)
2734                 ironlake_edp_pll_off(intel_dp);
2735 }
2736
2737 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2738                                 const struct intel_crtc_state *old_crtc_state,
2739                                 const struct drm_connector_state *old_conn_state)
2740 {
2741         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2742
2743         intel_dp_link_down(intel_dp);
2744 }
2745
2746 static void chv_post_disable_dp(struct intel_encoder *encoder,
2747                                 const struct intel_crtc_state *old_crtc_state,
2748                                 const struct drm_connector_state *old_conn_state)
2749 {
2750         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2751         struct drm_device *dev = encoder->base.dev;
2752         struct drm_i915_private *dev_priv = to_i915(dev);
2753
2754         intel_dp_link_down(intel_dp);
2755
2756         mutex_lock(&dev_priv->sb_lock);
2757
2758         /* Assert data lane reset */
2759         chv_data_lane_soft_reset(encoder, true);
2760
2761         mutex_unlock(&dev_priv->sb_lock);
2762 }
2763
2764 static void
2765 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2766                          uint32_t *DP,
2767                          uint8_t dp_train_pat)
2768 {
2769         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2770         struct drm_device *dev = intel_dig_port->base.base.dev;
2771         struct drm_i915_private *dev_priv = to_i915(dev);
2772         enum port port = intel_dig_port->port;
2773
2774         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2775                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2776                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2777
2778         if (HAS_DDI(dev_priv)) {
2779                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2780
2781                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2782                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2783                 else
2784                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2785
2786                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2787                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2788                 case DP_TRAINING_PATTERN_DISABLE:
2789                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2790
2791                         break;
2792                 case DP_TRAINING_PATTERN_1:
2793                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2794                         break;
2795                 case DP_TRAINING_PATTERN_2:
2796                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2797                         break;
2798                 case DP_TRAINING_PATTERN_3:
2799                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2800                         break;
2801                 }
2802                 I915_WRITE(DP_TP_CTL(port), temp);
2803
2804         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2805                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2806                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2807
2808                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2809                 case DP_TRAINING_PATTERN_DISABLE:
2810                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2811                         break;
2812                 case DP_TRAINING_PATTERN_1:
2813                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2814                         break;
2815                 case DP_TRAINING_PATTERN_2:
2816                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2817                         break;
2818                 case DP_TRAINING_PATTERN_3:
2819                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2820                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2821                         break;
2822                 }
2823
2824         } else {
2825                 if (IS_CHERRYVIEW(dev_priv))
2826                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2827                 else
2828                         *DP &= ~DP_LINK_TRAIN_MASK;
2829
2830                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2831                 case DP_TRAINING_PATTERN_DISABLE:
2832                         *DP |= DP_LINK_TRAIN_OFF;
2833                         break;
2834                 case DP_TRAINING_PATTERN_1:
2835                         *DP |= DP_LINK_TRAIN_PAT_1;
2836                         break;
2837                 case DP_TRAINING_PATTERN_2:
2838                         *DP |= DP_LINK_TRAIN_PAT_2;
2839                         break;
2840                 case DP_TRAINING_PATTERN_3:
2841                         if (IS_CHERRYVIEW(dev_priv)) {
2842                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2843                         } else {
2844                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2845                                 *DP |= DP_LINK_TRAIN_PAT_2;
2846                         }
2847                         break;
2848                 }
2849         }
2850 }
2851
2852 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2853                                  const struct intel_crtc_state *old_crtc_state)
2854 {
2855         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2856         struct drm_i915_private *dev_priv = to_i915(dev);
2857
2858         /* enable with pattern 1 (as per spec) */
2859
2860         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2861
2862         /*
2863          * Magic for VLV/CHV. We _must_ first set up the register
2864          * without actually enabling the port, and then do another
2865          * write to enable the port. Otherwise link training will
2866          * fail when the power sequencer is freshly used for this port.
2867          */
2868         intel_dp->DP |= DP_PORT_EN;
2869         if (old_crtc_state->has_audio)
2870                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2871
2872         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2873         POSTING_READ(intel_dp->output_reg);
2874 }
2875
2876 static void intel_enable_dp(struct intel_encoder *encoder,
2877                             const struct intel_crtc_state *pipe_config,
2878                             const struct drm_connector_state *conn_state)
2879 {
2880         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2881         struct drm_device *dev = encoder->base.dev;
2882         struct drm_i915_private *dev_priv = to_i915(dev);
2883         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2884         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2885         enum pipe pipe = crtc->pipe;
2886
2887         if (WARN_ON(dp_reg & DP_PORT_EN))
2888                 return;
2889
2890         pps_lock(intel_dp);
2891
2892         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2893                 vlv_init_panel_power_sequencer(intel_dp);
2894
2895         intel_dp_enable_port(intel_dp, pipe_config);
2896
2897         edp_panel_vdd_on(intel_dp);
2898         edp_panel_on(intel_dp);
2899         edp_panel_vdd_off(intel_dp, true);
2900
2901         pps_unlock(intel_dp);
2902
2903         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2904                 unsigned int lane_mask = 0x0;
2905
2906                 if (IS_CHERRYVIEW(dev_priv))
2907                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2908
2909                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2910                                     lane_mask);
2911         }
2912
2913         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2914         intel_dp_start_link_train(intel_dp);
2915         intel_dp_stop_link_train(intel_dp);
2916
2917         if (pipe_config->has_audio) {
2918                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2919                                  pipe_name(pipe));
2920                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2921         }
2922 }
2923
2924 static void g4x_enable_dp(struct intel_encoder *encoder,
2925                           const struct intel_crtc_state *pipe_config,
2926                           const struct drm_connector_state *conn_state)
2927 {
2928         intel_enable_dp(encoder, pipe_config, conn_state);
2929         intel_edp_backlight_on(pipe_config, conn_state);
2930 }
2931
2932 static void vlv_enable_dp(struct intel_encoder *encoder,
2933                           const struct intel_crtc_state *pipe_config,
2934                           const struct drm_connector_state *conn_state)
2935 {
2936         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2937
2938         intel_edp_backlight_on(pipe_config, conn_state);
2939         intel_psr_enable(intel_dp, pipe_config);
2940 }
2941
2942 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2943                               const struct intel_crtc_state *pipe_config,
2944                               const struct drm_connector_state *conn_state)
2945 {
2946         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2947         enum port port = dp_to_dig_port(intel_dp)->port;
2948
2949         intel_dp_prepare(encoder, pipe_config);
2950
2951         /* Only ilk+ has port A */
2952         if (port == PORT_A)
2953                 ironlake_edp_pll_on(intel_dp, pipe_config);
2954 }
2955
2956 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2957 {
2958         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2959         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2960         enum pipe pipe = intel_dp->pps_pipe;
2961         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2962
2963         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2964
2965         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2966                 return;
2967
2968         edp_panel_vdd_off_sync(intel_dp);
2969
2970         /*
2971          * VLV seems to get confused when multiple power seqeuencers
2972          * have the same port selected (even if only one has power/vdd
2973          * enabled). The failure manifests as vlv_wait_port_ready() failing
2974          * CHV on the other hand doesn't seem to mind having the same port
2975          * selected in multiple power seqeuencers, but let's clear the
2976          * port select always when logically disconnecting a power sequencer
2977          * from a port.
2978          */
2979         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2980                       pipe_name(pipe), port_name(intel_dig_port->port));
2981         I915_WRITE(pp_on_reg, 0);
2982         POSTING_READ(pp_on_reg);
2983
2984         intel_dp->pps_pipe = INVALID_PIPE;
2985 }
2986
2987 static void vlv_steal_power_sequencer(struct drm_device *dev,
2988                                       enum pipe pipe)
2989 {
2990         struct drm_i915_private *dev_priv = to_i915(dev);
2991         struct intel_encoder *encoder;
2992
2993         lockdep_assert_held(&dev_priv->pps_mutex);
2994
2995         for_each_intel_encoder(dev, encoder) {
2996                 struct intel_dp *intel_dp;
2997                 enum port port;
2998
2999                 if (encoder->type != INTEL_OUTPUT_DP &&
3000                     encoder->type != INTEL_OUTPUT_EDP)
3001                         continue;
3002
3003                 intel_dp = enc_to_intel_dp(&encoder->base);
3004                 port = dp_to_dig_port(intel_dp)->port;
3005
3006                 WARN(intel_dp->active_pipe == pipe,
3007                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3008                      pipe_name(pipe), port_name(port));
3009
3010                 if (intel_dp->pps_pipe != pipe)
3011                         continue;
3012
3013                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3014                               pipe_name(pipe), port_name(port));
3015
3016                 /* make sure vdd is off before we steal it */
3017                 vlv_detach_power_sequencer(intel_dp);
3018         }
3019 }
3020
3021 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
3022 {
3023         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3024         struct intel_encoder *encoder = &intel_dig_port->base;
3025         struct drm_device *dev = encoder->base.dev;
3026         struct drm_i915_private *dev_priv = to_i915(dev);
3027         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3028
3029         lockdep_assert_held(&dev_priv->pps_mutex);
3030
3031         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3032
3033         if (intel_dp->pps_pipe != INVALID_PIPE &&
3034             intel_dp->pps_pipe != crtc->pipe) {
3035                 /*
3036                  * If another power sequencer was being used on this
3037                  * port previously make sure to turn off vdd there while
3038                  * we still have control of it.
3039                  */
3040                 vlv_detach_power_sequencer(intel_dp);
3041         }
3042
3043         /*
3044          * We may be stealing the power
3045          * sequencer from another port.
3046          */
3047         vlv_steal_power_sequencer(dev, crtc->pipe);
3048
3049         intel_dp->active_pipe = crtc->pipe;
3050
3051         if (!intel_dp_is_edp(intel_dp))
3052                 return;
3053
3054         /* now it's all ours */
3055         intel_dp->pps_pipe = crtc->pipe;
3056
3057         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3058                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3059
3060         /* init power sequencer on this pipe and port */
3061         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3062         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3063 }
3064
3065 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3066                               const struct intel_crtc_state *pipe_config,
3067                               const struct drm_connector_state *conn_state)
3068 {
3069         vlv_phy_pre_encoder_enable(encoder);
3070
3071         intel_enable_dp(encoder, pipe_config, conn_state);
3072 }
3073
3074 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3075                                   const struct intel_crtc_state *pipe_config,
3076                                   const struct drm_connector_state *conn_state)
3077 {
3078         intel_dp_prepare(encoder, pipe_config);
3079
3080         vlv_phy_pre_pll_enable(encoder);
3081 }
3082
3083 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3084                               const struct intel_crtc_state *pipe_config,
3085                               const struct drm_connector_state *conn_state)
3086 {
3087         chv_phy_pre_encoder_enable(encoder);
3088
3089         intel_enable_dp(encoder, pipe_config, conn_state);
3090
3091         /* Second common lane will stay alive on its own now */
3092         chv_phy_release_cl2_override(encoder);
3093 }
3094
3095 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3096                                   const struct intel_crtc_state *pipe_config,
3097                                   const struct drm_connector_state *conn_state)
3098 {
3099         intel_dp_prepare(encoder, pipe_config);
3100
3101         chv_phy_pre_pll_enable(encoder);
3102 }
3103
3104 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3105                                     const struct intel_crtc_state *pipe_config,
3106                                     const struct drm_connector_state *conn_state)
3107 {
3108         chv_phy_post_pll_disable(encoder);
3109 }
3110
3111 /*
3112  * Fetch AUX CH registers 0x202 - 0x207 which contain
3113  * link status information
3114  */
3115 bool
3116 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3117 {
3118         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3119                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3120 }
3121
3122 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3123 {
3124         uint8_t psr_caps = 0;
3125
3126         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3127                 return false;
3128         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3129 }
3130
3131 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3132 {
3133         uint8_t dprx = 0;
3134
3135         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3136                               &dprx) != 1)
3137                 return false;
3138         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3139 }
3140
3141 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3142 {
3143         uint8_t alpm_caps = 0;
3144
3145         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3146                               &alpm_caps) != 1)
3147                 return false;
3148         return alpm_caps & DP_ALPM_CAP;
3149 }
3150
3151 /* These are source-specific values. */
3152 uint8_t
3153 intel_dp_voltage_max(struct intel_dp *intel_dp)
3154 {
3155         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3156         enum port port = dp_to_dig_port(intel_dp)->port;
3157
3158         if (INTEL_GEN(dev_priv) >= 9) {
3159                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3160                 return intel_ddi_dp_voltage_max(encoder);
3161         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3162                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3163         else if (IS_GEN7(dev_priv) && port == PORT_A)
3164                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3165         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3166                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3167         else
3168                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3169 }
3170
3171 uint8_t
3172 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3173 {
3174         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3175         enum port port = dp_to_dig_port(intel_dp)->port;
3176
3177         if (INTEL_GEN(dev_priv) >= 9) {
3178                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3179                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3180                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3181                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3182                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3183                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3184                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3185                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3186                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3187                 default:
3188                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3189                 }
3190         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3191                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3192                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3193                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3195                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3196                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3197                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3199                 default:
3200                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3201                 }
3202         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3203                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3205                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3206                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3207                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3209                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3210                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3211                 default:
3212                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3213                 }
3214         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3215                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3216                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3217                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3218                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3219                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3220                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3221                 default:
3222                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3223                 }
3224         } else {
3225                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3226                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3227                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3228                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3229                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3230                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3231                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3232                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3233                 default:
3234                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3235                 }
3236         }
3237 }
3238
3239 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3240 {
3241         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3242         unsigned long demph_reg_value, preemph_reg_value,
3243                 uniqtranscale_reg_value;
3244         uint8_t train_set = intel_dp->train_set[0];
3245
3246         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3247         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3248                 preemph_reg_value = 0x0004000;
3249                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3250                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3251                         demph_reg_value = 0x2B405555;
3252                         uniqtranscale_reg_value = 0x552AB83A;
3253                         break;
3254                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3255                         demph_reg_value = 0x2B404040;
3256                         uniqtranscale_reg_value = 0x5548B83A;
3257                         break;
3258                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3259                         demph_reg_value = 0x2B245555;
3260                         uniqtranscale_reg_value = 0x5560B83A;
3261                         break;
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3263                         demph_reg_value = 0x2B405555;
3264                         uniqtranscale_reg_value = 0x5598DA3A;
3265                         break;
3266                 default:
3267                         return 0;
3268                 }
3269                 break;
3270         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3271                 preemph_reg_value = 0x0002000;
3272                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3273                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3274                         demph_reg_value = 0x2B404040;
3275                         uniqtranscale_reg_value = 0x5552B83A;
3276                         break;
3277                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3278                         demph_reg_value = 0x2B404848;
3279                         uniqtranscale_reg_value = 0x5580B83A;
3280                         break;
3281                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3282                         demph_reg_value = 0x2B404040;
3283                         uniqtranscale_reg_value = 0x55ADDA3A;
3284                         break;
3285                 default:
3286                         return 0;
3287                 }
3288                 break;
3289         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3290                 preemph_reg_value = 0x0000000;
3291                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3292                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3293                         demph_reg_value = 0x2B305555;
3294                         uniqtranscale_reg_value = 0x5570B83A;
3295                         break;
3296                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3297                         demph_reg_value = 0x2B2B4040;
3298                         uniqtranscale_reg_value = 0x55ADDA3A;
3299                         break;
3300                 default:
3301                         return 0;
3302                 }
3303                 break;
3304         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3305                 preemph_reg_value = 0x0006000;
3306                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3307                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3308                         demph_reg_value = 0x1B405555;
3309                         uniqtranscale_reg_value = 0x55ADDA3A;
3310                         break;
3311                 default:
3312                         return 0;
3313                 }
3314                 break;
3315         default:
3316                 return 0;
3317         }
3318
3319         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3320                                  uniqtranscale_reg_value, 0);
3321
3322         return 0;
3323 }
3324
3325 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3326 {
3327         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3328         u32 deemph_reg_value, margin_reg_value;
3329         bool uniq_trans_scale = false;
3330         uint8_t train_set = intel_dp->train_set[0];
3331
3332         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3333         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3334                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3335                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3336                         deemph_reg_value = 128;
3337                         margin_reg_value = 52;
3338                         break;
3339                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3340                         deemph_reg_value = 128;
3341                         margin_reg_value = 77;
3342                         break;
3343                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3344                         deemph_reg_value = 128;
3345                         margin_reg_value = 102;
3346                         break;
3347                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3348                         deemph_reg_value = 128;
3349                         margin_reg_value = 154;
3350                         uniq_trans_scale = true;
3351                         break;
3352                 default:
3353                         return 0;
3354                 }
3355                 break;
3356         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3357                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3358                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3359                         deemph_reg_value = 85;
3360                         margin_reg_value = 78;
3361                         break;
3362                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3363                         deemph_reg_value = 85;
3364                         margin_reg_value = 116;
3365                         break;
3366                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3367                         deemph_reg_value = 85;
3368                         margin_reg_value = 154;
3369                         break;
3370                 default:
3371                         return 0;
3372                 }
3373                 break;
3374         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3375                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3376                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3377                         deemph_reg_value = 64;
3378                         margin_reg_value = 104;
3379                         break;
3380                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3381                         deemph_reg_value = 64;
3382                         margin_reg_value = 154;
3383                         break;
3384                 default:
3385                         return 0;
3386                 }
3387                 break;
3388         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3389                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3390                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3391                         deemph_reg_value = 43;
3392                         margin_reg_value = 154;
3393                         break;
3394                 default:
3395                         return 0;
3396                 }
3397                 break;
3398         default:
3399                 return 0;
3400         }
3401
3402         chv_set_phy_signal_level(encoder, deemph_reg_value,
3403                                  margin_reg_value, uniq_trans_scale);
3404
3405         return 0;
3406 }
3407
3408 static uint32_t
3409 gen4_signal_levels(uint8_t train_set)
3410 {
3411         uint32_t        signal_levels = 0;
3412
3413         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3414         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3415         default:
3416                 signal_levels |= DP_VOLTAGE_0_4;
3417                 break;
3418         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3419                 signal_levels |= DP_VOLTAGE_0_6;
3420                 break;
3421         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3422                 signal_levels |= DP_VOLTAGE_0_8;
3423                 break;
3424         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3425                 signal_levels |= DP_VOLTAGE_1_2;
3426                 break;
3427         }
3428         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3429         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3430         default:
3431                 signal_levels |= DP_PRE_EMPHASIS_0;
3432                 break;
3433         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3434                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3435                 break;
3436         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3437                 signal_levels |= DP_PRE_EMPHASIS_6;
3438                 break;
3439         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3440                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3441                 break;
3442         }
3443         return signal_levels;
3444 }
3445
3446 /* Gen6's DP voltage swing and pre-emphasis control */
3447 static uint32_t
3448 gen6_edp_signal_levels(uint8_t train_set)
3449 {
3450         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3451                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3452         switch (signal_levels) {
3453         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3454         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3455                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3456         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3457                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3458         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3459         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3460                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3461         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3462         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3463                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3464         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3465         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3466                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3467         default:
3468                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3469                               "0x%x\n", signal_levels);
3470                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3471         }
3472 }
3473
3474 /* Gen7's DP voltage swing and pre-emphasis control */
3475 static uint32_t
3476 gen7_edp_signal_levels(uint8_t train_set)
3477 {
3478         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3479                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3480         switch (signal_levels) {
3481         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3482                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3483         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3484                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3485         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3486                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3487
3488         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3489                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3490         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3491                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3492
3493         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3494                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3495         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3496                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3497
3498         default:
3499                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3500                               "0x%x\n", signal_levels);
3501                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3502         }
3503 }
3504
3505 void
3506 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3507 {
3508         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3509         enum port port = intel_dig_port->port;
3510         struct drm_device *dev = intel_dig_port->base.base.dev;
3511         struct drm_i915_private *dev_priv = to_i915(dev);
3512         uint32_t signal_levels, mask = 0;
3513         uint8_t train_set = intel_dp->train_set[0];
3514
3515         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3516                 signal_levels = bxt_signal_levels(intel_dp);
3517         } else if (HAS_DDI(dev_priv)) {
3518                 signal_levels = ddi_signal_levels(intel_dp);
3519                 mask = DDI_BUF_EMP_MASK;
3520         } else if (IS_CHERRYVIEW(dev_priv)) {
3521                 signal_levels = chv_signal_levels(intel_dp);
3522         } else if (IS_VALLEYVIEW(dev_priv)) {
3523                 signal_levels = vlv_signal_levels(intel_dp);
3524         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3525                 signal_levels = gen7_edp_signal_levels(train_set);
3526                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3527         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3528                 signal_levels = gen6_edp_signal_levels(train_set);
3529                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3530         } else {
3531                 signal_levels = gen4_signal_levels(train_set);
3532                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3533         }
3534
3535         if (mask)
3536                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3537
3538         DRM_DEBUG_KMS("Using vswing level %d\n",
3539                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3540         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3541                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3542                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3543
3544         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3545
3546         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3547         POSTING_READ(intel_dp->output_reg);
3548 }
3549
3550 void
3551 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3552                                        uint8_t dp_train_pat)
3553 {
3554         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3555         struct drm_i915_private *dev_priv =
3556                 to_i915(intel_dig_port->base.base.dev);
3557
3558         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3559
3560         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3561         POSTING_READ(intel_dp->output_reg);
3562 }
3563
3564 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3565 {
3566         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3567         struct drm_device *dev = intel_dig_port->base.base.dev;
3568         struct drm_i915_private *dev_priv = to_i915(dev);
3569         enum port port = intel_dig_port->port;
3570         uint32_t val;
3571
3572         if (!HAS_DDI(dev_priv))
3573                 return;
3574
3575         val = I915_READ(DP_TP_CTL(port));
3576         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3577         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3578         I915_WRITE(DP_TP_CTL(port), val);
3579
3580         /*
3581          * On PORT_A we can have only eDP in SST mode. There the only reason
3582          * we need to set idle transmission mode is to work around a HW issue
3583          * where we enable the pipe while not in idle link-training mode.
3584          * In this case there is requirement to wait for a minimum number of
3585          * idle patterns to be sent.
3586          */
3587         if (port == PORT_A)
3588                 return;
3589
3590         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3591                                     DP_TP_STATUS_IDLE_DONE,
3592                                     DP_TP_STATUS_IDLE_DONE,
3593                                     1))
3594                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3595 }
3596
3597 static void
3598 intel_dp_link_down(struct intel_dp *intel_dp)
3599 {
3600         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3601         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3602         enum port port = intel_dig_port->port;
3603         struct drm_device *dev = intel_dig_port->base.base.dev;
3604         struct drm_i915_private *dev_priv = to_i915(dev);
3605         uint32_t DP = intel_dp->DP;
3606
3607         if (WARN_ON(HAS_DDI(dev_priv)))
3608                 return;
3609
3610         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3611                 return;
3612
3613         DRM_DEBUG_KMS("\n");
3614
3615         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3616             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3617                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3618                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3619         } else {
3620                 if (IS_CHERRYVIEW(dev_priv))
3621                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3622                 else
3623                         DP &= ~DP_LINK_TRAIN_MASK;
3624                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3625         }
3626         I915_WRITE(intel_dp->output_reg, DP);
3627         POSTING_READ(intel_dp->output_reg);
3628
3629         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3630         I915_WRITE(intel_dp->output_reg, DP);
3631         POSTING_READ(intel_dp->output_reg);
3632
3633         /*
3634          * HW workaround for IBX, we need to move the port
3635          * to transcoder A after disabling it to allow the
3636          * matching HDMI port to be enabled on transcoder A.
3637          */
3638         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3639                 /*
3640                  * We get CPU/PCH FIFO underruns on the other pipe when
3641                  * doing the workaround. Sweep them under the rug.
3642                  */
3643                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3644                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3645
3646                 /* always enable with pattern 1 (as per spec) */
3647                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3648                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3649                 I915_WRITE(intel_dp->output_reg, DP);
3650                 POSTING_READ(intel_dp->output_reg);
3651
3652                 DP &= ~DP_PORT_EN;
3653                 I915_WRITE(intel_dp->output_reg, DP);
3654                 POSTING_READ(intel_dp->output_reg);
3655
3656                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3657                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3658                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3659         }
3660
3661         msleep(intel_dp->panel_power_down_delay);
3662
3663         intel_dp->DP = DP;
3664
3665         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3666                 pps_lock(intel_dp);
3667                 intel_dp->active_pipe = INVALID_PIPE;
3668                 pps_unlock(intel_dp);
3669         }
3670 }
3671
3672 bool
3673 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3674 {
3675         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3676                              sizeof(intel_dp->dpcd)) < 0)
3677                 return false; /* aux transfer failed */
3678
3679         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3680
3681         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3682 }
3683
3684 static bool
3685 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3686 {
3687         struct drm_i915_private *dev_priv =
3688                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3689
3690         /* this function is meant to be called only once */
3691         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3692
3693         if (!intel_dp_read_dpcd(intel_dp))
3694                 return false;
3695
3696         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3697                          drm_dp_is_branch(intel_dp->dpcd));
3698
3699         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3700                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3701                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3702
3703         /* Check if the panel supports PSR */
3704         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3705                          intel_dp->psr_dpcd,
3706                          sizeof(intel_dp->psr_dpcd));
3707         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3708                 dev_priv->psr.sink_support = true;
3709                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3710         }
3711
3712         if (INTEL_GEN(dev_priv) >= 9 &&
3713             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3714                 uint8_t frame_sync_cap;
3715
3716                 dev_priv->psr.sink_support = true;
3717                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3718                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3719                                       &frame_sync_cap) != 1)
3720                         frame_sync_cap = 0;
3721                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3722                 /* PSR2 needs frame sync as well */
3723                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3724                 DRM_DEBUG_KMS("PSR2 %s on sink",
3725                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3726
3727                 if (dev_priv->psr.psr2_support) {
3728                         dev_priv->psr.y_cord_support =
3729                                 intel_dp_get_y_cord_status(intel_dp);
3730                         dev_priv->psr.colorimetry_support =
3731                                 intel_dp_get_colorimetry_status(intel_dp);
3732                         dev_priv->psr.alpm =
3733                                 intel_dp_get_alpm_status(intel_dp);
3734                 }
3735
3736         }
3737
3738         /*
3739          * Read the eDP display control registers.
3740          *
3741          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3742          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3743          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3744          * method). The display control registers should read zero if they're
3745          * not supported anyway.
3746          */
3747         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3748                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3749                              sizeof(intel_dp->edp_dpcd))
3750                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3751                               intel_dp->edp_dpcd);
3752
3753         /* Intermediate frequency support */
3754         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3755                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3756                 int i;
3757
3758                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3759                                 sink_rates, sizeof(sink_rates));
3760
3761                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3762                         int val = le16_to_cpu(sink_rates[i]);
3763
3764                         if (val == 0)
3765                                 break;
3766
3767                         /* Value read multiplied by 200kHz gives the per-lane
3768                          * link rate in kHz. The source rates are, however,
3769                          * stored in terms of LS_Clk kHz. The full conversion
3770                          * back to symbols is
3771                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3772                          */
3773                         intel_dp->sink_rates[i] = (val * 200) / 10;
3774                 }
3775                 intel_dp->num_sink_rates = i;
3776         }
3777
3778         if (intel_dp->num_sink_rates)
3779                 intel_dp->use_rate_select = true;
3780         else
3781                 intel_dp_set_sink_rates(intel_dp);
3782
3783         intel_dp_set_common_rates(intel_dp);
3784
3785         return true;
3786 }
3787
3788
3789 static bool
3790 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3791 {
3792         u8 sink_count;
3793
3794         if (!intel_dp_read_dpcd(intel_dp))
3795                 return false;
3796
3797         /* Don't clobber cached eDP rates. */
3798         if (!intel_dp_is_edp(intel_dp)) {
3799                 intel_dp_set_sink_rates(intel_dp);
3800                 intel_dp_set_common_rates(intel_dp);
3801         }
3802
3803         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3804                 return false;
3805
3806         /*
3807          * Sink count can change between short pulse hpd hence
3808          * a member variable in intel_dp will track any changes
3809          * between short pulse interrupts.
3810          */
3811         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3812
3813         /*
3814          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3815          * a dongle is present but no display. Unless we require to know
3816          * if a dongle is present or not, we don't need to update
3817          * downstream port information. So, an early return here saves
3818          * time from performing other operations which are not required.
3819          */
3820         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3821                 return false;
3822
3823         if (!drm_dp_is_branch(intel_dp->dpcd))
3824                 return true; /* native DP sink */
3825
3826         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3827                 return true; /* no per-port downstream info */
3828
3829         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3830                              intel_dp->downstream_ports,
3831                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3832                 return false; /* downstream port status fetch failed */
3833
3834         return true;
3835 }
3836
3837 static bool
3838 intel_dp_can_mst(struct intel_dp *intel_dp)
3839 {
3840         u8 mstm_cap;
3841
3842         if (!i915_modparams.enable_dp_mst)
3843                 return false;
3844
3845         if (!intel_dp->can_mst)
3846                 return false;
3847
3848         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3849                 return false;
3850
3851         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3852                 return false;
3853
3854         return mstm_cap & DP_MST_CAP;
3855 }
3856
3857 static void
3858 intel_dp_configure_mst(struct intel_dp *intel_dp)
3859 {
3860         if (!i915_modparams.enable_dp_mst)
3861                 return;
3862
3863         if (!intel_dp->can_mst)
3864                 return;
3865
3866         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3867
3868         if (intel_dp->is_mst)
3869                 DRM_DEBUG_KMS("Sink is MST capable\n");
3870         else
3871                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3872
3873         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3874                                         intel_dp->is_mst);
3875 }
3876
3877 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3878 {
3879         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3880         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3881         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3882         u8 buf;
3883         int ret = 0;
3884         int count = 0;
3885         int attempts = 10;
3886
3887         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3888                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3889                 ret = -EIO;
3890                 goto out;
3891         }
3892
3893         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3894                                buf & ~DP_TEST_SINK_START) < 0) {
3895                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3896                 ret = -EIO;
3897                 goto out;
3898         }
3899
3900         do {
3901                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3902
3903                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3904                                       DP_TEST_SINK_MISC, &buf) < 0) {
3905                         ret = -EIO;
3906                         goto out;
3907                 }
3908                 count = buf & DP_TEST_COUNT_MASK;
3909         } while (--attempts && count);
3910
3911         if (attempts == 0) {
3912                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3913                 ret = -ETIMEDOUT;
3914         }
3915
3916  out:
3917         hsw_enable_ips(intel_crtc);
3918         return ret;
3919 }
3920
3921 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3922 {
3923         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3924         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3925         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3926         u8 buf;
3927         int ret;
3928
3929         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3930                 return -EIO;
3931
3932         if (!(buf & DP_TEST_CRC_SUPPORTED))
3933                 return -ENOTTY;
3934
3935         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3936                 return -EIO;
3937
3938         if (buf & DP_TEST_SINK_START) {
3939                 ret = intel_dp_sink_crc_stop(intel_dp);
3940                 if (ret)
3941                         return ret;
3942         }
3943
3944         hsw_disable_ips(intel_crtc);
3945
3946         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3947                                buf | DP_TEST_SINK_START) < 0) {
3948                 hsw_enable_ips(intel_crtc);
3949                 return -EIO;
3950         }
3951
3952         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3953         return 0;
3954 }
3955
3956 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3957 {
3958         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3959         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3960         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3961         u8 buf;
3962         int count, ret;
3963         int attempts = 6;
3964
3965         ret = intel_dp_sink_crc_start(intel_dp);
3966         if (ret)
3967                 return ret;
3968
3969         do {
3970                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3971
3972                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3973                                       DP_TEST_SINK_MISC, &buf) < 0) {
3974                         ret = -EIO;
3975                         goto stop;
3976                 }
3977                 count = buf & DP_TEST_COUNT_MASK;
3978
3979         } while (--attempts && count == 0);
3980
3981         if (attempts == 0) {
3982                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3983                 ret = -ETIMEDOUT;
3984                 goto stop;
3985         }
3986
3987         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3988                 ret = -EIO;
3989                 goto stop;
3990         }
3991
3992 stop:
3993         intel_dp_sink_crc_stop(intel_dp);
3994         return ret;
3995 }
3996
3997 static bool
3998 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3999 {
4000         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4001                                  sink_irq_vector) == 1;
4002 }
4003
4004 static bool
4005 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4006 {
4007         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4008                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4009                 DP_DPRX_ESI_LEN;
4010 }
4011
4012 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4013 {
4014         int status = 0;
4015         int test_link_rate;
4016         uint8_t test_lane_count, test_link_bw;
4017         /* (DP CTS 1.2)
4018          * 4.3.1.11
4019          */
4020         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4021         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4022                                    &test_lane_count);
4023
4024         if (status <= 0) {
4025                 DRM_DEBUG_KMS("Lane count read failed\n");
4026                 return DP_TEST_NAK;
4027         }
4028         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4029
4030         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4031                                    &test_link_bw);
4032         if (status <= 0) {
4033                 DRM_DEBUG_KMS("Link Rate read failed\n");
4034                 return DP_TEST_NAK;
4035         }
4036         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4037
4038         /* Validate the requested link rate and lane count */
4039         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4040                                         test_lane_count))
4041                 return DP_TEST_NAK;
4042
4043         intel_dp->compliance.test_lane_count = test_lane_count;
4044         intel_dp->compliance.test_link_rate = test_link_rate;
4045
4046         return DP_TEST_ACK;
4047 }
4048
4049 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4050 {
4051         uint8_t test_pattern;
4052         uint8_t test_misc;
4053         __be16 h_width, v_height;
4054         int status = 0;
4055
4056         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4057         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4058                                    &test_pattern);
4059         if (status <= 0) {
4060                 DRM_DEBUG_KMS("Test pattern read failed\n");
4061                 return DP_TEST_NAK;
4062         }
4063         if (test_pattern != DP_COLOR_RAMP)
4064                 return DP_TEST_NAK;
4065
4066         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4067                                   &h_width, 2);
4068         if (status <= 0) {
4069                 DRM_DEBUG_KMS("H Width read failed\n");
4070                 return DP_TEST_NAK;
4071         }
4072
4073         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4074                                   &v_height, 2);
4075         if (status <= 0) {
4076                 DRM_DEBUG_KMS("V Height read failed\n");
4077                 return DP_TEST_NAK;
4078         }
4079
4080         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4081                                    &test_misc);
4082         if (status <= 0) {
4083                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4084                 return DP_TEST_NAK;
4085         }
4086         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4087                 return DP_TEST_NAK;
4088         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4089                 return DP_TEST_NAK;
4090         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4091         case DP_TEST_BIT_DEPTH_6:
4092                 intel_dp->compliance.test_data.bpc = 6;
4093                 break;
4094         case DP_TEST_BIT_DEPTH_8:
4095                 intel_dp->compliance.test_data.bpc = 8;
4096                 break;
4097         default:
4098                 return DP_TEST_NAK;
4099         }
4100
4101         intel_dp->compliance.test_data.video_pattern = test_pattern;
4102         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4103         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4104         /* Set test active flag here so userspace doesn't interrupt things */
4105         intel_dp->compliance.test_active = 1;
4106
4107         return DP_TEST_ACK;
4108 }
4109
4110 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4111 {
4112         uint8_t test_result = DP_TEST_ACK;
4113         struct intel_connector *intel_connector = intel_dp->attached_connector;
4114         struct drm_connector *connector = &intel_connector->base;
4115
4116         if (intel_connector->detect_edid == NULL ||
4117             connector->edid_corrupt ||
4118             intel_dp->aux.i2c_defer_count > 6) {
4119                 /* Check EDID read for NACKs, DEFERs and corruption
4120                  * (DP CTS 1.2 Core r1.1)
4121                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4122                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4123                  *    4.2.2.6 : EDID corruption detected
4124                  * Use failsafe mode for all cases
4125                  */
4126                 if (intel_dp->aux.i2c_nack_count > 0 ||
4127                         intel_dp->aux.i2c_defer_count > 0)
4128                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4129                                       intel_dp->aux.i2c_nack_count,
4130                                       intel_dp->aux.i2c_defer_count);
4131                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4132         } else {
4133                 struct edid *block = intel_connector->detect_edid;
4134
4135                 /* We have to write the checksum
4136                  * of the last block read
4137                  */
4138                 block += intel_connector->detect_edid->extensions;
4139
4140                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4141                                        block->checksum) <= 0)
4142                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4143
4144                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4145                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4146         }
4147
4148         /* Set test active flag here so userspace doesn't interrupt things */
4149         intel_dp->compliance.test_active = 1;
4150
4151         return test_result;
4152 }
4153
4154 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4155 {
4156         uint8_t test_result = DP_TEST_NAK;
4157         return test_result;
4158 }
4159
4160 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4161 {
4162         uint8_t response = DP_TEST_NAK;
4163         uint8_t request = 0;
4164         int status;
4165
4166         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4167         if (status <= 0) {
4168                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4169                 goto update_status;
4170         }
4171
4172         switch (request) {
4173         case DP_TEST_LINK_TRAINING:
4174                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4175                 response = intel_dp_autotest_link_training(intel_dp);
4176                 break;
4177         case DP_TEST_LINK_VIDEO_PATTERN:
4178                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4179                 response = intel_dp_autotest_video_pattern(intel_dp);
4180                 break;
4181         case DP_TEST_LINK_EDID_READ:
4182                 DRM_DEBUG_KMS("EDID test requested\n");
4183                 response = intel_dp_autotest_edid(intel_dp);
4184                 break;
4185         case DP_TEST_LINK_PHY_TEST_PATTERN:
4186                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4187                 response = intel_dp_autotest_phy_pattern(intel_dp);
4188                 break;
4189         default:
4190                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4191                 break;
4192         }
4193
4194         if (response & DP_TEST_ACK)
4195                 intel_dp->compliance.test_type = request;
4196
4197 update_status:
4198         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4199         if (status <= 0)
4200                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4201 }
4202
4203 static int
4204 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4205 {
4206         bool bret;
4207
4208         if (intel_dp->is_mst) {
4209                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4210                 int ret = 0;
4211                 int retry;
4212                 bool handled;
4213                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4214 go_again:
4215                 if (bret == true) {
4216
4217                         /* check link status - esi[10] = 0x200c */
4218                         if (intel_dp->active_mst_links &&
4219                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4220                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4221                                 intel_dp_start_link_train(intel_dp);
4222                                 intel_dp_stop_link_train(intel_dp);
4223                         }
4224
4225                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4226                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4227
4228                         if (handled) {
4229                                 for (retry = 0; retry < 3; retry++) {
4230                                         int wret;
4231                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4232                                                                  DP_SINK_COUNT_ESI+1,
4233                                                                  &esi[1], 3);
4234                                         if (wret == 3) {
4235                                                 break;
4236                                         }
4237                                 }
4238
4239                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4240                                 if (bret == true) {
4241                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4242                                         goto go_again;
4243                                 }
4244                         } else
4245                                 ret = 0;
4246
4247                         return ret;
4248                 } else {
4249                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4250                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4251                         intel_dp->is_mst = false;
4252                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4253                         /* send a hotplug event */
4254                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4255                 }
4256         }
4257         return -EINVAL;
4258 }
4259
4260 static void
4261 intel_dp_retrain_link(struct intel_dp *intel_dp)
4262 {
4263         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4265         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4266
4267         /* Suppress underruns caused by re-training */
4268         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4269         if (crtc->config->has_pch_encoder)
4270                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4271                                                       intel_crtc_pch_transcoder(crtc), false);
4272
4273         intel_dp_start_link_train(intel_dp);
4274         intel_dp_stop_link_train(intel_dp);
4275
4276         /* Keep underrun reporting disabled until things are stable */
4277         intel_wait_for_vblank(dev_priv, crtc->pipe);
4278
4279         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4280         if (crtc->config->has_pch_encoder)
4281                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4282                                                       intel_crtc_pch_transcoder(crtc), true);
4283 }
4284
4285 static void
4286 intel_dp_check_link_status(struct intel_dp *intel_dp)
4287 {
4288         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4289         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4290         u8 link_status[DP_LINK_STATUS_SIZE];
4291
4292         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4293
4294         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4295                 DRM_ERROR("Failed to get link status\n");
4296                 return;
4297         }
4298
4299         if (!intel_encoder->base.crtc)
4300                 return;
4301
4302         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4303                 return;
4304
4305         /*
4306          * Validate the cached values of intel_dp->link_rate and
4307          * intel_dp->lane_count before attempting to retrain.
4308          */
4309         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4310                                         intel_dp->lane_count))
4311                 return;
4312
4313         /* Retrain if Channel EQ or CR not ok */
4314         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4315                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4316                               intel_encoder->base.name);
4317
4318                 intel_dp_retrain_link(intel_dp);
4319         }
4320 }
4321
4322 /*
4323  * According to DP spec
4324  * 5.1.2:
4325  *  1. Read DPCD
4326  *  2. Configure link according to Receiver Capabilities
4327  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4328  *  4. Check link status on receipt of hot-plug interrupt
4329  *
4330  * intel_dp_short_pulse -  handles short pulse interrupts
4331  * when full detection is not required.
4332  * Returns %true if short pulse is handled and full detection
4333  * is NOT required and %false otherwise.
4334  */
4335 static bool
4336 intel_dp_short_pulse(struct intel_dp *intel_dp)
4337 {
4338         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4339         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4340         u8 sink_irq_vector = 0;
4341         u8 old_sink_count = intel_dp->sink_count;
4342         bool ret;
4343
4344         /*
4345          * Clearing compliance test variables to allow capturing
4346          * of values for next automated test request.
4347          */
4348         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4349
4350         /*
4351          * Now read the DPCD to see if it's actually running
4352          * If the current value of sink count doesn't match with
4353          * the value that was stored earlier or dpcd read failed
4354          * we need to do full detection
4355          */
4356         ret = intel_dp_get_dpcd(intel_dp);
4357
4358         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4359                 /* No need to proceed if we are going to do full detect */
4360                 return false;
4361         }
4362
4363         /* Try to read the source of the interrupt */
4364         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4365             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4366             sink_irq_vector != 0) {
4367                 /* Clear interrupt source */
4368                 drm_dp_dpcd_writeb(&intel_dp->aux,
4369                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4370                                    sink_irq_vector);
4371
4372                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4373                         intel_dp_handle_test_request(intel_dp);
4374                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4375                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4376         }
4377
4378         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4379         intel_dp_check_link_status(intel_dp);
4380         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4381         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4382                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4383                 /* Send a Hotplug Uevent to userspace to start modeset */
4384                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4385         }
4386
4387         return true;
4388 }
4389
4390 /* XXX this is probably wrong for multiple downstream ports */
4391 static enum drm_connector_status
4392 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4393 {
4394         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4395         uint8_t *dpcd = intel_dp->dpcd;
4396         uint8_t type;
4397
4398         if (lspcon->active)
4399                 lspcon_resume(lspcon);
4400
4401         if (!intel_dp_get_dpcd(intel_dp))
4402                 return connector_status_disconnected;
4403
4404         if (intel_dp_is_edp(intel_dp))
4405                 return connector_status_connected;
4406
4407         /* if there's no downstream port, we're done */
4408         if (!drm_dp_is_branch(dpcd))
4409                 return connector_status_connected;
4410
4411         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4412         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4413             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4414
4415                 return intel_dp->sink_count ?
4416                 connector_status_connected : connector_status_disconnected;
4417         }
4418
4419         if (intel_dp_can_mst(intel_dp))
4420                 return connector_status_connected;
4421
4422         /* If no HPD, poke DDC gently */
4423         if (drm_probe_ddc(&intel_dp->aux.ddc))
4424                 return connector_status_connected;
4425
4426         /* Well we tried, say unknown for unreliable port types */
4427         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4428                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4429                 if (type == DP_DS_PORT_TYPE_VGA ||
4430                     type == DP_DS_PORT_TYPE_NON_EDID)
4431                         return connector_status_unknown;
4432         } else {
4433                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4434                         DP_DWN_STRM_PORT_TYPE_MASK;
4435                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4436                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4437                         return connector_status_unknown;
4438         }
4439
4440         /* Anything else is out of spec, warn and ignore */
4441         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4442         return connector_status_disconnected;
4443 }
4444
4445 static enum drm_connector_status
4446 edp_detect(struct intel_dp *intel_dp)
4447 {
4448         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4449         struct drm_i915_private *dev_priv = to_i915(dev);
4450         enum drm_connector_status status;
4451
4452         status = intel_panel_detect(dev_priv);
4453         if (status == connector_status_unknown)
4454                 status = connector_status_connected;
4455
4456         return status;
4457 }
4458
4459 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4460                                        struct intel_digital_port *port)
4461 {
4462         u32 bit;
4463
4464         switch (port->port) {
4465         case PORT_B:
4466                 bit = SDE_PORTB_HOTPLUG;
4467                 break;
4468         case PORT_C:
4469                 bit = SDE_PORTC_HOTPLUG;
4470                 break;
4471         case PORT_D:
4472                 bit = SDE_PORTD_HOTPLUG;
4473                 break;
4474         default:
4475                 MISSING_CASE(port->port);
4476                 return false;
4477         }
4478
4479         return I915_READ(SDEISR) & bit;
4480 }
4481
4482 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4483                                        struct intel_digital_port *port)
4484 {
4485         u32 bit;
4486
4487         switch (port->port) {
4488         case PORT_B:
4489                 bit = SDE_PORTB_HOTPLUG_CPT;
4490                 break;
4491         case PORT_C:
4492                 bit = SDE_PORTC_HOTPLUG_CPT;
4493                 break;
4494         case PORT_D:
4495                 bit = SDE_PORTD_HOTPLUG_CPT;
4496                 break;
4497         default:
4498                 MISSING_CASE(port->port);
4499                 return false;
4500         }
4501
4502         return I915_READ(SDEISR) & bit;
4503 }
4504
4505 static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
4506                                        struct intel_digital_port *port)
4507 {
4508         u32 bit;
4509
4510         switch (port->port) {
4511         case PORT_A:
4512                 bit = SDE_PORTA_HOTPLUG_SPT;
4513                 break;
4514         case PORT_E:
4515                 bit = SDE_PORTE_HOTPLUG_SPT;
4516                 break;
4517         default:
4518                 return cpt_digital_port_connected(dev_priv, port);
4519         }
4520
4521         return I915_READ(SDEISR) & bit;
4522 }
4523
4524 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4525                                        struct intel_digital_port *port)
4526 {
4527         u32 bit;
4528
4529         switch (port->port) {
4530         case PORT_B:
4531                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4532                 break;
4533         case PORT_C:
4534                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4535                 break;
4536         case PORT_D:
4537                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4538                 break;
4539         default:
4540                 MISSING_CASE(port->port);
4541                 return false;
4542         }
4543
4544         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4545 }
4546
4547 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4548                                         struct intel_digital_port *port)
4549 {
4550         u32 bit;
4551
4552         switch (port->port) {
4553         case PORT_B:
4554                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4555                 break;
4556         case PORT_C:
4557                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4558                 break;
4559         case PORT_D:
4560                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4561                 break;
4562         default:
4563                 MISSING_CASE(port->port);
4564                 return false;
4565         }
4566
4567         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4568 }
4569
4570 static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
4571                                        struct intel_digital_port *port)
4572 {
4573         if (port->port == PORT_A)
4574                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4575         else
4576                 return ibx_digital_port_connected(dev_priv, port);
4577 }
4578
4579 static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
4580                                        struct intel_digital_port *port)
4581 {
4582         if (port->port == PORT_A)
4583                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4584         else
4585                 return cpt_digital_port_connected(dev_priv, port);
4586 }
4587
4588 static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
4589                                        struct intel_digital_port *port)
4590 {
4591         if (port->port == PORT_A)
4592                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4593         else
4594                 return cpt_digital_port_connected(dev_priv, port);
4595 }
4596
4597 static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
4598                                        struct intel_digital_port *port)
4599 {
4600         if (port->port == PORT_A)
4601                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4602         else
4603                 return cpt_digital_port_connected(dev_priv, port);
4604 }
4605
4606 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4607                                        struct intel_digital_port *intel_dig_port)
4608 {
4609         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4610         enum port port;
4611         u32 bit;
4612
4613         port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
4614         switch (port) {
4615         case PORT_A:
4616                 bit = BXT_DE_PORT_HP_DDIA;
4617                 break;
4618         case PORT_B:
4619                 bit = BXT_DE_PORT_HP_DDIB;
4620                 break;
4621         case PORT_C:
4622                 bit = BXT_DE_PORT_HP_DDIC;
4623                 break;
4624         default:
4625                 MISSING_CASE(port);
4626                 return false;
4627         }
4628
4629         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4630 }
4631
4632 /*
4633  * intel_digital_port_connected - is the specified port connected?
4634  * @dev_priv: i915 private structure
4635  * @port: the port to test
4636  *
4637  * Return %true if @port is connected, %false otherwise.
4638  */
4639 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4640                                   struct intel_digital_port *port)
4641 {
4642         if (HAS_GMCH_DISPLAY(dev_priv)) {
4643                 if (IS_GM45(dev_priv))
4644                         return gm45_digital_port_connected(dev_priv, port);
4645                 else
4646                         return g4x_digital_port_connected(dev_priv, port);
4647         }
4648
4649         if (IS_GEN5(dev_priv))
4650                 return ilk_digital_port_connected(dev_priv, port);
4651         else if (IS_GEN6(dev_priv))
4652                 return snb_digital_port_connected(dev_priv, port);
4653         else if (IS_GEN7(dev_priv))
4654                 return ivb_digital_port_connected(dev_priv, port);
4655         else if (IS_GEN8(dev_priv))
4656                 return bdw_digital_port_connected(dev_priv, port);
4657         else if (IS_GEN9_LP(dev_priv))
4658                 return bxt_digital_port_connected(dev_priv, port);
4659         else
4660                 return spt_digital_port_connected(dev_priv, port);
4661 }
4662
4663 static struct edid *
4664 intel_dp_get_edid(struct intel_dp *intel_dp)
4665 {
4666         struct intel_connector *intel_connector = intel_dp->attached_connector;
4667
4668         /* use cached edid if we have one */
4669         if (intel_connector->edid) {
4670                 /* invalid edid */
4671                 if (IS_ERR(intel_connector->edid))
4672                         return NULL;
4673
4674                 return drm_edid_duplicate(intel_connector->edid);
4675         } else
4676                 return drm_get_edid(&intel_connector->base,
4677                                     &intel_dp->aux.ddc);
4678 }
4679
4680 static void
4681 intel_dp_set_edid(struct intel_dp *intel_dp)
4682 {
4683         struct intel_connector *intel_connector = intel_dp->attached_connector;
4684         struct edid *edid;
4685
4686         intel_dp_unset_edid(intel_dp);
4687         edid = intel_dp_get_edid(intel_dp);
4688         intel_connector->detect_edid = edid;
4689
4690         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4691 }
4692
4693 static void
4694 intel_dp_unset_edid(struct intel_dp *intel_dp)
4695 {
4696         struct intel_connector *intel_connector = intel_dp->attached_connector;
4697
4698         kfree(intel_connector->detect_edid);
4699         intel_connector->detect_edid = NULL;
4700
4701         intel_dp->has_audio = false;
4702 }
4703
4704 static int
4705 intel_dp_long_pulse(struct intel_connector *intel_connector)
4706 {
4707         struct drm_connector *connector = &intel_connector->base;
4708         struct intel_dp *intel_dp = intel_attached_dp(connector);
4709         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4710         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4711         struct drm_device *dev = connector->dev;
4712         enum drm_connector_status status;
4713         u8 sink_irq_vector = 0;
4714
4715         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4716
4717         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4718
4719         /* Can't disconnect eDP, but you can close the lid... */
4720         if (intel_dp_is_edp(intel_dp))
4721                 status = edp_detect(intel_dp);
4722         else if (intel_digital_port_connected(to_i915(dev),
4723                                               dp_to_dig_port(intel_dp)))
4724                 status = intel_dp_detect_dpcd(intel_dp);
4725         else
4726                 status = connector_status_disconnected;
4727
4728         if (status == connector_status_disconnected) {
4729                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4730
4731                 if (intel_dp->is_mst) {
4732                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4733                                       intel_dp->is_mst,
4734                                       intel_dp->mst_mgr.mst_state);
4735                         intel_dp->is_mst = false;
4736                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4737                                                         intel_dp->is_mst);
4738                 }
4739
4740                 goto out;
4741         }
4742
4743         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4744                 intel_encoder->type = INTEL_OUTPUT_DP;
4745
4746         if (intel_dp->reset_link_params) {
4747                 /* Initial max link lane count */
4748                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4749
4750                 /* Initial max link rate */
4751                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4752
4753                 intel_dp->reset_link_params = false;
4754         }
4755
4756         intel_dp_print_rates(intel_dp);
4757
4758         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4759                          drm_dp_is_branch(intel_dp->dpcd));
4760
4761         intel_dp_configure_mst(intel_dp);
4762
4763         if (intel_dp->is_mst) {
4764                 /*
4765                  * If we are in MST mode then this connector
4766                  * won't appear connected or have anything
4767                  * with EDID on it
4768                  */
4769                 status = connector_status_disconnected;
4770                 goto out;
4771         } else {
4772                 /*
4773                  * If display is now connected check links status,
4774                  * there has been known issues of link loss triggerring
4775                  * long pulse.
4776                  *
4777                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4778                  * weird HPD ping pong during modesets. So we can apparently
4779                  * end up with HPD going low during a modeset, and then
4780                  * going back up soon after. And once that happens we must
4781                  * retrain the link to get a picture. That's in case no
4782                  * userspace component reacted to intermittent HPD dip.
4783                  */
4784                 intel_dp_check_link_status(intel_dp);
4785         }
4786
4787         /*
4788          * Clearing NACK and defer counts to get their exact values
4789          * while reading EDID which are required by Compliance tests
4790          * 4.2.2.4 and 4.2.2.5
4791          */
4792         intel_dp->aux.i2c_nack_count = 0;
4793         intel_dp->aux.i2c_defer_count = 0;
4794
4795         intel_dp_set_edid(intel_dp);
4796         if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid)
4797                 status = connector_status_connected;
4798         intel_dp->detect_done = true;
4799
4800         /* Try to read the source of the interrupt */
4801         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4802             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4803             sink_irq_vector != 0) {
4804                 /* Clear interrupt source */
4805                 drm_dp_dpcd_writeb(&intel_dp->aux,
4806                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4807                                    sink_irq_vector);
4808
4809                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4810                         intel_dp_handle_test_request(intel_dp);
4811                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4812                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4813         }
4814
4815 out:
4816         if (status != connector_status_connected && !intel_dp->is_mst)
4817                 intel_dp_unset_edid(intel_dp);
4818
4819         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4820         return status;
4821 }
4822
4823 static int
4824 intel_dp_detect(struct drm_connector *connector,
4825                 struct drm_modeset_acquire_ctx *ctx,
4826                 bool force)
4827 {
4828         struct intel_dp *intel_dp = intel_attached_dp(connector);
4829         int status = connector->status;
4830
4831         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4832                       connector->base.id, connector->name);
4833
4834         /* If full detect is not performed yet, do a full detect */
4835         if (!intel_dp->detect_done)
4836                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4837
4838         intel_dp->detect_done = false;
4839
4840         return status;
4841 }
4842
4843 static void
4844 intel_dp_force(struct drm_connector *connector)
4845 {
4846         struct intel_dp *intel_dp = intel_attached_dp(connector);
4847         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4848         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4849
4850         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4851                       connector->base.id, connector->name);
4852         intel_dp_unset_edid(intel_dp);
4853
4854         if (connector->status != connector_status_connected)
4855                 return;
4856
4857         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4858
4859         intel_dp_set_edid(intel_dp);
4860
4861         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4862
4863         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4864                 intel_encoder->type = INTEL_OUTPUT_DP;
4865 }
4866
4867 static int intel_dp_get_modes(struct drm_connector *connector)
4868 {
4869         struct intel_connector *intel_connector = to_intel_connector(connector);
4870         struct edid *edid;
4871
4872         edid = intel_connector->detect_edid;
4873         if (edid) {
4874                 int ret = intel_connector_update_modes(connector, edid);
4875                 if (ret)
4876                         return ret;
4877         }
4878
4879         /* if eDP has no EDID, fall back to fixed mode */
4880         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4881             intel_connector->panel.fixed_mode) {
4882                 struct drm_display_mode *mode;
4883
4884                 mode = drm_mode_duplicate(connector->dev,
4885                                           intel_connector->panel.fixed_mode);
4886                 if (mode) {
4887                         drm_mode_probed_add(connector, mode);
4888                         return 1;
4889                 }
4890         }
4891
4892         return 0;
4893 }
4894
4895 static int
4896 intel_dp_connector_register(struct drm_connector *connector)
4897 {
4898         struct intel_dp *intel_dp = intel_attached_dp(connector);
4899         int ret;
4900
4901         ret = intel_connector_register(connector);
4902         if (ret)
4903                 return ret;
4904
4905         i915_debugfs_connector_add(connector);
4906
4907         DRM_DEBUG_KMS("registering %s bus for %s\n",
4908                       intel_dp->aux.name, connector->kdev->kobj.name);
4909
4910         intel_dp->aux.dev = connector->kdev;
4911         return drm_dp_aux_register(&intel_dp->aux);
4912 }
4913
4914 static void
4915 intel_dp_connector_unregister(struct drm_connector *connector)
4916 {
4917         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4918         intel_connector_unregister(connector);
4919 }
4920
4921 static void
4922 intel_dp_connector_destroy(struct drm_connector *connector)
4923 {
4924         struct intel_connector *intel_connector = to_intel_connector(connector);
4925
4926         kfree(intel_connector->detect_edid);
4927
4928         if (!IS_ERR_OR_NULL(intel_connector->edid))
4929                 kfree(intel_connector->edid);
4930
4931         /*
4932          * Can't call intel_dp_is_edp() since the encoder may have been
4933          * destroyed already.
4934          */
4935         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4936                 intel_panel_fini(&intel_connector->panel);
4937
4938         drm_connector_cleanup(connector);
4939         kfree(connector);
4940 }
4941
4942 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4943 {
4944         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4945         struct intel_dp *intel_dp = &intel_dig_port->dp;
4946
4947         intel_dp_mst_encoder_cleanup(intel_dig_port);
4948         if (intel_dp_is_edp(intel_dp)) {
4949                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4950                 /*
4951                  * vdd might still be enabled do to the delayed vdd off.
4952                  * Make sure vdd is actually turned off here.
4953                  */
4954                 pps_lock(intel_dp);
4955                 edp_panel_vdd_off_sync(intel_dp);
4956                 pps_unlock(intel_dp);
4957
4958                 if (intel_dp->edp_notifier.notifier_call) {
4959                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4960                         intel_dp->edp_notifier.notifier_call = NULL;
4961                 }
4962         }
4963
4964         intel_dp_aux_fini(intel_dp);
4965
4966         drm_encoder_cleanup(encoder);
4967         kfree(intel_dig_port);
4968 }
4969
4970 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4971 {
4972         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4973
4974         if (!intel_dp_is_edp(intel_dp))
4975                 return;
4976
4977         /*
4978          * vdd might still be enabled do to the delayed vdd off.
4979          * Make sure vdd is actually turned off here.
4980          */
4981         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4982         pps_lock(intel_dp);
4983         edp_panel_vdd_off_sync(intel_dp);
4984         pps_unlock(intel_dp);
4985 }
4986
4987 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4988 {
4989         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4990         struct drm_device *dev = intel_dig_port->base.base.dev;
4991         struct drm_i915_private *dev_priv = to_i915(dev);
4992
4993         lockdep_assert_held(&dev_priv->pps_mutex);
4994
4995         if (!edp_have_panel_vdd(intel_dp))
4996                 return;
4997
4998         /*
4999          * The VDD bit needs a power domain reference, so if the bit is
5000          * already enabled when we boot or resume, grab this reference and
5001          * schedule a vdd off, so we don't hold on to the reference
5002          * indefinitely.
5003          */
5004         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5005         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5006
5007         edp_panel_vdd_schedule_off(intel_dp);
5008 }
5009
5010 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5011 {
5012         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5013
5014         if ((intel_dp->DP & DP_PORT_EN) == 0)
5015                 return INVALID_PIPE;
5016
5017         if (IS_CHERRYVIEW(dev_priv))
5018                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5019         else
5020                 return PORT_TO_PIPE(intel_dp->DP);
5021 }
5022
5023 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5024 {
5025         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5026         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5027         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5028
5029         if (!HAS_DDI(dev_priv))
5030                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5031
5032         if (lspcon->active)
5033                 lspcon_resume(lspcon);
5034
5035         intel_dp->reset_link_params = true;
5036
5037         pps_lock(intel_dp);
5038
5039         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5040                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5041
5042         if (intel_dp_is_edp(intel_dp)) {
5043                 /* Reinit the power sequencer, in case BIOS did something with it. */
5044                 intel_dp_pps_init(encoder->dev, intel_dp);
5045                 intel_edp_panel_vdd_sanitize(intel_dp);
5046         }
5047
5048         pps_unlock(intel_dp);
5049 }
5050
5051 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5052         .force = intel_dp_force,
5053         .fill_modes = drm_helper_probe_single_connector_modes,
5054         .atomic_get_property = intel_digital_connector_atomic_get_property,
5055         .atomic_set_property = intel_digital_connector_atomic_set_property,
5056         .late_register = intel_dp_connector_register,
5057         .early_unregister = intel_dp_connector_unregister,
5058         .destroy = intel_dp_connector_destroy,
5059         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5060         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5061 };
5062
5063 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5064         .detect_ctx = intel_dp_detect,
5065         .get_modes = intel_dp_get_modes,
5066         .mode_valid = intel_dp_mode_valid,
5067         .atomic_check = intel_digital_connector_atomic_check,
5068 };
5069
5070 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5071         .reset = intel_dp_encoder_reset,
5072         .destroy = intel_dp_encoder_destroy,
5073 };
5074
5075 enum irqreturn
5076 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5077 {
5078         struct intel_dp *intel_dp = &intel_dig_port->dp;
5079         struct drm_device *dev = intel_dig_port->base.base.dev;
5080         struct drm_i915_private *dev_priv = to_i915(dev);
5081         enum irqreturn ret = IRQ_NONE;
5082
5083         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5084             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5085                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5086
5087         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5088                 /*
5089                  * vdd off can generate a long pulse on eDP which
5090                  * would require vdd on to handle it, and thus we
5091                  * would end up in an endless cycle of
5092                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5093                  */
5094                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5095                               port_name(intel_dig_port->port));
5096                 return IRQ_HANDLED;
5097         }
5098
5099         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5100                       port_name(intel_dig_port->port),
5101                       long_hpd ? "long" : "short");
5102
5103         if (long_hpd) {
5104                 intel_dp->reset_link_params = true;
5105                 intel_dp->detect_done = false;
5106                 return IRQ_NONE;
5107         }
5108
5109         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5110
5111         if (intel_dp->is_mst) {
5112                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5113                         /*
5114                          * If we were in MST mode, and device is not
5115                          * there, get out of MST mode
5116                          */
5117                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5118                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5119                         intel_dp->is_mst = false;
5120                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5121                                                         intel_dp->is_mst);
5122                         intel_dp->detect_done = false;
5123                         goto put_power;
5124                 }
5125         }
5126
5127         if (!intel_dp->is_mst) {
5128                 if (!intel_dp_short_pulse(intel_dp)) {
5129                         intel_dp->detect_done = false;
5130                         goto put_power;
5131                 }
5132         }
5133
5134         ret = IRQ_HANDLED;
5135
5136 put_power:
5137         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5138
5139         return ret;
5140 }
5141
5142 /* check the VBT to see whether the eDP is on another port */
5143 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5144 {
5145         /*
5146          * eDP not supported on g4x. so bail out early just
5147          * for a bit extra safety in case the VBT is bonkers.
5148          */
5149         if (INTEL_GEN(dev_priv) < 5)
5150                 return false;
5151
5152         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5153                 return true;
5154
5155         return intel_bios_is_port_edp(dev_priv, port);
5156 }
5157
5158 static void
5159 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5160 {
5161         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5162
5163         intel_attach_force_audio_property(connector);
5164         intel_attach_broadcast_rgb_property(connector);
5165
5166         if (intel_dp_is_edp(intel_dp)) {
5167                 u32 allowed_scalers;
5168
5169                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5170                 if (!HAS_GMCH_DISPLAY(dev_priv))
5171                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5172
5173                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5174
5175                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5176
5177         }
5178 }
5179
5180 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5181 {
5182         intel_dp->panel_power_off_time = ktime_get_boottime();
5183         intel_dp->last_power_on = jiffies;
5184         intel_dp->last_backlight_off = jiffies;
5185 }
5186
5187 static void
5188 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5189                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5190 {
5191         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5192         struct pps_registers regs;
5193
5194         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5195
5196         /* Workaround: Need to write PP_CONTROL with the unlock key as
5197          * the very first thing. */
5198         pp_ctl = ironlake_get_pp_control(intel_dp);
5199
5200         pp_on = I915_READ(regs.pp_on);
5201         pp_off = I915_READ(regs.pp_off);
5202         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5203                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5204                 pp_div = I915_READ(regs.pp_div);
5205         }
5206
5207         /* Pull timing values out of registers */
5208         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5209                      PANEL_POWER_UP_DELAY_SHIFT;
5210
5211         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5212                   PANEL_LIGHT_ON_DELAY_SHIFT;
5213
5214         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5215                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5216
5217         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5218                    PANEL_POWER_DOWN_DELAY_SHIFT;
5219
5220         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5221                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5222                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5223         } else {
5224                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5225                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5226         }
5227 }
5228
5229 static void
5230 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5231 {
5232         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5233                       state_name,
5234                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5235 }
5236
5237 static void
5238 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5239                        struct intel_dp *intel_dp)
5240 {
5241         struct edp_power_seq hw;
5242         struct edp_power_seq *sw = &intel_dp->pps_delays;
5243
5244         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5245
5246         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5247             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5248                 DRM_ERROR("PPS state mismatch\n");
5249                 intel_pps_dump_state("sw", sw);
5250                 intel_pps_dump_state("hw", &hw);
5251         }
5252 }
5253
5254 static void
5255 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5256                                     struct intel_dp *intel_dp)
5257 {
5258         struct drm_i915_private *dev_priv = to_i915(dev);
5259         struct edp_power_seq cur, vbt, spec,
5260                 *final = &intel_dp->pps_delays;
5261
5262         lockdep_assert_held(&dev_priv->pps_mutex);
5263
5264         /* already initialized? */
5265         if (final->t11_t12 != 0)
5266                 return;
5267
5268         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5269
5270         intel_pps_dump_state("cur", &cur);
5271
5272         vbt = dev_priv->vbt.edp.pps;
5273         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5274          * of 500ms appears to be too short. Ocassionally the panel
5275          * just fails to power back on. Increasing the delay to 800ms
5276          * seems sufficient to avoid this problem.
5277          */
5278         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5279                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5280                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5281                               vbt.t11_t12);
5282         }
5283         /* T11_T12 delay is special and actually in units of 100ms, but zero
5284          * based in the hw (so we need to add 100 ms). But the sw vbt
5285          * table multiplies it with 1000 to make it in units of 100usec,
5286          * too. */
5287         vbt.t11_t12 += 100 * 10;
5288
5289         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5290          * our hw here, which are all in 100usec. */
5291         spec.t1_t3 = 210 * 10;
5292         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5293         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5294         spec.t10 = 500 * 10;
5295         /* This one is special and actually in units of 100ms, but zero
5296          * based in the hw (so we need to add 100 ms). But the sw vbt
5297          * table multiplies it with 1000 to make it in units of 100usec,
5298          * too. */
5299         spec.t11_t12 = (510 + 100) * 10;
5300
5301         intel_pps_dump_state("vbt", &vbt);
5302
5303         /* Use the max of the register settings and vbt. If both are
5304          * unset, fall back to the spec limits. */
5305 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5306                                        spec.field : \
5307                                        max(cur.field, vbt.field))
5308         assign_final(t1_t3);
5309         assign_final(t8);
5310         assign_final(t9);
5311         assign_final(t10);
5312         assign_final(t11_t12);
5313 #undef assign_final
5314
5315 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5316         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5317         intel_dp->backlight_on_delay = get_delay(t8);
5318         intel_dp->backlight_off_delay = get_delay(t9);
5319         intel_dp->panel_power_down_delay = get_delay(t10);
5320         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5321 #undef get_delay
5322
5323         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5324                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5325                       intel_dp->panel_power_cycle_delay);
5326
5327         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5328                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5329
5330         /*
5331          * We override the HW backlight delays to 1 because we do manual waits
5332          * on them. For T8, even BSpec recommends doing it. For T9, if we
5333          * don't do this, we'll end up waiting for the backlight off delay
5334          * twice: once when we do the manual sleep, and once when we disable
5335          * the panel and wait for the PP_STATUS bit to become zero.
5336          */
5337         final->t8 = 1;
5338         final->t9 = 1;
5339 }
5340
5341 static void
5342 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5343                                               struct intel_dp *intel_dp,
5344                                               bool force_disable_vdd)
5345 {
5346         struct drm_i915_private *dev_priv = to_i915(dev);
5347         u32 pp_on, pp_off, pp_div, port_sel = 0;
5348         int div = dev_priv->rawclk_freq / 1000;
5349         struct pps_registers regs;
5350         enum port port = dp_to_dig_port(intel_dp)->port;
5351         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5352
5353         lockdep_assert_held(&dev_priv->pps_mutex);
5354
5355         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5356
5357         /*
5358          * On some VLV machines the BIOS can leave the VDD
5359          * enabled even on power seqeuencers which aren't
5360          * hooked up to any port. This would mess up the
5361          * power domain tracking the first time we pick
5362          * one of these power sequencers for use since
5363          * edp_panel_vdd_on() would notice that the VDD was
5364          * already on and therefore wouldn't grab the power
5365          * domain reference. Disable VDD first to avoid this.
5366          * This also avoids spuriously turning the VDD on as
5367          * soon as the new power seqeuencer gets initialized.
5368          */
5369         if (force_disable_vdd) {
5370                 u32 pp = ironlake_get_pp_control(intel_dp);
5371
5372                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5373
5374                 if (pp & EDP_FORCE_VDD)
5375                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5376
5377                 pp &= ~EDP_FORCE_VDD;
5378
5379                 I915_WRITE(regs.pp_ctrl, pp);
5380         }
5381
5382         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5383                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5384         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5385                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5386         /* Compute the divisor for the pp clock, simply match the Bspec
5387          * formula. */
5388         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5389                 pp_div = I915_READ(regs.pp_ctrl);
5390                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5391                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5392                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5393         } else {
5394                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5395                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5396                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5397         }
5398
5399         /* Haswell doesn't have any port selection bits for the panel
5400          * power sequencer any more. */
5401         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5402                 port_sel = PANEL_PORT_SELECT_VLV(port);
5403         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5404                 if (port == PORT_A)
5405                         port_sel = PANEL_PORT_SELECT_DPA;
5406                 else
5407                         port_sel = PANEL_PORT_SELECT_DPD;
5408         }
5409
5410         pp_on |= port_sel;
5411
5412         I915_WRITE(regs.pp_on, pp_on);
5413         I915_WRITE(regs.pp_off, pp_off);
5414         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5415                 I915_WRITE(regs.pp_ctrl, pp_div);
5416         else
5417                 I915_WRITE(regs.pp_div, pp_div);
5418
5419         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5420                       I915_READ(regs.pp_on),
5421                       I915_READ(regs.pp_off),
5422                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5423                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5424                       I915_READ(regs.pp_div));
5425 }
5426
5427 static void intel_dp_pps_init(struct drm_device *dev,
5428                               struct intel_dp *intel_dp)
5429 {
5430         struct drm_i915_private *dev_priv = to_i915(dev);
5431
5432         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5433                 vlv_initial_power_sequencer_setup(intel_dp);
5434         } else {
5435                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5436                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5437         }
5438 }
5439
5440 /**
5441  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5442  * @dev_priv: i915 device
5443  * @crtc_state: a pointer to the active intel_crtc_state
5444  * @refresh_rate: RR to be programmed
5445  *
5446  * This function gets called when refresh rate (RR) has to be changed from
5447  * one frequency to another. Switches can be between high and low RR
5448  * supported by the panel or to any other RR based on media playback (in
5449  * this case, RR value needs to be passed from user space).
5450  *
5451  * The caller of this function needs to take a lock on dev_priv->drrs.
5452  */
5453 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5454                                     const struct intel_crtc_state *crtc_state,
5455                                     int refresh_rate)
5456 {
5457         struct intel_encoder *encoder;
5458         struct intel_digital_port *dig_port = NULL;
5459         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5461         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5462
5463         if (refresh_rate <= 0) {
5464                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5465                 return;
5466         }
5467
5468         if (intel_dp == NULL) {
5469                 DRM_DEBUG_KMS("DRRS not supported.\n");
5470                 return;
5471         }
5472
5473         dig_port = dp_to_dig_port(intel_dp);
5474         encoder = &dig_port->base;
5475         intel_crtc = to_intel_crtc(encoder->base.crtc);
5476
5477         if (!intel_crtc) {
5478                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5479                 return;
5480         }
5481
5482         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5483                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5484                 return;
5485         }
5486
5487         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5488                         refresh_rate)
5489                 index = DRRS_LOW_RR;
5490
5491         if (index == dev_priv->drrs.refresh_rate_type) {
5492                 DRM_DEBUG_KMS(
5493                         "DRRS requested for previously set RR...ignoring\n");
5494                 return;
5495         }
5496
5497         if (!crtc_state->base.active) {
5498                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5499                 return;
5500         }
5501
5502         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5503                 switch (index) {
5504                 case DRRS_HIGH_RR:
5505                         intel_dp_set_m_n(intel_crtc, M1_N1);
5506                         break;
5507                 case DRRS_LOW_RR:
5508                         intel_dp_set_m_n(intel_crtc, M2_N2);
5509                         break;
5510                 case DRRS_MAX_RR:
5511                 default:
5512                         DRM_ERROR("Unsupported refreshrate type\n");
5513                 }
5514         } else if (INTEL_GEN(dev_priv) > 6) {
5515                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5516                 u32 val;
5517
5518                 val = I915_READ(reg);
5519                 if (index > DRRS_HIGH_RR) {
5520                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5521                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5522                         else
5523                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5524                 } else {
5525                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5526                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5527                         else
5528                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5529                 }
5530                 I915_WRITE(reg, val);
5531         }
5532
5533         dev_priv->drrs.refresh_rate_type = index;
5534
5535         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5536 }
5537
5538 /**
5539  * intel_edp_drrs_enable - init drrs struct if supported
5540  * @intel_dp: DP struct
5541  * @crtc_state: A pointer to the active crtc state.
5542  *
5543  * Initializes frontbuffer_bits and drrs.dp
5544  */
5545 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5546                            const struct intel_crtc_state *crtc_state)
5547 {
5548         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5549         struct drm_i915_private *dev_priv = to_i915(dev);
5550
5551         if (!crtc_state->has_drrs) {
5552                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5553                 return;
5554         }
5555
5556         if (dev_priv->psr.enabled) {
5557                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5558                 return;
5559         }
5560
5561         mutex_lock(&dev_priv->drrs.mutex);
5562         if (WARN_ON(dev_priv->drrs.dp)) {
5563                 DRM_ERROR("DRRS already enabled\n");
5564                 goto unlock;
5565         }
5566
5567         dev_priv->drrs.busy_frontbuffer_bits = 0;
5568
5569         dev_priv->drrs.dp = intel_dp;
5570
5571 unlock:
5572         mutex_unlock(&dev_priv->drrs.mutex);
5573 }
5574
5575 /**
5576  * intel_edp_drrs_disable - Disable DRRS
5577  * @intel_dp: DP struct
5578  * @old_crtc_state: Pointer to old crtc_state.
5579  *
5580  */
5581 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5582                             const struct intel_crtc_state *old_crtc_state)
5583 {
5584         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5585         struct drm_i915_private *dev_priv = to_i915(dev);
5586
5587         if (!old_crtc_state->has_drrs)
5588                 return;
5589
5590         mutex_lock(&dev_priv->drrs.mutex);
5591         if (!dev_priv->drrs.dp) {
5592                 mutex_unlock(&dev_priv->drrs.mutex);
5593                 return;
5594         }
5595
5596         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5597                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5598                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5599
5600         dev_priv->drrs.dp = NULL;
5601         mutex_unlock(&dev_priv->drrs.mutex);
5602
5603         cancel_delayed_work_sync(&dev_priv->drrs.work);
5604 }
5605
5606 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5607 {
5608         struct drm_i915_private *dev_priv =
5609                 container_of(work, typeof(*dev_priv), drrs.work.work);
5610         struct intel_dp *intel_dp;
5611
5612         mutex_lock(&dev_priv->drrs.mutex);
5613
5614         intel_dp = dev_priv->drrs.dp;
5615
5616         if (!intel_dp)
5617                 goto unlock;
5618
5619         /*
5620          * The delayed work can race with an invalidate hence we need to
5621          * recheck.
5622          */
5623
5624         if (dev_priv->drrs.busy_frontbuffer_bits)
5625                 goto unlock;
5626
5627         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5628                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5629
5630                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5631                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5632         }
5633
5634 unlock:
5635         mutex_unlock(&dev_priv->drrs.mutex);
5636 }
5637
5638 /**
5639  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5640  * @dev_priv: i915 device
5641  * @frontbuffer_bits: frontbuffer plane tracking bits
5642  *
5643  * This function gets called everytime rendering on the given planes start.
5644  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5645  *
5646  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5647  */
5648 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5649                                unsigned int frontbuffer_bits)
5650 {
5651         struct drm_crtc *crtc;
5652         enum pipe pipe;
5653
5654         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5655                 return;
5656
5657         cancel_delayed_work(&dev_priv->drrs.work);
5658
5659         mutex_lock(&dev_priv->drrs.mutex);
5660         if (!dev_priv->drrs.dp) {
5661                 mutex_unlock(&dev_priv->drrs.mutex);
5662                 return;
5663         }
5664
5665         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5666         pipe = to_intel_crtc(crtc)->pipe;
5667
5668         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5669         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5670
5671         /* invalidate means busy screen hence upclock */
5672         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5673                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5674                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5675
5676         mutex_unlock(&dev_priv->drrs.mutex);
5677 }
5678
5679 /**
5680  * intel_edp_drrs_flush - Restart Idleness DRRS
5681  * @dev_priv: i915 device
5682  * @frontbuffer_bits: frontbuffer plane tracking bits
5683  *
5684  * This function gets called every time rendering on the given planes has
5685  * completed or flip on a crtc is completed. So DRRS should be upclocked
5686  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5687  * if no other planes are dirty.
5688  *
5689  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5690  */
5691 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5692                           unsigned int frontbuffer_bits)
5693 {
5694         struct drm_crtc *crtc;
5695         enum pipe pipe;
5696
5697         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5698                 return;
5699
5700         cancel_delayed_work(&dev_priv->drrs.work);
5701
5702         mutex_lock(&dev_priv->drrs.mutex);
5703         if (!dev_priv->drrs.dp) {
5704                 mutex_unlock(&dev_priv->drrs.mutex);
5705                 return;
5706         }
5707
5708         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5709         pipe = to_intel_crtc(crtc)->pipe;
5710
5711         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5712         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5713
5714         /* flush means busy screen hence upclock */
5715         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5716                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5717                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5718
5719         /*
5720          * flush also means no more activity hence schedule downclock, if all
5721          * other fbs are quiescent too
5722          */
5723         if (!dev_priv->drrs.busy_frontbuffer_bits)
5724                 schedule_delayed_work(&dev_priv->drrs.work,
5725                                 msecs_to_jiffies(1000));
5726         mutex_unlock(&dev_priv->drrs.mutex);
5727 }
5728
5729 /**
5730  * DOC: Display Refresh Rate Switching (DRRS)
5731  *
5732  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5733  * which enables swtching between low and high refresh rates,
5734  * dynamically, based on the usage scenario. This feature is applicable
5735  * for internal panels.
5736  *
5737  * Indication that the panel supports DRRS is given by the panel EDID, which
5738  * would list multiple refresh rates for one resolution.
5739  *
5740  * DRRS is of 2 types - static and seamless.
5741  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5742  * (may appear as a blink on screen) and is used in dock-undock scenario.
5743  * Seamless DRRS involves changing RR without any visual effect to the user
5744  * and can be used during normal system usage. This is done by programming
5745  * certain registers.
5746  *
5747  * Support for static/seamless DRRS may be indicated in the VBT based on
5748  * inputs from the panel spec.
5749  *
5750  * DRRS saves power by switching to low RR based on usage scenarios.
5751  *
5752  * The implementation is based on frontbuffer tracking implementation.  When
5753  * there is a disturbance on the screen triggered by user activity or a periodic
5754  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5755  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5756  * made.
5757  *
5758  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5759  * and intel_edp_drrs_flush() are called.
5760  *
5761  * DRRS can be further extended to support other internal panels and also
5762  * the scenario of video playback wherein RR is set based on the rate
5763  * requested by userspace.
5764  */
5765
5766 /**
5767  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5768  * @intel_connector: eDP connector
5769  * @fixed_mode: preferred mode of panel
5770  *
5771  * This function is  called only once at driver load to initialize basic
5772  * DRRS stuff.
5773  *
5774  * Returns:
5775  * Downclock mode if panel supports it, else return NULL.
5776  * DRRS support is determined by the presence of downclock mode (apart
5777  * from VBT setting).
5778  */
5779 static struct drm_display_mode *
5780 intel_dp_drrs_init(struct intel_connector *intel_connector,
5781                 struct drm_display_mode *fixed_mode)
5782 {
5783         struct drm_connector *connector = &intel_connector->base;
5784         struct drm_device *dev = connector->dev;
5785         struct drm_i915_private *dev_priv = to_i915(dev);
5786         struct drm_display_mode *downclock_mode = NULL;
5787
5788         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5789         mutex_init(&dev_priv->drrs.mutex);
5790
5791         if (INTEL_GEN(dev_priv) <= 6) {
5792                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5793                 return NULL;
5794         }
5795
5796         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5797                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5798                 return NULL;
5799         }
5800
5801         downclock_mode = intel_find_panel_downclock
5802                                         (dev_priv, fixed_mode, connector);
5803
5804         if (!downclock_mode) {
5805                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5806                 return NULL;
5807         }
5808
5809         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5810
5811         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5812         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5813         return downclock_mode;
5814 }
5815
5816 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5817                                      struct intel_connector *intel_connector)
5818 {
5819         struct drm_connector *connector = &intel_connector->base;
5820         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5821         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5822         struct drm_device *dev = intel_encoder->base.dev;
5823         struct drm_i915_private *dev_priv = to_i915(dev);
5824         struct drm_display_mode *fixed_mode = NULL;
5825         struct drm_display_mode *alt_fixed_mode = NULL;
5826         struct drm_display_mode *downclock_mode = NULL;
5827         bool has_dpcd;
5828         struct drm_display_mode *scan;
5829         struct edid *edid;
5830         enum pipe pipe = INVALID_PIPE;
5831
5832         if (!intel_dp_is_edp(intel_dp))
5833                 return true;
5834
5835         /*
5836          * On IBX/CPT we may get here with LVDS already registered. Since the
5837          * driver uses the only internal power sequencer available for both
5838          * eDP and LVDS bail out early in this case to prevent interfering
5839          * with an already powered-on LVDS power sequencer.
5840          */
5841         if (intel_get_lvds_encoder(dev)) {
5842                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5843                 DRM_INFO("LVDS was detected, not registering eDP\n");
5844
5845                 return false;
5846         }
5847
5848         pps_lock(intel_dp);
5849
5850         intel_dp_init_panel_power_timestamps(intel_dp);
5851         intel_dp_pps_init(dev, intel_dp);
5852         intel_edp_panel_vdd_sanitize(intel_dp);
5853
5854         pps_unlock(intel_dp);
5855
5856         /* Cache DPCD and EDID for edp. */
5857         has_dpcd = intel_edp_init_dpcd(intel_dp);
5858
5859         if (!has_dpcd) {
5860                 /* if this fails, presume the device is a ghost */
5861                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5862                 goto out_vdd_off;
5863         }
5864
5865         mutex_lock(&dev->mode_config.mutex);
5866         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5867         if (edid) {
5868                 if (drm_add_edid_modes(connector, edid)) {
5869                         drm_mode_connector_update_edid_property(connector,
5870                                                                 edid);
5871                         drm_edid_to_eld(connector, edid);
5872                 } else {
5873                         kfree(edid);
5874                         edid = ERR_PTR(-EINVAL);
5875                 }
5876         } else {
5877                 edid = ERR_PTR(-ENOENT);
5878         }
5879         intel_connector->edid = edid;
5880
5881         /* prefer fixed mode from EDID if available, save an alt mode also */
5882         list_for_each_entry(scan, &connector->probed_modes, head) {
5883                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5884                         fixed_mode = drm_mode_duplicate(dev, scan);
5885                         downclock_mode = intel_dp_drrs_init(
5886                                                 intel_connector, fixed_mode);
5887                 } else if (!alt_fixed_mode) {
5888                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
5889                 }
5890         }
5891
5892         /* fallback to VBT if available for eDP */
5893         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5894                 fixed_mode = drm_mode_duplicate(dev,
5895                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5896                 if (fixed_mode) {
5897                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5898                         connector->display_info.width_mm = fixed_mode->width_mm;
5899                         connector->display_info.height_mm = fixed_mode->height_mm;
5900                 }
5901         }
5902         mutex_unlock(&dev->mode_config.mutex);
5903
5904         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5905                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5906                 register_reboot_notifier(&intel_dp->edp_notifier);
5907
5908                 /*
5909                  * Figure out the current pipe for the initial backlight setup.
5910                  * If the current pipe isn't valid, try the PPS pipe, and if that
5911                  * fails just assume pipe A.
5912                  */
5913                 pipe = vlv_active_pipe(intel_dp);
5914
5915                 if (pipe != PIPE_A && pipe != PIPE_B)
5916                         pipe = intel_dp->pps_pipe;
5917
5918                 if (pipe != PIPE_A && pipe != PIPE_B)
5919                         pipe = PIPE_A;
5920
5921                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5922                               pipe_name(pipe));
5923         }
5924
5925         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5926                          downclock_mode);
5927         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5928         intel_panel_setup_backlight(connector, pipe);
5929
5930         return true;
5931
5932 out_vdd_off:
5933         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5934         /*
5935          * vdd might still be enabled do to the delayed vdd off.
5936          * Make sure vdd is actually turned off here.
5937          */
5938         pps_lock(intel_dp);
5939         edp_panel_vdd_off_sync(intel_dp);
5940         pps_unlock(intel_dp);
5941
5942         return false;
5943 }
5944
5945 /* Set up the hotplug pin and aux power domain. */
5946 static void
5947 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5948 {
5949         struct intel_encoder *encoder = &intel_dig_port->base;
5950         struct intel_dp *intel_dp = &intel_dig_port->dp;
5951
5952         encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port);
5953
5954         switch (intel_dig_port->port) {
5955         case PORT_A:
5956                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5957                 break;
5958         case PORT_B:
5959                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5960                 break;
5961         case PORT_C:
5962                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5963                 break;
5964         case PORT_D:
5965                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5966                 break;
5967         case PORT_E:
5968                 /* FIXME: Check VBT for actual wiring of PORT E */
5969                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5970                 break;
5971         default:
5972                 MISSING_CASE(intel_dig_port->port);
5973         }
5974 }
5975
5976 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5977 {
5978         struct intel_connector *intel_connector;
5979         struct drm_connector *connector;
5980
5981         intel_connector = container_of(work, typeof(*intel_connector),
5982                                        modeset_retry_work);
5983         connector = &intel_connector->base;
5984         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5985                       connector->name);
5986
5987         /* Grab the locks before changing connector property*/
5988         mutex_lock(&connector->dev->mode_config.mutex);
5989         /* Set connector link status to BAD and send a Uevent to notify
5990          * userspace to do a modeset.
5991          */
5992         drm_mode_connector_set_link_status_property(connector,
5993                                                     DRM_MODE_LINK_STATUS_BAD);
5994         mutex_unlock(&connector->dev->mode_config.mutex);
5995         /* Send Hotplug uevent so userspace can reprobe */
5996         drm_kms_helper_hotplug_event(connector->dev);
5997 }
5998
5999 bool
6000 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6001                         struct intel_connector *intel_connector)
6002 {
6003         struct drm_connector *connector = &intel_connector->base;
6004         struct intel_dp *intel_dp = &intel_dig_port->dp;
6005         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6006         struct drm_device *dev = intel_encoder->base.dev;
6007         struct drm_i915_private *dev_priv = to_i915(dev);
6008         enum port port = intel_dig_port->port;
6009         int type;
6010
6011         /* Initialize the work for modeset in case of link train failure */
6012         INIT_WORK(&intel_connector->modeset_retry_work,
6013                   intel_dp_modeset_retry_work_fn);
6014
6015         if (WARN(intel_dig_port->max_lanes < 1,
6016                  "Not enough lanes (%d) for DP on port %c\n",
6017                  intel_dig_port->max_lanes, port_name(port)))
6018                 return false;
6019
6020         intel_dp_set_source_rates(intel_dp);
6021
6022         intel_dp->reset_link_params = true;
6023         intel_dp->pps_pipe = INVALID_PIPE;
6024         intel_dp->active_pipe = INVALID_PIPE;
6025
6026         /* intel_dp vfuncs */
6027         if (INTEL_GEN(dev_priv) >= 9)
6028                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6029         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6030                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6031         else if (HAS_PCH_SPLIT(dev_priv))
6032                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6033         else
6034                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6035
6036         if (INTEL_GEN(dev_priv) >= 9)
6037                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6038         else
6039                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6040
6041         if (HAS_DDI(dev_priv))
6042                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6043
6044         /* Preserve the current hw state. */
6045         intel_dp->DP = I915_READ(intel_dp->output_reg);
6046         intel_dp->attached_connector = intel_connector;
6047
6048         if (intel_dp_is_port_edp(dev_priv, port))
6049                 type = DRM_MODE_CONNECTOR_eDP;
6050         else
6051                 type = DRM_MODE_CONNECTOR_DisplayPort;
6052
6053         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6054                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6055
6056         /*
6057          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6058          * for DP the encoder type can be set by the caller to
6059          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6060          */
6061         if (type == DRM_MODE_CONNECTOR_eDP)
6062                 intel_encoder->type = INTEL_OUTPUT_EDP;
6063
6064         /* eDP only on port B and/or C on vlv/chv */
6065         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6066                     intel_dp_is_edp(intel_dp) &&
6067                     port != PORT_B && port != PORT_C))
6068                 return false;
6069
6070         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6071                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6072                         port_name(port));
6073
6074         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6075         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6076
6077         connector->interlace_allowed = true;
6078         connector->doublescan_allowed = 0;
6079
6080         intel_dp_init_connector_port_info(intel_dig_port);
6081
6082         intel_dp_aux_init(intel_dp);
6083
6084         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6085                           edp_panel_vdd_work);
6086
6087         intel_connector_attach_encoder(intel_connector, intel_encoder);
6088
6089         if (HAS_DDI(dev_priv))
6090                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6091         else
6092                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6093
6094         /* init MST on ports that can support it */
6095         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6096             (port == PORT_B || port == PORT_C || port == PORT_D))
6097                 intel_dp_mst_encoder_init(intel_dig_port,
6098                                           intel_connector->base.base.id);
6099
6100         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6101                 intel_dp_aux_fini(intel_dp);
6102                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6103                 goto fail;
6104         }
6105
6106         intel_dp_add_properties(intel_dp, connector);
6107
6108         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6109          * 0xd.  Failure to do so will result in spurious interrupts being
6110          * generated on the port when a cable is not attached.
6111          */
6112         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6113                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6114                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6115         }
6116
6117         return true;
6118
6119 fail:
6120         drm_connector_cleanup(connector);
6121
6122         return false;
6123 }
6124
6125 bool intel_dp_init(struct drm_i915_private *dev_priv,
6126                    i915_reg_t output_reg,
6127                    enum port port)
6128 {
6129         struct intel_digital_port *intel_dig_port;
6130         struct intel_encoder *intel_encoder;
6131         struct drm_encoder *encoder;
6132         struct intel_connector *intel_connector;
6133
6134         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6135         if (!intel_dig_port)
6136                 return false;
6137
6138         intel_connector = intel_connector_alloc();
6139         if (!intel_connector)
6140                 goto err_connector_alloc;
6141
6142         intel_encoder = &intel_dig_port->base;
6143         encoder = &intel_encoder->base;
6144
6145         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6146                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6147                              "DP %c", port_name(port)))
6148                 goto err_encoder_init;
6149
6150         intel_encoder->compute_config = intel_dp_compute_config;
6151         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6152         intel_encoder->get_config = intel_dp_get_config;
6153         intel_encoder->suspend = intel_dp_encoder_suspend;
6154         if (IS_CHERRYVIEW(dev_priv)) {
6155                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6156                 intel_encoder->pre_enable = chv_pre_enable_dp;
6157                 intel_encoder->enable = vlv_enable_dp;
6158                 intel_encoder->disable = vlv_disable_dp;
6159                 intel_encoder->post_disable = chv_post_disable_dp;
6160                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6161         } else if (IS_VALLEYVIEW(dev_priv)) {
6162                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6163                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6164                 intel_encoder->enable = vlv_enable_dp;
6165                 intel_encoder->disable = vlv_disable_dp;
6166                 intel_encoder->post_disable = vlv_post_disable_dp;
6167         } else if (INTEL_GEN(dev_priv) >= 5) {
6168                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6169                 intel_encoder->enable = g4x_enable_dp;
6170                 intel_encoder->disable = ilk_disable_dp;
6171                 intel_encoder->post_disable = ilk_post_disable_dp;
6172         } else {
6173                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6174                 intel_encoder->enable = g4x_enable_dp;
6175                 intel_encoder->disable = g4x_disable_dp;
6176         }
6177
6178         intel_dig_port->port = port;
6179         intel_dig_port->dp.output_reg = output_reg;
6180         intel_dig_port->max_lanes = 4;
6181
6182         intel_encoder->type = INTEL_OUTPUT_DP;
6183         intel_encoder->power_domain = intel_port_to_power_domain(port);
6184         if (IS_CHERRYVIEW(dev_priv)) {
6185                 if (port == PORT_D)
6186                         intel_encoder->crtc_mask = 1 << 2;
6187                 else
6188                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6189         } else {
6190                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6191         }
6192         intel_encoder->cloneable = 0;
6193         intel_encoder->port = port;
6194
6195         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6196         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6197
6198         if (port != PORT_A)
6199                 intel_infoframe_init(intel_dig_port);
6200
6201         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6202                 goto err_init_connector;
6203
6204         return true;
6205
6206 err_init_connector:
6207         drm_encoder_cleanup(encoder);
6208 err_encoder_init:
6209         kfree(intel_connector);
6210 err_connector_alloc:
6211         kfree(intel_dig_port);
6212         return false;
6213 }
6214
6215 void intel_dp_mst_suspend(struct drm_device *dev)
6216 {
6217         struct drm_i915_private *dev_priv = to_i915(dev);
6218         int i;
6219
6220         /* disable MST */
6221         for (i = 0; i < I915_MAX_PORTS; i++) {
6222                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6223
6224                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6225                         continue;
6226
6227                 if (intel_dig_port->dp.is_mst)
6228                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6229         }
6230 }
6231
6232 void intel_dp_mst_resume(struct drm_device *dev)
6233 {
6234         struct drm_i915_private *dev_priv = to_i915(dev);
6235         int i;
6236
6237         for (i = 0; i < I915_MAX_PORTS; i++) {
6238                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6239                 int ret;
6240
6241                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6242                         continue;
6243
6244                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6245                 if (ret)
6246                         intel_dp_check_mst_status(&intel_dig_port->dp);
6247         }
6248 }