drivers/spi/spi-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Cadence SPI controller driver (master and slave mode)
   4  *
   5  * Copyright (C) 2008 - 2014 Xilinx, Inc.
   6  *
   7  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/spi/spi.h>
  22
  23 /* Name of this driver */
  24 #define CDNS_SPI_NAME           "cdns-spi"
  25
  26 /* Register offset definitions */
  27 #define CDNS_SPI_CR     0x00 /* Configuration  Register, RW */
  28 #define CDNS_SPI_ISR    0x04 /* Interrupt Status Register, RO */
  29 #define CDNS_SPI_IER    0x08 /* Interrupt Enable Register, WO */
  30 #define CDNS_SPI_IDR    0x0c /* Interrupt Disable Register, WO */
  31 #define CDNS_SPI_IMR    0x10 /* Interrupt Enabled Mask Register, RO */
  32 #define CDNS_SPI_ER     0x14 /* Enable/Disable Register, RW */
  33 #define CDNS_SPI_DR     0x18 /* Delay Register, RW */
  34 #define CDNS_SPI_TXD    0x1C /* Data Transmit Register, WO */
  35 #define CDNS_SPI_RXD    0x20 /* Data Receive Register, RO */
  36 #define CDNS_SPI_SICR   0x24 /* Slave Idle Count Register, RW */
  37 #define CDNS_SPI_THLD   0x28 /* Transmit FIFO Watermark Register,RW */
  38
  39 #define SPI_AUTOSUSPEND_TIMEOUT         3000
  40 /*
  41  * SPI Configuration Register bit Masks
  42  *
  43  * This register contains various control bits that affect the operation
  44  * of the SPI controller
  45  */
  46 #define CDNS_SPI_CR_MANSTRT     0x00010000 /* Manual TX Start */
  47 #define CDNS_SPI_CR_CPHA                0x00000004 /* Clock Phase Control */
  48 #define CDNS_SPI_CR_CPOL                0x00000002 /* Clock Polarity Control */
  49 #define CDNS_SPI_CR_SSCTRL              0x00003C00 /* Slave Select Mask */
  50 #define CDNS_SPI_CR_PERI_SEL    0x00000200 /* Peripheral Select Decode */
  51 #define CDNS_SPI_CR_BAUD_DIV    0x00000038 /* Baud Rate Divisor Mask */
  52 #define CDNS_SPI_CR_MSTREN              0x00000001 /* Master Enable Mask */
  53 #define CDNS_SPI_CR_MANSTRTEN   0x00008000 /* Manual TX Enable Mask */
  54 #define CDNS_SPI_CR_SSFORCE     0x00004000 /* Manual SS Enable Mask */
  55 #define CDNS_SPI_CR_BAUD_DIV_4  0x00000008 /* Default Baud Div Mask */
  56 #define CDNS_SPI_CR_DEFAULT     (CDNS_SPI_CR_MSTREN | \
  57                                         CDNS_SPI_CR_SSCTRL | \
  58                                         CDNS_SPI_CR_SSFORCE | \
  59                                         CDNS_SPI_CR_BAUD_DIV_4)
  60
  61 /*
  62  * SPI Configuration Register - Baud rate and slave select
  63  *
  64  * These are the values used in the calculation of baud rate divisor and
  65  * setting the slave select.
  66  */
  67
  68 #define CDNS_SPI_BAUD_DIV_MAX           7 /* Baud rate divisor maximum */
  69 #define CDNS_SPI_BAUD_DIV_MIN           1 /* Baud rate divisor minimum */
  70 #define CDNS_SPI_BAUD_DIV_SHIFT         3 /* Baud rate divisor shift in CR */
  71 #define CDNS_SPI_SS_SHIFT               10 /* Slave Select field shift in CR */
  72 #define CDNS_SPI_SS0                    0x1 /* Slave Select zero */
  73 #define CDNS_SPI_NOSS                   0xF /* No Slave select */
  74
  75 /*
  76  * SPI Interrupt Registers bit Masks
  77  *
  78  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  79  * bit definitions.
  80  */
  81 #define CDNS_SPI_IXR_TXOW       0x00000004 /* SPI TX FIFO Overwater */
  82 #define CDNS_SPI_IXR_MODF       0x00000002 /* SPI Mode Fault */
  83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  84 #define CDNS_SPI_IXR_DEFAULT    (CDNS_SPI_IXR_TXOW | \
  85                                         CDNS_SPI_IXR_MODF)
  86 #define CDNS_SPI_IXR_TXFULL     0x00000008 /* SPI TX Full */
  87 #define CDNS_SPI_IXR_ALL        0x0000007F /* SPI all interrupts */
  88
  89 /*
  90  * SPI Enable Register bit Masks
  91  *
  92  * This register is used to enable or disable the SPI controller
  93  */
  94 #define CDNS_SPI_ER_ENABLE      0x00000001 /* SPI Enable Bit Mask */
  95 #define CDNS_SPI_ER_DISABLE     0x0 /* SPI Disable Bit Mask */
  96
  97 /* Default number of chip select lines */
  98 #define CDNS_SPI_DEFAULT_NUM_CS         4
  99
 100 /**
 101  * struct cdns_spi - This definition defines spi driver instance
 102  * @regs:               Virtual address of the SPI controller registers
 103  * @ref_clk:            Pointer to the peripheral clock
 104  * @pclk:               Pointer to the APB clock
 105  * @clk_rate:           Reference clock frequency, taken from @ref_clk
 106  * @speed_hz:           Current SPI bus clock speed in Hz
 107  * @txbuf:              Pointer to the TX buffer
 108  * @rxbuf:              Pointer to the RX buffer
 109  * @tx_bytes:           Number of bytes left to transfer
 110  * @rx_bytes:           Number of bytes requested
 111  * @dev_busy:           Device busy flag
 112  * @is_decoded_cs:      Flag for decoder property set or not
 113  * @tx_fifo_depth:      Depth of the TX FIFO
 114  */
 115 struct cdns_spi {
 116         void __iomem *regs;
 117         struct clk *ref_clk;
 118         struct clk *pclk;
 119         unsigned int clk_rate;
 120         u32 speed_hz;
 121         const u8 *txbuf;
 122         u8 *rxbuf;
 123         int tx_bytes;
 124         int rx_bytes;
 125         u8 dev_busy;
 126         u32 is_decoded_cs;
 127         unsigned int tx_fifo_depth;
 128 };
 129
 130 /* Macros for the SPI controller read/write */
 131 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
 132 {
 133         return readl_relaxed(xspi->regs + offset);
 134 }
 135
 136 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
 137 {
 138         writel_relaxed(val, xspi->regs + offset);
 139 }
 140
 141 /**
 142  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
 143  * @xspi:       Pointer to the cdns_spi structure
 144  * @is_slave:   Flag to indicate slave or master mode
 145  * * On reset the SPI controller is configured to slave or  master mode.
 146  * In master mode baud rate divisor is set to 4, threshold value for TX FIFO
 147  * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
 148  *
 149  * This function initializes the SPI controller to disable and clear all the
 150  * interrupts, enable manual slave select and manual start, deselect all the
 151  * chip select lines, and enable the SPI controller.
 152  */
 153 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_slave)
 154 {
 155         u32 ctrl_reg = 0;
 156
 157         if (!is_slave)
 158                 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
 159
 160         if (xspi->is_decoded_cs)
 161                 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
 162
 163         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 164         cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
 165
 166         /* Clear the RX FIFO */
 167         while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
 168                 cdns_spi_read(xspi, CDNS_SPI_RXD);
 169
 170         cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
 171         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 172         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 173 }
 174
 175 /**
 176  * cdns_spi_chipselect - Select or deselect the chip select line
 177  * @spi:        Pointer to the spi_device structure
 178  * @is_high:    Select(0) or deselect (1) the chip select line
 179  */
 180 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
 181 {
 182         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 183         u32 ctrl_reg;
 184
 185         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 186
 187         if (is_high) {
 188                 /* Deselect the slave */
 189                 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
 190         } else {
 191                 /* Select the slave */
 192                 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
 193                 if (!(xspi->is_decoded_cs))
 194                         ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
 195                                      CDNS_SPI_SS_SHIFT) &
 196                                      CDNS_SPI_CR_SSCTRL;
 197                 else
 198                         ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
 199                                      CDNS_SPI_CR_SSCTRL;
 200         }
 201
 202         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 203 }
 204
 205 /**
 206  * cdns_spi_config_clock_mode - Sets clock polarity and phase
 207  * @spi:        Pointer to the spi_device structure
 208  *
 209  * Sets the requested clock polarity and phase.
 210  */
 211 static void cdns_spi_config_clock_mode(struct spi_device *spi)
 212 {
 213         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 214         u32 ctrl_reg, new_ctrl_reg;
 215
 216         new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 217         ctrl_reg = new_ctrl_reg;
 218
 219         /* Set the SPI clock phase and clock polarity */
 220         new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
 221         if (spi->mode & SPI_CPHA)
 222                 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
 223         if (spi->mode & SPI_CPOL)
 224                 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
 225
 226         if (new_ctrl_reg != ctrl_reg) {
 227                 /*
 228                  * Just writing the CR register does not seem to apply the clock
 229                  * setting changes. This is problematic when changing the clock
 230                  * polarity as it will cause the SPI slave to see spurious clock
 231                  * transitions. To workaround the issue toggle the ER register.
 232                  */
 233                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 234                 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
 235                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 236         }
 237 }
 238
 239 /**
 240  * cdns_spi_config_clock_freq - Sets clock frequency
 241  * @spi:        Pointer to the spi_device structure
 242  * @transfer:   Pointer to the spi_transfer structure which provides
 243  *              information about next transfer setup parameters
 244  *
 245  * Sets the requested clock frequency.
 246  * Note: If the requested frequency is not an exact match with what can be
 247  * obtained using the prescalar value the driver sets the clock frequency which
 248  * is lower than the requested frequency (maximum lower) for the transfer. If
 249  * the requested frequency is higher or lower than that is supported by the SPI
 250  * controller the driver will set the highest or lowest frequency supported by
 251  * controller.
 252  */
 253 static void cdns_spi_config_clock_freq(struct spi_device *spi,
 254                                        struct spi_transfer *transfer)
 255 {
 256         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 257         u32 ctrl_reg, baud_rate_val;
 258         unsigned long frequency;
 259
 260         frequency = xspi->clk_rate;
 261
 262         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 263
 264         /* Set the clock frequency */
 265         if (xspi->speed_hz != transfer->speed_hz) {
 266                 /* first valid value is 1 */
 267                 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
 268                 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
 269                        (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
 270                         baud_rate_val++;
 271
 272                 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
 273                 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
 274
 275                 xspi->speed_hz = frequency / (2 << baud_rate_val);
 276         }
 277         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 278 }
 279
 280 /**
 281  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
 282  * @spi:        Pointer to the spi_device structure
 283  * @transfer:   Pointer to the spi_transfer structure which provides
 284  *              information about next transfer setup parameters
 285  *
 286  * Sets the operational mode of SPI controller for the next SPI transfer and
 287  * sets the requested clock frequency.
 288  *
 289  * Return:      Always 0
 290  */
 291 static int cdns_spi_setup_transfer(struct spi_device *spi,
 292                                    struct spi_transfer *transfer)
 293 {
 294         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 295
 296         cdns_spi_config_clock_freq(spi, transfer);
 297
 298         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
 299                 __func__, spi->mode, spi->bits_per_word,
 300                 xspi->speed_hz);
 301
 302         return 0;
 303 }
 304
 305 /**
 306  * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
 307  * @xspi:       Pointer to the cdns_spi structure
 308  * @ntx:        Number of bytes to pack into the TX FIFO
 309  * @nrx:        Number of bytes to drain from the RX FIFO
 310  */
 311 static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
 312 {
 313         ntx = clamp(ntx, 0, xspi->tx_bytes);
 314         nrx = clamp(nrx, 0, xspi->rx_bytes);
 315
 316         xspi->tx_bytes -= ntx;
 317         xspi->rx_bytes -= nrx;
 318
 319         while (ntx || nrx) {
 320                 /* When xspi in busy condition, bytes may send failed,
 321                  * then spi control did't work thoroughly, add one byte delay
 322                  */
 323                 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
 324                         udelay(10);
 325
 326                 if (ntx) {
 327                         if (xspi->txbuf)
 328                                 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
 329                         else
 330                                 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
 331
 332                         ntx--;
 333                 }
 334
 335                 if (nrx) {
 336                         u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
 337
 338                         if (xspi->rxbuf)
 339                                 *xspi->rxbuf++ = data;
 340
 341                         nrx--;
 342                 }
 343         }
 344 }
 345
 346 /**
 347  * cdns_spi_irq - Interrupt service routine of the SPI controller
 348  * @irq:        IRQ number
 349  * @dev_id:     Pointer to the xspi structure
 350  *
 351  * This function handles TX empty and Mode Fault interrupts only.
 352  * On TX empty interrupt this function reads the received data from RX FIFO and
 353  * fills the TX FIFO if there is any data remaining to be transferred.
 354  * On Mode Fault interrupt this function indicates that transfer is completed,
 355  * the SPI subsystem will identify the error as the remaining bytes to be
 356  * transferred is non-zero.
 357  *
 358  * Return:      IRQ_HANDLED when handled; IRQ_NONE otherwise.
 359  */
 360 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
 361 {
 362         struct spi_controller *ctlr = dev_id;
 363         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 364         irqreturn_t status;
 365         u32 intr_status;
 366
 367         status = IRQ_NONE;
 368         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 369         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 370
 371         if (intr_status & CDNS_SPI_IXR_MODF) {
 372                 /* Indicate that transfer is completed, the SPI subsystem will
 373                  * identify the error as the remaining bytes to be
 374                  * transferred is non-zero
 375                  */
 376                 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
 377                 spi_finalize_current_transfer(ctlr);
 378                 status = IRQ_HANDLED;
 379         } else if (intr_status & CDNS_SPI_IXR_TXOW) {
 380                 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
 381                 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
 382
 383                 if (threshold > 1)
 384                         trans_cnt -= threshold;
 385
 386                 /* Set threshold to one if number of pending are
 387                  * less than half fifo
 388                  */
 389                 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
 390                         cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
 391
 392                 if (xspi->tx_bytes) {
 393                         cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
 394                 } else {
 395                         cdns_spi_process_fifo(xspi, 0, trans_cnt);
 396                         cdns_spi_write(xspi, CDNS_SPI_IDR,
 397                                        CDNS_SPI_IXR_DEFAULT);
 398                         spi_finalize_current_transfer(ctlr);
 399                 }
 400                 status = IRQ_HANDLED;
 401         }
 402
 403         return status;
 404 }
 405
 406 static int cdns_prepare_message(struct spi_controller *ctlr,
 407                                 struct spi_message *msg)
 408 {
 409         if (!spi_controller_is_slave(ctlr))
 410                 cdns_spi_config_clock_mode(msg->spi);
 411         return 0;
 412 }
 413
 414 /**
 415  * cdns_transfer_one - Initiates the SPI transfer
 416  * @ctlr:       Pointer to spi_controller structure
 417  * @spi:        Pointer to the spi_device structure
 418  * @transfer:   Pointer to the spi_transfer structure which provides
 419  *              information about next transfer parameters
 420  *
 421  * This function in master mode fills the TX FIFO, starts the SPI transfer and
 422  * returns a positive transfer count so that core will wait for completion.
 423  * This function in slave mode fills the TX FIFO and wait for transfer trigger.
 424  *
 425  * Return:      Number of bytes transferred in the last transfer
 426  */
 427 static int cdns_transfer_one(struct spi_controller *ctlr,
 428                              struct spi_device *spi,
 429                              struct spi_transfer *transfer)
 430 {
 431         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 432
 433         xspi->txbuf = transfer->tx_buf;
 434         xspi->rxbuf = transfer->rx_buf;
 435         xspi->tx_bytes = transfer->len;
 436         xspi->rx_bytes = transfer->len;
 437
 438         if (!spi_controller_is_slave(ctlr)) {
 439                 cdns_spi_setup_transfer(spi, transfer);
 440         } else {
 441                 /* Set TX empty threshold to half of FIFO depth
 442                  * only if TX bytes are more than half FIFO depth.
 443                  */
 444                 if (xspi->tx_bytes > xspi->tx_fifo_depth)
 445                         cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
 446         }
 447
 448         cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
 449         spi_transfer_delay_exec(transfer);
 450
 451         cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
 452         return transfer->len;
 453 }
 454
 455 /**
 456  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
 457  * @ctlr:       Pointer to the spi_controller structure which provides
 458  *              information about the controller.
 459  *
 460  * This function enables SPI master controller.
 461  *
 462  * Return:      0 always
 463  */
 464 static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
 465 {
 466         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 467
 468         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 469
 470         return 0;
 471 }
 472
 473 /**
 474  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
 475  * @ctlr:       Pointer to the spi_controller structure which provides
 476  *              information about the controller.
 477  *
 478  * This function disables the SPI master controller when no slave selected.
 479  * This function flush out if any pending data in FIFO.
 480  *
 481  * Return:      0 always
 482  */
 483 static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
 484 {
 485         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 486         u32 ctrl_reg;
 487         unsigned int cnt = xspi->tx_fifo_depth;
 488
 489         if (spi_controller_is_slave(ctlr)) {
 490                 while (cnt--)
 491                         cdns_spi_read(xspi, CDNS_SPI_RXD);
 492         }
 493
 494         /* Disable the SPI if slave is deselected */
 495         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 496         ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >>  CDNS_SPI_SS_SHIFT;
 497         if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_slave(ctlr))
 498                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 499
 500         /* Reset to default */
 501         cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
 502         return 0;
 503 }
 504
 505 /**
 506  * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
 507  * @xspi:       Pointer to the cdns_spi structure
 508  *
 509  * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
 510  * IP. The FIFO threshold register is sized so that its maximum value can be the
 511  * FIFO size - 1. This is used to detect the size of the FIFO.
 512  */
 513 static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
 514 {
 515         /* The MSBs will get truncated giving us the size of the FIFO */
 516         cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
 517         xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
 518
 519         /* Reset to default */
 520         cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
 521 }
 522
 523 /**
 524  * cdns_slave_abort - Abort slave transfer
 525  * @ctlr:       Pointer to the spi_controller structure
 526  *
 527  * This function abort slave transfer if there any transfer timeout.
 528  *
 529  * Return:      0 always
 530  */
 531 static int cdns_slave_abort(struct spi_controller *ctlr)
 532 {
 533         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 534         u32 intr_status;
 535
 536         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 537         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 538         cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
 539         spi_finalize_current_transfer(ctlr);
 540
 541         return 0;
 542 }
 543
 544 /**
 545  * cdns_spi_probe - Probe method for the SPI driver
 546  * @pdev:       Pointer to the platform_device structure
 547  *
 548  * This function initializes the driver data structures and the hardware.
 549  *
 550  * Return:      0 on success and error value on error
 551  */
 552 static int cdns_spi_probe(struct platform_device *pdev)
 553 {
 554         int ret = 0, irq;
 555         struct spi_controller *ctlr;
 556         struct cdns_spi *xspi;
 557         u32 num_cs;
 558         bool slave;
 559
 560         slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
 561         if (slave)
 562                 ctlr = spi_alloc_slave(&pdev->dev, sizeof(*xspi));
 563         else
 564                 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xspi));
 565
 566         if (!ctlr)
 567                 return -ENOMEM;
 568
 569         xspi = spi_controller_get_devdata(ctlr);
 570         ctlr->dev.of_node = pdev->dev.of_node;
 571         platform_set_drvdata(pdev, ctlr);
 572
 573         xspi->regs = devm_platform_ioremap_resource(pdev, 0);
 574         if (IS_ERR(xspi->regs)) {
 575                 ret = PTR_ERR(xspi->regs);
 576                 goto remove_ctlr;
 577         }
 578
 579         xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
 580         if (IS_ERR(xspi->pclk)) {
 581                 dev_err(&pdev->dev, "pclk clock not found.\n");
 582                 ret = PTR_ERR(xspi->pclk);
 583                 goto remove_ctlr;
 584         }
 585
 586         ret = clk_prepare_enable(xspi->pclk);
 587         if (ret) {
 588                 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
 589                 goto remove_ctlr;
 590         }
 591
 592         if (!spi_controller_is_slave(ctlr)) {
 593                 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
 594                 if (IS_ERR(xspi->ref_clk)) {
 595                         dev_err(&pdev->dev, "ref_clk clock not found.\n");
 596                         ret = PTR_ERR(xspi->ref_clk);
 597                         goto clk_dis_apb;
 598                 }
 599
 600                 ret = clk_prepare_enable(xspi->ref_clk);
 601                 if (ret) {
 602                         dev_err(&pdev->dev, "Unable to enable device clock.\n");
 603                         goto clk_dis_apb;
 604                 }
 605
 606                 pm_runtime_use_autosuspend(&pdev->dev);
 607                 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 608                 pm_runtime_get_noresume(&pdev->dev);
 609                 pm_runtime_set_active(&pdev->dev);
 610                 pm_runtime_enable(&pdev->dev);
 611
 612                 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 613                 if (ret < 0)
 614                         ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
 615                 else
 616                         ctlr->num_chipselect = num_cs;
 617
 618                 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
 619                                            &xspi->is_decoded_cs);
 620                 if (ret < 0)
 621                         xspi->is_decoded_cs = 0;
 622         }
 623
 624         cdns_spi_detect_fifo_depth(xspi);
 625
 626         /* SPI controller initializations */
 627         cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
 628
 629         irq = platform_get_irq(pdev, 0);
 630         if (irq <= 0) {
 631                 ret = -ENXIO;
 632                 goto clk_dis_all;
 633         }
 634
 635         ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
 636                                0, pdev->name, ctlr);
 637         if (ret != 0) {
 638                 ret = -ENXIO;
 639                 dev_err(&pdev->dev, "request_irq failed\n");
 640                 goto clk_dis_all;
 641         }
 642
 643         ctlr->use_gpio_descriptors = true;
 644         ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
 645         ctlr->prepare_message = cdns_prepare_message;
 646         ctlr->transfer_one = cdns_transfer_one;
 647         ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 648         ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
 649         ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 650
 651         if (!spi_controller_is_slave(ctlr)) {
 652                 ctlr->mode_bits |=  SPI_CS_HIGH;
 653                 ctlr->set_cs = cdns_spi_chipselect;
 654                 ctlr->auto_runtime_pm = true;
 655                 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
 656                 /* Set to default valid value */
 657                 ctlr->max_speed_hz = xspi->clk_rate / 4;
 658                 xspi->speed_hz = ctlr->max_speed_hz;
 659                 pm_runtime_mark_last_busy(&pdev->dev);
 660                 pm_runtime_put_autosuspend(&pdev->dev);
 661         } else {
 662                 ctlr->mode_bits |= SPI_NO_CS;
 663                 ctlr->slave_abort = cdns_slave_abort;
 664         }
 665         ret = spi_register_controller(ctlr);
 666         if (ret) {
 667                 dev_err(&pdev->dev, "spi_register_controller failed\n");
 668                 goto clk_dis_all;
 669         }
 670
 671         return ret;
 672
 673 clk_dis_all:
 674         if (!spi_controller_is_slave(ctlr)) {
 675                 pm_runtime_set_suspended(&pdev->dev);
 676                 pm_runtime_disable(&pdev->dev);
 677                 clk_disable_unprepare(xspi->ref_clk);
 678         }
 679 clk_dis_apb:
 680         clk_disable_unprepare(xspi->pclk);
 681 remove_ctlr:
 682         spi_controller_put(ctlr);
 683         return ret;
 684 }
 685
 686 /**
 687  * cdns_spi_remove - Remove method for the SPI driver
 688  * @pdev:       Pointer to the platform_device structure
 689  *
 690  * This function is called if a device is physically removed from the system or
 691  * if the driver module is being unloaded. It frees all resources allocated to
 692  * the device.
 693  *
 694  * Return:      0 on success and error value on error
 695  */
 696 static void cdns_spi_remove(struct platform_device *pdev)
 697 {
 698         struct spi_controller *ctlr = platform_get_drvdata(pdev);
 699         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 700
 701         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 702
 703         clk_disable_unprepare(xspi->ref_clk);
 704         clk_disable_unprepare(xspi->pclk);
 705         pm_runtime_set_suspended(&pdev->dev);
 706         pm_runtime_disable(&pdev->dev);
 707
 708         spi_unregister_controller(ctlr);
 709 }
 710
 711 /**
 712  * cdns_spi_suspend - Suspend method for the SPI driver
 713  * @dev:        Address of the platform_device structure
 714  *
 715  * This function disables the SPI controller and
 716  * changes the driver state to "suspend"
 717  *
 718  * Return:      0 on success and error value on error
 719  */
 720 static int __maybe_unused cdns_spi_suspend(struct device *dev)
 721 {
 722         struct spi_controller *ctlr = dev_get_drvdata(dev);
 723
 724         return spi_controller_suspend(ctlr);
 725 }
 726
 727 /**
 728  * cdns_spi_resume - Resume method for the SPI driver
 729  * @dev:        Address of the platform_device structure
 730  *
 731  * This function changes the driver state to "ready"
 732  *
 733  * Return:      0 on success and error value on error
 734  */
 735 static int __maybe_unused cdns_spi_resume(struct device *dev)
 736 {
 737         struct spi_controller *ctlr = dev_get_drvdata(dev);
 738         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 739
 740         cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
 741         return spi_controller_resume(ctlr);
 742 }
 743
 744 /**
 745  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
 746  * @dev:        Address of the platform_device structure
 747  *
 748  * This function enables the clocks
 749  *
 750  * Return:      0 on success and error value on error
 751  */
 752 static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
 753 {
 754         struct spi_controller *ctlr = dev_get_drvdata(dev);
 755         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 756         int ret;
 757
 758         ret = clk_prepare_enable(xspi->pclk);
 759         if (ret) {
 760                 dev_err(dev, "Cannot enable APB clock.\n");
 761                 return ret;
 762         }
 763
 764         ret = clk_prepare_enable(xspi->ref_clk);
 765         if (ret) {
 766                 dev_err(dev, "Cannot enable device clock.\n");
 767                 clk_disable_unprepare(xspi->pclk);
 768                 return ret;
 769         }
 770         return 0;
 771 }
 772
 773 /**
 774  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
 775  * @dev:        Address of the platform_device structure
 776  *
 777  * This function disables the clocks
 778  *
 779  * Return:      Always 0
 780  */
 781 static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
 782 {
 783         struct spi_controller *ctlr = dev_get_drvdata(dev);
 784         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 785
 786         clk_disable_unprepare(xspi->ref_clk);
 787         clk_disable_unprepare(xspi->pclk);
 788
 789         return 0;
 790 }
 791
 792 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
 793         SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
 794                            cdns_spi_runtime_resume, NULL)
 795         SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
 796 };
 797
 798 static const struct of_device_id cdns_spi_of_match[] = {
 799         { .compatible = "xlnx,zynq-spi-r1p6" },
 800         { .compatible = "cdns,spi-r1p6" },
 801         { /* end of table */ }
 802 };
 803 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
 804
 805 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
 806 static struct platform_driver cdns_spi_driver = {
 807         .probe  = cdns_spi_probe,
 808         .remove_new = cdns_spi_remove,
 809         .driver = {
 810                 .name = CDNS_SPI_NAME,
 811                 .of_match_table = cdns_spi_of_match,
 812                 .pm = &cdns_spi_dev_pm_ops,
 813         },
 814 };
 815
 816 module_platform_driver(cdns_spi_driver);
 817
 818 MODULE_AUTHOR("Xilinx, Inc.");
 819 MODULE_DESCRIPTION("Cadence SPI driver");
 820 MODULE_LICENSE("GPL");