drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  54
  55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  56 {
  57         SDMA0_REGISTER_OFFSET,
  58         SDMA1_REGISTER_OFFSET
  59 };
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  64         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  65         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  72         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  73 };
  74
  75 /*
  76  * sDMA - System DMA
  77  * Starting with CIK, the GPU has new asynchronous
  78  * DMA engines.  These engines are used for compute
  79  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  80  * and each one supports 1 ring buffer used for gfx
  81  * and 2 queues used for compute.
  82  *
  83  * The programming model is very similar to the CP
  84  * (ring buffer, IBs, etc.), but sDMA has it's own
  85  * packet format that is different from the PM4 format
  86  * used by the CP. sDMA supports copying data, writing
  87  * embedded data, solid fills, and a number of other
  88  * things.  It also has support for tiling/detiling of
  89  * buffers.
  90  */
  91
  92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  93 {
  94         switch (adev->asic_type) {
  95         case CHIP_TOPAZ:
  96                 amdgpu_program_register_sequence(adev,
  97                                                  iceland_mgcg_cgcg_init,
  98                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  99                 amdgpu_program_register_sequence(adev,
 100                                                  golden_settings_iceland_a11,
 101                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 /**
 109  * sdma_v2_4_init_microcode - load ucode images from disk
 110  *
 111  * @adev: amdgpu_device pointer
 112  *
 113  * Use the firmware interface to load the ucode images into
 114  * the driver (not loaded into hw).
 115  * Returns 0 on success, error on failure.
 116  */
 117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 118 {
 119         const char *chip_name;
 120         char fw_name[30];
 121         int err, i;
 122         struct amdgpu_firmware_info *info = NULL;
 123         const struct common_firmware_header *header = NULL;
 124
 125         DRM_DEBUG("\n");
 126
 127         switch (adev->asic_type) {
 128         case CHIP_TOPAZ:
 129                 chip_name = "topaz";
 130                 break;
 131         default: BUG();
 132         }
 133
 134         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 135                 if (i == 0)
 136                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 137                 else
 138                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 139                 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
 140                 if (err)
 141                         goto out;
 142                 err = amdgpu_ucode_validate(adev->sdma[i].fw);
 143                 if (err)
 144                         goto out;
 145
 146                 if (adev->firmware.smu_load) {
 147                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 148                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 149                         info->fw = adev->sdma[i].fw;
 150                         header = (const struct common_firmware_header *)info->fw->data;
 151                         adev->firmware.fw_size +=
 152                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 153                 }
 154         }
 155
 156 out:
 157         if (err) {
 158                 printk(KERN_ERR
 159                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 160                        fw_name);
 161                 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 162                         release_firmware(adev->sdma[i].fw);
 163                         adev->sdma[i].fw = NULL;
 164                 }
 165         }
 166         return err;
 167 }
 168
 169 /**
 170  * sdma_v2_4_ring_get_rptr - get the current read pointer
 171  *
 172  * @ring: amdgpu ring pointer
 173  *
 174  * Get the current rptr from the hardware (VI+).
 175  */
 176 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 177 {
 178         u32 rptr;
 179
 180         /* XXX check if swapping is necessary on BE */
 181         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 182
 183         return rptr;
 184 }
 185
 186 /**
 187  * sdma_v2_4_ring_get_wptr - get the current write pointer
 188  *
 189  * @ring: amdgpu ring pointer
 190  *
 191  * Get the current wptr from the hardware (VI+).
 192  */
 193 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 194 {
 195         struct amdgpu_device *adev = ring->adev;
 196         int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
 197         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 198
 199         return wptr;
 200 }
 201
 202 /**
 203  * sdma_v2_4_ring_set_wptr - commit the write pointer
 204  *
 205  * @ring: amdgpu ring pointer
 206  *
 207  * Write the wptr back to the hardware (VI+).
 208  */
 209 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 210 {
 211         struct amdgpu_device *adev = ring->adev;
 212         int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
 213
 214         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 215 }
 216
 217 /**
 218  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 219  *
 220  * @ring: amdgpu ring pointer
 221  * @ib: IB object to schedule
 222  *
 223  * Schedule an IB in the DMA ring (VI).
 224  */
 225 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 226                                    struct amdgpu_ib *ib)
 227 {
 228         u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 229         u32 next_rptr = ring->wptr + 5;
 230
 231         while ((next_rptr & 7) != 2)
 232                 next_rptr++;
 233
 234         next_rptr += 6;
 235
 236         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 237                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 238         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 239         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 240         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 241         amdgpu_ring_write(ring, next_rptr);
 242
 243         /* IB packet must end on a 8 DW boundary */
 244         while ((ring->wptr & 7) != 2)
 245                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
 246         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 247                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 248         /* base must be 32 byte aligned */
 249         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 250         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 251         amdgpu_ring_write(ring, ib->length_dw);
 252         amdgpu_ring_write(ring, 0);
 253         amdgpu_ring_write(ring, 0);
 254
 255 }
 256
 257 /**
 258  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 259  *
 260  * @ring: amdgpu ring pointer
 261  *
 262  * Emit an hdp flush packet on the requested DMA ring.
 263  */
 264 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 265 {
 266         u32 ref_and_mask = 0;
 267
 268         if (ring == &ring->adev->sdma[0].ring)
 269                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 270         else
 271                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 272
 273         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 274                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 275                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 276         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 277         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 278         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 279         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 280         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 281                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 282 }
 283
 284 /**
 285  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 286  *
 287  * @ring: amdgpu ring pointer
 288  * @fence: amdgpu fence object
 289  *
 290  * Add a DMA fence packet to the ring to write
 291  * the fence seq number and DMA trap packet to generate
 292  * an interrupt if needed (VI).
 293  */
 294 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 295                                       bool write64bits)
 296 {
 297         /* write the fence */
 298         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 299         amdgpu_ring_write(ring, lower_32_bits(addr));
 300         amdgpu_ring_write(ring, upper_32_bits(addr));
 301         amdgpu_ring_write(ring, lower_32_bits(seq));
 302
 303         /* optionally write high bits as well */
 304         if (write64bits) {
 305                 addr += 4;
 306                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 307                 amdgpu_ring_write(ring, lower_32_bits(addr));
 308                 amdgpu_ring_write(ring, upper_32_bits(addr));
 309                 amdgpu_ring_write(ring, upper_32_bits(seq));
 310         }
 311
 312         /* generate an interrupt */
 313         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 314         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 315 }
 316
 317 /**
 318  * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
 319  *
 320  * @ring: amdgpu_ring structure holding ring information
 321  * @semaphore: amdgpu semaphore object
 322  * @emit_wait: wait or signal semaphore
 323  *
 324  * Add a DMA semaphore packet to the ring wait on or signal
 325  * other rings (VI).
 326  */
 327 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
 328                                           struct amdgpu_semaphore *semaphore,
 329                                           bool emit_wait)
 330 {
 331         u64 addr = semaphore->gpu_addr;
 332         u32 sig = emit_wait ? 0 : 1;
 333
 334         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
 335                           SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
 336         amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
 337         amdgpu_ring_write(ring, upper_32_bits(addr));
 338
 339         return true;
 340 }
 341
 342 /**
 343  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 344  *
 345  * @adev: amdgpu_device pointer
 346  *
 347  * Stop the gfx async dma ring buffers (VI).
 348  */
 349 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 350 {
 351         struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
 352         struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
 353         u32 rb_cntl, ib_cntl;
 354         int i;
 355
 356         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 357             (adev->mman.buffer_funcs_ring == sdma1))
 358                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 359
 360         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 361                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 362                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 363                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 364                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 365                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 366                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 367         }
 368         sdma0->ready = false;
 369         sdma1->ready = false;
 370 }
 371
 372 /**
 373  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 374  *
 375  * @adev: amdgpu_device pointer
 376  *
 377  * Stop the compute async dma queues (VI).
 378  */
 379 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 380 {
 381         /* XXX todo */
 382 }
 383
 384 /**
 385  * sdma_v2_4_enable - stop the async dma engines
 386  *
 387  * @adev: amdgpu_device pointer
 388  * @enable: enable/disable the DMA MEs.
 389  *
 390  * Halt or unhalt the async dma engines (VI).
 391  */
 392 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 393 {
 394         u32 f32_cntl;
 395         int i;
 396
 397         if (enable == false) {
 398                 sdma_v2_4_gfx_stop(adev);
 399                 sdma_v2_4_rlc_stop(adev);
 400         }
 401
 402         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 403                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 404                 if (enable)
 405                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 406                 else
 407                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 408                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 409         }
 410 }
 411
 412 /**
 413  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 414  *
 415  * @adev: amdgpu_device pointer
 416  *
 417  * Set up the gfx DMA ring buffers and enable them (VI).
 418  * Returns 0 for success, error for failure.
 419  */
 420 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 421 {
 422         struct amdgpu_ring *ring;
 423         u32 rb_cntl, ib_cntl;
 424         u32 rb_bufsz;
 425         u32 wb_offset;
 426         int i, j, r;
 427
 428         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 429                 ring = &adev->sdma[i].ring;
 430                 wb_offset = (ring->rptr_offs * 4);
 431
 432                 mutex_lock(&adev->srbm_mutex);
 433                 for (j = 0; j < 16; j++) {
 434                         vi_srbm_select(adev, 0, 0, 0, j);
 435                         /* SDMA GFX */
 436                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 437                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 438                 }
 439                 vi_srbm_select(adev, 0, 0, 0, 0);
 440                 mutex_unlock(&adev->srbm_mutex);
 441
 442                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 443
 444                 /* Set ring buffer size in dwords */
 445                 rb_bufsz = order_base_2(ring->ring_size / 4);
 446                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 447                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 448 #ifdef __BIG_ENDIAN
 449                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 450                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 451                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 452 #endif
 453                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 454
 455                 /* Initialize the ring buffer's read and write pointers */
 456                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 457                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 458
 459                 /* set the wb address whether it's enabled or not */
 460                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 461                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 462                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 463                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 464
 465                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 466
 467                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 468                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 469
 470                 ring->wptr = 0;
 471                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 472
 473                 /* enable DMA RB */
 474                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 475                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 476
 477                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 478                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 479 #ifdef __BIG_ENDIAN
 480                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 481 #endif
 482                 /* enable DMA IBs */
 483                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 484
 485                 ring->ready = true;
 486
 487                 r = amdgpu_ring_test_ring(ring);
 488                 if (r) {
 489                         ring->ready = false;
 490                         return r;
 491                 }
 492
 493                 if (adev->mman.buffer_funcs_ring == ring)
 494                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 495         }
 496
 497         return 0;
 498 }
 499
 500 /**
 501  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 502  *
 503  * @adev: amdgpu_device pointer
 504  *
 505  * Set up the compute DMA queues and enable them (VI).
 506  * Returns 0 for success, error for failure.
 507  */
 508 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 509 {
 510         /* XXX todo */
 511         return 0;
 512 }
 513
 514 /**
 515  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 516  *
 517  * @adev: amdgpu_device pointer
 518  *
 519  * Loads the sDMA0/1 ucode.
 520  * Returns 0 for success, -EINVAL if the ucode is not available.
 521  */
 522 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 523 {
 524         const struct sdma_firmware_header_v1_0 *hdr;
 525         const __le32 *fw_data;
 526         u32 fw_size;
 527         int i, j;
 528         bool smc_loads_fw = false; /* XXX fix me */
 529
 530         if (!adev->sdma[0].fw || !adev->sdma[1].fw)
 531                 return -EINVAL;
 532
 533         /* halt the MEs */
 534         sdma_v2_4_enable(adev, false);
 535
 536         if (smc_loads_fw) {
 537                 /* XXX query SMC for fw load complete */
 538         } else {
 539                 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 540                         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 541                         amdgpu_ucode_print_sdma_hdr(&hdr->header);
 542                         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 543                         adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 544
 545                         fw_data = (const __le32 *)
 546                                 (adev->sdma[i].fw->data +
 547                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 548                         WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 549                         for (j = 0; j < fw_size; j++)
 550                                 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 551                         WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
 552                 }
 553         }
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * sdma_v2_4_start - setup and start the async dma engines
 560  *
 561  * @adev: amdgpu_device pointer
 562  *
 563  * Set up the DMA engines and enable them (VI).
 564  * Returns 0 for success, error for failure.
 565  */
 566 static int sdma_v2_4_start(struct amdgpu_device *adev)
 567 {
 568         int r;
 569
 570         if (!adev->firmware.smu_load) {
 571                 r = sdma_v2_4_load_microcode(adev);
 572                 if (r)
 573                         return r;
 574         } else {
 575                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 576                                                 AMDGPU_UCODE_ID_SDMA0);
 577                 if (r)
 578                         return -EINVAL;
 579                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 580                                                 AMDGPU_UCODE_ID_SDMA1);
 581                 if (r)
 582                         return -EINVAL;
 583         }
 584
 585         /* unhalt the MEs */
 586         sdma_v2_4_enable(adev, true);
 587
 588         /* start the gfx rings and rlc compute queues */
 589         r = sdma_v2_4_gfx_resume(adev);
 590         if (r)
 591                 return r;
 592         r = sdma_v2_4_rlc_resume(adev);
 593         if (r)
 594                 return r;
 595
 596         return 0;
 597 }
 598
 599 /**
 600  * sdma_v2_4_ring_test_ring - simple async dma engine test
 601  *
 602  * @ring: amdgpu_ring structure holding ring information
 603  *
 604  * Test the DMA engine by writing using it to write an
 605  * value to memory. (VI).
 606  * Returns 0 for success, error for failure.
 607  */
 608 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 609 {
 610         struct amdgpu_device *adev = ring->adev;
 611         unsigned i;
 612         unsigned index;
 613         int r;
 614         u32 tmp;
 615         u64 gpu_addr;
 616
 617         r = amdgpu_wb_get(adev, &index);
 618         if (r) {
 619                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 620                 return r;
 621         }
 622
 623         gpu_addr = adev->wb.gpu_addr + (index * 4);
 624         tmp = 0xCAFEDEAD;
 625         adev->wb.wb[index] = cpu_to_le32(tmp);
 626
 627         r = amdgpu_ring_lock(ring, 5);
 628         if (r) {
 629                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 630                 amdgpu_wb_free(adev, index);
 631                 return r;
 632         }
 633
 634         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 635                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 636         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 637         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 638         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 639         amdgpu_ring_write(ring, 0xDEADBEEF);
 640         amdgpu_ring_unlock_commit(ring);
 641
 642         for (i = 0; i < adev->usec_timeout; i++) {
 643                 tmp = le32_to_cpu(adev->wb.wb[index]);
 644                 if (tmp == 0xDEADBEEF)
 645                         break;
 646                 DRM_UDELAY(1);
 647         }
 648
 649         if (i < adev->usec_timeout) {
 650                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 651         } else {
 652                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 653                           ring->idx, tmp);
 654                 r = -EINVAL;
 655         }
 656         amdgpu_wb_free(adev, index);
 657
 658         return r;
 659 }
 660
 661 /**
 662  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 663  *
 664  * @ring: amdgpu_ring structure holding ring information
 665  *
 666  * Test a simple IB in the DMA ring (VI).
 667  * Returns 0 on success, error on failure.
 668  */
 669 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
 670 {
 671         struct amdgpu_device *adev = ring->adev;
 672         struct amdgpu_ib ib;
 673         unsigned i;
 674         unsigned index;
 675         int r;
 676         u32 tmp = 0;
 677         u64 gpu_addr;
 678
 679         r = amdgpu_wb_get(adev, &index);
 680         if (r) {
 681                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 682                 return r;
 683         }
 684
 685         gpu_addr = adev->wb.gpu_addr + (index * 4);
 686         tmp = 0xCAFEDEAD;
 687         adev->wb.wb[index] = cpu_to_le32(tmp);
 688
 689         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 690         if (r) {
 691                 amdgpu_wb_free(adev, index);
 692                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 693                 return r;
 694         }
 695
 696         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 697                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 698         ib.ptr[1] = lower_32_bits(gpu_addr);
 699         ib.ptr[2] = upper_32_bits(gpu_addr);
 700         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 701         ib.ptr[4] = 0xDEADBEEF;
 702         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 703         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 704         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 705         ib.length_dw = 8;
 706
 707         r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
 708         if (r) {
 709                 amdgpu_ib_free(adev, &ib);
 710                 amdgpu_wb_free(adev, index);
 711                 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
 712                 return r;
 713         }
 714         r = amdgpu_fence_wait(ib.fence, false);
 715         if (r) {
 716                 amdgpu_ib_free(adev, &ib);
 717                 amdgpu_wb_free(adev, index);
 718                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 719                 return r;
 720         }
 721         for (i = 0; i < adev->usec_timeout; i++) {
 722                 tmp = le32_to_cpu(adev->wb.wb[index]);
 723                 if (tmp == 0xDEADBEEF)
 724                         break;
 725                 DRM_UDELAY(1);
 726         }
 727         if (i < adev->usec_timeout) {
 728                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 729                          ib.fence->ring->idx, i);
 730         } else {
 731                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 732                 r = -EINVAL;
 733         }
 734         amdgpu_ib_free(adev, &ib);
 735         amdgpu_wb_free(adev, index);
 736         return r;
 737 }
 738
 739 /**
 740  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 741  *
 742  * @ib: indirect buffer to fill with commands
 743  * @pe: addr of the page entry
 744  * @src: src addr to copy from
 745  * @count: number of page entries to update
 746  *
 747  * Update PTEs by copying them from the GART using sDMA (CIK).
 748  */
 749 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 750                                   uint64_t pe, uint64_t src,
 751                                   unsigned count)
 752 {
 753         while (count) {
 754                 unsigned bytes = count * 8;
 755                 if (bytes > 0x1FFFF8)
 756                         bytes = 0x1FFFF8;
 757
 758                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 759                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 760                 ib->ptr[ib->length_dw++] = bytes;
 761                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 762                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 763                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 764                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 765                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 766
 767                 pe += bytes;
 768                 src += bytes;
 769                 count -= bytes / 8;
 770         }
 771 }
 772
 773 /**
 774  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 775  *
 776  * @ib: indirect buffer to fill with commands
 777  * @pe: addr of the page entry
 778  * @addr: dst addr to write into pe
 779  * @count: number of page entries to update
 780  * @incr: increase next addr by incr bytes
 781  * @flags: access flags
 782  *
 783  * Update PTEs by writing them manually using sDMA (CIK).
 784  */
 785 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
 786                                    uint64_t pe,
 787                                    uint64_t addr, unsigned count,
 788                                    uint32_t incr, uint32_t flags)
 789 {
 790         uint64_t value;
 791         unsigned ndw;
 792
 793         while (count) {
 794                 ndw = count * 2;
 795                 if (ndw > 0xFFFFE)
 796                         ndw = 0xFFFFE;
 797
 798                 /* for non-physically contiguous pages (system) */
 799                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 800                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 801                 ib->ptr[ib->length_dw++] = pe;
 802                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 803                 ib->ptr[ib->length_dw++] = ndw;
 804                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 805                         if (flags & AMDGPU_PTE_SYSTEM) {
 806                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 807                                 value &= 0xFFFFFFFFFFFFF000ULL;
 808                         } else if (flags & AMDGPU_PTE_VALID) {
 809                                 value = addr;
 810                         } else {
 811                                 value = 0;
 812                         }
 813                         addr += incr;
 814                         value |= flags;
 815                         ib->ptr[ib->length_dw++] = value;
 816                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 817                 }
 818         }
 819 }
 820
 821 /**
 822  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 823  *
 824  * @ib: indirect buffer to fill with commands
 825  * @pe: addr of the page entry
 826  * @addr: dst addr to write into pe
 827  * @count: number of page entries to update
 828  * @incr: increase next addr by incr bytes
 829  * @flags: access flags
 830  *
 831  * Update the page tables using sDMA (CIK).
 832  */
 833 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
 834                                      uint64_t pe,
 835                                      uint64_t addr, unsigned count,
 836                                      uint32_t incr, uint32_t flags)
 837 {
 838         uint64_t value;
 839         unsigned ndw;
 840
 841         while (count) {
 842                 ndw = count;
 843                 if (ndw > 0x7FFFF)
 844                         ndw = 0x7FFFF;
 845
 846                 if (flags & AMDGPU_PTE_VALID)
 847                         value = addr;
 848                 else
 849                         value = 0;
 850
 851                 /* for physically contiguous pages (vram) */
 852                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 853                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 854                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 855                 ib->ptr[ib->length_dw++] = flags; /* mask */
 856                 ib->ptr[ib->length_dw++] = 0;
 857                 ib->ptr[ib->length_dw++] = value; /* value */
 858                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 859                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 860                 ib->ptr[ib->length_dw++] = 0;
 861                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 862
 863                 pe += ndw * 8;
 864                 addr += ndw * incr;
 865                 count -= ndw;
 866         }
 867 }
 868
 869 /**
 870  * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
 871  *
 872  * @ib: indirect buffer to fill with padding
 873  *
 874  */
 875 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
 876 {
 877         while (ib->length_dw & 0x7)
 878                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 879 }
 880
 881 /**
 882  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 883  *
 884  * @ring: amdgpu_ring pointer
 885  * @vm: amdgpu_vm pointer
 886  *
 887  * Update the page table base and flush the VM TLB
 888  * using sDMA (VI).
 889  */
 890 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 891                                          unsigned vm_id, uint64_t pd_addr)
 892 {
 893         u32 srbm_gfx_cntl = 0;
 894         u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
 895                                        SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 896
 897         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 898                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 899         if (vm_id < 8) {
 900                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 901         } else {
 902                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 903         }
 904         amdgpu_ring_write(ring, pd_addr >> 12);
 905
 906         /* update SH_MEM_* regs */
 907         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
 908         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 909                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 910         amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
 911         amdgpu_ring_write(ring, srbm_gfx_cntl);
 912
 913         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 914                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 915         amdgpu_ring_write(ring, mmSH_MEM_BASES);
 916         amdgpu_ring_write(ring, 0);
 917
 918         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 919                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 920         amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
 921         amdgpu_ring_write(ring, sh_mem_cfg);
 922
 923         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 924                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 925         amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
 926         amdgpu_ring_write(ring, 1);
 927
 928         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 929                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 930         amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
 931         amdgpu_ring_write(ring, 0);
 932
 933         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
 934         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 935                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 936         amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
 937         amdgpu_ring_write(ring, srbm_gfx_cntl);
 938
 939
 940         /* flush TLB */
 941         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 942                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 943         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 944         amdgpu_ring_write(ring, 1 << vm_id);
 945
 946         /* wait for flush */
 947         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 948                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 949                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 950         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 951         amdgpu_ring_write(ring, 0);
 952         amdgpu_ring_write(ring, 0); /* reference */
 953         amdgpu_ring_write(ring, 0); /* mask */
 954         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 955                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 956 }
 957
 958 static int sdma_v2_4_early_init(void *handle)
 959 {
 960         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 961
 962         sdma_v2_4_set_ring_funcs(adev);
 963         sdma_v2_4_set_buffer_funcs(adev);
 964         sdma_v2_4_set_vm_pte_funcs(adev);
 965         sdma_v2_4_set_irq_funcs(adev);
 966
 967         return 0;
 968 }
 969
 970 static int sdma_v2_4_sw_init(void *handle)
 971 {
 972         struct amdgpu_ring *ring;
 973         int r;
 974         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 975
 976         /* SDMA trap event */
 977         r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
 978         if (r)
 979                 return r;
 980
 981         /* SDMA Privileged inst */
 982         r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
 983         if (r)
 984                 return r;
 985
 986         /* SDMA Privileged inst */
 987         r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
 988         if (r)
 989                 return r;
 990
 991         r = sdma_v2_4_init_microcode(adev);
 992         if (r) {
 993                 DRM_ERROR("Failed to load sdma firmware!\n");
 994                 return r;
 995         }
 996
 997         ring = &adev->sdma[0].ring;
 998         ring->ring_obj = NULL;
 999         ring->use_doorbell = false;
1000
1001         ring = &adev->sdma[1].ring;
1002         ring->ring_obj = NULL;
1003         ring->use_doorbell = false;
1004
1005         ring = &adev->sdma[0].ring;
1006         sprintf(ring->name, "sdma0");
1007         r = amdgpu_ring_init(adev, ring, 256 * 1024,
1008                              SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1009                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1010                              AMDGPU_RING_TYPE_SDMA);
1011         if (r)
1012                 return r;
1013
1014         ring = &adev->sdma[1].ring;
1015         sprintf(ring->name, "sdma1");
1016         r = amdgpu_ring_init(adev, ring, 256 * 1024,
1017                              SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1018                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1019                              AMDGPU_RING_TYPE_SDMA);
1020         if (r)
1021                 return r;
1022
1023         return r;
1024 }
1025
1026 static int sdma_v2_4_sw_fini(void *handle)
1027 {
1028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029
1030         amdgpu_ring_fini(&adev->sdma[0].ring);
1031         amdgpu_ring_fini(&adev->sdma[1].ring);
1032
1033         return 0;
1034 }
1035
1036 static int sdma_v2_4_hw_init(void *handle)
1037 {
1038         int r;
1039         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1040
1041         sdma_v2_4_init_golden_registers(adev);
1042
1043         r = sdma_v2_4_start(adev);
1044         if (r)
1045                 return r;
1046
1047         return r;
1048 }
1049
1050 static int sdma_v2_4_hw_fini(void *handle)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         sdma_v2_4_enable(adev, false);
1055
1056         return 0;
1057 }
1058
1059 static int sdma_v2_4_suspend(void *handle)
1060 {
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062
1063         return sdma_v2_4_hw_fini(adev);
1064 }
1065
1066 static int sdma_v2_4_resume(void *handle)
1067 {
1068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
1070         return sdma_v2_4_hw_init(adev);
1071 }
1072
1073 static bool sdma_v2_4_is_idle(void *handle)
1074 {
1075         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1076         u32 tmp = RREG32(mmSRBM_STATUS2);
1077
1078         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1079                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1080             return false;
1081
1082         return true;
1083 }
1084
1085 static int sdma_v2_4_wait_for_idle(void *handle)
1086 {
1087         unsigned i;
1088         u32 tmp;
1089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090
1091         for (i = 0; i < adev->usec_timeout; i++) {
1092                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1093                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1094
1095                 if (!tmp)
1096                         return 0;
1097                 udelay(1);
1098         }
1099         return -ETIMEDOUT;
1100 }
1101
1102 static void sdma_v2_4_print_status(void *handle)
1103 {
1104         int i, j;
1105         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1106
1107         dev_info(adev->dev, "VI SDMA registers\n");
1108         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1109                  RREG32(mmSRBM_STATUS2));
1110         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1111                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1112                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1113                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1114                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1115                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1116                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1117                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1118                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1119                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1120                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1121                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1122                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1123                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1124                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1125                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1126                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1127                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1128                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1129                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1130                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1131                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1132                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1133                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1134                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1135                 mutex_lock(&adev->srbm_mutex);
1136                 for (j = 0; j < 16; j++) {
1137                         vi_srbm_select(adev, 0, 0, 0, j);
1138                         dev_info(adev->dev, "  VM %d:\n", j);
1139                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1140                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1141                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1142                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1143                 }
1144                 vi_srbm_select(adev, 0, 0, 0, 0);
1145                 mutex_unlock(&adev->srbm_mutex);
1146         }
1147 }
1148
1149 static int sdma_v2_4_soft_reset(void *handle)
1150 {
1151         u32 srbm_soft_reset = 0;
1152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153         u32 tmp = RREG32(mmSRBM_STATUS2);
1154
1155         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1156                 /* sdma0 */
1157                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1158                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1159                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1160                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1161         }
1162         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1163                 /* sdma1 */
1164                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1165                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1166                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1167                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1168         }
1169
1170         if (srbm_soft_reset) {
1171                 sdma_v2_4_print_status((void *)adev);
1172
1173                 tmp = RREG32(mmSRBM_SOFT_RESET);
1174                 tmp |= srbm_soft_reset;
1175                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1176                 WREG32(mmSRBM_SOFT_RESET, tmp);
1177                 tmp = RREG32(mmSRBM_SOFT_RESET);
1178
1179                 udelay(50);
1180
1181                 tmp &= ~srbm_soft_reset;
1182                 WREG32(mmSRBM_SOFT_RESET, tmp);
1183                 tmp = RREG32(mmSRBM_SOFT_RESET);
1184
1185                 /* Wait a little for things to settle down */
1186                 udelay(50);
1187
1188                 sdma_v2_4_print_status((void *)adev);
1189         }
1190
1191         return 0;
1192 }
1193
1194 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1195                                         struct amdgpu_irq_src *src,
1196                                         unsigned type,
1197                                         enum amdgpu_interrupt_state state)
1198 {
1199         u32 sdma_cntl;
1200
1201         switch (type) {
1202         case AMDGPU_SDMA_IRQ_TRAP0:
1203                 switch (state) {
1204                 case AMDGPU_IRQ_STATE_DISABLE:
1205                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1206                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1207                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1208                         break;
1209                 case AMDGPU_IRQ_STATE_ENABLE:
1210                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1211                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1212                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1213                         break;
1214                 default:
1215                         break;
1216                 }
1217                 break;
1218         case AMDGPU_SDMA_IRQ_TRAP1:
1219                 switch (state) {
1220                 case AMDGPU_IRQ_STATE_DISABLE:
1221                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1222                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1223                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1224                         break;
1225                 case AMDGPU_IRQ_STATE_ENABLE:
1226                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1227                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1228                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1229                         break;
1230                 default:
1231                         break;
1232                 }
1233                 break;
1234         default:
1235                 break;
1236         }
1237         return 0;
1238 }
1239
1240 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1241                                       struct amdgpu_irq_src *source,
1242                                       struct amdgpu_iv_entry *entry)
1243 {
1244         u8 instance_id, queue_id;
1245
1246         instance_id = (entry->ring_id & 0x3) >> 0;
1247         queue_id = (entry->ring_id & 0xc) >> 2;
1248         DRM_DEBUG("IH: SDMA trap\n");
1249         switch (instance_id) {
1250         case 0:
1251                 switch (queue_id) {
1252                 case 0:
1253                         amdgpu_fence_process(&adev->sdma[0].ring);
1254                         break;
1255                 case 1:
1256                         /* XXX compute */
1257                         break;
1258                 case 2:
1259                         /* XXX compute */
1260                         break;
1261                 }
1262                 break;
1263         case 1:
1264                 switch (queue_id) {
1265                 case 0:
1266                         amdgpu_fence_process(&adev->sdma[1].ring);
1267                         break;
1268                 case 1:
1269                         /* XXX compute */
1270                         break;
1271                 case 2:
1272                         /* XXX compute */
1273                         break;
1274                 }
1275                 break;
1276         }
1277         return 0;
1278 }
1279
1280 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1281                                               struct amdgpu_irq_src *source,
1282                                               struct amdgpu_iv_entry *entry)
1283 {
1284         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1285         schedule_work(&adev->reset_work);
1286         return 0;
1287 }
1288
1289 static int sdma_v2_4_set_clockgating_state(void *handle,
1290                                           enum amd_clockgating_state state)
1291 {
1292         /* XXX handled via the smc on VI */
1293         return 0;
1294 }
1295
1296 static int sdma_v2_4_set_powergating_state(void *handle,
1297                                           enum amd_powergating_state state)
1298 {
1299         return 0;
1300 }
1301
1302 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1303         .early_init = sdma_v2_4_early_init,
1304         .late_init = NULL,
1305         .sw_init = sdma_v2_4_sw_init,
1306         .sw_fini = sdma_v2_4_sw_fini,
1307         .hw_init = sdma_v2_4_hw_init,
1308         .hw_fini = sdma_v2_4_hw_fini,
1309         .suspend = sdma_v2_4_suspend,
1310         .resume = sdma_v2_4_resume,
1311         .is_idle = sdma_v2_4_is_idle,
1312         .wait_for_idle = sdma_v2_4_wait_for_idle,
1313         .soft_reset = sdma_v2_4_soft_reset,
1314         .print_status = sdma_v2_4_print_status,
1315         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1316         .set_powergating_state = sdma_v2_4_set_powergating_state,
1317 };
1318
1319 /**
1320  * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
1321  *
1322  * @ring: amdgpu_ring structure holding ring information
1323  *
1324  * Check if the async DMA engine is locked up (VI).
1325  * Returns true if the engine appears to be locked up, false if not.
1326  */
1327 static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
1328 {
1329
1330         if (sdma_v2_4_is_idle(ring->adev)) {
1331                 amdgpu_ring_lockup_update(ring);
1332                 return false;
1333         }
1334         return amdgpu_ring_test_lockup(ring);
1335 }
1336
1337 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1338         .get_rptr = sdma_v2_4_ring_get_rptr,
1339         .get_wptr = sdma_v2_4_ring_get_wptr,
1340         .set_wptr = sdma_v2_4_ring_set_wptr,
1341         .parse_cs = NULL,
1342         .emit_ib = sdma_v2_4_ring_emit_ib,
1343         .emit_fence = sdma_v2_4_ring_emit_fence,
1344         .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1345         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1346         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1347         .test_ring = sdma_v2_4_ring_test_ring,
1348         .test_ib = sdma_v2_4_ring_test_ib,
1349         .is_lockup = sdma_v2_4_ring_is_lockup,
1350 };
1351
1352 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1353 {
1354         adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs;
1355         adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs;
1356 }
1357
1358 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1359         .set = sdma_v2_4_set_trap_irq_state,
1360         .process = sdma_v2_4_process_trap_irq,
1361 };
1362
1363 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1364         .process = sdma_v2_4_process_illegal_inst_irq,
1365 };
1366
1367 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1368 {
1369         adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1370         adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1371         adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1372 }
1373
1374 /**
1375  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1376  *
1377  * @ring: amdgpu_ring structure holding ring information
1378  * @src_offset: src GPU address
1379  * @dst_offset: dst GPU address
1380  * @byte_count: number of bytes to xfer
1381  *
1382  * Copy GPU buffers using the DMA engine (VI).
1383  * Used by the amdgpu ttm implementation to move pages if
1384  * registered as the asic copy callback.
1385  */
1386 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ring *ring,
1387                                        uint64_t src_offset,
1388                                        uint64_t dst_offset,
1389                                        uint32_t byte_count)
1390 {
1391         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1392                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
1393         amdgpu_ring_write(ring, byte_count);
1394         amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1395         amdgpu_ring_write(ring, lower_32_bits(src_offset));
1396         amdgpu_ring_write(ring, upper_32_bits(src_offset));
1397         amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1398         amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1399 }
1400
1401 /**
1402  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1403  *
1404  * @ring: amdgpu_ring structure holding ring information
1405  * @src_data: value to write to buffer
1406  * @dst_offset: dst GPU address
1407  * @byte_count: number of bytes to xfer
1408  *
1409  * Fill GPU buffers using the DMA engine (VI).
1410  */
1411 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring,
1412                                        uint32_t src_data,
1413                                        uint64_t dst_offset,
1414                                        uint32_t byte_count)
1415 {
1416         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
1417         amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1418         amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1419         amdgpu_ring_write(ring, src_data);
1420         amdgpu_ring_write(ring, byte_count);
1421 }
1422
1423 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1424         .copy_max_bytes = 0x1fffff,
1425         .copy_num_dw = 7,
1426         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1427
1428         .fill_max_bytes = 0x1fffff,
1429         .fill_num_dw = 7,
1430         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1431 };
1432
1433 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1434 {
1435         if (adev->mman.buffer_funcs == NULL) {
1436                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1437                 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1438         }
1439 }
1440
1441 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1442         .copy_pte = sdma_v2_4_vm_copy_pte,
1443         .write_pte = sdma_v2_4_vm_write_pte,
1444         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1445         .pad_ib = sdma_v2_4_vm_pad_ib,
1446 };
1447
1448 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1449 {
1450         if (adev->vm_manager.vm_pte_funcs == NULL) {
1451                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1452                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1453         }
1454 }