drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  89
  90 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  91 {
  92         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  93         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  94         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  95         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  96         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  97         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  98         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  99         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 100         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 101         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 102         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 103         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 104         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 105         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 106         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 107         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 108 };
 109
 110 static const u32 golden_settings_tonga_a11[] =
 111 {
 112         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 113         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 114         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 115         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 116         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 117         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 118         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 119         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 120         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 121         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 122         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 123         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 124 };
 125
 126 static const u32 tonga_golden_common_all[] =
 127 {
 128         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 129         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 130         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 131         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 132         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 133         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 134         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 135         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 136 };
 137
 138 static const u32 tonga_mgcg_cgcg_init[] =
 139 {
 140         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 141         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 142         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 143         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 144         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 145         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 146         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 147         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 148         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 149         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 150         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 151         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 152         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 153         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 154         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 155         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 156         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 157         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 158         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 159         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 160         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 161         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 162         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 163         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 165         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 166         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 167         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 168         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 169         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 170         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 171         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 172         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 173         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 174         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 175         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 176         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 177         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 178         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 179         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 180         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 181         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 182         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 183         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 184         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 185         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 186         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 187         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 188         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 189         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 190         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 191         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 192         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 193         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 194         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 195         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 196         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 197         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 198         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 199         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 200         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 201         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 202         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 203         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 204         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 205         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 206         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 207         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 208         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 209         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 210         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 211         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 212         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 213         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 214         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 215 };
 216
 217 static const u32 golden_settings_iceland_a11[] =
 218 {
 219         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 220         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 221         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 222         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 223         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 224         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 225         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 226         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 227         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 228         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 229         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 230         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 231         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 232 };
 233
 234 static const u32 iceland_golden_common_all[] =
 235 {
 236         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 237         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 238         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 239         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 240         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 241         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 242         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 243         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 244 };
 245
 246 static const u32 iceland_mgcg_cgcg_init[] =
 247 {
 248         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 249         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 250         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 251         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 252         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 253         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 254         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 255         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 256         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 257         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 258         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 259         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 260         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 261         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 262         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 263         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 264         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 265         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 266         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 267         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 268         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 269         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 270         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 271         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 272         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 273         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 274         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 275         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 276         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 277         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 278         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 279         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 280         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 281         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 282         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 283         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 284         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 285         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 286         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 287         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 288         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 289         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 290         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 291         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 292         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 293         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 294         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 295         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 296         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 297         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 298         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 299         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 300         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 301         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 302         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 303         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 304         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 305         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 306         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 307         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 308         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 309         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 310         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 311         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 312 };
 313
 314 static const u32 cz_golden_settings_a11[] =
 315 {
 316         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 317         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 318         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 319         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 320         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 321         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 322         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 323         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 324 };
 325
 326 static const u32 cz_golden_common_all[] =
 327 {
 328         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 329         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 330         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 331         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 332         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 333         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 334         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 335         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 336 };
 337
 338 static const u32 cz_mgcg_cgcg_init[] =
 339 {
 340         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 341         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 342         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 343         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 344         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 345         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 346         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 347         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 348         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 349         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 350         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 351         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 352         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 353         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 354         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 355         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 356         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 357         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 358         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 359         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 360         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 361         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 362         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 363         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 364         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 365         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 366         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 367         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 368         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 369         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 370         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 371         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 372         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 373         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 374         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 375         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 376         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 377         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 378         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 379         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 380         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 381         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 382         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 383         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 384         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 385         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 386         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 387         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 388         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 389         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 390         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 391         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 392         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 393         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 394         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 395         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 396         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 397         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 398         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 399         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 400         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 401         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 402         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 403         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 404         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 405         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 406         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 407         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 408         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 409         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 410         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 411         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 412         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 413         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 414         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 415 };
 416
 417 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 418 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 419 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 420
 421 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 422 {
 423         switch (adev->asic_type) {
 424         case CHIP_TOPAZ:
 425                 amdgpu_program_register_sequence(adev,
 426                                                  iceland_mgcg_cgcg_init,
 427                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 428                 amdgpu_program_register_sequence(adev,
 429                                                  golden_settings_iceland_a11,
 430                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 431                 amdgpu_program_register_sequence(adev,
 432                                                  iceland_golden_common_all,
 433                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 434                 break;
 435         case CHIP_TONGA:
 436                 amdgpu_program_register_sequence(adev,
 437                                                  tonga_mgcg_cgcg_init,
 438                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 439                 amdgpu_program_register_sequence(adev,
 440                                                  golden_settings_tonga_a11,
 441                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 442                 amdgpu_program_register_sequence(adev,
 443                                                  tonga_golden_common_all,
 444                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 445                 break;
 446         case CHIP_CARRIZO:
 447                 amdgpu_program_register_sequence(adev,
 448                                                  cz_mgcg_cgcg_init,
 449                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 450                 amdgpu_program_register_sequence(adev,
 451                                                  cz_golden_settings_a11,
 452                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 453                 amdgpu_program_register_sequence(adev,
 454                                                  cz_golden_common_all,
 455                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 456                 break;
 457         default:
 458                 break;
 459         }
 460 }
 461
 462 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 463 {
 464         int i;
 465
 466         adev->gfx.scratch.num_reg = 7;
 467         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 468         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 469                 adev->gfx.scratch.free[i] = true;
 470                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 471         }
 472 }
 473
 474 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 475 {
 476         struct amdgpu_device *adev = ring->adev;
 477         uint32_t scratch;
 478         uint32_t tmp = 0;
 479         unsigned i;
 480         int r;
 481
 482         r = amdgpu_gfx_scratch_get(adev, &scratch);
 483         if (r) {
 484                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 485                 return r;
 486         }
 487         WREG32(scratch, 0xCAFEDEAD);
 488         r = amdgpu_ring_lock(ring, 3);
 489         if (r) {
 490                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 491                           ring->idx, r);
 492                 amdgpu_gfx_scratch_free(adev, scratch);
 493                 return r;
 494         }
 495         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 496         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 497         amdgpu_ring_write(ring, 0xDEADBEEF);
 498         amdgpu_ring_unlock_commit(ring);
 499
 500         for (i = 0; i < adev->usec_timeout; i++) {
 501                 tmp = RREG32(scratch);
 502                 if (tmp == 0xDEADBEEF)
 503                         break;
 504                 DRM_UDELAY(1);
 505         }
 506         if (i < adev->usec_timeout) {
 507                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 508                          ring->idx, i);
 509         } else {
 510                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 511                           ring->idx, scratch, tmp);
 512                 r = -EINVAL;
 513         }
 514         amdgpu_gfx_scratch_free(adev, scratch);
 515         return r;
 516 }
 517
 518 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 519 {
 520         struct amdgpu_device *adev = ring->adev;
 521         struct amdgpu_ib ib;
 522         uint32_t scratch;
 523         uint32_t tmp = 0;
 524         unsigned i;
 525         int r;
 526
 527         r = amdgpu_gfx_scratch_get(adev, &scratch);
 528         if (r) {
 529                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 530                 return r;
 531         }
 532         WREG32(scratch, 0xCAFEDEAD);
 533         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 534         if (r) {
 535                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 536                 amdgpu_gfx_scratch_free(adev, scratch);
 537                 return r;
 538         }
 539         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 540         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 541         ib.ptr[2] = 0xDEADBEEF;
 542         ib.length_dw = 3;
 543         r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
 544         if (r) {
 545                 amdgpu_gfx_scratch_free(adev, scratch);
 546                 amdgpu_ib_free(adev, &ib);
 547                 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
 548                 return r;
 549         }
 550         r = amdgpu_fence_wait(ib.fence, false);
 551         if (r) {
 552                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 553                 amdgpu_gfx_scratch_free(adev, scratch);
 554                 amdgpu_ib_free(adev, &ib);
 555                 return r;
 556         }
 557         for (i = 0; i < adev->usec_timeout; i++) {
 558                 tmp = RREG32(scratch);
 559                 if (tmp == 0xDEADBEEF)
 560                         break;
 561                 DRM_UDELAY(1);
 562         }
 563         if (i < adev->usec_timeout) {
 564                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 565                          ib.fence->ring->idx, i);
 566         } else {
 567                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 568                           scratch, tmp);
 569                 r = -EINVAL;
 570         }
 571         amdgpu_gfx_scratch_free(adev, scratch);
 572         amdgpu_ib_free(adev, &ib);
 573         return r;
 574 }
 575
 576 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 577 {
 578         const char *chip_name;
 579         char fw_name[30];
 580         int err;
 581         struct amdgpu_firmware_info *info = NULL;
 582         const struct common_firmware_header *header = NULL;
 583
 584         DRM_DEBUG("\n");
 585
 586         switch (adev->asic_type) {
 587         case CHIP_TOPAZ:
 588                 chip_name = "topaz";
 589                 break;
 590         case CHIP_TONGA:
 591                 chip_name = "tonga";
 592                 break;
 593         case CHIP_CARRIZO:
 594                 chip_name = "carrizo";
 595                 break;
 596         default:
 597                 BUG();
 598         }
 599
 600         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 601         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 602         if (err)
 603                 goto out;
 604         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 605         if (err)
 606                 goto out;
 607
 608         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 609         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 610         if (err)
 611                 goto out;
 612         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 613         if (err)
 614                 goto out;
 615
 616         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 617         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 618         if (err)
 619                 goto out;
 620         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 621         if (err)
 622                 goto out;
 623
 624         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 625         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 626         if (err)
 627                 goto out;
 628         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 629
 630         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 631         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 632         if (err)
 633                 goto out;
 634         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 635         if (err)
 636                 goto out;
 637
 638         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 639         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 640         if (!err) {
 641                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 642                 if (err)
 643                         goto out;
 644         } else {
 645                 err = 0;
 646                 adev->gfx.mec2_fw = NULL;
 647         }
 648
 649         if (adev->firmware.smu_load) {
 650                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 651                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 652                 info->fw = adev->gfx.pfp_fw;
 653                 header = (const struct common_firmware_header *)info->fw->data;
 654                 adev->firmware.fw_size +=
 655                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 656
 657                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 658                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 659                 info->fw = adev->gfx.me_fw;
 660                 header = (const struct common_firmware_header *)info->fw->data;
 661                 adev->firmware.fw_size +=
 662                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 663
 664                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 665                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 666                 info->fw = adev->gfx.ce_fw;
 667                 header = (const struct common_firmware_header *)info->fw->data;
 668                 adev->firmware.fw_size +=
 669                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 670
 671                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 672                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 673                 info->fw = adev->gfx.rlc_fw;
 674                 header = (const struct common_firmware_header *)info->fw->data;
 675                 adev->firmware.fw_size +=
 676                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 677
 678                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 679                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 680                 info->fw = adev->gfx.mec_fw;
 681                 header = (const struct common_firmware_header *)info->fw->data;
 682                 adev->firmware.fw_size +=
 683                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 684
 685                 if (adev->gfx.mec2_fw) {
 686                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 687                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 688                         info->fw = adev->gfx.mec2_fw;
 689                         header = (const struct common_firmware_header *)info->fw->data;
 690                         adev->firmware.fw_size +=
 691                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 692                 }
 693
 694         }
 695
 696 out:
 697         if (err) {
 698                 dev_err(adev->dev,
 699                         "gfx8: Failed to load firmware \"%s\"\n",
 700                         fw_name);
 701                 release_firmware(adev->gfx.pfp_fw);
 702                 adev->gfx.pfp_fw = NULL;
 703                 release_firmware(adev->gfx.me_fw);
 704                 adev->gfx.me_fw = NULL;
 705                 release_firmware(adev->gfx.ce_fw);
 706                 adev->gfx.ce_fw = NULL;
 707                 release_firmware(adev->gfx.rlc_fw);
 708                 adev->gfx.rlc_fw = NULL;
 709                 release_firmware(adev->gfx.mec_fw);
 710                 adev->gfx.mec_fw = NULL;
 711                 release_firmware(adev->gfx.mec2_fw);
 712                 adev->gfx.mec2_fw = NULL;
 713         }
 714         return err;
 715 }
 716
 717 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 718 {
 719         int r;
 720
 721         if (adev->gfx.mec.hpd_eop_obj) {
 722                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 723                 if (unlikely(r != 0))
 724                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 725                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 726                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 727
 728                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 729                 adev->gfx.mec.hpd_eop_obj = NULL;
 730         }
 731 }
 732
 733 #define MEC_HPD_SIZE 2048
 734
 735 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 736 {
 737         int r;
 738         u32 *hpd;
 739
 740         /*
 741          * we assign only 1 pipe because all other pipes will
 742          * be handled by KFD
 743          */
 744         adev->gfx.mec.num_mec = 1;
 745         adev->gfx.mec.num_pipe = 1;
 746         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 747
 748         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 749                 r = amdgpu_bo_create(adev,
 750                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 751                                      PAGE_SIZE, true,
 752                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
 753                                      &adev->gfx.mec.hpd_eop_obj);
 754                 if (r) {
 755                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 756                         return r;
 757                 }
 758         }
 759
 760         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 761         if (unlikely(r != 0)) {
 762                 gfx_v8_0_mec_fini(adev);
 763                 return r;
 764         }
 765         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 766                           &adev->gfx.mec.hpd_eop_gpu_addr);
 767         if (r) {
 768                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 769                 gfx_v8_0_mec_fini(adev);
 770                 return r;
 771         }
 772         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 773         if (r) {
 774                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 775                 gfx_v8_0_mec_fini(adev);
 776                 return r;
 777         }
 778
 779         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 780
 781         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 782         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 783
 784         return 0;
 785 }
 786
 787 static int gfx_v8_0_sw_init(void *handle)
 788 {
 789         int i, r;
 790         struct amdgpu_ring *ring;
 791         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 792
 793         /* EOP Event */
 794         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
 795         if (r)
 796                 return r;
 797
 798         /* Privileged reg */
 799         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
 800         if (r)
 801                 return r;
 802
 803         /* Privileged inst */
 804         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
 805         if (r)
 806                 return r;
 807
 808         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 809
 810         gfx_v8_0_scratch_init(adev);
 811
 812         r = gfx_v8_0_init_microcode(adev);
 813         if (r) {
 814                 DRM_ERROR("Failed to load gfx firmware!\n");
 815                 return r;
 816         }
 817
 818         r = gfx_v8_0_mec_init(adev);
 819         if (r) {
 820                 DRM_ERROR("Failed to init MEC BOs!\n");
 821                 return r;
 822         }
 823
 824         r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
 825         if (r) {
 826                 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
 827                 return r;
 828         }
 829
 830         /* set up the gfx ring */
 831         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 832                 ring = &adev->gfx.gfx_ring[i];
 833                 ring->ring_obj = NULL;
 834                 sprintf(ring->name, "gfx");
 835                 /* no gfx doorbells on iceland */
 836                 if (adev->asic_type != CHIP_TOPAZ) {
 837                         ring->use_doorbell = true;
 838                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
 839                 }
 840
 841                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 842                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 843                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
 844                                      AMDGPU_RING_TYPE_GFX);
 845                 if (r)
 846                         return r;
 847         }
 848
 849         /* set up the compute queues */
 850         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 851                 unsigned irq_type;
 852
 853                 /* max 32 queues per MEC */
 854                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
 855                         DRM_ERROR("Too many (%d) compute rings!\n", i);
 856                         break;
 857                 }
 858                 ring = &adev->gfx.compute_ring[i];
 859                 ring->ring_obj = NULL;
 860                 ring->use_doorbell = true;
 861                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
 862                 ring->me = 1; /* first MEC */
 863                 ring->pipe = i / 8;
 864                 ring->queue = i % 8;
 865                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
 866                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
 867                 /* type-2 packets are deprecated on MEC, use type-3 instead */
 868                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 869                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 870                                      &adev->gfx.eop_irq, irq_type,
 871                                      AMDGPU_RING_TYPE_COMPUTE);
 872                 if (r)
 873                         return r;
 874         }
 875
 876         /* reserve GDS, GWS and OA resource for gfx */
 877         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
 878                         PAGE_SIZE, true,
 879                         AMDGPU_GEM_DOMAIN_GDS, 0,
 880                         NULL, &adev->gds.gds_gfx_bo);
 881         if (r)
 882                 return r;
 883
 884         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
 885                 PAGE_SIZE, true,
 886                 AMDGPU_GEM_DOMAIN_GWS, 0,
 887                 NULL, &adev->gds.gws_gfx_bo);
 888         if (r)
 889                 return r;
 890
 891         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
 892                         PAGE_SIZE, true,
 893                         AMDGPU_GEM_DOMAIN_OA, 0,
 894                         NULL, &adev->gds.oa_gfx_bo);
 895         if (r)
 896                 return r;
 897
 898         return 0;
 899 }
 900
 901 static int gfx_v8_0_sw_fini(void *handle)
 902 {
 903         int i;
 904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 905
 906         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
 907         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
 908         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
 909
 910         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 911                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
 912         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 913                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 914
 915         amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
 916
 917         gfx_v8_0_mec_fini(adev);
 918
 919         return 0;
 920 }
 921
 922 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
 923 {
 924         const u32 num_tile_mode_states = 32;
 925         const u32 num_secondary_tile_mode_states = 16;
 926         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 927
 928         switch (adev->gfx.config.mem_row_size_in_kb) {
 929         case 1:
 930                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 931                 break;
 932         case 2:
 933         default:
 934                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 935                 break;
 936         case 4:
 937                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 938                 break;
 939         }
 940
 941         switch (adev->asic_type) {
 942         case CHIP_TOPAZ:
 943                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 944                         switch (reg_offset) {
 945                         case 0:
 946                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 947                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 948                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 949                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 950                                 break;
 951                         case 1:
 952                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 953                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 954                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 955                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 956                                 break;
 957                         case 2:
 958                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 959                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 960                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 961                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 962                                 break;
 963                         case 3:
 964                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 965                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 966                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 967                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 968                                 break;
 969                         case 4:
 970                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 971                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 972                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 973                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 974                                 break;
 975                         case 5:
 976                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 977                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 978                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 979                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 980                                 break;
 981                         case 6:
 982                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 983                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 984                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 985                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 986                                 break;
 987                         case 8:
 988                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 989                                                 PIPE_CONFIG(ADDR_SURF_P2));
 990                                 break;
 991                         case 9:
 992                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 993                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 994                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 995                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 996                                 break;
 997                         case 10:
 998                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 999                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1000                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1001                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1002                                 break;
1003                         case 11:
1004                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1005                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1006                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1007                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1008                                 break;
1009                         case 13:
1010                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1011                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1012                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1013                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1014                                 break;
1015                         case 14:
1016                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1017                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1018                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1019                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1020                                 break;
1021                         case 15:
1022                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1023                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1024                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1025                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1026                                 break;
1027                         case 16:
1028                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1029                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1030                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1031                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1032                                 break;
1033                         case 18:
1034                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1035                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1036                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1037                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1038                                 break;
1039                         case 19:
1040                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1041                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1042                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1043                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1044                                 break;
1045                         case 20:
1046                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1047                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1048                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1049                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1050                                 break;
1051                         case 21:
1052                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1053                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1054                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1055                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1056                                 break;
1057                         case 22:
1058                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1059                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1060                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1061                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1062                                 break;
1063                         case 24:
1064                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1065                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1066                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1067                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1068                                 break;
1069                         case 25:
1070                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1071                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1072                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1073                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1074                                 break;
1075                         case 26:
1076                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1077                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1078                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1079                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1080                                 break;
1081                         case 27:
1082                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1083                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1084                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1085                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1086                                 break;
1087                         case 28:
1088                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1089                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1090                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1091                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1092                                 break;
1093                         case 29:
1094                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1095                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1096                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1097                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1098                                 break;
1099                         case 7:
1100                         case 12:
1101                         case 17:
1102                         case 23:
1103                                 /* unused idx */
1104                                 continue;
1105                         default:
1106                                 gb_tile_moden = 0;
1107                                 break;
1108                         };
1109                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1110                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1111                 }
1112                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1113                         switch (reg_offset) {
1114                         case 0:
1115                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1116                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1117                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1118                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1119                                 break;
1120                         case 1:
1121                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1122                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1123                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1124                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1125                                 break;
1126                         case 2:
1127                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1128                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1129                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1130                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1131                                 break;
1132                         case 3:
1133                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1134                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1135                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1136                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1137                                 break;
1138                         case 4:
1139                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1140                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1141                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1142                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1143                                 break;
1144                         case 5:
1145                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1147                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1148                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1149                                 break;
1150                         case 6:
1151                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1152                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1153                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1154                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1155                                 break;
1156                         case 8:
1157                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1158                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1159                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1160                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1161                                 break;
1162                         case 9:
1163                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1164                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1165                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1166                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1167                                 break;
1168                         case 10:
1169                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1170                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1171                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1172                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1173                                 break;
1174                         case 11:
1175                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1176                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1177                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1178                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1179                                 break;
1180                         case 12:
1181                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1182                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1183                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1184                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1185                                 break;
1186                         case 13:
1187                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1189                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1190                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1191                                 break;
1192                         case 14:
1193                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1194                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1195                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1196                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1197                                 break;
1198                         case 7:
1199                                 /* unused idx */
1200                                 continue;
1201                         default:
1202                                 gb_tile_moden = 0;
1203                                 break;
1204                         };
1205                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1206                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1207                 }
1208         case CHIP_TONGA:
1209                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1210                         switch (reg_offset) {
1211                         case 0:
1212                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1214                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1215                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1216                                 break;
1217                         case 1:
1218                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1220                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1221                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1222                                 break;
1223                         case 2:
1224                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1226                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1227                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228                                 break;
1229                         case 3:
1230                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1231                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1232                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1233                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1234                                 break;
1235                         case 4:
1236                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1238                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1239                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1240                                 break;
1241                         case 5:
1242                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1243                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1244                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1245                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1246                                 break;
1247                         case 6:
1248                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1250                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1251                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1252                                 break;
1253                         case 7:
1254                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1255                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1256                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1257                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1258                                 break;
1259                         case 8:
1260                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1261                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1262                                 break;
1263                         case 9:
1264                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1265                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1266                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1267                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1268                                 break;
1269                         case 10:
1270                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1271                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1272                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1273                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1274                                 break;
1275                         case 11:
1276                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1277                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1278                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1279                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1280                                 break;
1281                         case 12:
1282                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1283                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1284                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1285                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1286                                 break;
1287                         case 13:
1288                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1289                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1290                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1292                                 break;
1293                         case 14:
1294                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1295                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1296                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1297                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1298                                 break;
1299                         case 15:
1300                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1301                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1302                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1303                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1304                                 break;
1305                         case 16:
1306                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1307                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1308                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1309                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1310                                 break;
1311                         case 17:
1312                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1313                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1314                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1315                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1316                                 break;
1317                         case 18:
1318                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1319                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1320                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1321                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1322                                 break;
1323                         case 19:
1324                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1325                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1326                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1327                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1328                                 break;
1329                         case 20:
1330                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1331                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1332                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1333                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1334                                 break;
1335                         case 21:
1336                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1337                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1338                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1339                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1340                                 break;
1341                         case 22:
1342                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1343                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1344                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1345                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1346                                 break;
1347                         case 23:
1348                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1349                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1350                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1351                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1352                                 break;
1353                         case 24:
1354                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1355                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1356                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1357                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1358                                 break;
1359                         case 25:
1360                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1361                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1362                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1363                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1364                                 break;
1365                         case 26:
1366                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1367                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1368                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1369                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1370                                 break;
1371                         case 27:
1372                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1373                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1374                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1375                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1376                                 break;
1377                         case 28:
1378                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1379                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1380                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1381                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1382                                 break;
1383                         case 29:
1384                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1385                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1386                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1387                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1388                                 break;
1389                         case 30:
1390                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1391                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1392                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1393                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1394                                 break;
1395                         default:
1396                                 gb_tile_moden = 0;
1397                                 break;
1398                         };
1399                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1400                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1401                 }
1402                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1403                         switch (reg_offset) {
1404                         case 0:
1405                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1406                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1407                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1408                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1409                                 break;
1410                         case 1:
1411                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1412                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1413                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1414                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1415                                 break;
1416                         case 2:
1417                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1418                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1419                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1420                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1421                                 break;
1422                         case 3:
1423                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1424                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1425                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1426                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1427                                 break;
1428                         case 4:
1429                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1430                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1431                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1432                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1433                                 break;
1434                         case 5:
1435                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1436                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1437                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1438                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1439                                 break;
1440                         case 6:
1441                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1442                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1443                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1444                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1445                                 break;
1446                         case 8:
1447                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1448                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1449                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1450                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1451                                 break;
1452                         case 9:
1453                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1454                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1455                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1456                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1457                                 break;
1458                         case 10:
1459                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1460                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1461                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1462                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1463                                 break;
1464                         case 11:
1465                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1466                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1467                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1468                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1469                                 break;
1470                         case 12:
1471                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1472                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1473                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1474                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1475                                 break;
1476                         case 13:
1477                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1478                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1479                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1480                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1481                                 break;
1482                         case 14:
1483                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1484                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1485                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1486                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1487                                 break;
1488                         case 7:
1489                                 /* unused idx */
1490                                 continue;
1491                         default:
1492                                 gb_tile_moden = 0;
1493                                 break;
1494                         };
1495                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1496                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1497                 }
1498                 break;
1499         case CHIP_CARRIZO:
1500         default:
1501                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1502                         switch (reg_offset) {
1503                         case 0:
1504                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1505                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1506                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1507                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1508                                 break;
1509                         case 1:
1510                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1511                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1512                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1513                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1514                                 break;
1515                         case 2:
1516                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1517                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1518                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1519                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1520                                 break;
1521                         case 3:
1522                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1523                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1524                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1525                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1526                                 break;
1527                         case 4:
1528                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1529                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1530                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1531                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1532                                 break;
1533                         case 5:
1534                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1535                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1536                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1537                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1538                                 break;
1539                         case 6:
1540                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1541                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1542                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1543                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1544                                 break;
1545                         case 8:
1546                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1547                                                 PIPE_CONFIG(ADDR_SURF_P2));
1548                                 break;
1549                         case 9:
1550                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1551                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1552                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1553                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1554                                 break;
1555                         case 10:
1556                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1557                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1558                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1559                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1560                                 break;
1561                         case 11:
1562                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1563                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1564                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1565                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1566                                 break;
1567                         case 13:
1568                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1569                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1570                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1571                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1572                                 break;
1573                         case 14:
1574                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1575                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1576                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1577                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1578                                 break;
1579                         case 15:
1580                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1581                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1582                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1583                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1584                                 break;
1585                         case 16:
1586                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1587                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1588                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1589                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1590                                 break;
1591                         case 18:
1592                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1593                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1594                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1595                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1596                                 break;
1597                         case 19:
1598                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1599                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1600                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1601                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1602                                 break;
1603                         case 20:
1604                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1605                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1606                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1607                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1608                                 break;
1609                         case 21:
1610                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1611                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1612                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1613                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1614                                 break;
1615                         case 22:
1616                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1617                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1618                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1619                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1620                                 break;
1621                         case 24:
1622                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1623                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1624                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1625                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1626                                 break;
1627                         case 25:
1628                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1629                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1630                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1631                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1632                                 break;
1633                         case 26:
1634                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1635                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1636                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1637                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1638                                 break;
1639                         case 27:
1640                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1641                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1642                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1643                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1644                                 break;
1645                         case 28:
1646                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1647                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1648                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1649                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1650                                 break;
1651                         case 29:
1652                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1653                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1654                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1655                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1656                                 break;
1657                         case 7:
1658                         case 12:
1659                         case 17:
1660                         case 23:
1661                                 /* unused idx */
1662                                 continue;
1663                         default:
1664                                 gb_tile_moden = 0;
1665                                 break;
1666                         };
1667                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1668                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1669                 }
1670                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1671                         switch (reg_offset) {
1672                         case 0:
1673                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1674                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1675                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1676                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1677                                 break;
1678                         case 1:
1679                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1680                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1681                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1682                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1683                                 break;
1684                         case 2:
1685                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1686                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1687                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1688                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1689                                 break;
1690                         case 3:
1691                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1692                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1693                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1694                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1695                                 break;
1696                         case 4:
1697                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1698                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1699                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1700                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1701                                 break;
1702                         case 5:
1703                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1704                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1705                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1706                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1707                                 break;
1708                         case 6:
1709                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1710                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1711                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1712                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1713                                 break;
1714                         case 8:
1715                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1716                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1717                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1718                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1719                                 break;
1720                         case 9:
1721                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1722                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1723                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1724                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1725                                 break;
1726                         case 10:
1727                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1728                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1729                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1730                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1731                                 break;
1732                         case 11:
1733                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1734                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1735                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1736                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1737                                 break;
1738                         case 12:
1739                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1740                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1741                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1742                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1743                                 break;
1744                         case 13:
1745                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1746                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1747                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1748                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1749                                 break;
1750                         case 14:
1751                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1752                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1753                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1754                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1755                                 break;
1756                         case 7:
1757                                 /* unused idx */
1758                                 continue;
1759                         default:
1760                                 gb_tile_moden = 0;
1761                                 break;
1762                         };
1763                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1764                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1765                 }
1766         }
1767 }
1768
1769 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1770 {
1771         u32 i, mask = 0;
1772
1773         for (i = 0; i < bit_width; i++) {
1774                 mask <<= 1;
1775                 mask |= 1;
1776         }
1777         return mask;
1778 }
1779
1780 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1781 {
1782         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1783
1784         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1785                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1786                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1787         } else if (se_num == 0xffffffff) {
1788                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1789                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1790         } else if (sh_num == 0xffffffff) {
1791                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1792                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1793         } else {
1794                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1795                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1796         }
1797         WREG32(mmGRBM_GFX_INDEX, data);
1798 }
1799
1800 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1801                                     u32 max_rb_num_per_se,
1802                                     u32 sh_per_se)
1803 {
1804         u32 data, mask;
1805
1806         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1807         if (data & 1)
1808                 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1809         else
1810                 data = 0;
1811
1812         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1813
1814         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1815
1816         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1817
1818         return data & mask;
1819 }
1820
1821 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1822                               u32 se_num, u32 sh_per_se,
1823                               u32 max_rb_num_per_se)
1824 {
1825         int i, j;
1826         u32 data, mask;
1827         u32 disabled_rbs = 0;
1828         u32 enabled_rbs = 0;
1829
1830         mutex_lock(&adev->grbm_idx_mutex);
1831         for (i = 0; i < se_num; i++) {
1832                 for (j = 0; j < sh_per_se; j++) {
1833                         gfx_v8_0_select_se_sh(adev, i, j);
1834                         data = gfx_v8_0_get_rb_disabled(adev,
1835                                               max_rb_num_per_se, sh_per_se);
1836                         disabled_rbs |= data << ((i * sh_per_se + j) *
1837                                                  RB_BITMAP_WIDTH_PER_SH);
1838                 }
1839         }
1840         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1841         mutex_unlock(&adev->grbm_idx_mutex);
1842
1843         mask = 1;
1844         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1845                 if (!(disabled_rbs & mask))
1846                         enabled_rbs |= mask;
1847                 mask <<= 1;
1848         }
1849
1850         adev->gfx.config.backend_enable_mask = enabled_rbs;
1851
1852         mutex_lock(&adev->grbm_idx_mutex);
1853         for (i = 0; i < se_num; i++) {
1854                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1855                 data = 0;
1856                 for (j = 0; j < sh_per_se; j++) {
1857                         switch (enabled_rbs & 3) {
1858                         case 0:
1859                                 if (j == 0)
1860                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1861                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1862                                 else
1863                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1864                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1865                                 break;
1866                         case 1:
1867                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
1868                                          (i * sh_per_se + j) * 2);
1869                                 break;
1870                         case 2:
1871                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
1872                                          (i * sh_per_se + j) * 2);
1873                                 break;
1874                         case 3:
1875                         default:
1876                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
1877                                          (i * sh_per_se + j) * 2);
1878                                 break;
1879                         }
1880                         enabled_rbs >>= 2;
1881                 }
1882                 WREG32(mmPA_SC_RASTER_CONFIG, data);
1883         }
1884         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1885         mutex_unlock(&adev->grbm_idx_mutex);
1886 }
1887
1888 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1889 {
1890         u32 gb_addr_config;
1891         u32 mc_shared_chmap, mc_arb_ramcfg;
1892         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1893         u32 tmp;
1894         int i;
1895
1896         switch (adev->asic_type) {
1897         case CHIP_TOPAZ:
1898                 adev->gfx.config.max_shader_engines = 1;
1899                 adev->gfx.config.max_tile_pipes = 2;
1900                 adev->gfx.config.max_cu_per_sh = 6;
1901                 adev->gfx.config.max_sh_per_se = 1;
1902                 adev->gfx.config.max_backends_per_se = 2;
1903                 adev->gfx.config.max_texture_channel_caches = 2;
1904                 adev->gfx.config.max_gprs = 256;
1905                 adev->gfx.config.max_gs_threads = 32;
1906                 adev->gfx.config.max_hw_contexts = 8;
1907
1908                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1909                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1910                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1911                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1912                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1913                 break;
1914         case CHIP_TONGA:
1915                 adev->gfx.config.max_shader_engines = 4;
1916                 adev->gfx.config.max_tile_pipes = 8;
1917                 adev->gfx.config.max_cu_per_sh = 8;
1918                 adev->gfx.config.max_sh_per_se = 1;
1919                 adev->gfx.config.max_backends_per_se = 2;
1920                 adev->gfx.config.max_texture_channel_caches = 8;
1921                 adev->gfx.config.max_gprs = 256;
1922                 adev->gfx.config.max_gs_threads = 32;
1923                 adev->gfx.config.max_hw_contexts = 8;
1924
1925                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1926                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1927                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1928                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1929                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1930                 break;
1931         case CHIP_CARRIZO:
1932                 adev->gfx.config.max_shader_engines = 1;
1933                 adev->gfx.config.max_tile_pipes = 2;
1934                 adev->gfx.config.max_cu_per_sh = 8;
1935                 adev->gfx.config.max_sh_per_se = 1;
1936                 adev->gfx.config.max_backends_per_se = 2;
1937                 adev->gfx.config.max_texture_channel_caches = 2;
1938                 adev->gfx.config.max_gprs = 256;
1939                 adev->gfx.config.max_gs_threads = 32;
1940                 adev->gfx.config.max_hw_contexts = 8;
1941
1942                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1943                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1944                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1945                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1946                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1947                 break;
1948         default:
1949                 adev->gfx.config.max_shader_engines = 2;
1950                 adev->gfx.config.max_tile_pipes = 4;
1951                 adev->gfx.config.max_cu_per_sh = 2;
1952                 adev->gfx.config.max_sh_per_se = 1;
1953                 adev->gfx.config.max_backends_per_se = 2;
1954                 adev->gfx.config.max_texture_channel_caches = 4;
1955                 adev->gfx.config.max_gprs = 256;
1956                 adev->gfx.config.max_gs_threads = 32;
1957                 adev->gfx.config.max_hw_contexts = 8;
1958
1959                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1960                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1961                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1962                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1963                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1964                 break;
1965         }
1966
1967         tmp = RREG32(mmGRBM_CNTL);
1968         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
1969         WREG32(mmGRBM_CNTL, tmp);
1970
1971         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1972         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1973         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1974
1975         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1976         adev->gfx.config.mem_max_burst_length_bytes = 256;
1977         if (adev->flags & AMDGPU_IS_APU) {
1978                 /* Get memory bank mapping mode. */
1979                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1980                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1981                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1982
1983                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1984                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1985                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1986
1987                 /* Validate settings in case only one DIMM installed. */
1988                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1989                         dimm00_addr_map = 0;
1990                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1991                         dimm01_addr_map = 0;
1992                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1993                         dimm10_addr_map = 0;
1994                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1995                         dimm11_addr_map = 0;
1996
1997                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1998                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1999                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2000                         adev->gfx.config.mem_row_size_in_kb = 2;
2001                 else
2002                         adev->gfx.config.mem_row_size_in_kb = 1;
2003         } else {
2004                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2005                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2006                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2007                         adev->gfx.config.mem_row_size_in_kb = 4;
2008         }
2009
2010         adev->gfx.config.shader_engine_tile_size = 32;
2011         adev->gfx.config.num_gpus = 1;
2012         adev->gfx.config.multi_gpu_tile_size = 64;
2013
2014         /* fix up row size */
2015         switch (adev->gfx.config.mem_row_size_in_kb) {
2016         case 1:
2017         default:
2018                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2019                 break;
2020         case 2:
2021                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2022                 break;
2023         case 4:
2024                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2025                 break;
2026         }
2027         adev->gfx.config.gb_addr_config = gb_addr_config;
2028
2029         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2030         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2031         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2032         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2033                gb_addr_config & 0x70);
2034         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2035                gb_addr_config & 0x70);
2036         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2037         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2038         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2039
2040         gfx_v8_0_tiling_mode_table_init(adev);
2041
2042         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2043                                  adev->gfx.config.max_sh_per_se,
2044                                  adev->gfx.config.max_backends_per_se);
2045
2046         /* XXX SH_MEM regs */
2047         /* where to put LDS, scratch, GPUVM in FSA64 space */
2048         mutex_lock(&adev->srbm_mutex);
2049         for (i = 0; i < 16; i++) {
2050                 vi_srbm_select(adev, 0, 0, 0, i);
2051                 /* CP and shaders */
2052                 if (i == 0) {
2053                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2054                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2055                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2056                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2057                         WREG32(mmSH_MEM_CONFIG, tmp);
2058                 } else {
2059                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2060                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2061                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2062                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2063                         WREG32(mmSH_MEM_CONFIG, tmp);
2064                 }
2065
2066                 WREG32(mmSH_MEM_APE1_BASE, 1);
2067                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2068                 WREG32(mmSH_MEM_BASES, 0);
2069         }
2070         vi_srbm_select(adev, 0, 0, 0, 0);
2071         mutex_unlock(&adev->srbm_mutex);
2072
2073         mutex_lock(&adev->grbm_idx_mutex);
2074         /*
2075          * making sure that the following register writes will be broadcasted
2076          * to all the shaders
2077          */
2078         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2079
2080         WREG32(mmPA_SC_FIFO_SIZE,
2081                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2082                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2083                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2084                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2085                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2086                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2087                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2088                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2089         mutex_unlock(&adev->grbm_idx_mutex);
2090
2091 }
2092
2093 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2094 {
2095         u32 i, j, k;
2096         u32 mask;
2097
2098         mutex_lock(&adev->grbm_idx_mutex);
2099         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2100                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2101                         gfx_v8_0_select_se_sh(adev, i, j);
2102                         for (k = 0; k < adev->usec_timeout; k++) {
2103                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2104                                         break;
2105                                 udelay(1);
2106                         }
2107                 }
2108         }
2109         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2110         mutex_unlock(&adev->grbm_idx_mutex);
2111
2112         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2113                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2114                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2115                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2116         for (k = 0; k < adev->usec_timeout; k++) {
2117                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2118                         break;
2119                 udelay(1);
2120         }
2121 }
2122
2123 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2124                                                bool enable)
2125 {
2126         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2127
2128         if (enable) {
2129                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2130                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2131                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2132                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2133         } else {
2134                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2135                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2136                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2137                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2138         }
2139         WREG32(mmCP_INT_CNTL_RING0, tmp);
2140 }
2141
2142 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2143 {
2144         u32 tmp = RREG32(mmRLC_CNTL);
2145
2146         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2147         WREG32(mmRLC_CNTL, tmp);
2148
2149         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2150
2151         gfx_v8_0_wait_for_rlc_serdes(adev);
2152 }
2153
2154 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2155 {
2156         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2157
2158         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2159         WREG32(mmGRBM_SOFT_RESET, tmp);
2160         udelay(50);
2161         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2162         WREG32(mmGRBM_SOFT_RESET, tmp);
2163         udelay(50);
2164 }
2165
2166 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2167 {
2168         u32 tmp = RREG32(mmRLC_CNTL);
2169
2170         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2171         WREG32(mmRLC_CNTL, tmp);
2172
2173         /* carrizo do enable cp interrupt after cp inited */
2174         if (adev->asic_type != CHIP_CARRIZO)
2175                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2176
2177         udelay(50);
2178 }
2179
2180 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2181 {
2182         const struct rlc_firmware_header_v2_0 *hdr;
2183         const __le32 *fw_data;
2184         unsigned i, fw_size;
2185
2186         if (!adev->gfx.rlc_fw)
2187                 return -EINVAL;
2188
2189         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2190         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2191         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
2192
2193         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2194                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2195         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2196
2197         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2198         for (i = 0; i < fw_size; i++)
2199                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2200         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2201
2202         return 0;
2203 }
2204
2205 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2206 {
2207         int r;
2208
2209         gfx_v8_0_rlc_stop(adev);
2210
2211         /* disable CG */
2212         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2213
2214         /* disable PG */
2215         WREG32(mmRLC_PG_CNTL, 0);
2216
2217         gfx_v8_0_rlc_reset(adev);
2218
2219         if (!adev->firmware.smu_load) {
2220                 /* legacy rlc firmware loading */
2221                 r = gfx_v8_0_rlc_load_microcode(adev);
2222                 if (r)
2223                         return r;
2224         } else {
2225                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2226                                                 AMDGPU_UCODE_ID_RLC_G);
2227                 if (r)
2228                         return -EINVAL;
2229         }
2230
2231         gfx_v8_0_rlc_start(adev);
2232
2233         return 0;
2234 }
2235
2236 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2237 {
2238         int i;
2239         u32 tmp = RREG32(mmCP_ME_CNTL);
2240
2241         if (enable) {
2242                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2243                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2244                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2245         } else {
2246                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2247                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2248                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2249                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2250                         adev->gfx.gfx_ring[i].ready = false;
2251         }
2252         WREG32(mmCP_ME_CNTL, tmp);
2253         udelay(50);
2254 }
2255
2256 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2257 {
2258         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2259         const struct gfx_firmware_header_v1_0 *ce_hdr;
2260         const struct gfx_firmware_header_v1_0 *me_hdr;
2261         const __le32 *fw_data;
2262         unsigned i, fw_size;
2263
2264         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2265                 return -EINVAL;
2266
2267         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2268                 adev->gfx.pfp_fw->data;
2269         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2270                 adev->gfx.ce_fw->data;
2271         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2272                 adev->gfx.me_fw->data;
2273
2274         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2275         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2276         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2277         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2278         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2279         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2280
2281         gfx_v8_0_cp_gfx_enable(adev, false);
2282
2283         /* PFP */
2284         fw_data = (const __le32 *)
2285                 (adev->gfx.pfp_fw->data +
2286                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2287         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2288         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2289         for (i = 0; i < fw_size; i++)
2290                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2291         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2292
2293         /* CE */
2294         fw_data = (const __le32 *)
2295                 (adev->gfx.ce_fw->data +
2296                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2297         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2298         WREG32(mmCP_CE_UCODE_ADDR, 0);
2299         for (i = 0; i < fw_size; i++)
2300                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2301         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2302
2303         /* ME */
2304         fw_data = (const __le32 *)
2305                 (adev->gfx.me_fw->data +
2306                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2307         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2308         WREG32(mmCP_ME_RAM_WADDR, 0);
2309         for (i = 0; i < fw_size; i++)
2310                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2311         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2312
2313         return 0;
2314 }
2315
2316 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2317 {
2318         u32 count = 0;
2319         const struct cs_section_def *sect = NULL;
2320         const struct cs_extent_def *ext = NULL;
2321
2322         /* begin clear state */
2323         count += 2;
2324         /* context control state */
2325         count += 3;
2326
2327         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2328                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2329                         if (sect->id == SECT_CONTEXT)
2330                                 count += 2 + ext->reg_count;
2331                         else
2332                                 return 0;
2333                 }
2334         }
2335         /* pa_sc_raster_config/pa_sc_raster_config1 */
2336         count += 4;
2337         /* end clear state */
2338         count += 2;
2339         /* clear state */
2340         count += 2;
2341
2342         return count;
2343 }
2344
2345 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2346 {
2347         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2348         const struct cs_section_def *sect = NULL;
2349         const struct cs_extent_def *ext = NULL;
2350         int r, i;
2351
2352         /* init the CP */
2353         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2354         WREG32(mmCP_ENDIAN_SWAP, 0);
2355         WREG32(mmCP_DEVICE_ID, 1);
2356
2357         gfx_v8_0_cp_gfx_enable(adev, true);
2358
2359         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2360         if (r) {
2361                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2362                 return r;
2363         }
2364
2365         /* clear state buffer */
2366         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2367         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2368
2369         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2370         amdgpu_ring_write(ring, 0x80000000);
2371         amdgpu_ring_write(ring, 0x80000000);
2372
2373         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2374                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2375                         if (sect->id == SECT_CONTEXT) {
2376                                 amdgpu_ring_write(ring,
2377                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2378                                                ext->reg_count));
2379                                 amdgpu_ring_write(ring,
2380                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2381                                 for (i = 0; i < ext->reg_count; i++)
2382                                         amdgpu_ring_write(ring, ext->extent[i]);
2383                         }
2384                 }
2385         }
2386
2387         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2388         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2389         switch (adev->asic_type) {
2390         case CHIP_TONGA:
2391                 amdgpu_ring_write(ring, 0x16000012);
2392                 amdgpu_ring_write(ring, 0x0000002A);
2393                 break;
2394         case CHIP_TOPAZ:
2395         case CHIP_CARRIZO:
2396                 amdgpu_ring_write(ring, 0x00000002);
2397                 amdgpu_ring_write(ring, 0x00000000);
2398                 break;
2399         default:
2400                 BUG();
2401         }
2402
2403         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2404         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2405
2406         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2407         amdgpu_ring_write(ring, 0);
2408
2409         /* init the CE partitions */
2410         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2411         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2412         amdgpu_ring_write(ring, 0x8000);
2413         amdgpu_ring_write(ring, 0x8000);
2414
2415         amdgpu_ring_unlock_commit(ring);
2416
2417         return 0;
2418 }
2419
2420 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2421 {
2422         struct amdgpu_ring *ring;
2423         u32 tmp;
2424         u32 rb_bufsz;
2425         u64 rb_addr, rptr_addr;
2426         int r;
2427
2428         /* Set the write pointer delay */
2429         WREG32(mmCP_RB_WPTR_DELAY, 0);
2430
2431         /* set the RB to use vmid 0 */
2432         WREG32(mmCP_RB_VMID, 0);
2433
2434         /* Set ring buffer size */
2435         ring = &adev->gfx.gfx_ring[0];
2436         rb_bufsz = order_base_2(ring->ring_size / 8);
2437         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2438         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2439         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2440         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2441 #ifdef __BIG_ENDIAN
2442         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2443 #endif
2444         WREG32(mmCP_RB0_CNTL, tmp);
2445
2446         /* Initialize the ring buffer's read and write pointers */
2447         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2448         ring->wptr = 0;
2449         WREG32(mmCP_RB0_WPTR, ring->wptr);
2450
2451         /* set the wb address wether it's enabled or not */
2452         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2453         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2454         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2455
2456         mdelay(1);
2457         WREG32(mmCP_RB0_CNTL, tmp);
2458
2459         rb_addr = ring->gpu_addr >> 8;
2460         WREG32(mmCP_RB0_BASE, rb_addr);
2461         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2462
2463         /* no gfx doorbells on iceland */
2464         if (adev->asic_type != CHIP_TOPAZ) {
2465                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2466                 if (ring->use_doorbell) {
2467                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2468                                             DOORBELL_OFFSET, ring->doorbell_index);
2469                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2470                                             DOORBELL_EN, 1);
2471                 } else {
2472                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2473                                             DOORBELL_EN, 0);
2474                 }
2475                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2476
2477                 if (adev->asic_type == CHIP_TONGA) {
2478                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2479                                             DOORBELL_RANGE_LOWER,
2480                                             AMDGPU_DOORBELL_GFX_RING0);
2481                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2482
2483                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2484                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2485                 }
2486
2487         }
2488
2489         /* start the ring */
2490         gfx_v8_0_cp_gfx_start(adev);
2491         ring->ready = true;
2492         r = amdgpu_ring_test_ring(ring);
2493         if (r) {
2494                 ring->ready = false;
2495                 return r;
2496         }
2497
2498         return 0;
2499 }
2500
2501 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2502 {
2503         int i;
2504
2505         if (enable) {
2506                 WREG32(mmCP_MEC_CNTL, 0);
2507         } else {
2508                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2509                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2510                         adev->gfx.compute_ring[i].ready = false;
2511         }
2512         udelay(50);
2513 }
2514
2515 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2516 {
2517         gfx_v8_0_cp_compute_enable(adev, true);
2518
2519         return 0;
2520 }
2521
2522 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2523 {
2524         const struct gfx_firmware_header_v1_0 *mec_hdr;
2525         const __le32 *fw_data;
2526         unsigned i, fw_size;
2527
2528         if (!adev->gfx.mec_fw)
2529                 return -EINVAL;
2530
2531         gfx_v8_0_cp_compute_enable(adev, false);
2532
2533         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2534         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2535         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2536
2537         fw_data = (const __le32 *)
2538                 (adev->gfx.mec_fw->data +
2539                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2540         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2541
2542         /* MEC1 */
2543         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2544         for (i = 0; i < fw_size; i++)
2545                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2546         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2547
2548         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2549         if (adev->gfx.mec2_fw) {
2550                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2551
2552                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2553                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2554                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2555
2556                 fw_data = (const __le32 *)
2557                         (adev->gfx.mec2_fw->data +
2558                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2559                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2560
2561                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2562                 for (i = 0; i < fw_size; i++)
2563                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2564                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2565         }
2566
2567         return 0;
2568 }
2569
2570 struct vi_mqd {
2571         uint32_t header;  /* ordinal0 */
2572         uint32_t compute_dispatch_initiator;  /* ordinal1 */
2573         uint32_t compute_dim_x;  /* ordinal2 */
2574         uint32_t compute_dim_y;  /* ordinal3 */
2575         uint32_t compute_dim_z;  /* ordinal4 */
2576         uint32_t compute_start_x;  /* ordinal5 */
2577         uint32_t compute_start_y;  /* ordinal6 */
2578         uint32_t compute_start_z;  /* ordinal7 */
2579         uint32_t compute_num_thread_x;  /* ordinal8 */
2580         uint32_t compute_num_thread_y;  /* ordinal9 */
2581         uint32_t compute_num_thread_z;  /* ordinal10 */
2582         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
2583         uint32_t compute_perfcount_enable;  /* ordinal12 */
2584         uint32_t compute_pgm_lo;  /* ordinal13 */
2585         uint32_t compute_pgm_hi;  /* ordinal14 */
2586         uint32_t compute_tba_lo;  /* ordinal15 */
2587         uint32_t compute_tba_hi;  /* ordinal16 */
2588         uint32_t compute_tma_lo;  /* ordinal17 */
2589         uint32_t compute_tma_hi;  /* ordinal18 */
2590         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
2591         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
2592         uint32_t compute_vmid;  /* ordinal21 */
2593         uint32_t compute_resource_limits;  /* ordinal22 */
2594         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
2595         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
2596         uint32_t compute_tmpring_size;  /* ordinal25 */
2597         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
2598         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
2599         uint32_t compute_restart_x;  /* ordinal28 */
2600         uint32_t compute_restart_y;  /* ordinal29 */
2601         uint32_t compute_restart_z;  /* ordinal30 */
2602         uint32_t compute_thread_trace_enable;  /* ordinal31 */
2603         uint32_t compute_misc_reserved;  /* ordinal32 */
2604         uint32_t compute_dispatch_id;  /* ordinal33 */
2605         uint32_t compute_threadgroup_id;  /* ordinal34 */
2606         uint32_t compute_relaunch;  /* ordinal35 */
2607         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
2608         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
2609         uint32_t compute_wave_restore_control;  /* ordinal38 */
2610         uint32_t reserved9;  /* ordinal39 */
2611         uint32_t reserved10;  /* ordinal40 */
2612         uint32_t reserved11;  /* ordinal41 */
2613         uint32_t reserved12;  /* ordinal42 */
2614         uint32_t reserved13;  /* ordinal43 */
2615         uint32_t reserved14;  /* ordinal44 */
2616         uint32_t reserved15;  /* ordinal45 */
2617         uint32_t reserved16;  /* ordinal46 */
2618         uint32_t reserved17;  /* ordinal47 */
2619         uint32_t reserved18;  /* ordinal48 */
2620         uint32_t reserved19;  /* ordinal49 */
2621         uint32_t reserved20;  /* ordinal50 */
2622         uint32_t reserved21;  /* ordinal51 */
2623         uint32_t reserved22;  /* ordinal52 */
2624         uint32_t reserved23;  /* ordinal53 */
2625         uint32_t reserved24;  /* ordinal54 */
2626         uint32_t reserved25;  /* ordinal55 */
2627         uint32_t reserved26;  /* ordinal56 */
2628         uint32_t reserved27;  /* ordinal57 */
2629         uint32_t reserved28;  /* ordinal58 */
2630         uint32_t reserved29;  /* ordinal59 */
2631         uint32_t reserved30;  /* ordinal60 */
2632         uint32_t reserved31;  /* ordinal61 */
2633         uint32_t reserved32;  /* ordinal62 */
2634         uint32_t reserved33;  /* ordinal63 */
2635         uint32_t reserved34;  /* ordinal64 */
2636         uint32_t compute_user_data_0;  /* ordinal65 */
2637         uint32_t compute_user_data_1;  /* ordinal66 */
2638         uint32_t compute_user_data_2;  /* ordinal67 */
2639         uint32_t compute_user_data_3;  /* ordinal68 */
2640         uint32_t compute_user_data_4;  /* ordinal69 */
2641         uint32_t compute_user_data_5;  /* ordinal70 */
2642         uint32_t compute_user_data_6;  /* ordinal71 */
2643         uint32_t compute_user_data_7;  /* ordinal72 */
2644         uint32_t compute_user_data_8;  /* ordinal73 */
2645         uint32_t compute_user_data_9;  /* ordinal74 */
2646         uint32_t compute_user_data_10;  /* ordinal75 */
2647         uint32_t compute_user_data_11;  /* ordinal76 */
2648         uint32_t compute_user_data_12;  /* ordinal77 */
2649         uint32_t compute_user_data_13;  /* ordinal78 */
2650         uint32_t compute_user_data_14;  /* ordinal79 */
2651         uint32_t compute_user_data_15;  /* ordinal80 */
2652         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
2653         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
2654         uint32_t reserved35;  /* ordinal83 */
2655         uint32_t reserved36;  /* ordinal84 */
2656         uint32_t reserved37;  /* ordinal85 */
2657         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
2658         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
2659         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
2660         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
2661         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
2662         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
2663         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
2664         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
2665         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
2666         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
2667         uint32_t reserved38;  /* ordinal96 */
2668         uint32_t reserved39;  /* ordinal97 */
2669         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
2670         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
2671         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
2672         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
2673         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
2674         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
2675         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
2676         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
2677         uint32_t reserved40;  /* ordinal106 */
2678         uint32_t reserved41;  /* ordinal107 */
2679         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
2680         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
2681         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
2682         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
2683         uint32_t reserved42;  /* ordinal112 */
2684         uint32_t reserved43;  /* ordinal113 */
2685         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
2686         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
2687         uint32_t cp_packet_id_lo;  /* ordinal116 */
2688         uint32_t cp_packet_id_hi;  /* ordinal117 */
2689         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
2690         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
2691         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
2692         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
2693         uint32_t gds_save_mask_lo;  /* ordinal122 */
2694         uint32_t gds_save_mask_hi;  /* ordinal123 */
2695         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
2696         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
2697         uint32_t reserved44;  /* ordinal126 */
2698         uint32_t reserved45;  /* ordinal127 */
2699         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
2700         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
2701         uint32_t cp_hqd_active;  /* ordinal130 */
2702         uint32_t cp_hqd_vmid;  /* ordinal131 */
2703         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
2704         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
2705         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
2706         uint32_t cp_hqd_quantum;  /* ordinal135 */
2707         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
2708         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
2709         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
2710         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
2711         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
2712         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
2713         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
2714         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
2715         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
2716         uint32_t cp_hqd_pq_control;  /* ordinal145 */
2717         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
2718         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
2719         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
2720         uint32_t cp_hqd_ib_control;  /* ordinal149 */
2721         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
2722         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
2723         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
2724         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
2725         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
2726         uint32_t cp_hqd_msg_type;  /* ordinal155 */
2727         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
2728         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
2729         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
2730         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
2731         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
2732         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
2733         uint32_t cp_mqd_control;  /* ordinal162 */
2734         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
2735         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
2736         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
2737         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
2738         uint32_t cp_hqd_eop_control;  /* ordinal167 */
2739         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
2740         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
2741         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
2742         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
2743         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
2744         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
2745         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
2746         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
2747         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
2748         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
2749         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
2750         uint32_t cp_hqd_error;  /* ordinal179 */
2751         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
2752         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
2753         uint32_t reserved46;  /* ordinal182 */
2754         uint32_t reserved47;  /* ordinal183 */
2755         uint32_t reserved48;  /* ordinal184 */
2756         uint32_t reserved49;  /* ordinal185 */
2757         uint32_t reserved50;  /* ordinal186 */
2758         uint32_t reserved51;  /* ordinal187 */
2759         uint32_t reserved52;  /* ordinal188 */
2760         uint32_t reserved53;  /* ordinal189 */
2761         uint32_t reserved54;  /* ordinal190 */
2762         uint32_t reserved55;  /* ordinal191 */
2763         uint32_t iqtimer_pkt_header;  /* ordinal192 */
2764         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
2765         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
2766         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
2767         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
2768         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
2769         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
2770         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
2771         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
2772         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
2773         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
2774         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
2775         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
2776         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
2777         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
2778         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
2779         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
2780         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
2781         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
2782         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
2783         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
2784         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
2785         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
2786         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
2787         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
2788         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
2789         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
2790         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
2791         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
2792         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
2793         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
2794         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
2795         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
2796         uint32_t reserved56;  /* ordinal225 */
2797         uint32_t reserved57;  /* ordinal226 */
2798         uint32_t reserved58;  /* ordinal227 */
2799         uint32_t set_resources_header;  /* ordinal228 */
2800         uint32_t set_resources_dw1;  /* ordinal229 */
2801         uint32_t set_resources_dw2;  /* ordinal230 */
2802         uint32_t set_resources_dw3;  /* ordinal231 */
2803         uint32_t set_resources_dw4;  /* ordinal232 */
2804         uint32_t set_resources_dw5;  /* ordinal233 */
2805         uint32_t set_resources_dw6;  /* ordinal234 */
2806         uint32_t set_resources_dw7;  /* ordinal235 */
2807         uint32_t reserved59;  /* ordinal236 */
2808         uint32_t reserved60;  /* ordinal237 */
2809         uint32_t reserved61;  /* ordinal238 */
2810         uint32_t reserved62;  /* ordinal239 */
2811         uint32_t reserved63;  /* ordinal240 */
2812         uint32_t reserved64;  /* ordinal241 */
2813         uint32_t reserved65;  /* ordinal242 */
2814         uint32_t reserved66;  /* ordinal243 */
2815         uint32_t reserved67;  /* ordinal244 */
2816         uint32_t reserved68;  /* ordinal245 */
2817         uint32_t reserved69;  /* ordinal246 */
2818         uint32_t reserved70;  /* ordinal247 */
2819         uint32_t reserved71;  /* ordinal248 */
2820         uint32_t reserved72;  /* ordinal249 */
2821         uint32_t reserved73;  /* ordinal250 */
2822         uint32_t reserved74;  /* ordinal251 */
2823         uint32_t reserved75;  /* ordinal252 */
2824         uint32_t reserved76;  /* ordinal253 */
2825         uint32_t reserved77;  /* ordinal254 */
2826         uint32_t reserved78;  /* ordinal255 */
2827
2828         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
2829 };
2830
2831 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
2832 {
2833         int i, r;
2834
2835         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2836                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2837
2838                 if (ring->mqd_obj) {
2839                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
2840                         if (unlikely(r != 0))
2841                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2842
2843                         amdgpu_bo_unpin(ring->mqd_obj);
2844                         amdgpu_bo_unreserve(ring->mqd_obj);
2845
2846                         amdgpu_bo_unref(&ring->mqd_obj);
2847                         ring->mqd_obj = NULL;
2848                 }
2849         }
2850 }
2851
2852 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
2853 {
2854         int r, i, j;
2855         u32 tmp;
2856         bool use_doorbell = true;
2857         u64 hqd_gpu_addr;
2858         u64 mqd_gpu_addr;
2859         u64 eop_gpu_addr;
2860         u64 wb_gpu_addr;
2861         u32 *buf;
2862         struct vi_mqd *mqd;
2863
2864         /* init the pipes */
2865         mutex_lock(&adev->srbm_mutex);
2866         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2867                 int me = (i < 4) ? 1 : 2;
2868                 int pipe = (i < 4) ? i : (i - 4);
2869
2870                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
2871                 eop_gpu_addr >>= 8;
2872
2873                 vi_srbm_select(adev, me, pipe, 0, 0);
2874
2875                 /* write the EOP addr */
2876                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
2877                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
2878
2879                 /* set the VMID assigned */
2880                 WREG32(mmCP_HQD_VMID, 0);
2881
2882                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2883                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
2884                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2885                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
2886                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
2887         }
2888         vi_srbm_select(adev, 0, 0, 0, 0);
2889         mutex_unlock(&adev->srbm_mutex);
2890
2891         /* init the queues.  Just two for now. */
2892         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2893                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2894
2895                 if (ring->mqd_obj == NULL) {
2896                         r = amdgpu_bo_create(adev,
2897                                              sizeof(struct vi_mqd),
2898                                              PAGE_SIZE, true,
2899                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
2900                                              &ring->mqd_obj);
2901                         if (r) {
2902                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2903                                 return r;
2904                         }
2905                 }
2906
2907                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2908                 if (unlikely(r != 0)) {
2909                         gfx_v8_0_cp_compute_fini(adev);
2910                         return r;
2911                 }
2912                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2913                                   &mqd_gpu_addr);
2914                 if (r) {
2915                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2916                         gfx_v8_0_cp_compute_fini(adev);
2917                         return r;
2918                 }
2919                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2920                 if (r) {
2921                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2922                         gfx_v8_0_cp_compute_fini(adev);
2923                         return r;
2924                 }
2925
2926                 /* init the mqd struct */
2927                 memset(buf, 0, sizeof(struct vi_mqd));
2928
2929                 mqd = (struct vi_mqd *)buf;
2930                 mqd->header = 0xC0310800;
2931                 mqd->compute_pipelinestat_enable = 0x00000001;
2932                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2933                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2934                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2935                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2936                 mqd->compute_misc_reserved = 0x00000003;
2937
2938                 mutex_lock(&adev->srbm_mutex);
2939                 vi_srbm_select(adev, ring->me,
2940                                ring->pipe,
2941                                ring->queue, 0);
2942
2943                 /* disable wptr polling */
2944                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2945                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2946                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2947
2948                 mqd->cp_hqd_eop_base_addr_lo =
2949                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
2950                 mqd->cp_hqd_eop_base_addr_hi =
2951                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
2952
2953                 /* enable doorbell? */
2954                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2955                 if (use_doorbell) {
2956                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
2957                 } else {
2958                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
2959                 }
2960                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
2961                 mqd->cp_hqd_pq_doorbell_control = tmp;
2962
2963                 /* disable the queue if it's active */
2964                 mqd->cp_hqd_dequeue_request = 0;
2965                 mqd->cp_hqd_pq_rptr = 0;
2966                 mqd->cp_hqd_pq_wptr= 0;
2967                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2968                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2969                         for (j = 0; j < adev->usec_timeout; j++) {
2970                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2971                                         break;
2972                                 udelay(1);
2973                         }
2974                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
2975                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
2976                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
2977                 }
2978
2979                 /* set the pointer to the MQD */
2980                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2981                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2982                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
2983                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
2984
2985                 /* set MQD vmid to 0 */
2986                 tmp = RREG32(mmCP_MQD_CONTROL);
2987                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2988                 WREG32(mmCP_MQD_CONTROL, tmp);
2989                 mqd->cp_mqd_control = tmp;
2990
2991                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2992                 hqd_gpu_addr = ring->gpu_addr >> 8;
2993                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2994                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2995                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
2996                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
2997
2998                 /* set up the HQD, this is similar to CP_RB0_CNTL */
2999                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3000                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3001                                     (order_base_2(ring->ring_size / 4) - 1));
3002                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3003                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3004 #ifdef __BIG_ENDIAN
3005                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3006 #endif
3007                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3008                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3009                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3010                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3011                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3012                 mqd->cp_hqd_pq_control = tmp;
3013
3014                 /* set the wb address wether it's enabled or not */
3015                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3016                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3017                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3018                         upper_32_bits(wb_gpu_addr) & 0xffff;
3019                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3020                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3021                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3022                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3023
3024                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3025                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3026                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3027                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3028                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3029                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3030                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3031
3032                 /* enable the doorbell if requested */
3033                 if (use_doorbell) {
3034                         if (adev->asic_type == CHIP_CARRIZO) {
3035                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3036                                        AMDGPU_DOORBELL_KIQ << 2);
3037                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3038                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3039                         }
3040                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3041                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3042                                             DOORBELL_OFFSET, ring->doorbell_index);
3043                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3044                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3045                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3046                         mqd->cp_hqd_pq_doorbell_control = tmp;
3047
3048                 } else {
3049                         mqd->cp_hqd_pq_doorbell_control = 0;
3050                 }
3051                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3052                        mqd->cp_hqd_pq_doorbell_control);
3053
3054                 /* set the vmid for the queue */
3055                 mqd->cp_hqd_vmid = 0;
3056                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3057
3058                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3059                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3060                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3061                 mqd->cp_hqd_persistent_state = tmp;
3062
3063                 /* activate the queue */
3064                 mqd->cp_hqd_active = 1;
3065                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3066
3067                 vi_srbm_select(adev, 0, 0, 0, 0);
3068                 mutex_unlock(&adev->srbm_mutex);
3069
3070                 amdgpu_bo_kunmap(ring->mqd_obj);
3071                 amdgpu_bo_unreserve(ring->mqd_obj);
3072         }
3073
3074         if (use_doorbell) {
3075                 tmp = RREG32(mmCP_PQ_STATUS);
3076                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3077                 WREG32(mmCP_PQ_STATUS, tmp);
3078         }
3079
3080         r = gfx_v8_0_cp_compute_start(adev);
3081         if (r)
3082                 return r;
3083
3084         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3085                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3086
3087                 ring->ready = true;
3088                 r = amdgpu_ring_test_ring(ring);
3089                 if (r)
3090                         ring->ready = false;
3091         }
3092
3093         return 0;
3094 }
3095
3096 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3097 {
3098         int r;
3099
3100         if (adev->asic_type != CHIP_CARRIZO)
3101                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3102
3103         if (!adev->firmware.smu_load) {
3104                 /* legacy firmware loading */
3105                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3106                 if (r)
3107                         return r;
3108
3109                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3110                 if (r)
3111                         return r;
3112         } else {
3113                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3114                                                 AMDGPU_UCODE_ID_CP_CE);
3115                 if (r)
3116                         return -EINVAL;
3117
3118                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3119                                                 AMDGPU_UCODE_ID_CP_PFP);
3120                 if (r)
3121                         return -EINVAL;
3122
3123                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3124                                                 AMDGPU_UCODE_ID_CP_ME);
3125                 if (r)
3126                         return -EINVAL;
3127
3128                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3129                                                 AMDGPU_UCODE_ID_CP_MEC1);
3130                 if (r)
3131                         return -EINVAL;
3132         }
3133
3134         r = gfx_v8_0_cp_gfx_resume(adev);
3135         if (r)
3136                 return r;
3137
3138         r = gfx_v8_0_cp_compute_resume(adev);
3139         if (r)
3140                 return r;
3141
3142         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3143
3144         return 0;
3145 }
3146
3147 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3148 {
3149         gfx_v8_0_cp_gfx_enable(adev, enable);
3150         gfx_v8_0_cp_compute_enable(adev, enable);
3151 }
3152
3153 static int gfx_v8_0_hw_init(void *handle)
3154 {
3155         int r;
3156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3157
3158         gfx_v8_0_init_golden_registers(adev);
3159
3160         gfx_v8_0_gpu_init(adev);
3161
3162         r = gfx_v8_0_rlc_resume(adev);
3163         if (r)
3164                 return r;
3165
3166         r = gfx_v8_0_cp_resume(adev);
3167         if (r)
3168                 return r;
3169
3170         return r;
3171 }
3172
3173 static int gfx_v8_0_hw_fini(void *handle)
3174 {
3175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3176
3177         gfx_v8_0_cp_enable(adev, false);
3178         gfx_v8_0_rlc_stop(adev);
3179         gfx_v8_0_cp_compute_fini(adev);
3180
3181         return 0;
3182 }
3183
3184 static int gfx_v8_0_suspend(void *handle)
3185 {
3186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3187
3188         return gfx_v8_0_hw_fini(adev);
3189 }
3190
3191 static int gfx_v8_0_resume(void *handle)
3192 {
3193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3194
3195         return gfx_v8_0_hw_init(adev);
3196 }
3197
3198 static bool gfx_v8_0_is_idle(void *handle)
3199 {
3200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3201
3202         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3203                 return false;
3204         else
3205                 return true;
3206 }
3207
3208 static int gfx_v8_0_wait_for_idle(void *handle)
3209 {
3210         unsigned i;
3211         u32 tmp;
3212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3213
3214         for (i = 0; i < adev->usec_timeout; i++) {
3215                 /* read MC_STATUS */
3216                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3217
3218                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3219                         return 0;
3220                 udelay(1);
3221         }
3222         return -ETIMEDOUT;
3223 }
3224
3225 static void gfx_v8_0_print_status(void *handle)
3226 {
3227         int i;
3228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3229
3230         dev_info(adev->dev, "GFX 8.x registers\n");
3231         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3232                  RREG32(mmGRBM_STATUS));
3233         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3234                  RREG32(mmGRBM_STATUS2));
3235         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3236                  RREG32(mmGRBM_STATUS_SE0));
3237         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3238                  RREG32(mmGRBM_STATUS_SE1));
3239         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3240                  RREG32(mmGRBM_STATUS_SE2));
3241         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3242                  RREG32(mmGRBM_STATUS_SE3));
3243         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3244         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3245                  RREG32(mmCP_STALLED_STAT1));
3246         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3247                  RREG32(mmCP_STALLED_STAT2));
3248         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3249                  RREG32(mmCP_STALLED_STAT3));
3250         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3251                  RREG32(mmCP_CPF_BUSY_STAT));
3252         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3253                  RREG32(mmCP_CPF_STALLED_STAT1));
3254         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3255         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3256         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3257                  RREG32(mmCP_CPC_STALLED_STAT1));
3258         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3259
3260         for (i = 0; i < 32; i++) {
3261                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3262                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3263         }
3264         for (i = 0; i < 16; i++) {
3265                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3266                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3267         }
3268         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3269                 dev_info(adev->dev, "  se: %d\n", i);
3270                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3271                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3272                          RREG32(mmPA_SC_RASTER_CONFIG));
3273                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3274                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3275         }
3276         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3277
3278         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3279                  RREG32(mmGB_ADDR_CONFIG));
3280         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3281                  RREG32(mmHDP_ADDR_CONFIG));
3282         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3283                  RREG32(mmDMIF_ADDR_CALC));
3284         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3285                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3286         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3287                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3288         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3289                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3290         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3291                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3292         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3293                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3294
3295         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3296                  RREG32(mmCP_MEQ_THRESHOLDS));
3297         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3298                  RREG32(mmSX_DEBUG_1));
3299         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3300                  RREG32(mmTA_CNTL_AUX));
3301         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3302                  RREG32(mmSPI_CONFIG_CNTL));
3303         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3304                  RREG32(mmSQ_CONFIG));
3305         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3306                  RREG32(mmDB_DEBUG));
3307         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3308                  RREG32(mmDB_DEBUG2));
3309         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3310                  RREG32(mmDB_DEBUG3));
3311         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3312                  RREG32(mmCB_HW_CONTROL));
3313         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3314                  RREG32(mmSPI_CONFIG_CNTL_1));
3315         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3316                  RREG32(mmPA_SC_FIFO_SIZE));
3317         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3318                  RREG32(mmVGT_NUM_INSTANCES));
3319         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3320                  RREG32(mmCP_PERFMON_CNTL));
3321         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3322                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3323         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3324                  RREG32(mmVGT_CACHE_INVALIDATION));
3325         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3326                  RREG32(mmVGT_GS_VERTEX_REUSE));
3327         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3328                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3329         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3330                  RREG32(mmPA_CL_ENHANCE));
3331         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3332                  RREG32(mmPA_SC_ENHANCE));
3333
3334         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3335                  RREG32(mmCP_ME_CNTL));
3336         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3337                  RREG32(mmCP_MAX_CONTEXT));
3338         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3339                  RREG32(mmCP_ENDIAN_SWAP));
3340         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3341                  RREG32(mmCP_DEVICE_ID));
3342
3343         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3344                  RREG32(mmCP_SEM_WAIT_TIMER));
3345
3346         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3347                  RREG32(mmCP_RB_WPTR_DELAY));
3348         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3349                  RREG32(mmCP_RB_VMID));
3350         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3351                  RREG32(mmCP_RB0_CNTL));
3352         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3353                  RREG32(mmCP_RB0_WPTR));
3354         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3355                  RREG32(mmCP_RB0_RPTR_ADDR));
3356         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3357                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3358         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3359                  RREG32(mmCP_RB0_CNTL));
3360         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3361                  RREG32(mmCP_RB0_BASE));
3362         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3363                  RREG32(mmCP_RB0_BASE_HI));
3364         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3365                  RREG32(mmCP_MEC_CNTL));
3366         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3367                  RREG32(mmCP_CPF_DEBUG));
3368
3369         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3370                  RREG32(mmSCRATCH_ADDR));
3371         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3372                  RREG32(mmSCRATCH_UMSK));
3373
3374         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3375                  RREG32(mmCP_INT_CNTL_RING0));
3376         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3377                  RREG32(mmRLC_LB_CNTL));
3378         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3379                  RREG32(mmRLC_CNTL));
3380         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3381                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3382         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3383                  RREG32(mmRLC_LB_CNTR_INIT));
3384         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3385                  RREG32(mmRLC_LB_CNTR_MAX));
3386         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3387                  RREG32(mmRLC_LB_INIT_CU_MASK));
3388         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3389                  RREG32(mmRLC_LB_PARAMS));
3390         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3391                  RREG32(mmRLC_LB_CNTL));
3392         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3393                  RREG32(mmRLC_MC_CNTL));
3394         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3395                  RREG32(mmRLC_UCODE_CNTL));
3396
3397         mutex_lock(&adev->srbm_mutex);
3398         for (i = 0; i < 16; i++) {
3399                 vi_srbm_select(adev, 0, 0, 0, i);
3400                 dev_info(adev->dev, "  VM %d:\n", i);
3401                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3402                          RREG32(mmSH_MEM_CONFIG));
3403                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3404                          RREG32(mmSH_MEM_APE1_BASE));
3405                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
3406                          RREG32(mmSH_MEM_APE1_LIMIT));
3407                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
3408                          RREG32(mmSH_MEM_BASES));
3409         }
3410         vi_srbm_select(adev, 0, 0, 0, 0);
3411         mutex_unlock(&adev->srbm_mutex);
3412 }
3413
3414 static int gfx_v8_0_soft_reset(void *handle)
3415 {
3416         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3417         u32 tmp;
3418         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3419
3420         /* GRBM_STATUS */
3421         tmp = RREG32(mmGRBM_STATUS);
3422         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3423                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3424                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3425                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3426                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3427                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3428                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3429                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3430                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3431                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3432         }
3433
3434         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3435                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3436                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3437                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3438                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3439         }
3440
3441         /* GRBM_STATUS2 */
3442         tmp = RREG32(mmGRBM_STATUS2);
3443         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3444                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3445                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3446
3447         /* SRBM_STATUS */
3448         tmp = RREG32(mmSRBM_STATUS);
3449         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3450                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3451                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3452
3453         if (grbm_soft_reset || srbm_soft_reset) {
3454                 gfx_v8_0_print_status((void *)adev);
3455                 /* stop the rlc */
3456                 gfx_v8_0_rlc_stop(adev);
3457
3458                 /* Disable GFX parsing/prefetching */
3459                 gfx_v8_0_cp_gfx_enable(adev, false);
3460
3461                 /* Disable MEC parsing/prefetching */
3462                 /* XXX todo */
3463
3464                 if (grbm_soft_reset) {
3465                         tmp = RREG32(mmGRBM_SOFT_RESET);
3466                         tmp |= grbm_soft_reset;
3467                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3468                         WREG32(mmGRBM_SOFT_RESET, tmp);
3469                         tmp = RREG32(mmGRBM_SOFT_RESET);
3470
3471                         udelay(50);
3472
3473                         tmp &= ~grbm_soft_reset;
3474                         WREG32(mmGRBM_SOFT_RESET, tmp);
3475                         tmp = RREG32(mmGRBM_SOFT_RESET);
3476                 }
3477
3478                 if (srbm_soft_reset) {
3479                         tmp = RREG32(mmSRBM_SOFT_RESET);
3480                         tmp |= srbm_soft_reset;
3481                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3482                         WREG32(mmSRBM_SOFT_RESET, tmp);
3483                         tmp = RREG32(mmSRBM_SOFT_RESET);
3484
3485                         udelay(50);
3486
3487                         tmp &= ~srbm_soft_reset;
3488                         WREG32(mmSRBM_SOFT_RESET, tmp);
3489                         tmp = RREG32(mmSRBM_SOFT_RESET);
3490                 }
3491                 /* Wait a little for things to settle down */
3492                 udelay(50);
3493                 gfx_v8_0_print_status((void *)adev);
3494         }
3495         return 0;
3496 }
3497
3498 /**
3499  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3500  *
3501  * @adev: amdgpu_device pointer
3502  *
3503  * Fetches a GPU clock counter snapshot.
3504  * Returns the 64 bit clock counter snapshot.
3505  */
3506 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3507 {
3508         uint64_t clock;
3509
3510         mutex_lock(&adev->gfx.gpu_clock_mutex);
3511         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3512         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3513                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3514         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3515         return clock;
3516 }
3517
3518 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3519                                           uint32_t vmid,
3520                                           uint32_t gds_base, uint32_t gds_size,
3521                                           uint32_t gws_base, uint32_t gws_size,
3522                                           uint32_t oa_base, uint32_t oa_size)
3523 {
3524         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3525         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3526
3527         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3528         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3529
3530         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3531         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3532
3533         /* GDS Base */
3534         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3535         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3536                                 WRITE_DATA_DST_SEL(0)));
3537         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3538         amdgpu_ring_write(ring, 0);
3539         amdgpu_ring_write(ring, gds_base);
3540
3541         /* GDS Size */
3542         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3543         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3544                                 WRITE_DATA_DST_SEL(0)));
3545         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3546         amdgpu_ring_write(ring, 0);
3547         amdgpu_ring_write(ring, gds_size);
3548
3549         /* GWS */
3550         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3551         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3552                                 WRITE_DATA_DST_SEL(0)));
3553         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3554         amdgpu_ring_write(ring, 0);
3555         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3556
3557         /* OA */
3558         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3559         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3560                                 WRITE_DATA_DST_SEL(0)));
3561         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3562         amdgpu_ring_write(ring, 0);
3563         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3564 }
3565
3566 static int gfx_v8_0_early_init(void *handle)
3567 {
3568         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3569
3570         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3571         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3572         gfx_v8_0_set_ring_funcs(adev);
3573         gfx_v8_0_set_irq_funcs(adev);
3574         gfx_v8_0_set_gds_init(adev);
3575
3576         return 0;
3577 }
3578
3579 static int gfx_v8_0_set_powergating_state(void *handle,
3580                                           enum amd_powergating_state state)
3581 {
3582         return 0;
3583 }
3584
3585 static int gfx_v8_0_set_clockgating_state(void *handle,
3586                                           enum amd_clockgating_state state)
3587 {
3588         return 0;
3589 }
3590
3591 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3592 {
3593         u32 rptr;
3594
3595         rptr = ring->adev->wb.wb[ring->rptr_offs];
3596
3597         return rptr;
3598 }
3599
3600 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3601 {
3602         struct amdgpu_device *adev = ring->adev;
3603         u32 wptr;
3604
3605         if (ring->use_doorbell)
3606                 /* XXX check if swapping is necessary on BE */
3607                 wptr = ring->adev->wb.wb[ring->wptr_offs];
3608         else
3609                 wptr = RREG32(mmCP_RB0_WPTR);
3610
3611         return wptr;
3612 }
3613
3614 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3615 {
3616         struct amdgpu_device *adev = ring->adev;
3617
3618         if (ring->use_doorbell) {
3619                 /* XXX check if swapping is necessary on BE */
3620                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3621                 WDOORBELL32(ring->doorbell_index, ring->wptr);
3622         } else {
3623                 WREG32(mmCP_RB0_WPTR, ring->wptr);
3624                 (void)RREG32(mmCP_RB0_WPTR);
3625         }
3626 }
3627
3628 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3629 {
3630         u32 ref_and_mask, reg_mem_engine;
3631
3632         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3633                 switch (ring->me) {
3634                 case 1:
3635                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3636                         break;
3637                 case 2:
3638                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3639                         break;
3640                 default:
3641                         return;
3642                 }
3643                 reg_mem_engine = 0;
3644         } else {
3645                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3646                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3647         }
3648
3649         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3650         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3651                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3652                                  reg_mem_engine));
3653         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3654         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3655         amdgpu_ring_write(ring, ref_and_mask);
3656         amdgpu_ring_write(ring, ref_and_mask);
3657         amdgpu_ring_write(ring, 0x20); /* poll interval */
3658 }
3659
3660 static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3661                                   struct amdgpu_ib *ib)
3662 {
3663         bool need_ctx_switch = ring->current_ctx != ib->ctx;
3664         u32 header, control = 0;
3665         u32 next_rptr = ring->wptr + 5;
3666
3667         /* drop the CE preamble IB for the same context */
3668         if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
3669             (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
3670             !need_ctx_switch)
3671                 return;
3672
3673         if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
3674                 control |= INDIRECT_BUFFER_VALID;
3675
3676         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
3677                 next_rptr += 2;
3678
3679         next_rptr += 4;
3680         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3681         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3682         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3683         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3684         amdgpu_ring_write(ring, next_rptr);
3685
3686         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3687         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
3688                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3689                 amdgpu_ring_write(ring, 0);
3690         }
3691
3692         if (ib->flags & AMDGPU_IB_FLAG_CE)
3693                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3694         else
3695                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3696
3697         control |= ib->length_dw |
3698                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3699
3700         amdgpu_ring_write(ring, header);
3701         amdgpu_ring_write(ring,
3702 #ifdef __BIG_ENDIAN
3703                           (2 << 0) |
3704 #endif
3705                           (ib->gpu_addr & 0xFFFFFFFC));
3706         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3707         amdgpu_ring_write(ring, control);
3708 }
3709
3710 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3711                                          u64 seq, bool write64bit)
3712 {
3713         /* EVENT_WRITE_EOP - flush caches, send int */
3714         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3715         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3716                                  EOP_TC_ACTION_EN |
3717                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3718                                  EVENT_INDEX(5)));
3719         amdgpu_ring_write(ring, addr & 0xfffffffc);
3720         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3721                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2));
3722         amdgpu_ring_write(ring, lower_32_bits(seq));
3723         amdgpu_ring_write(ring, upper_32_bits(seq));
3724 }
3725
3726 /**
3727  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3728  *
3729  * @ring: amdgpu ring buffer object
3730  * @semaphore: amdgpu semaphore object
3731  * @emit_wait: Is this a sempahore wait?
3732  *
3733  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3734  * from running ahead of semaphore waits.
3735  */
3736 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3737                                          struct amdgpu_semaphore *semaphore,
3738                                          bool emit_wait)
3739 {
3740         uint64_t addr = semaphore->gpu_addr;
3741         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3742
3743         if (ring->adev->asic_type == CHIP_TOPAZ ||
3744             ring->adev->asic_type == CHIP_TONGA) {
3745                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3746                 amdgpu_ring_write(ring, lower_32_bits(addr));
3747                 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3748         } else {
3749                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3750                 amdgpu_ring_write(ring, lower_32_bits(addr));
3751                 amdgpu_ring_write(ring, upper_32_bits(addr));
3752                 amdgpu_ring_write(ring, sel);
3753         }
3754
3755         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3756                 /* Prevent the PFP from running ahead of the semaphore wait */
3757                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3758                 amdgpu_ring_write(ring, 0x0);
3759         }
3760
3761         return true;
3762 }
3763
3764 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
3765 {
3766         struct amdgpu_device *adev = ring->adev;
3767         u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3768
3769         /* instruct DE to set a magic number */
3770         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3771         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3772                                                          WRITE_DATA_DST_SEL(5)));
3773         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3774         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3775         amdgpu_ring_write(ring, 1);
3776
3777         /* let CE wait till condition satisfied */
3778         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3779         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3780                                                          WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3781                                                          WAIT_REG_MEM_FUNCTION(3) |  /* == */
3782                                                          WAIT_REG_MEM_ENGINE(2)));   /* ce */
3783         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3784         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3785         amdgpu_ring_write(ring, 1);
3786         amdgpu_ring_write(ring, 0xffffffff);
3787         amdgpu_ring_write(ring, 4); /* poll interval */
3788
3789         /* instruct CE to reset wb of ce_sync to zero */
3790         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3791         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3792                                                          WRITE_DATA_DST_SEL(5) |
3793                                                          WR_CONFIRM));
3794         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3795         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3796         amdgpu_ring_write(ring, 0);
3797 }
3798
3799 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3800                                         unsigned vm_id, uint64_t pd_addr)
3801 {
3802         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3803         u32 srbm_gfx_cntl = 0;
3804
3805         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3806         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3807                                  WRITE_DATA_DST_SEL(0)));
3808         if (vm_id < 8) {
3809                 amdgpu_ring_write(ring,
3810                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3811         } else {
3812                 amdgpu_ring_write(ring,
3813                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3814         }
3815         amdgpu_ring_write(ring, 0);
3816         amdgpu_ring_write(ring, pd_addr >> 12);
3817
3818         /* update SH_MEM_* regs */
3819         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
3820         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3821         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3822                                  WRITE_DATA_DST_SEL(0)));
3823         amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
3824         amdgpu_ring_write(ring, 0);
3825         amdgpu_ring_write(ring, srbm_gfx_cntl);
3826
3827         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
3828         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3829                                  WRITE_DATA_DST_SEL(0)));
3830         amdgpu_ring_write(ring, mmSH_MEM_BASES);
3831         amdgpu_ring_write(ring, 0);
3832
3833         amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
3834         amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
3835         amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
3836         amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
3837
3838         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
3839         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3840         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3841                                  WRITE_DATA_DST_SEL(0)));
3842         amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
3843         amdgpu_ring_write(ring, 0);
3844         amdgpu_ring_write(ring, srbm_gfx_cntl);
3845
3846
3847         /* bits 0-15 are the VM contexts0-15 */
3848         /* invalidate the cache */
3849         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3850         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3851                                  WRITE_DATA_DST_SEL(0)));
3852         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3853         amdgpu_ring_write(ring, 0);
3854         amdgpu_ring_write(ring, 1 << vm_id);
3855
3856         /* wait for the invalidate to complete */
3857         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3858         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3859                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3860                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3861         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3862         amdgpu_ring_write(ring, 0);
3863         amdgpu_ring_write(ring, 0); /* ref */
3864         amdgpu_ring_write(ring, 0); /* mask */
3865         amdgpu_ring_write(ring, 0x20); /* poll interval */
3866
3867         /* compute doesn't have PFP */
3868         if (usepfp) {
3869                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3870                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3871                 amdgpu_ring_write(ring, 0x0);
3872
3873                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3874                 gfx_v8_0_ce_sync_me(ring);
3875         }
3876 }
3877
3878 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
3879 {
3880         if (gfx_v8_0_is_idle(ring->adev)) {
3881                 amdgpu_ring_lockup_update(ring);
3882                 return false;
3883         }
3884         return amdgpu_ring_test_lockup(ring);
3885 }
3886
3887 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3888 {
3889         return ring->adev->wb.wb[ring->rptr_offs];
3890 }
3891
3892 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3893 {
3894         return ring->adev->wb.wb[ring->wptr_offs];
3895 }
3896
3897 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3898 {
3899         struct amdgpu_device *adev = ring->adev;
3900
3901         /* XXX check if swapping is necessary on BE */
3902         adev->wb.wb[ring->wptr_offs] = ring->wptr;
3903         WDOORBELL32(ring->doorbell_index, ring->wptr);
3904 }
3905
3906 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
3907                                              u64 addr, u64 seq,
3908                                              bool write64bits)
3909 {
3910         /* RELEASE_MEM - flush caches, send int */
3911         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3912         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3913                                  EOP_TC_ACTION_EN |
3914                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3915                                  EVENT_INDEX(5)));
3916         amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2));
3917         amdgpu_ring_write(ring, addr & 0xfffffffc);
3918         amdgpu_ring_write(ring, upper_32_bits(addr));
3919         amdgpu_ring_write(ring, lower_32_bits(seq));
3920         amdgpu_ring_write(ring, upper_32_bits(seq));
3921 }
3922
3923 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3924                                                  enum amdgpu_interrupt_state state)
3925 {
3926         u32 cp_int_cntl;
3927
3928         switch (state) {
3929         case AMDGPU_IRQ_STATE_DISABLE:
3930                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3931                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3932                                             TIME_STAMP_INT_ENABLE, 0);
3933                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3934                 break;
3935         case AMDGPU_IRQ_STATE_ENABLE:
3936                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3937                 cp_int_cntl =
3938                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3939                                       TIME_STAMP_INT_ENABLE, 1);
3940                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3941                 break;
3942         default:
3943                 break;
3944         }
3945 }
3946
3947 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3948                                                      int me, int pipe,
3949                                                      enum amdgpu_interrupt_state state)
3950 {
3951         u32 mec_int_cntl, mec_int_cntl_reg;
3952
3953         /*
3954          * amdgpu controls only pipe 0 of MEC1. That's why this function only
3955          * handles the setting of interrupts for this specific pipe. All other
3956          * pipes' interrupts are set by amdkfd.
3957          */
3958
3959         if (me == 1) {
3960                 switch (pipe) {
3961                 case 0:
3962                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
3963                         break;
3964                 default:
3965                         DRM_DEBUG("invalid pipe %d\n", pipe);
3966                         return;
3967                 }
3968         } else {
3969                 DRM_DEBUG("invalid me %d\n", me);
3970                 return;
3971         }
3972
3973         switch (state) {
3974         case AMDGPU_IRQ_STATE_DISABLE:
3975                 mec_int_cntl = RREG32(mec_int_cntl_reg);
3976                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3977                                              TIME_STAMP_INT_ENABLE, 0);
3978                 WREG32(mec_int_cntl_reg, mec_int_cntl);
3979                 break;
3980         case AMDGPU_IRQ_STATE_ENABLE:
3981                 mec_int_cntl = RREG32(mec_int_cntl_reg);
3982                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3983                                              TIME_STAMP_INT_ENABLE, 1);
3984                 WREG32(mec_int_cntl_reg, mec_int_cntl);
3985                 break;
3986         default:
3987                 break;
3988         }
3989 }
3990
3991 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3992                                              struct amdgpu_irq_src *source,
3993                                              unsigned type,
3994                                              enum amdgpu_interrupt_state state)
3995 {
3996         u32 cp_int_cntl;
3997
3998         switch (state) {
3999         case AMDGPU_IRQ_STATE_DISABLE:
4000                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4001                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4002                                             PRIV_REG_INT_ENABLE, 0);
4003                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4004                 break;
4005         case AMDGPU_IRQ_STATE_ENABLE:
4006                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4007                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4008                                             PRIV_REG_INT_ENABLE, 0);
4009                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4010                 break;
4011         default:
4012                 break;
4013         }
4014
4015         return 0;
4016 }
4017
4018 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4019                                               struct amdgpu_irq_src *source,
4020                                               unsigned type,
4021                                               enum amdgpu_interrupt_state state)
4022 {
4023         u32 cp_int_cntl;
4024
4025         switch (state) {
4026         case AMDGPU_IRQ_STATE_DISABLE:
4027                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4028                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4029                                             PRIV_INSTR_INT_ENABLE, 0);
4030                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4031                 break;
4032         case AMDGPU_IRQ_STATE_ENABLE:
4033                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4034                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4035                                             PRIV_INSTR_INT_ENABLE, 1);
4036                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4037                 break;
4038         default:
4039                 break;
4040         }
4041
4042         return 0;
4043 }
4044
4045 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4046                                             struct amdgpu_irq_src *src,
4047                                             unsigned type,
4048                                             enum amdgpu_interrupt_state state)
4049 {
4050         switch (type) {
4051         case AMDGPU_CP_IRQ_GFX_EOP:
4052                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4053                 break;
4054         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4055                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4056                 break;
4057         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4058                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4059                 break;
4060         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4061                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4062                 break;
4063         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4064                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4065                 break;
4066         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4067                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4068                 break;
4069         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4070                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4071                 break;
4072         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4073                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4074                 break;
4075         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4076                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4077                 break;
4078         default:
4079                 break;
4080         }
4081         return 0;
4082 }
4083
4084 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4085                             struct amdgpu_irq_src *source,
4086                             struct amdgpu_iv_entry *entry)
4087 {
4088         int i;
4089         u8 me_id, pipe_id, queue_id;
4090         struct amdgpu_ring *ring;
4091
4092         DRM_DEBUG("IH: CP EOP\n");
4093         me_id = (entry->ring_id & 0x0c) >> 2;
4094         pipe_id = (entry->ring_id & 0x03) >> 0;
4095         queue_id = (entry->ring_id & 0x70) >> 4;
4096
4097         switch (me_id) {
4098         case 0:
4099                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4100                 break;
4101         case 1:
4102         case 2:
4103                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4104                         ring = &adev->gfx.compute_ring[i];
4105                         /* Per-queue interrupt is supported for MEC starting from VI.
4106                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4107                           */
4108                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4109                                 amdgpu_fence_process(ring);
4110                 }
4111                 break;
4112         }
4113         return 0;
4114 }
4115
4116 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4117                                  struct amdgpu_irq_src *source,
4118                                  struct amdgpu_iv_entry *entry)
4119 {
4120         DRM_ERROR("Illegal register access in command stream\n");
4121         schedule_work(&adev->reset_work);
4122         return 0;
4123 }
4124
4125 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4126                                   struct amdgpu_irq_src *source,
4127                                   struct amdgpu_iv_entry *entry)
4128 {
4129         DRM_ERROR("Illegal instruction in command stream\n");
4130         schedule_work(&adev->reset_work);
4131         return 0;
4132 }
4133
4134 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4135         .early_init = gfx_v8_0_early_init,
4136         .late_init = NULL,
4137         .sw_init = gfx_v8_0_sw_init,
4138         .sw_fini = gfx_v8_0_sw_fini,
4139         .hw_init = gfx_v8_0_hw_init,
4140         .hw_fini = gfx_v8_0_hw_fini,
4141         .suspend = gfx_v8_0_suspend,
4142         .resume = gfx_v8_0_resume,
4143         .is_idle = gfx_v8_0_is_idle,
4144         .wait_for_idle = gfx_v8_0_wait_for_idle,
4145         .soft_reset = gfx_v8_0_soft_reset,
4146         .print_status = gfx_v8_0_print_status,
4147         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4148         .set_powergating_state = gfx_v8_0_set_powergating_state,
4149 };
4150
4151 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4152         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4153         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4154         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4155         .parse_cs = NULL,
4156         .emit_ib = gfx_v8_0_ring_emit_ib,
4157         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4158         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4159         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4160         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4161         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4162         .test_ring = gfx_v8_0_ring_test_ring,
4163         .test_ib = gfx_v8_0_ring_test_ib,
4164         .is_lockup = gfx_v8_0_ring_is_lockup,
4165 };
4166
4167 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4168         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4169         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4170         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4171         .parse_cs = NULL,
4172         .emit_ib = gfx_v8_0_ring_emit_ib,
4173         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4174         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4175         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4176         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4177         .test_ring = gfx_v8_0_ring_test_ring,
4178         .test_ib = gfx_v8_0_ring_test_ib,
4179         .is_lockup = gfx_v8_0_ring_is_lockup,
4180 };
4181
4182 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4183 {
4184         int i;
4185
4186         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4187                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4188
4189         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4190                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4191 }
4192
4193 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4194         .set = gfx_v8_0_set_eop_interrupt_state,
4195         .process = gfx_v8_0_eop_irq,
4196 };
4197
4198 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4199         .set = gfx_v8_0_set_priv_reg_fault_state,
4200         .process = gfx_v8_0_priv_reg_irq,
4201 };
4202
4203 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4204         .set = gfx_v8_0_set_priv_inst_fault_state,
4205         .process = gfx_v8_0_priv_inst_irq,
4206 };
4207
4208 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4209 {
4210         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4211         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4212
4213         adev->gfx.priv_reg_irq.num_types = 1;
4214         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4215
4216         adev->gfx.priv_inst_irq.num_types = 1;
4217         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4218 }
4219
4220 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4221 {
4222         /* init asci gds info */
4223         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4224         adev->gds.gws.total_size = 64;
4225         adev->gds.oa.total_size = 16;
4226
4227         if (adev->gds.mem.total_size == 64 * 1024) {
4228                 adev->gds.mem.gfx_partition_size = 4096;
4229                 adev->gds.mem.cs_partition_size = 4096;
4230
4231                 adev->gds.gws.gfx_partition_size = 4;
4232                 adev->gds.gws.cs_partition_size = 4;
4233
4234                 adev->gds.oa.gfx_partition_size = 4;
4235                 adev->gds.oa.cs_partition_size = 1;
4236         } else {
4237                 adev->gds.mem.gfx_partition_size = 1024;
4238                 adev->gds.mem.cs_partition_size = 1024;
4239
4240                 adev->gds.gws.gfx_partition_size = 16;
4241                 adev->gds.gws.cs_partition_size = 16;
4242
4243                 adev->gds.oa.gfx_partition_size = 4;
4244                 adev->gds.oa.cs_partition_size = 4;
4245         }
4246 }
4247
4248 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4249                 u32 se, u32 sh)
4250 {
4251         u32 mask = 0, tmp, tmp1;
4252         int i;
4253
4254         gfx_v8_0_select_se_sh(adev, se, sh);
4255         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4256         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4257         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4258
4259         tmp &= 0xffff0000;
4260
4261         tmp |= tmp1;
4262         tmp >>= 16;
4263
4264         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4265                 mask <<= 1;
4266                 mask |= 1;
4267         }
4268
4269         return (~tmp) & mask;
4270 }
4271
4272 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4273                                                  struct amdgpu_cu_info *cu_info)
4274 {
4275         int i, j, k, counter, active_cu_number = 0;
4276         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4277
4278         if (!adev || !cu_info)
4279                 return -EINVAL;
4280
4281         mutex_lock(&adev->grbm_idx_mutex);
4282         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4283                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4284                         mask = 1;
4285                         ao_bitmap = 0;
4286                         counter = 0;
4287                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4288                         cu_info->bitmap[i][j] = bitmap;
4289
4290                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4291                                 if (bitmap & mask) {
4292                                         if (counter < 2)
4293                                                 ao_bitmap |= mask;
4294                                         counter ++;
4295                                 }
4296                                 mask <<= 1;
4297                         }
4298                         active_cu_number += counter;
4299                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4300                 }
4301         }
4302
4303         cu_info->number = active_cu_number;
4304         cu_info->ao_cu_mask = ao_cu_mask;
4305         mutex_unlock(&adev->grbm_idx_mutex);
4306         return 0;
4307 }