2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
31 #include <linux/pci.h>
32 #include <linux/hwmon.h>
33 #include <linux/hwmon-sysfs.h>
34 #include <linux/nospec.h>
35 #include <linux/pm_runtime.h>
36 #include <asm/processor.h>
38 static const struct hwmon_temp_label {
39 enum PP_HWMON_TEMP channel;
42 {PP_TEMP_EDGE, "edge"},
43 {PP_TEMP_JUNCTION, "junction"},
47 const char * const amdgpu_pp_profile_name[] = {
61 * DOC: power_dpm_state
63 * The power_dpm_state file is a legacy interface and is only provided for
64 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
65 * certain power related parameters. The file power_dpm_state is used for this.
66 * It accepts the following arguments:
76 * On older GPUs, the vbios provided a special power state for battery
77 * operation. Selecting battery switched to this state. This is no
78 * longer provided on newer GPUs so the option does nothing in that case.
82 * On older GPUs, the vbios provided a special power state for balanced
83 * operation. Selecting balanced switched to this state. This is no
84 * longer provided on newer GPUs so the option does nothing in that case.
88 * On older GPUs, the vbios provided a special power state for performance
89 * operation. Selecting performance switched to this state. This is no
90 * longer provided on newer GPUs so the option does nothing in that case.
94 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
95 struct device_attribute *attr,
98 struct drm_device *ddev = dev_get_drvdata(dev);
99 struct amdgpu_device *adev = drm_to_adev(ddev);
100 enum amd_pm_state_type pm;
103 if (amdgpu_in_reset(adev))
105 if (adev->in_suspend && !adev->in_runpm)
108 ret = pm_runtime_get_sync(ddev->dev);
110 pm_runtime_put_autosuspend(ddev->dev);
114 amdgpu_dpm_get_current_power_state(adev, &pm);
116 pm_runtime_mark_last_busy(ddev->dev);
117 pm_runtime_put_autosuspend(ddev->dev);
119 return sysfs_emit(buf, "%s\n",
120 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
121 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
124 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
125 struct device_attribute *attr,
129 struct drm_device *ddev = dev_get_drvdata(dev);
130 struct amdgpu_device *adev = drm_to_adev(ddev);
131 enum amd_pm_state_type state;
134 if (amdgpu_in_reset(adev))
136 if (adev->in_suspend && !adev->in_runpm)
139 if (strncmp("battery", buf, strlen("battery")) == 0)
140 state = POWER_STATE_TYPE_BATTERY;
141 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
142 state = POWER_STATE_TYPE_BALANCED;
143 else if (strncmp("performance", buf, strlen("performance")) == 0)
144 state = POWER_STATE_TYPE_PERFORMANCE;
148 ret = pm_runtime_get_sync(ddev->dev);
150 pm_runtime_put_autosuspend(ddev->dev);
154 amdgpu_dpm_set_power_state(adev, state);
156 pm_runtime_mark_last_busy(ddev->dev);
157 pm_runtime_put_autosuspend(ddev->dev);
164 * DOC: power_dpm_force_performance_level
166 * The amdgpu driver provides a sysfs API for adjusting certain power
167 * related parameters. The file power_dpm_force_performance_level is
168 * used for this. It accepts the following arguments:
188 * When auto is selected, the driver will attempt to dynamically select
189 * the optimal power profile for current conditions in the driver.
193 * When low is selected, the clocks are forced to the lowest power state.
197 * When high is selected, the clocks are forced to the highest power state.
201 * When manual is selected, the user can manually adjust which power states
202 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
203 * and pp_dpm_pcie files and adjust the power state transition heuristics
204 * via the pp_power_profile_mode sysfs file.
211 * When the profiling modes are selected, clock and power gating are
212 * disabled and the clocks are set for different profiling cases. This
213 * mode is recommended for profiling specific work loads where you do
214 * not want clock or power gating for clock fluctuation to interfere
215 * with your results. profile_standard sets the clocks to a fixed clock
216 * level which varies from asic to asic. profile_min_sclk forces the sclk
217 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
218 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
222 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
223 struct device_attribute *attr,
226 struct drm_device *ddev = dev_get_drvdata(dev);
227 struct amdgpu_device *adev = drm_to_adev(ddev);
228 enum amd_dpm_forced_level level = 0xff;
231 if (amdgpu_in_reset(adev))
233 if (adev->in_suspend && !adev->in_runpm)
236 ret = pm_runtime_get_sync(ddev->dev);
238 pm_runtime_put_autosuspend(ddev->dev);
242 level = amdgpu_dpm_get_performance_level(adev);
244 pm_runtime_mark_last_busy(ddev->dev);
245 pm_runtime_put_autosuspend(ddev->dev);
247 return sysfs_emit(buf, "%s\n",
248 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
249 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
250 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
251 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
252 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
253 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
254 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
255 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
256 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
260 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
261 struct device_attribute *attr,
265 struct drm_device *ddev = dev_get_drvdata(dev);
266 struct amdgpu_device *adev = drm_to_adev(ddev);
267 enum amd_dpm_forced_level level;
270 if (amdgpu_in_reset(adev))
272 if (adev->in_suspend && !adev->in_runpm)
275 if (strncmp("low", buf, strlen("low")) == 0) {
276 level = AMD_DPM_FORCED_LEVEL_LOW;
277 } else if (strncmp("high", buf, strlen("high")) == 0) {
278 level = AMD_DPM_FORCED_LEVEL_HIGH;
279 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
280 level = AMD_DPM_FORCED_LEVEL_AUTO;
281 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
282 level = AMD_DPM_FORCED_LEVEL_MANUAL;
283 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
284 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
285 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
286 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
287 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
288 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
289 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
290 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
291 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
292 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
293 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
294 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
299 ret = pm_runtime_get_sync(ddev->dev);
301 pm_runtime_put_autosuspend(ddev->dev);
305 mutex_lock(&adev->pm.stable_pstate_ctx_lock);
306 if (amdgpu_dpm_force_performance_level(adev, level)) {
307 pm_runtime_mark_last_busy(ddev->dev);
308 pm_runtime_put_autosuspend(ddev->dev);
309 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
312 /* override whatever a user ctx may have set */
313 adev->pm.stable_pstate_ctx = NULL;
314 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
316 pm_runtime_mark_last_busy(ddev->dev);
317 pm_runtime_put_autosuspend(ddev->dev);
322 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
323 struct device_attribute *attr,
326 struct drm_device *ddev = dev_get_drvdata(dev);
327 struct amdgpu_device *adev = drm_to_adev(ddev);
328 struct pp_states_info data;
332 if (amdgpu_in_reset(adev))
334 if (adev->in_suspend && !adev->in_runpm)
337 ret = pm_runtime_get_sync(ddev->dev);
339 pm_runtime_put_autosuspend(ddev->dev);
343 if (amdgpu_dpm_get_pp_num_states(adev, &data))
344 memset(&data, 0, sizeof(data));
346 pm_runtime_mark_last_busy(ddev->dev);
347 pm_runtime_put_autosuspend(ddev->dev);
349 buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
350 for (i = 0; i < data.nums; i++)
351 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
352 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
353 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
354 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
355 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
360 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
361 struct device_attribute *attr,
364 struct drm_device *ddev = dev_get_drvdata(dev);
365 struct amdgpu_device *adev = drm_to_adev(ddev);
366 struct pp_states_info data = {0};
367 enum amd_pm_state_type pm = 0;
370 if (amdgpu_in_reset(adev))
372 if (adev->in_suspend && !adev->in_runpm)
375 ret = pm_runtime_get_sync(ddev->dev);
377 pm_runtime_put_autosuspend(ddev->dev);
381 amdgpu_dpm_get_current_power_state(adev, &pm);
383 ret = amdgpu_dpm_get_pp_num_states(adev, &data);
385 pm_runtime_mark_last_busy(ddev->dev);
386 pm_runtime_put_autosuspend(ddev->dev);
391 for (i = 0; i < data.nums; i++) {
392 if (pm == data.states[i])
399 return sysfs_emit(buf, "%d\n", i);
402 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
403 struct device_attribute *attr,
406 struct drm_device *ddev = dev_get_drvdata(dev);
407 struct amdgpu_device *adev = drm_to_adev(ddev);
409 if (amdgpu_in_reset(adev))
411 if (adev->in_suspend && !adev->in_runpm)
414 if (adev->pm.pp_force_state_enabled)
415 return amdgpu_get_pp_cur_state(dev, attr, buf);
417 return sysfs_emit(buf, "\n");
420 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
421 struct device_attribute *attr,
425 struct drm_device *ddev = dev_get_drvdata(dev);
426 struct amdgpu_device *adev = drm_to_adev(ddev);
427 enum amd_pm_state_type state = 0;
428 struct pp_states_info data;
432 if (amdgpu_in_reset(adev))
434 if (adev->in_suspend && !adev->in_runpm)
437 adev->pm.pp_force_state_enabled = false;
439 if (strlen(buf) == 1)
442 ret = kstrtoul(buf, 0, &idx);
443 if (ret || idx >= ARRAY_SIZE(data.states))
446 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
448 ret = pm_runtime_get_sync(ddev->dev);
450 pm_runtime_put_autosuspend(ddev->dev);
454 ret = amdgpu_dpm_get_pp_num_states(adev, &data);
458 state = data.states[idx];
460 /* only set user selected power states */
461 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
462 state != POWER_STATE_TYPE_DEFAULT) {
463 ret = amdgpu_dpm_dispatch_task(adev,
464 AMD_PP_TASK_ENABLE_USER_STATE, &state);
468 adev->pm.pp_force_state_enabled = true;
471 pm_runtime_mark_last_busy(ddev->dev);
472 pm_runtime_put_autosuspend(ddev->dev);
477 pm_runtime_mark_last_busy(ddev->dev);
478 pm_runtime_put_autosuspend(ddev->dev);
485 * The amdgpu driver provides a sysfs API for uploading new powerplay
486 * tables. The file pp_table is used for this. Reading the file
487 * will dump the current power play table. Writing to the file
488 * will attempt to upload a new powerplay table and re-initialize
489 * powerplay using that new table.
493 static ssize_t amdgpu_get_pp_table(struct device *dev,
494 struct device_attribute *attr,
497 struct drm_device *ddev = dev_get_drvdata(dev);
498 struct amdgpu_device *adev = drm_to_adev(ddev);
502 if (amdgpu_in_reset(adev))
504 if (adev->in_suspend && !adev->in_runpm)
507 ret = pm_runtime_get_sync(ddev->dev);
509 pm_runtime_put_autosuspend(ddev->dev);
513 size = amdgpu_dpm_get_pp_table(adev, &table);
515 pm_runtime_mark_last_busy(ddev->dev);
516 pm_runtime_put_autosuspend(ddev->dev);
521 if (size >= PAGE_SIZE)
522 size = PAGE_SIZE - 1;
524 memcpy(buf, table, size);
529 static ssize_t amdgpu_set_pp_table(struct device *dev,
530 struct device_attribute *attr,
534 struct drm_device *ddev = dev_get_drvdata(dev);
535 struct amdgpu_device *adev = drm_to_adev(ddev);
538 if (amdgpu_in_reset(adev))
540 if (adev->in_suspend && !adev->in_runpm)
543 ret = pm_runtime_get_sync(ddev->dev);
545 pm_runtime_put_autosuspend(ddev->dev);
549 ret = amdgpu_dpm_set_pp_table(adev, buf, count);
551 pm_runtime_mark_last_busy(ddev->dev);
552 pm_runtime_put_autosuspend(ddev->dev);
561 * DOC: pp_od_clk_voltage
563 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
564 * in each power level within a power state. The pp_od_clk_voltage is used for
567 * Note that the actual memory controller clock rate are exposed, not
568 * the effective memory clock of the DRAMs. To translate it, use the
571 * Clock conversion (Mhz):
573 * HBM: effective_memory_clock = memory_controller_clock * 1
575 * G5: effective_memory_clock = memory_controller_clock * 1
577 * G6: effective_memory_clock = memory_controller_clock * 2
579 * DRAM data rate (MT/s):
581 * HBM: effective_memory_clock * 2 = data_rate
583 * G5: effective_memory_clock * 4 = data_rate
585 * G6: effective_memory_clock * 8 = data_rate
589 * data_rate * vram_bit_width / 8 = memory_bandwidth
595 * memory_controller_clock = 1750 Mhz
597 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
599 * data rate = 1750 * 4 = 7000 MT/s
601 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
605 * memory_controller_clock = 875 Mhz
607 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
609 * data rate = 1750 * 8 = 14000 MT/s
611 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
613 * < For Vega10 and previous ASICs >
615 * Reading the file will display:
617 * - a list of engine clock levels and voltages labeled OD_SCLK
619 * - a list of memory clock levels and voltages labeled OD_MCLK
621 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
623 * To manually adjust these settings, first select manual using
624 * power_dpm_force_performance_level. Enter a new value for each
625 * level by writing a string that contains "s/m level clock voltage" to
626 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
627 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
628 * 810 mV. When you have edited all of the states as needed, write
629 * "c" (commit) to the file to commit your changes. If you want to reset to the
630 * default power levels, write "r" (reset) to the file to reset them.
633 * < For Vega20 and newer ASICs >
635 * Reading the file will display:
637 * - minimum and maximum engine clock labeled OD_SCLK
639 * - minimum(not available for Vega20 and Navi1x) and maximum memory
640 * clock labeled OD_MCLK
642 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
643 * They can be used to calibrate the sclk voltage curve. This is
644 * available for Vega20 and NV1X.
646 * - voltage offset(in mV) applied on target voltage calculation.
647 * This is available for Sienna Cichlid, Navy Flounder, Dimgrey
648 * Cavefish and some later SMU13 ASICs. For these ASICs, the target
649 * voltage calculation can be illustrated by "voltage = voltage
650 * calculated from v/f curve + overdrive vddgfx offset"
652 * - a list of valid ranges for sclk, mclk, voltage curve points
653 * or voltage offset labeled OD_RANGE
657 * Reading the file will display:
659 * - minimum and maximum engine clock labeled OD_SCLK
661 * - a list of valid ranges for sclk labeled OD_RANGE
665 * Reading the file will display:
667 * - minimum and maximum engine clock labeled OD_SCLK
668 * - minimum and maximum core clocks labeled OD_CCLK
670 * - a list of valid ranges for sclk and cclk labeled OD_RANGE
672 * To manually adjust these settings:
674 * - First select manual using power_dpm_force_performance_level
676 * - For clock frequency setting, enter a new value by writing a
677 * string that contains "s/m index clock" to the file. The index
678 * should be 0 if to set minimum clock. And 1 if to set maximum
679 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
680 * "m 1 800" will update maximum mclk to be 800Mhz. For core
681 * clocks on VanGogh, the string contains "p core index clock".
682 * E.g., "p 2 0 800" would set the minimum core clock on core
685 * For sclk voltage curve supported by Vega20 and NV1X, enter the new
686 * values by writing a string that contains "vc point clock voltage"
687 * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
688 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV.
689 * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
692 * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
693 * Cavefish and some later SMU13 ASICs, enter the new value by writing a
694 * string that contains "vo offset". E.g., "vo -10" will update the extra
695 * voltage offset applied to the whole v/f curve line as -10mv.
697 * - When you have edited all of the states as needed, write "c" (commit)
698 * to the file to commit your changes
700 * - If you want to reset to the default power levels, write "r" (reset)
701 * to the file to reset them
705 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
706 struct device_attribute *attr,
710 struct drm_device *ddev = dev_get_drvdata(dev);
711 struct amdgpu_device *adev = drm_to_adev(ddev);
713 uint32_t parameter_size = 0;
718 const char delimiter[3] = {' ', '\n', '\0'};
721 if (amdgpu_in_reset(adev))
723 if (adev->in_suspend && !adev->in_runpm)
730 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
731 else if (*buf == 'p')
732 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
733 else if (*buf == 'm')
734 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
735 else if (*buf == 'r')
736 type = PP_OD_RESTORE_DEFAULT_TABLE;
737 else if (*buf == 'c')
738 type = PP_OD_COMMIT_DPM_TABLE;
739 else if (!strncmp(buf, "vc", 2))
740 type = PP_OD_EDIT_VDDC_CURVE;
741 else if (!strncmp(buf, "vo", 2))
742 type = PP_OD_EDIT_VDDGFX_OFFSET;
746 memcpy(buf_cpy, buf, count+1);
750 if ((type == PP_OD_EDIT_VDDC_CURVE) ||
751 (type == PP_OD_EDIT_VDDGFX_OFFSET))
753 while (isspace(*++tmp_str));
755 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
756 if (strlen(sub_str) == 0)
758 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
763 while (isspace(*tmp_str))
767 ret = pm_runtime_get_sync(ddev->dev);
769 pm_runtime_put_autosuspend(ddev->dev);
773 if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
779 if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
780 parameter, parameter_size))
783 if (type == PP_OD_COMMIT_DPM_TABLE) {
784 if (amdgpu_dpm_dispatch_task(adev,
785 AMD_PP_TASK_READJUST_POWER_STATE,
790 pm_runtime_mark_last_busy(ddev->dev);
791 pm_runtime_put_autosuspend(ddev->dev);
796 pm_runtime_mark_last_busy(ddev->dev);
797 pm_runtime_put_autosuspend(ddev->dev);
801 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
802 struct device_attribute *attr,
805 struct drm_device *ddev = dev_get_drvdata(dev);
806 struct amdgpu_device *adev = drm_to_adev(ddev);
809 enum pp_clock_type od_clocks[6] = {
819 if (amdgpu_in_reset(adev))
821 if (adev->in_suspend && !adev->in_runpm)
824 ret = pm_runtime_get_sync(ddev->dev);
826 pm_runtime_put_autosuspend(ddev->dev);
830 for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
831 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
835 if (ret == -ENOENT) {
836 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
837 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
838 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
839 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
840 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
841 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
845 size = sysfs_emit(buf, "\n");
847 pm_runtime_mark_last_busy(ddev->dev);
848 pm_runtime_put_autosuspend(ddev->dev);
856 * The amdgpu driver provides a sysfs API for adjusting what powerplay
857 * features to be enabled. The file pp_features is used for this. And
858 * this is only available for Vega10 and later dGPUs.
860 * Reading back the file will show you the followings:
861 * - Current ppfeature masks
862 * - List of the all supported powerplay features with their naming,
863 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
865 * To manually enable or disable a specific feature, just set or clear
866 * the corresponding bit from original ppfeature masks and input the
867 * new ppfeature masks.
869 static ssize_t amdgpu_set_pp_features(struct device *dev,
870 struct device_attribute *attr,
874 struct drm_device *ddev = dev_get_drvdata(dev);
875 struct amdgpu_device *adev = drm_to_adev(ddev);
876 uint64_t featuremask;
879 if (amdgpu_in_reset(adev))
881 if (adev->in_suspend && !adev->in_runpm)
884 ret = kstrtou64(buf, 0, &featuremask);
888 ret = pm_runtime_get_sync(ddev->dev);
890 pm_runtime_put_autosuspend(ddev->dev);
894 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
896 pm_runtime_mark_last_busy(ddev->dev);
897 pm_runtime_put_autosuspend(ddev->dev);
905 static ssize_t amdgpu_get_pp_features(struct device *dev,
906 struct device_attribute *attr,
909 struct drm_device *ddev = dev_get_drvdata(dev);
910 struct amdgpu_device *adev = drm_to_adev(ddev);
914 if (amdgpu_in_reset(adev))
916 if (adev->in_suspend && !adev->in_runpm)
919 ret = pm_runtime_get_sync(ddev->dev);
921 pm_runtime_put_autosuspend(ddev->dev);
925 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
927 size = sysfs_emit(buf, "\n");
929 pm_runtime_mark_last_busy(ddev->dev);
930 pm_runtime_put_autosuspend(ddev->dev);
936 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
938 * The amdgpu driver provides a sysfs API for adjusting what power levels
939 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
940 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
943 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
944 * Vega10 and later ASICs.
945 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
947 * Reading back the files will show you the available power levels within
948 * the power state and the clock information for those levels.
950 * To manually adjust these states, first select manual using
951 * power_dpm_force_performance_level.
952 * Secondly, enter a new value for each level by inputing a string that
953 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
956 * .. code-block:: bash
958 * echo "4 5 6" > pp_dpm_sclk
960 * will enable sclk levels 4, 5, and 6.
962 * NOTE: change to the dcefclk max dpm level is not supported now
965 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
966 enum pp_clock_type type,
969 struct drm_device *ddev = dev_get_drvdata(dev);
970 struct amdgpu_device *adev = drm_to_adev(ddev);
974 if (amdgpu_in_reset(adev))
976 if (adev->in_suspend && !adev->in_runpm)
979 ret = pm_runtime_get_sync(ddev->dev);
981 pm_runtime_put_autosuspend(ddev->dev);
985 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
987 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
990 size = sysfs_emit(buf, "\n");
992 pm_runtime_mark_last_busy(ddev->dev);
993 pm_runtime_put_autosuspend(ddev->dev);
999 * Worst case: 32 bits individually specified, in octal at 12 characters
1000 * per line (+1 for \n).
1002 #define AMDGPU_MASK_BUF_MAX (32 * 13)
1004 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1007 unsigned long level;
1008 char *sub_str = NULL;
1010 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1011 const char delimiter[3] = {' ', '\n', '\0'};
1016 bytes = min(count, sizeof(buf_cpy) - 1);
1017 memcpy(buf_cpy, buf, bytes);
1018 buf_cpy[bytes] = '\0';
1020 while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1021 if (strlen(sub_str)) {
1022 ret = kstrtoul(sub_str, 0, &level);
1023 if (ret || level > 31)
1025 *mask |= 1 << level;
1033 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1034 enum pp_clock_type type,
1038 struct drm_device *ddev = dev_get_drvdata(dev);
1039 struct amdgpu_device *adev = drm_to_adev(ddev);
1043 if (amdgpu_in_reset(adev))
1045 if (adev->in_suspend && !adev->in_runpm)
1048 ret = amdgpu_read_mask(buf, count, &mask);
1052 ret = pm_runtime_get_sync(ddev->dev);
1054 pm_runtime_put_autosuspend(ddev->dev);
1058 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1060 pm_runtime_mark_last_busy(ddev->dev);
1061 pm_runtime_put_autosuspend(ddev->dev);
1069 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1070 struct device_attribute *attr,
1073 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1076 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1077 struct device_attribute *attr,
1081 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1084 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1085 struct device_attribute *attr,
1088 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1091 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1092 struct device_attribute *attr,
1096 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1099 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1100 struct device_attribute *attr,
1103 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1106 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1107 struct device_attribute *attr,
1111 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1114 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1115 struct device_attribute *attr,
1118 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1121 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1122 struct device_attribute *attr,
1126 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1129 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1130 struct device_attribute *attr,
1133 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1136 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1137 struct device_attribute *attr,
1141 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1144 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1145 struct device_attribute *attr,
1148 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1151 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1152 struct device_attribute *attr,
1156 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1159 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1160 struct device_attribute *attr,
1163 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1166 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1167 struct device_attribute *attr,
1171 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1174 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1175 struct device_attribute *attr,
1178 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1181 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1182 struct device_attribute *attr,
1186 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1189 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1190 struct device_attribute *attr,
1193 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1196 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1197 struct device_attribute *attr,
1201 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1204 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1205 struct device_attribute *attr,
1208 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1211 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1212 struct device_attribute *attr,
1216 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1219 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1220 struct device_attribute *attr,
1223 struct drm_device *ddev = dev_get_drvdata(dev);
1224 struct amdgpu_device *adev = drm_to_adev(ddev);
1228 if (amdgpu_in_reset(adev))
1230 if (adev->in_suspend && !adev->in_runpm)
1233 ret = pm_runtime_get_sync(ddev->dev);
1235 pm_runtime_put_autosuspend(ddev->dev);
1239 value = amdgpu_dpm_get_sclk_od(adev);
1241 pm_runtime_mark_last_busy(ddev->dev);
1242 pm_runtime_put_autosuspend(ddev->dev);
1244 return sysfs_emit(buf, "%d\n", value);
1247 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1248 struct device_attribute *attr,
1252 struct drm_device *ddev = dev_get_drvdata(dev);
1253 struct amdgpu_device *adev = drm_to_adev(ddev);
1257 if (amdgpu_in_reset(adev))
1259 if (adev->in_suspend && !adev->in_runpm)
1262 ret = kstrtol(buf, 0, &value);
1267 ret = pm_runtime_get_sync(ddev->dev);
1269 pm_runtime_put_autosuspend(ddev->dev);
1273 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1275 pm_runtime_mark_last_busy(ddev->dev);
1276 pm_runtime_put_autosuspend(ddev->dev);
1281 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1282 struct device_attribute *attr,
1285 struct drm_device *ddev = dev_get_drvdata(dev);
1286 struct amdgpu_device *adev = drm_to_adev(ddev);
1290 if (amdgpu_in_reset(adev))
1292 if (adev->in_suspend && !adev->in_runpm)
1295 ret = pm_runtime_get_sync(ddev->dev);
1297 pm_runtime_put_autosuspend(ddev->dev);
1301 value = amdgpu_dpm_get_mclk_od(adev);
1303 pm_runtime_mark_last_busy(ddev->dev);
1304 pm_runtime_put_autosuspend(ddev->dev);
1306 return sysfs_emit(buf, "%d\n", value);
1309 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1310 struct device_attribute *attr,
1314 struct drm_device *ddev = dev_get_drvdata(dev);
1315 struct amdgpu_device *adev = drm_to_adev(ddev);
1319 if (amdgpu_in_reset(adev))
1321 if (adev->in_suspend && !adev->in_runpm)
1324 ret = kstrtol(buf, 0, &value);
1329 ret = pm_runtime_get_sync(ddev->dev);
1331 pm_runtime_put_autosuspend(ddev->dev);
1335 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1337 pm_runtime_mark_last_busy(ddev->dev);
1338 pm_runtime_put_autosuspend(ddev->dev);
1344 * DOC: pp_power_profile_mode
1346 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1347 * related to switching between power levels in a power state. The file
1348 * pp_power_profile_mode is used for this.
1350 * Reading this file outputs a list of all of the predefined power profiles
1351 * and the relevant heuristics settings for that profile.
1353 * To select a profile or create a custom profile, first select manual using
1354 * power_dpm_force_performance_level. Writing the number of a predefined
1355 * profile to pp_power_profile_mode will enable those heuristics. To
1356 * create a custom set of heuristics, write a string of numbers to the file
1357 * starting with the number of the custom profile along with a setting
1358 * for each heuristic parameter. Due to differences across asic families
1359 * the heuristic parameters vary from family to family.
1363 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1364 struct device_attribute *attr,
1367 struct drm_device *ddev = dev_get_drvdata(dev);
1368 struct amdgpu_device *adev = drm_to_adev(ddev);
1372 if (amdgpu_in_reset(adev))
1374 if (adev->in_suspend && !adev->in_runpm)
1377 ret = pm_runtime_get_sync(ddev->dev);
1379 pm_runtime_put_autosuspend(ddev->dev);
1383 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1385 size = sysfs_emit(buf, "\n");
1387 pm_runtime_mark_last_busy(ddev->dev);
1388 pm_runtime_put_autosuspend(ddev->dev);
1394 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1395 struct device_attribute *attr,
1400 struct drm_device *ddev = dev_get_drvdata(dev);
1401 struct amdgpu_device *adev = drm_to_adev(ddev);
1402 uint32_t parameter_size = 0;
1404 char *sub_str, buf_cpy[128];
1408 long int profile_mode = 0;
1409 const char delimiter[3] = {' ', '\n', '\0'};
1411 if (amdgpu_in_reset(adev))
1413 if (adev->in_suspend && !adev->in_runpm)
1418 ret = kstrtol(tmp, 0, &profile_mode);
1422 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1423 if (count < 2 || count > 127)
1425 while (isspace(*++buf))
1427 memcpy(buf_cpy, buf, count-i);
1429 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1430 if (strlen(sub_str) == 0)
1432 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
1436 while (isspace(*tmp_str))
1440 parameter[parameter_size] = profile_mode;
1442 ret = pm_runtime_get_sync(ddev->dev);
1444 pm_runtime_put_autosuspend(ddev->dev);
1448 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1450 pm_runtime_mark_last_busy(ddev->dev);
1451 pm_runtime_put_autosuspend(ddev->dev);
1459 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1460 enum amd_pp_sensors sensor,
1463 int r, size = sizeof(uint32_t);
1465 if (amdgpu_in_reset(adev))
1467 if (adev->in_suspend && !adev->in_runpm)
1470 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1472 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1476 /* get the sensor value */
1477 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1479 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1480 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1486 * DOC: gpu_busy_percent
1488 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1489 * is as a percentage. The file gpu_busy_percent is used for this.
1490 * The SMU firmware computes a percentage of load based on the
1491 * aggregate activity level in the IP cores.
1493 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1494 struct device_attribute *attr,
1497 struct drm_device *ddev = dev_get_drvdata(dev);
1498 struct amdgpu_device *adev = drm_to_adev(ddev);
1502 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1506 return sysfs_emit(buf, "%d\n", value);
1510 * DOC: mem_busy_percent
1512 * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1513 * is as a percentage. The file mem_busy_percent is used for this.
1514 * The SMU firmware computes a percentage of load based on the
1515 * aggregate activity level in the IP cores.
1517 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1518 struct device_attribute *attr,
1521 struct drm_device *ddev = dev_get_drvdata(dev);
1522 struct amdgpu_device *adev = drm_to_adev(ddev);
1526 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1530 return sysfs_emit(buf, "%d\n", value);
1536 * The amdgpu driver provides a sysfs API for estimating how much data
1537 * has been received and sent by the GPU in the last second through PCIe.
1538 * The file pcie_bw is used for this.
1539 * The Perf counters count the number of received and sent messages and return
1540 * those values, as well as the maximum payload size of a PCIe packet (mps).
1541 * Note that it is not possible to easily and quickly obtain the size of each
1542 * packet transmitted, so we output the max payload size (mps) to allow for
1543 * quick estimation of the PCIe bandwidth usage
1545 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1546 struct device_attribute *attr,
1549 struct drm_device *ddev = dev_get_drvdata(dev);
1550 struct amdgpu_device *adev = drm_to_adev(ddev);
1551 uint64_t count0 = 0, count1 = 0;
1554 if (amdgpu_in_reset(adev))
1556 if (adev->in_suspend && !adev->in_runpm)
1559 if (adev->flags & AMD_IS_APU)
1562 if (!adev->asic_funcs->get_pcie_usage)
1565 ret = pm_runtime_get_sync(ddev->dev);
1567 pm_runtime_put_autosuspend(ddev->dev);
1571 amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1573 pm_runtime_mark_last_busy(ddev->dev);
1574 pm_runtime_put_autosuspend(ddev->dev);
1576 return sysfs_emit(buf, "%llu %llu %i\n",
1577 count0, count1, pcie_get_mps(adev->pdev));
1583 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1584 * The file unique_id is used for this.
1585 * This will provide a Unique ID that will persist from machine to machine
1587 * NOTE: This will only work for GFX9 and newer. This file will be absent
1588 * on unsupported ASICs (GFX8 and older)
1590 static ssize_t amdgpu_get_unique_id(struct device *dev,
1591 struct device_attribute *attr,
1594 struct drm_device *ddev = dev_get_drvdata(dev);
1595 struct amdgpu_device *adev = drm_to_adev(ddev);
1597 if (amdgpu_in_reset(adev))
1599 if (adev->in_suspend && !adev->in_runpm)
1602 if (adev->unique_id)
1603 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1609 * DOC: thermal_throttling_logging
1611 * Thermal throttling pulls down the clock frequency and thus the performance.
1612 * It's an useful mechanism to protect the chip from overheating. Since it
1613 * impacts performance, the user controls whether it is enabled and if so,
1614 * the log frequency.
1616 * Reading back the file shows you the status(enabled or disabled) and
1617 * the interval(in seconds) between each thermal logging.
1619 * Writing an integer to the file, sets a new logging interval, in seconds.
1620 * The value should be between 1 and 3600. If the value is less than 1,
1621 * thermal logging is disabled. Values greater than 3600 are ignored.
1623 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1624 struct device_attribute *attr,
1627 struct drm_device *ddev = dev_get_drvdata(dev);
1628 struct amdgpu_device *adev = drm_to_adev(ddev);
1630 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1631 adev_to_drm(adev)->unique,
1632 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1633 adev->throttling_logging_rs.interval / HZ + 1);
1636 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1637 struct device_attribute *attr,
1641 struct drm_device *ddev = dev_get_drvdata(dev);
1642 struct amdgpu_device *adev = drm_to_adev(ddev);
1643 long throttling_logging_interval;
1644 unsigned long flags;
1647 ret = kstrtol(buf, 0, &throttling_logging_interval);
1651 if (throttling_logging_interval > 3600)
1654 if (throttling_logging_interval > 0) {
1655 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1657 * Reset the ratelimit timer internals.
1658 * This can effectively restart the timer.
1660 adev->throttling_logging_rs.interval =
1661 (throttling_logging_interval - 1) * HZ;
1662 adev->throttling_logging_rs.begin = 0;
1663 adev->throttling_logging_rs.printed = 0;
1664 adev->throttling_logging_rs.missed = 0;
1665 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1667 atomic_set(&adev->throttling_logging_enabled, 1);
1669 atomic_set(&adev->throttling_logging_enabled, 0);
1676 * DOC: apu_thermal_cap
1678 * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1679 * limit temperature in millidegrees Celsius
1681 * Reading back the file shows you core limit value
1683 * Writing an integer to the file, sets a new thermal limit. The value
1684 * should be between 0 and 100. If the value is less than 0 or greater
1685 * than 100, then the write request will be ignored.
1687 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1688 struct device_attribute *attr,
1693 struct drm_device *ddev = dev_get_drvdata(dev);
1694 struct amdgpu_device *adev = drm_to_adev(ddev);
1696 ret = pm_runtime_get_sync(ddev->dev);
1698 pm_runtime_put_autosuspend(ddev->dev);
1702 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1704 size = sysfs_emit(buf, "%u\n", limit);
1706 size = sysfs_emit(buf, "failed to get thermal limit\n");
1708 pm_runtime_mark_last_busy(ddev->dev);
1709 pm_runtime_put_autosuspend(ddev->dev);
1714 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1715 struct device_attribute *attr,
1721 struct drm_device *ddev = dev_get_drvdata(dev);
1722 struct amdgpu_device *adev = drm_to_adev(ddev);
1724 ret = kstrtou32(buf, 10, &value);
1729 dev_err(dev, "Invalid argument !\n");
1733 ret = pm_runtime_get_sync(ddev->dev);
1735 pm_runtime_put_autosuspend(ddev->dev);
1739 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1741 dev_err(dev, "failed to update thermal limit\n");
1745 pm_runtime_mark_last_busy(ddev->dev);
1746 pm_runtime_put_autosuspend(ddev->dev);
1754 * The amdgpu driver provides a sysfs API for retrieving current gpu
1755 * metrics data. The file gpu_metrics is used for this. Reading the
1756 * file will dump all the current gpu metrics data.
1758 * These data include temperature, frequency, engines utilization,
1759 * power consume, throttler status, fan speed and cpu core statistics(
1760 * available for APU only). That's it will give a snapshot of all sensors
1763 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1764 struct device_attribute *attr,
1767 struct drm_device *ddev = dev_get_drvdata(dev);
1768 struct amdgpu_device *adev = drm_to_adev(ddev);
1773 if (amdgpu_in_reset(adev))
1775 if (adev->in_suspend && !adev->in_runpm)
1778 ret = pm_runtime_get_sync(ddev->dev);
1780 pm_runtime_put_autosuspend(ddev->dev);
1784 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1788 if (size >= PAGE_SIZE)
1789 size = PAGE_SIZE - 1;
1791 memcpy(buf, gpu_metrics, size);
1794 pm_runtime_mark_last_busy(ddev->dev);
1795 pm_runtime_put_autosuspend(ddev->dev);
1800 static int amdgpu_show_powershift_percent(struct device *dev,
1801 char *buf, enum amd_pp_sensors sensor)
1803 struct drm_device *ddev = dev_get_drvdata(dev);
1804 struct amdgpu_device *adev = drm_to_adev(ddev);
1808 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1809 if (r == -EOPNOTSUPP) {
1810 /* sensor not available on dGPU, try to read from APU */
1812 mutex_lock(&mgpu_info.mutex);
1813 for (i = 0; i < mgpu_info.num_gpu; i++) {
1814 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1815 adev = mgpu_info.gpu_ins[i].adev;
1819 mutex_unlock(&mgpu_info.mutex);
1821 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1827 return sysfs_emit(buf, "%u%%\n", ss_power);
1831 * DOC: smartshift_apu_power
1833 * The amdgpu driver provides a sysfs API for reporting APU power
1834 * shift in percentage if platform supports smartshift. Value 0 means that
1835 * there is no powershift and values between [1-100] means that the power
1836 * is shifted to APU, the percentage of boost is with respect to APU power
1837 * limit on the platform.
1840 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1843 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1847 * DOC: smartshift_dgpu_power
1849 * The amdgpu driver provides a sysfs API for reporting dGPU power
1850 * shift in percentage if platform supports smartshift. Value 0 means that
1851 * there is no powershift and values between [1-100] means that the power is
1852 * shifted to dGPU, the percentage of boost is with respect to dGPU power
1853 * limit on the platform.
1856 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1859 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1863 * DOC: smartshift_bias
1865 * The amdgpu driver provides a sysfs API for reporting the
1866 * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1867 * and the default is 0. -100 sets maximum preference to APU
1868 * and 100 sets max perference to dGPU.
1871 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1872 struct device_attribute *attr,
1877 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1882 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1883 struct device_attribute *attr,
1884 const char *buf, size_t count)
1886 struct drm_device *ddev = dev_get_drvdata(dev);
1887 struct amdgpu_device *adev = drm_to_adev(ddev);
1891 if (amdgpu_in_reset(adev))
1893 if (adev->in_suspend && !adev->in_runpm)
1896 r = pm_runtime_get_sync(ddev->dev);
1898 pm_runtime_put_autosuspend(ddev->dev);
1902 r = kstrtoint(buf, 10, &bias);
1906 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1907 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1908 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1909 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1911 amdgpu_smartshift_bias = bias;
1914 /* TODO: update bias level with SMU message */
1917 pm_runtime_mark_last_busy(ddev->dev);
1918 pm_runtime_put_autosuspend(ddev->dev);
1922 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1923 uint32_t mask, enum amdgpu_device_attr_states *states)
1925 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1926 *states = ATTR_STATE_UNSUPPORTED;
1931 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1932 uint32_t mask, enum amdgpu_device_attr_states *states)
1936 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1937 *states = ATTR_STATE_UNSUPPORTED;
1938 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1940 *states = ATTR_STATE_UNSUPPORTED;
1941 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1943 *states = ATTR_STATE_UNSUPPORTED;
1948 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1949 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1950 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1951 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1952 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1953 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1954 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1955 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1956 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1957 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1958 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1959 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1960 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1961 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1962 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1963 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1964 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1965 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
1966 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC),
1967 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1968 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC),
1969 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1970 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1971 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC),
1972 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1973 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1974 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1975 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1976 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1977 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC,
1978 .attr_update = ss_power_attr_update),
1979 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC,
1980 .attr_update = ss_power_attr_update),
1981 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC,
1982 .attr_update = ss_bias_attr_update),
1985 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1986 uint32_t mask, enum amdgpu_device_attr_states *states)
1988 struct device_attribute *dev_attr = &attr->dev_attr;
1989 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
1990 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
1991 const char *attr_name = dev_attr->attr.name;
1993 if (!(attr->flags & mask)) {
1994 *states = ATTR_STATE_UNSUPPORTED;
1998 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name))
2000 if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2001 if (gc_ver < IP_VERSION(9, 0, 0))
2002 *states = ATTR_STATE_UNSUPPORTED;
2003 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2004 if (gc_ver < IP_VERSION(9, 0, 0) ||
2005 !amdgpu_device_has_display_hardware(adev))
2006 *states = ATTR_STATE_UNSUPPORTED;
2007 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2008 if (mp1_ver < IP_VERSION(10, 0, 0))
2009 *states = ATTR_STATE_UNSUPPORTED;
2010 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2011 *states = ATTR_STATE_UNSUPPORTED;
2012 if (amdgpu_dpm_is_overdrive_supported(adev))
2013 *states = ATTR_STATE_SUPPORTED;
2014 } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2015 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2016 *states = ATTR_STATE_UNSUPPORTED;
2017 } else if (DEVICE_ATTR_IS(pcie_bw)) {
2018 /* PCIe Perf counters won't work on APU nodes */
2019 if (adev->flags & AMD_IS_APU)
2020 *states = ATTR_STATE_UNSUPPORTED;
2021 } else if (DEVICE_ATTR_IS(unique_id)) {
2023 case IP_VERSION(9, 0, 1):
2024 case IP_VERSION(9, 4, 0):
2025 case IP_VERSION(9, 4, 1):
2026 case IP_VERSION(9, 4, 2):
2027 case IP_VERSION(9, 4, 3):
2028 case IP_VERSION(10, 3, 0):
2029 case IP_VERSION(11, 0, 0):
2030 case IP_VERSION(11, 0, 1):
2031 case IP_VERSION(11, 0, 2):
2032 *states = ATTR_STATE_SUPPORTED;
2035 *states = ATTR_STATE_UNSUPPORTED;
2037 } else if (DEVICE_ATTR_IS(pp_features)) {
2038 if ((adev->flags & AMD_IS_APU &&
2039 gc_ver != IP_VERSION(9, 4, 3)) ||
2040 gc_ver < IP_VERSION(9, 0, 0))
2041 *states = ATTR_STATE_UNSUPPORTED;
2042 } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2043 if (gc_ver < IP_VERSION(9, 1, 0))
2044 *states = ATTR_STATE_UNSUPPORTED;
2045 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2046 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2047 gc_ver == IP_VERSION(10, 3, 0) ||
2048 gc_ver == IP_VERSION(10, 1, 2) ||
2049 gc_ver == IP_VERSION(11, 0, 0) ||
2050 gc_ver == IP_VERSION(11, 0, 2) ||
2051 gc_ver == IP_VERSION(11, 0, 3) ||
2052 gc_ver == IP_VERSION(9, 4, 3)))
2053 *states = ATTR_STATE_UNSUPPORTED;
2054 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2055 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2056 gc_ver == IP_VERSION(10, 3, 0) ||
2057 gc_ver == IP_VERSION(11, 0, 2) ||
2058 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2059 *states = ATTR_STATE_UNSUPPORTED;
2060 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2061 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2062 gc_ver == IP_VERSION(10, 3, 0) ||
2063 gc_ver == IP_VERSION(10, 1, 2) ||
2064 gc_ver == IP_VERSION(11, 0, 0) ||
2065 gc_ver == IP_VERSION(11, 0, 2) ||
2066 gc_ver == IP_VERSION(11, 0, 3) ||
2067 gc_ver == IP_VERSION(9, 4, 3)))
2068 *states = ATTR_STATE_UNSUPPORTED;
2069 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2070 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2071 gc_ver == IP_VERSION(10, 3, 0) ||
2072 gc_ver == IP_VERSION(11, 0, 2) ||
2073 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2074 *states = ATTR_STATE_UNSUPPORTED;
2075 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2076 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2077 *states = ATTR_STATE_UNSUPPORTED;
2078 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2079 *states = ATTR_STATE_UNSUPPORTED;
2083 case IP_VERSION(9, 4, 1):
2084 case IP_VERSION(9, 4, 2):
2085 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2086 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2087 DEVICE_ATTR_IS(pp_dpm_socclk) ||
2088 DEVICE_ATTR_IS(pp_dpm_fclk)) {
2089 dev_attr->attr.mode &= ~S_IWUGO;
2090 dev_attr->store = NULL;
2093 case IP_VERSION(10, 3, 0):
2094 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2095 amdgpu_sriov_vf(adev)) {
2096 dev_attr->attr.mode &= ~0222;
2097 dev_attr->store = NULL;
2104 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2105 /* SMU MP1 does not support dcefclk level setting */
2106 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2107 dev_attr->attr.mode &= ~S_IWUGO;
2108 dev_attr->store = NULL;
2112 /* setting should not be allowed from VF if not in one VF mode */
2113 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2114 dev_attr->attr.mode &= ~S_IWUGO;
2115 dev_attr->store = NULL;
2118 #undef DEVICE_ATTR_IS
2124 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2125 struct amdgpu_device_attr *attr,
2126 uint32_t mask, struct list_head *attr_list)
2129 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2130 struct amdgpu_device_attr_entry *attr_entry;
2131 struct device_attribute *dev_attr;
2134 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2135 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2140 dev_attr = &attr->dev_attr;
2141 name = dev_attr->attr.name;
2143 attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2145 ret = attr_update(adev, attr, mask, &attr_states);
2147 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2152 if (attr_states == ATTR_STATE_UNSUPPORTED)
2155 ret = device_create_file(adev->dev, dev_attr);
2157 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2161 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2165 attr_entry->attr = attr;
2166 INIT_LIST_HEAD(&attr_entry->entry);
2168 list_add_tail(&attr_entry->entry, attr_list);
2173 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2175 struct device_attribute *dev_attr = &attr->dev_attr;
2177 device_remove_file(adev->dev, dev_attr);
2180 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2181 struct list_head *attr_list);
2183 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2184 struct amdgpu_device_attr *attrs,
2187 struct list_head *attr_list)
2192 for (i = 0; i < counts; i++) {
2193 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2201 amdgpu_device_attr_remove_groups(adev, attr_list);
2206 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2207 struct list_head *attr_list)
2209 struct amdgpu_device_attr_entry *entry, *entry_tmp;
2211 if (list_empty(attr_list))
2214 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2215 amdgpu_device_attr_remove(adev, entry->attr);
2216 list_del(&entry->entry);
2221 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2222 struct device_attribute *attr,
2225 struct amdgpu_device *adev = dev_get_drvdata(dev);
2226 int channel = to_sensor_dev_attr(attr)->index;
2229 if (channel >= PP_TEMP_MAX)
2233 case PP_TEMP_JUNCTION:
2234 /* get current junction temperature */
2235 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2239 /* get current edge temperature */
2240 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2244 /* get current memory temperature */
2245 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2256 return sysfs_emit(buf, "%d\n", temp);
2259 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2260 struct device_attribute *attr,
2263 struct amdgpu_device *adev = dev_get_drvdata(dev);
2264 int hyst = to_sensor_dev_attr(attr)->index;
2268 temp = adev->pm.dpm.thermal.min_temp;
2270 temp = adev->pm.dpm.thermal.max_temp;
2272 return sysfs_emit(buf, "%d\n", temp);
2275 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2276 struct device_attribute *attr,
2279 struct amdgpu_device *adev = dev_get_drvdata(dev);
2280 int hyst = to_sensor_dev_attr(attr)->index;
2284 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2286 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2288 return sysfs_emit(buf, "%d\n", temp);
2291 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2292 struct device_attribute *attr,
2295 struct amdgpu_device *adev = dev_get_drvdata(dev);
2296 int hyst = to_sensor_dev_attr(attr)->index;
2300 temp = adev->pm.dpm.thermal.min_mem_temp;
2302 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2304 return sysfs_emit(buf, "%d\n", temp);
2307 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2308 struct device_attribute *attr,
2311 int channel = to_sensor_dev_attr(attr)->index;
2313 if (channel >= PP_TEMP_MAX)
2316 return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2319 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2320 struct device_attribute *attr,
2323 struct amdgpu_device *adev = dev_get_drvdata(dev);
2324 int channel = to_sensor_dev_attr(attr)->index;
2327 if (channel >= PP_TEMP_MAX)
2331 case PP_TEMP_JUNCTION:
2332 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2335 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2338 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2342 return sysfs_emit(buf, "%d\n", temp);
2345 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2346 struct device_attribute *attr,
2349 struct amdgpu_device *adev = dev_get_drvdata(dev);
2353 if (amdgpu_in_reset(adev))
2355 if (adev->in_suspend && !adev->in_runpm)
2358 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2360 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2364 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2366 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2367 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2372 return sysfs_emit(buf, "%u\n", pwm_mode);
2375 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2376 struct device_attribute *attr,
2380 struct amdgpu_device *adev = dev_get_drvdata(dev);
2384 if (amdgpu_in_reset(adev))
2386 if (adev->in_suspend && !adev->in_runpm)
2389 err = kstrtoint(buf, 10, &value);
2393 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2395 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2399 ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2401 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2402 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2410 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2411 struct device_attribute *attr,
2414 return sysfs_emit(buf, "%i\n", 0);
2417 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2418 struct device_attribute *attr,
2421 return sysfs_emit(buf, "%i\n", 255);
2424 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2425 struct device_attribute *attr,
2426 const char *buf, size_t count)
2428 struct amdgpu_device *adev = dev_get_drvdata(dev);
2433 if (amdgpu_in_reset(adev))
2435 if (adev->in_suspend && !adev->in_runpm)
2438 err = kstrtou32(buf, 10, &value);
2442 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2444 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2448 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2452 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2453 pr_info("manual fan speed control should be enabled first\n");
2458 err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2461 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2462 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2470 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2471 struct device_attribute *attr,
2474 struct amdgpu_device *adev = dev_get_drvdata(dev);
2478 if (amdgpu_in_reset(adev))
2480 if (adev->in_suspend && !adev->in_runpm)
2483 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2485 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2489 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2491 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2492 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2497 return sysfs_emit(buf, "%i\n", speed);
2500 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2501 struct device_attribute *attr,
2504 struct amdgpu_device *adev = dev_get_drvdata(dev);
2508 if (amdgpu_in_reset(adev))
2510 if (adev->in_suspend && !adev->in_runpm)
2513 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2515 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2519 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2521 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2522 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2527 return sysfs_emit(buf, "%i\n", speed);
2530 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2531 struct device_attribute *attr,
2534 struct amdgpu_device *adev = dev_get_drvdata(dev);
2538 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2544 return sysfs_emit(buf, "%d\n", min_rpm);
2547 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2548 struct device_attribute *attr,
2551 struct amdgpu_device *adev = dev_get_drvdata(dev);
2555 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2561 return sysfs_emit(buf, "%d\n", max_rpm);
2564 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2565 struct device_attribute *attr,
2568 struct amdgpu_device *adev = dev_get_drvdata(dev);
2572 if (amdgpu_in_reset(adev))
2574 if (adev->in_suspend && !adev->in_runpm)
2577 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2579 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2583 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2585 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2586 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2591 return sysfs_emit(buf, "%i\n", rpm);
2594 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2595 struct device_attribute *attr,
2596 const char *buf, size_t count)
2598 struct amdgpu_device *adev = dev_get_drvdata(dev);
2603 if (amdgpu_in_reset(adev))
2605 if (adev->in_suspend && !adev->in_runpm)
2608 err = kstrtou32(buf, 10, &value);
2612 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2614 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2618 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2622 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2627 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2630 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2631 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2639 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2640 struct device_attribute *attr,
2643 struct amdgpu_device *adev = dev_get_drvdata(dev);
2647 if (amdgpu_in_reset(adev))
2649 if (adev->in_suspend && !adev->in_runpm)
2652 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2654 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2658 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2660 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2661 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2666 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2669 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2670 struct device_attribute *attr,
2674 struct amdgpu_device *adev = dev_get_drvdata(dev);
2679 if (amdgpu_in_reset(adev))
2681 if (adev->in_suspend && !adev->in_runpm)
2684 err = kstrtoint(buf, 10, &value);
2689 pwm_mode = AMD_FAN_CTRL_AUTO;
2690 else if (value == 1)
2691 pwm_mode = AMD_FAN_CTRL_MANUAL;
2695 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2697 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2701 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2703 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2704 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2712 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2713 struct device_attribute *attr,
2716 struct amdgpu_device *adev = dev_get_drvdata(dev);
2720 /* get the voltage */
2721 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2726 return sysfs_emit(buf, "%d\n", vddgfx);
2729 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2730 struct device_attribute *attr,
2733 return sysfs_emit(buf, "vddgfx\n");
2736 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2737 struct device_attribute *attr,
2740 struct amdgpu_device *adev = dev_get_drvdata(dev);
2744 /* only APUs have vddnb */
2745 if (!(adev->flags & AMD_IS_APU))
2748 /* get the voltage */
2749 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2754 return sysfs_emit(buf, "%d\n", vddnb);
2757 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2758 struct device_attribute *attr,
2761 return sysfs_emit(buf, "vddnb\n");
2764 static int amdgpu_hwmon_get_power(struct device *dev,
2765 enum amd_pp_sensors sensor)
2767 struct amdgpu_device *adev = dev_get_drvdata(dev);
2772 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2776 /* convert to microwatts */
2777 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2782 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2783 struct device_attribute *attr,
2788 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2792 return sysfs_emit(buf, "%zd\n", val);
2795 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2796 struct device_attribute *attr,
2801 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2805 return sysfs_emit(buf, "%zd\n", val);
2808 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2809 struct device_attribute *attr,
2812 return sysfs_emit(buf, "%i\n", 0);
2816 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2817 struct device_attribute *attr,
2819 enum pp_power_limit_level pp_limit_level)
2821 struct amdgpu_device *adev = dev_get_drvdata(dev);
2822 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2827 if (amdgpu_in_reset(adev))
2829 if (adev->in_suspend && !adev->in_runpm)
2832 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2834 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2838 r = amdgpu_dpm_get_power_limit(adev, &limit,
2839 pp_limit_level, power_type);
2842 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2844 size = sysfs_emit(buf, "\n");
2846 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2847 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2853 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2854 struct device_attribute *attr,
2857 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2861 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2862 struct device_attribute *attr,
2865 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2869 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2870 struct device_attribute *attr,
2873 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2877 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2878 struct device_attribute *attr,
2881 struct amdgpu_device *adev = dev_get_drvdata(dev);
2882 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2884 if (gc_ver == IP_VERSION(10, 3, 1))
2885 return sysfs_emit(buf, "%s\n",
2886 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
2887 "fastPPT" : "slowPPT");
2889 return sysfs_emit(buf, "PPT\n");
2892 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2893 struct device_attribute *attr,
2897 struct amdgpu_device *adev = dev_get_drvdata(dev);
2898 int limit_type = to_sensor_dev_attr(attr)->index;
2902 if (amdgpu_in_reset(adev))
2904 if (adev->in_suspend && !adev->in_runpm)
2907 if (amdgpu_sriov_vf(adev))
2910 err = kstrtou32(buf, 10, &value);
2914 value = value / 1000000; /* convert to Watt */
2915 value |= limit_type << 24;
2917 err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2919 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2923 err = amdgpu_dpm_set_power_limit(adev, value);
2925 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2926 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2934 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2935 struct device_attribute *attr,
2938 struct amdgpu_device *adev = dev_get_drvdata(dev);
2943 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2948 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
2951 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2952 struct device_attribute *attr,
2955 return sysfs_emit(buf, "sclk\n");
2958 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2959 struct device_attribute *attr,
2962 struct amdgpu_device *adev = dev_get_drvdata(dev);
2967 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2972 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
2975 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2976 struct device_attribute *attr,
2979 return sysfs_emit(buf, "mclk\n");
2985 * The amdgpu driver exposes the following sensor interfaces:
2987 * - GPU temperature (via the on-die sensor)
2991 * - Northbridge voltage (APUs only)
2997 * - GPU gfx/compute engine clock
2999 * - GPU memory clock (dGPU only)
3001 * hwmon interfaces for GPU temperature:
3003 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3004 * - temp2_input and temp3_input are supported on SOC15 dGPUs only
3006 * - temp[1-3]_label: temperature channel label
3007 * - temp2_label and temp3_label are supported on SOC15 dGPUs only
3009 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3010 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3012 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3013 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3015 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3016 * - these are supported on SOC15 dGPUs only
3018 * hwmon interfaces for GPU voltage:
3020 * - in0_input: the voltage on the GPU in millivolts
3022 * - in1_input: the voltage on the Northbridge in millivolts
3024 * hwmon interfaces for GPU power:
3026 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU.
3028 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU.
3030 * - power1_cap_min: minimum cap supported in microWatts
3032 * - power1_cap_max: maximum cap supported in microWatts
3034 * - power1_cap: selected power cap in microWatts
3036 * hwmon interfaces for GPU fan:
3038 * - pwm1: pulse width modulation fan level (0-255)
3040 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3042 * - pwm1_min: pulse width modulation fan control minimum level (0)
3044 * - pwm1_max: pulse width modulation fan control maximum level (255)
3046 * - fan1_min: a minimum value Unit: revolution/min (RPM)
3048 * - fan1_max: a maximum value Unit: revolution/max (RPM)
3050 * - fan1_input: fan speed in RPM
3052 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3054 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3056 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3057 * That will get the former one overridden.
3059 * hwmon interfaces for GPU clocks:
3061 * - freq1_input: the gfx/compute clock in hertz
3063 * - freq2_input: the memory clock in hertz
3065 * You can use hwmon tools like sensors to view this information on your system.
3069 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3070 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3071 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3072 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3073 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3074 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3075 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3076 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3077 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3078 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3079 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3080 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3081 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3082 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3083 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3084 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3085 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3086 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3087 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3088 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3089 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3090 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3091 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3092 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3093 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3094 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3095 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3096 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3097 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3098 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3099 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3100 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3101 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3102 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3103 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3104 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3105 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3106 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3107 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3108 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3109 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3110 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3111 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3112 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3113 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3115 static struct attribute *hwmon_attributes[] = {
3116 &sensor_dev_attr_temp1_input.dev_attr.attr,
3117 &sensor_dev_attr_temp1_crit.dev_attr.attr,
3118 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3119 &sensor_dev_attr_temp2_input.dev_attr.attr,
3120 &sensor_dev_attr_temp2_crit.dev_attr.attr,
3121 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3122 &sensor_dev_attr_temp3_input.dev_attr.attr,
3123 &sensor_dev_attr_temp3_crit.dev_attr.attr,
3124 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3125 &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3126 &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3127 &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3128 &sensor_dev_attr_temp1_label.dev_attr.attr,
3129 &sensor_dev_attr_temp2_label.dev_attr.attr,
3130 &sensor_dev_attr_temp3_label.dev_attr.attr,
3131 &sensor_dev_attr_pwm1.dev_attr.attr,
3132 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3133 &sensor_dev_attr_pwm1_min.dev_attr.attr,
3134 &sensor_dev_attr_pwm1_max.dev_attr.attr,
3135 &sensor_dev_attr_fan1_input.dev_attr.attr,
3136 &sensor_dev_attr_fan1_min.dev_attr.attr,
3137 &sensor_dev_attr_fan1_max.dev_attr.attr,
3138 &sensor_dev_attr_fan1_target.dev_attr.attr,
3139 &sensor_dev_attr_fan1_enable.dev_attr.attr,
3140 &sensor_dev_attr_in0_input.dev_attr.attr,
3141 &sensor_dev_attr_in0_label.dev_attr.attr,
3142 &sensor_dev_attr_in1_input.dev_attr.attr,
3143 &sensor_dev_attr_in1_label.dev_attr.attr,
3144 &sensor_dev_attr_power1_average.dev_attr.attr,
3145 &sensor_dev_attr_power1_input.dev_attr.attr,
3146 &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3147 &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3148 &sensor_dev_attr_power1_cap.dev_attr.attr,
3149 &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3150 &sensor_dev_attr_power1_label.dev_attr.attr,
3151 &sensor_dev_attr_power2_average.dev_attr.attr,
3152 &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3153 &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3154 &sensor_dev_attr_power2_cap.dev_attr.attr,
3155 &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3156 &sensor_dev_attr_power2_label.dev_attr.attr,
3157 &sensor_dev_attr_freq1_input.dev_attr.attr,
3158 &sensor_dev_attr_freq1_label.dev_attr.attr,
3159 &sensor_dev_attr_freq2_input.dev_attr.attr,
3160 &sensor_dev_attr_freq2_label.dev_attr.attr,
3164 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3165 struct attribute *attr, int index)
3167 struct device *dev = kobj_to_dev(kobj);
3168 struct amdgpu_device *adev = dev_get_drvdata(dev);
3169 umode_t effective_mode = attr->mode;
3170 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3173 /* under multi-vf mode, the hwmon attributes are all not supported */
3174 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3177 /* under pp one vf mode manage of hwmon attributes is not supported */
3178 if (amdgpu_sriov_is_pp_one_vf(adev))
3179 effective_mode &= ~S_IWUSR;
3181 /* Skip fan attributes if fan is not present */
3182 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3183 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3184 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3185 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3186 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3187 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3188 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3189 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3190 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3193 /* Skip fan attributes on APU */
3194 if ((adev->flags & AMD_IS_APU) &&
3195 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3196 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3197 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3198 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3199 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3200 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3201 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3202 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3203 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3206 /* Skip crit temp on APU */
3207 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3208 (gc_ver == IP_VERSION(9, 4, 3))) &&
3209 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3210 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3213 /* Skip limit attributes if DPM is not enabled */
3214 if (!adev->pm.dpm_enabled &&
3215 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3216 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3217 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3218 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3219 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3220 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3221 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3222 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3223 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3224 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3225 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3228 /* mask fan attributes if we have no bindings for this asic to expose */
3229 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3230 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3231 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3232 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3233 effective_mode &= ~S_IRUGO;
3235 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3236 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3237 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3238 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3239 effective_mode &= ~S_IWUSR;
3241 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3242 if (((adev->family == AMDGPU_FAMILY_SI) ||
3243 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3244 (gc_ver != IP_VERSION(9, 4, 3)))) &&
3245 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3246 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3247 attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3248 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3251 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3252 if (((adev->family == AMDGPU_FAMILY_SI) ||
3253 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3254 (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3257 /* not all products support both average and instantaneous */
3258 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3259 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3261 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3262 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3265 /* hide max/min values if we can't both query and manage the fan */
3266 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3267 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3268 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3269 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3270 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3271 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3274 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3275 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3276 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3277 attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3280 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */
3281 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */
3282 (gc_ver == IP_VERSION(9, 4, 3))) &&
3283 (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3284 attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3287 /* only APUs other than gc 9,4,3 have vddnb */
3288 if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3289 (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3290 attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3293 /* no mclk on APUs other than gc 9,4,3*/
3294 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3295 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3296 attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3299 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3300 (gc_ver != IP_VERSION(9, 4, 3)) &&
3301 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3302 attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3303 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3304 attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3305 attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3306 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3309 /* hotspot temperature for gc 9,4,3*/
3310 if ((gc_ver == IP_VERSION(9, 4, 3)) &&
3311 (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3312 attr == &sensor_dev_attr_temp1_label.dev_attr.attr))
3315 /* only SOC15 dGPUs support hotspot and mem temperatures */
3316 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) ||
3317 (gc_ver == IP_VERSION(9, 4, 3))) &&
3318 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3319 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3320 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3321 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3322 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3325 /* only Vangogh has fast PPT limit and power labels */
3326 if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3327 (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3328 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3329 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3330 attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3331 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3332 attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3335 return effective_mode;
3338 static const struct attribute_group hwmon_attrgroup = {
3339 .attrs = hwmon_attributes,
3340 .is_visible = hwmon_attributes_visible,
3343 static const struct attribute_group *hwmon_groups[] = {
3348 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3353 if (adev->pm.sysfs_initialized)
3356 INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3358 if (adev->pm.dpm_enabled == 0)
3361 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3364 if (IS_ERR(adev->pm.int_hwmon_dev)) {
3365 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3367 "Unable to register hwmon device: %d\n", ret);
3371 switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3372 case SRIOV_VF_MODE_ONE_VF:
3373 mask = ATTR_FLAG_ONEVF;
3375 case SRIOV_VF_MODE_MULTI_VF:
3378 case SRIOV_VF_MODE_BARE_METAL:
3380 mask = ATTR_FLAG_MASK_ALL;
3384 ret = amdgpu_device_attr_create_groups(adev,
3385 amdgpu_device_attrs,
3386 ARRAY_SIZE(amdgpu_device_attrs),
3388 &adev->pm.pm_attr_list);
3392 adev->pm.sysfs_initialized = true;
3397 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3399 if (adev->pm.int_hwmon_dev)
3400 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3402 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3408 #if defined(CONFIG_DEBUG_FS)
3410 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3411 struct amdgpu_device *adev)
3416 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3418 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3419 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3422 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3423 (void *)p_val, &size)) {
3424 for (i = 0; i < num_cpu_cores; i++)
3425 seq_printf(m, "\t%u MHz (CPU%d)\n",
3433 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3435 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3436 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3438 uint64_t value64 = 0;
3443 size = sizeof(value);
3444 seq_printf(m, "GFX Clocks and Power:\n");
3446 amdgpu_debugfs_prints_cpu_info(m, adev);
3448 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3449 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3450 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3451 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3452 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3453 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3454 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3455 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3456 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3457 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3458 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3459 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3460 size = sizeof(uint32_t);
3461 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size))
3462 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3463 size = sizeof(uint32_t);
3464 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size))
3465 seq_printf(m, "\t%u.%u W (current GPU)\n", query >> 8, query & 0xff);
3466 size = sizeof(value);
3467 seq_printf(m, "\n");
3470 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3471 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3474 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3475 seq_printf(m, "GPU Load: %u %%\n", value);
3477 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3478 seq_printf(m, "MEM Load: %u %%\n", value);
3480 seq_printf(m, "\n");
3482 /* SMC feature mask */
3483 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3484 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3486 /* ASICs greater than CHIP_VEGA20 supports these sensors */
3487 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3489 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3491 seq_printf(m, "VCN: Disabled\n");
3493 seq_printf(m, "VCN: Enabled\n");
3494 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3495 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3496 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3497 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3500 seq_printf(m, "\n");
3503 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3505 seq_printf(m, "UVD: Disabled\n");
3507 seq_printf(m, "UVD: Enabled\n");
3508 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3509 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3510 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3511 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3514 seq_printf(m, "\n");
3517 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3519 seq_printf(m, "VCE: Disabled\n");
3521 seq_printf(m, "VCE: Enabled\n");
3522 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3523 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3531 static const struct cg_flag_name clocks[] = {
3532 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
3533 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
3534 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
3535 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
3536 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
3537 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
3538 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
3539 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
3540 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
3541 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
3542 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
3543 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
3544 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
3545 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
3546 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
3547 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
3548 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
3549 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
3550 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
3551 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
3552 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
3553 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
3554 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
3555 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
3556 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
3557 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
3558 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
3559 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
3560 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
3561 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
3562 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
3563 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
3564 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
3565 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
3569 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3573 for (i = 0; clocks[i].flag; i++)
3574 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3575 (flags & clocks[i].flag) ? "On" : "Off");
3578 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3580 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3581 struct drm_device *dev = adev_to_drm(adev);
3585 if (amdgpu_in_reset(adev))
3587 if (adev->in_suspend && !adev->in_runpm)
3590 r = pm_runtime_get_sync(dev->dev);
3592 pm_runtime_put_autosuspend(dev->dev);
3596 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3597 r = amdgpu_debugfs_pm_info_pp(m, adev);
3602 amdgpu_device_ip_get_clockgating_state(adev, &flags);
3604 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3605 amdgpu_parse_cg_state(m, flags);
3606 seq_printf(m, "\n");
3609 pm_runtime_mark_last_busy(dev->dev);
3610 pm_runtime_put_autosuspend(dev->dev);
3615 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3618 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3620 * Reads debug memory region allocated to PMFW
3622 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3623 size_t size, loff_t *pos)
3625 struct amdgpu_device *adev = file_inode(f)->i_private;
3626 size_t smu_prv_buf_size;
3630 if (amdgpu_in_reset(adev))
3632 if (adev->in_suspend && !adev->in_runpm)
3635 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3639 if (!smu_prv_buf || !smu_prv_buf_size)
3642 return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3646 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3647 .owner = THIS_MODULE,
3648 .open = simple_open,
3649 .read = amdgpu_pm_prv_buffer_read,
3650 .llseek = default_llseek,
3655 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3657 #if defined(CONFIG_DEBUG_FS)
3658 struct drm_minor *minor = adev_to_drm(adev)->primary;
3659 struct dentry *root = minor->debugfs_root;
3661 if (!adev->pm.dpm_enabled)
3664 debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3665 &amdgpu_debugfs_pm_info_fops);
3667 if (adev->pm.smu_prv_buffer_size > 0)
3668 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3670 &amdgpu_debugfs_pm_prv_buffer_fops,
3671 adev->pm.smu_prv_buffer_size);
3673 amdgpu_dpm_stb_debug_fs_init(adev);