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1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Rafał Miłecki <[email protected]>
23  *          Alex Deucher <[email protected]>
24  */
25
26 #include "amdgpu.h"
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "atom.h"
31 #include <linux/pci.h>
32 #include <linux/hwmon.h>
33 #include <linux/hwmon-sysfs.h>
34 #include <linux/nospec.h>
35 #include <linux/pm_runtime.h>
36 #include <asm/processor.h>
37
38 static const struct hwmon_temp_label {
39         enum PP_HWMON_TEMP channel;
40         const char *label;
41 } temp_label[] = {
42         {PP_TEMP_EDGE, "edge"},
43         {PP_TEMP_JUNCTION, "junction"},
44         {PP_TEMP_MEM, "mem"},
45 };
46
47 const char * const amdgpu_pp_profile_name[] = {
48         "BOOTUP_DEFAULT",
49         "3D_FULL_SCREEN",
50         "POWER_SAVING",
51         "VIDEO",
52         "VR",
53         "COMPUTE",
54         "CUSTOM",
55         "WINDOW_3D",
56         "CAPPED",
57         "UNCAPPED",
58 };
59
60 /**
61  * DOC: power_dpm_state
62  *
63  * The power_dpm_state file is a legacy interface and is only provided for
64  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
65  * certain power related parameters.  The file power_dpm_state is used for this.
66  * It accepts the following arguments:
67  *
68  * - battery
69  *
70  * - balanced
71  *
72  * - performance
73  *
74  * battery
75  *
76  * On older GPUs, the vbios provided a special power state for battery
77  * operation.  Selecting battery switched to this state.  This is no
78  * longer provided on newer GPUs so the option does nothing in that case.
79  *
80  * balanced
81  *
82  * On older GPUs, the vbios provided a special power state for balanced
83  * operation.  Selecting balanced switched to this state.  This is no
84  * longer provided on newer GPUs so the option does nothing in that case.
85  *
86  * performance
87  *
88  * On older GPUs, the vbios provided a special power state for performance
89  * operation.  Selecting performance switched to this state.  This is no
90  * longer provided on newer GPUs so the option does nothing in that case.
91  *
92  */
93
94 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
95                                           struct device_attribute *attr,
96                                           char *buf)
97 {
98         struct drm_device *ddev = dev_get_drvdata(dev);
99         struct amdgpu_device *adev = drm_to_adev(ddev);
100         enum amd_pm_state_type pm;
101         int ret;
102
103         if (amdgpu_in_reset(adev))
104                 return -EPERM;
105         if (adev->in_suspend && !adev->in_runpm)
106                 return -EPERM;
107
108         ret = pm_runtime_get_sync(ddev->dev);
109         if (ret < 0) {
110                 pm_runtime_put_autosuspend(ddev->dev);
111                 return ret;
112         }
113
114         amdgpu_dpm_get_current_power_state(adev, &pm);
115
116         pm_runtime_mark_last_busy(ddev->dev);
117         pm_runtime_put_autosuspend(ddev->dev);
118
119         return sysfs_emit(buf, "%s\n",
120                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
121                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
122 }
123
124 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
125                                           struct device_attribute *attr,
126                                           const char *buf,
127                                           size_t count)
128 {
129         struct drm_device *ddev = dev_get_drvdata(dev);
130         struct amdgpu_device *adev = drm_to_adev(ddev);
131         enum amd_pm_state_type  state;
132         int ret;
133
134         if (amdgpu_in_reset(adev))
135                 return -EPERM;
136         if (adev->in_suspend && !adev->in_runpm)
137                 return -EPERM;
138
139         if (strncmp("battery", buf, strlen("battery")) == 0)
140                 state = POWER_STATE_TYPE_BATTERY;
141         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
142                 state = POWER_STATE_TYPE_BALANCED;
143         else if (strncmp("performance", buf, strlen("performance")) == 0)
144                 state = POWER_STATE_TYPE_PERFORMANCE;
145         else
146                 return -EINVAL;
147
148         ret = pm_runtime_get_sync(ddev->dev);
149         if (ret < 0) {
150                 pm_runtime_put_autosuspend(ddev->dev);
151                 return ret;
152         }
153
154         amdgpu_dpm_set_power_state(adev, state);
155
156         pm_runtime_mark_last_busy(ddev->dev);
157         pm_runtime_put_autosuspend(ddev->dev);
158
159         return count;
160 }
161
162
163 /**
164  * DOC: power_dpm_force_performance_level
165  *
166  * The amdgpu driver provides a sysfs API for adjusting certain power
167  * related parameters.  The file power_dpm_force_performance_level is
168  * used for this.  It accepts the following arguments:
169  *
170  * - auto
171  *
172  * - low
173  *
174  * - high
175  *
176  * - manual
177  *
178  * - profile_standard
179  *
180  * - profile_min_sclk
181  *
182  * - profile_min_mclk
183  *
184  * - profile_peak
185  *
186  * auto
187  *
188  * When auto is selected, the driver will attempt to dynamically select
189  * the optimal power profile for current conditions in the driver.
190  *
191  * low
192  *
193  * When low is selected, the clocks are forced to the lowest power state.
194  *
195  * high
196  *
197  * When high is selected, the clocks are forced to the highest power state.
198  *
199  * manual
200  *
201  * When manual is selected, the user can manually adjust which power states
202  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
203  * and pp_dpm_pcie files and adjust the power state transition heuristics
204  * via the pp_power_profile_mode sysfs file.
205  *
206  * profile_standard
207  * profile_min_sclk
208  * profile_min_mclk
209  * profile_peak
210  *
211  * When the profiling modes are selected, clock and power gating are
212  * disabled and the clocks are set for different profiling cases. This
213  * mode is recommended for profiling specific work loads where you do
214  * not want clock or power gating for clock fluctuation to interfere
215  * with your results. profile_standard sets the clocks to a fixed clock
216  * level which varies from asic to asic.  profile_min_sclk forces the sclk
217  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
218  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
219  *
220  */
221
222 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
223                                                             struct device_attribute *attr,
224                                                             char *buf)
225 {
226         struct drm_device *ddev = dev_get_drvdata(dev);
227         struct amdgpu_device *adev = drm_to_adev(ddev);
228         enum amd_dpm_forced_level level = 0xff;
229         int ret;
230
231         if (amdgpu_in_reset(adev))
232                 return -EPERM;
233         if (adev->in_suspend && !adev->in_runpm)
234                 return -EPERM;
235
236         ret = pm_runtime_get_sync(ddev->dev);
237         if (ret < 0) {
238                 pm_runtime_put_autosuspend(ddev->dev);
239                 return ret;
240         }
241
242         level = amdgpu_dpm_get_performance_level(adev);
243
244         pm_runtime_mark_last_busy(ddev->dev);
245         pm_runtime_put_autosuspend(ddev->dev);
246
247         return sysfs_emit(buf, "%s\n",
248                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
249                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
250                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
251                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
252                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
253                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
254                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
255                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
256                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
257                           "unknown");
258 }
259
260 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
261                                                             struct device_attribute *attr,
262                                                             const char *buf,
263                                                             size_t count)
264 {
265         struct drm_device *ddev = dev_get_drvdata(dev);
266         struct amdgpu_device *adev = drm_to_adev(ddev);
267         enum amd_dpm_forced_level level;
268         int ret = 0;
269
270         if (amdgpu_in_reset(adev))
271                 return -EPERM;
272         if (adev->in_suspend && !adev->in_runpm)
273                 return -EPERM;
274
275         if (strncmp("low", buf, strlen("low")) == 0) {
276                 level = AMD_DPM_FORCED_LEVEL_LOW;
277         } else if (strncmp("high", buf, strlen("high")) == 0) {
278                 level = AMD_DPM_FORCED_LEVEL_HIGH;
279         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
280                 level = AMD_DPM_FORCED_LEVEL_AUTO;
281         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
282                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
283         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
284                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
285         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
286                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
287         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
288                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
289         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
290                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
291         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
292                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
293         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
294                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
295         }  else {
296                 return -EINVAL;
297         }
298
299         ret = pm_runtime_get_sync(ddev->dev);
300         if (ret < 0) {
301                 pm_runtime_put_autosuspend(ddev->dev);
302                 return ret;
303         }
304
305         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
306         if (amdgpu_dpm_force_performance_level(adev, level)) {
307                 pm_runtime_mark_last_busy(ddev->dev);
308                 pm_runtime_put_autosuspend(ddev->dev);
309                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
310                 return -EINVAL;
311         }
312         /* override whatever a user ctx may have set */
313         adev->pm.stable_pstate_ctx = NULL;
314         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
315
316         pm_runtime_mark_last_busy(ddev->dev);
317         pm_runtime_put_autosuspend(ddev->dev);
318
319         return count;
320 }
321
322 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
323                 struct device_attribute *attr,
324                 char *buf)
325 {
326         struct drm_device *ddev = dev_get_drvdata(dev);
327         struct amdgpu_device *adev = drm_to_adev(ddev);
328         struct pp_states_info data;
329         uint32_t i;
330         int buf_len, ret;
331
332         if (amdgpu_in_reset(adev))
333                 return -EPERM;
334         if (adev->in_suspend && !adev->in_runpm)
335                 return -EPERM;
336
337         ret = pm_runtime_get_sync(ddev->dev);
338         if (ret < 0) {
339                 pm_runtime_put_autosuspend(ddev->dev);
340                 return ret;
341         }
342
343         if (amdgpu_dpm_get_pp_num_states(adev, &data))
344                 memset(&data, 0, sizeof(data));
345
346         pm_runtime_mark_last_busy(ddev->dev);
347         pm_runtime_put_autosuspend(ddev->dev);
348
349         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
350         for (i = 0; i < data.nums; i++)
351                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
352                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
353                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
354                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
355                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
356
357         return buf_len;
358 }
359
360 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
361                 struct device_attribute *attr,
362                 char *buf)
363 {
364         struct drm_device *ddev = dev_get_drvdata(dev);
365         struct amdgpu_device *adev = drm_to_adev(ddev);
366         struct pp_states_info data = {0};
367         enum amd_pm_state_type pm = 0;
368         int i = 0, ret = 0;
369
370         if (amdgpu_in_reset(adev))
371                 return -EPERM;
372         if (adev->in_suspend && !adev->in_runpm)
373                 return -EPERM;
374
375         ret = pm_runtime_get_sync(ddev->dev);
376         if (ret < 0) {
377                 pm_runtime_put_autosuspend(ddev->dev);
378                 return ret;
379         }
380
381         amdgpu_dpm_get_current_power_state(adev, &pm);
382
383         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
384
385         pm_runtime_mark_last_busy(ddev->dev);
386         pm_runtime_put_autosuspend(ddev->dev);
387
388         if (ret)
389                 return ret;
390
391         for (i = 0; i < data.nums; i++) {
392                 if (pm == data.states[i])
393                         break;
394         }
395
396         if (i == data.nums)
397                 i = -EINVAL;
398
399         return sysfs_emit(buf, "%d\n", i);
400 }
401
402 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
403                 struct device_attribute *attr,
404                 char *buf)
405 {
406         struct drm_device *ddev = dev_get_drvdata(dev);
407         struct amdgpu_device *adev = drm_to_adev(ddev);
408
409         if (amdgpu_in_reset(adev))
410                 return -EPERM;
411         if (adev->in_suspend && !adev->in_runpm)
412                 return -EPERM;
413
414         if (adev->pm.pp_force_state_enabled)
415                 return amdgpu_get_pp_cur_state(dev, attr, buf);
416         else
417                 return sysfs_emit(buf, "\n");
418 }
419
420 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
421                 struct device_attribute *attr,
422                 const char *buf,
423                 size_t count)
424 {
425         struct drm_device *ddev = dev_get_drvdata(dev);
426         struct amdgpu_device *adev = drm_to_adev(ddev);
427         enum amd_pm_state_type state = 0;
428         struct pp_states_info data;
429         unsigned long idx;
430         int ret;
431
432         if (amdgpu_in_reset(adev))
433                 return -EPERM;
434         if (adev->in_suspend && !adev->in_runpm)
435                 return -EPERM;
436
437         adev->pm.pp_force_state_enabled = false;
438
439         if (strlen(buf) == 1)
440                 return count;
441
442         ret = kstrtoul(buf, 0, &idx);
443         if (ret || idx >= ARRAY_SIZE(data.states))
444                 return -EINVAL;
445
446         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
447
448         ret = pm_runtime_get_sync(ddev->dev);
449         if (ret < 0) {
450                 pm_runtime_put_autosuspend(ddev->dev);
451                 return ret;
452         }
453
454         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
455         if (ret)
456                 goto err_out;
457
458         state = data.states[idx];
459
460         /* only set user selected power states */
461         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
462             state != POWER_STATE_TYPE_DEFAULT) {
463                 ret = amdgpu_dpm_dispatch_task(adev,
464                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
465                 if (ret)
466                         goto err_out;
467
468                 adev->pm.pp_force_state_enabled = true;
469         }
470
471         pm_runtime_mark_last_busy(ddev->dev);
472         pm_runtime_put_autosuspend(ddev->dev);
473
474         return count;
475
476 err_out:
477         pm_runtime_mark_last_busy(ddev->dev);
478         pm_runtime_put_autosuspend(ddev->dev);
479         return ret;
480 }
481
482 /**
483  * DOC: pp_table
484  *
485  * The amdgpu driver provides a sysfs API for uploading new powerplay
486  * tables.  The file pp_table is used for this.  Reading the file
487  * will dump the current power play table.  Writing to the file
488  * will attempt to upload a new powerplay table and re-initialize
489  * powerplay using that new table.
490  *
491  */
492
493 static ssize_t amdgpu_get_pp_table(struct device *dev,
494                 struct device_attribute *attr,
495                 char *buf)
496 {
497         struct drm_device *ddev = dev_get_drvdata(dev);
498         struct amdgpu_device *adev = drm_to_adev(ddev);
499         char *table = NULL;
500         int size, ret;
501
502         if (amdgpu_in_reset(adev))
503                 return -EPERM;
504         if (adev->in_suspend && !adev->in_runpm)
505                 return -EPERM;
506
507         ret = pm_runtime_get_sync(ddev->dev);
508         if (ret < 0) {
509                 pm_runtime_put_autosuspend(ddev->dev);
510                 return ret;
511         }
512
513         size = amdgpu_dpm_get_pp_table(adev, &table);
514
515         pm_runtime_mark_last_busy(ddev->dev);
516         pm_runtime_put_autosuspend(ddev->dev);
517
518         if (size <= 0)
519                 return size;
520
521         if (size >= PAGE_SIZE)
522                 size = PAGE_SIZE - 1;
523
524         memcpy(buf, table, size);
525
526         return size;
527 }
528
529 static ssize_t amdgpu_set_pp_table(struct device *dev,
530                 struct device_attribute *attr,
531                 const char *buf,
532                 size_t count)
533 {
534         struct drm_device *ddev = dev_get_drvdata(dev);
535         struct amdgpu_device *adev = drm_to_adev(ddev);
536         int ret = 0;
537
538         if (amdgpu_in_reset(adev))
539                 return -EPERM;
540         if (adev->in_suspend && !adev->in_runpm)
541                 return -EPERM;
542
543         ret = pm_runtime_get_sync(ddev->dev);
544         if (ret < 0) {
545                 pm_runtime_put_autosuspend(ddev->dev);
546                 return ret;
547         }
548
549         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
550
551         pm_runtime_mark_last_busy(ddev->dev);
552         pm_runtime_put_autosuspend(ddev->dev);
553
554         if (ret)
555                 return ret;
556
557         return count;
558 }
559
560 /**
561  * DOC: pp_od_clk_voltage
562  *
563  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
564  * in each power level within a power state.  The pp_od_clk_voltage is used for
565  * this.
566  *
567  * Note that the actual memory controller clock rate are exposed, not
568  * the effective memory clock of the DRAMs. To translate it, use the
569  * following formula:
570  *
571  * Clock conversion (Mhz):
572  *
573  * HBM: effective_memory_clock = memory_controller_clock * 1
574  *
575  * G5: effective_memory_clock = memory_controller_clock * 1
576  *
577  * G6: effective_memory_clock = memory_controller_clock * 2
578  *
579  * DRAM data rate (MT/s):
580  *
581  * HBM: effective_memory_clock * 2 = data_rate
582  *
583  * G5: effective_memory_clock * 4 = data_rate
584  *
585  * G6: effective_memory_clock * 8 = data_rate
586  *
587  * Bandwidth (MB/s):
588  *
589  * data_rate * vram_bit_width / 8 = memory_bandwidth
590  *
591  * Some examples:
592  *
593  * G5 on RX460:
594  *
595  * memory_controller_clock = 1750 Mhz
596  *
597  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
598  *
599  * data rate = 1750 * 4 = 7000 MT/s
600  *
601  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
602  *
603  * G6 on RX5700:
604  *
605  * memory_controller_clock = 875 Mhz
606  *
607  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
608  *
609  * data rate = 1750 * 8 = 14000 MT/s
610  *
611  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
612  *
613  * < For Vega10 and previous ASICs >
614  *
615  * Reading the file will display:
616  *
617  * - a list of engine clock levels and voltages labeled OD_SCLK
618  *
619  * - a list of memory clock levels and voltages labeled OD_MCLK
620  *
621  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
622  *
623  * To manually adjust these settings, first select manual using
624  * power_dpm_force_performance_level. Enter a new value for each
625  * level by writing a string that contains "s/m level clock voltage" to
626  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
627  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
628  * 810 mV.  When you have edited all of the states as needed, write
629  * "c" (commit) to the file to commit your changes.  If you want to reset to the
630  * default power levels, write "r" (reset) to the file to reset them.
631  *
632  *
633  * < For Vega20 and newer ASICs >
634  *
635  * Reading the file will display:
636  *
637  * - minimum and maximum engine clock labeled OD_SCLK
638  *
639  * - minimum(not available for Vega20 and Navi1x) and maximum memory
640  *   clock labeled OD_MCLK
641  *
642  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
643  *   They can be used to calibrate the sclk voltage curve. This is
644  *   available for Vega20 and NV1X.
645  *
646  * - voltage offset(in mV) applied on target voltage calculation.
647  *   This is available for Sienna Cichlid, Navy Flounder, Dimgrey
648  *   Cavefish and some later SMU13 ASICs. For these ASICs, the target
649  *   voltage calculation can be illustrated by "voltage = voltage
650  *   calculated from v/f curve + overdrive vddgfx offset"
651  *
652  * - a list of valid ranges for sclk, mclk, voltage curve points
653  *   or voltage offset labeled OD_RANGE
654  *
655  * < For APUs >
656  *
657  * Reading the file will display:
658  *
659  * - minimum and maximum engine clock labeled OD_SCLK
660  *
661  * - a list of valid ranges for sclk labeled OD_RANGE
662  *
663  * < For VanGogh >
664  *
665  * Reading the file will display:
666  *
667  * - minimum and maximum engine clock labeled OD_SCLK
668  * - minimum and maximum core clocks labeled OD_CCLK
669  *
670  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
671  *
672  * To manually adjust these settings:
673  *
674  * - First select manual using power_dpm_force_performance_level
675  *
676  * - For clock frequency setting, enter a new value by writing a
677  *   string that contains "s/m index clock" to the file. The index
678  *   should be 0 if to set minimum clock. And 1 if to set maximum
679  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
680  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
681  *   clocks on VanGogh, the string contains "p core index clock".
682  *   E.g., "p 2 0 800" would set the minimum core clock on core
683  *   2 to 800Mhz.
684  *
685  *   For sclk voltage curve supported by Vega20 and NV1X, enter the new
686  *   values by writing a string that contains "vc point clock voltage"
687  *   to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
688  *   600" will update point1 with clock set as 300Mhz and voltage as 600mV.
689  *   "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
690  *   voltage 1000mV.
691  *
692  *   For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
693  *   Cavefish and some later SMU13 ASICs, enter the new value by writing a
694  *   string that contains "vo offset". E.g., "vo -10" will update the extra
695  *   voltage offset applied to the whole v/f curve line as -10mv.
696  *
697  * - When you have edited all of the states as needed, write "c" (commit)
698  *   to the file to commit your changes
699  *
700  * - If you want to reset to the default power levels, write "r" (reset)
701  *   to the file to reset them
702  *
703  */
704
705 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
706                 struct device_attribute *attr,
707                 const char *buf,
708                 size_t count)
709 {
710         struct drm_device *ddev = dev_get_drvdata(dev);
711         struct amdgpu_device *adev = drm_to_adev(ddev);
712         int ret;
713         uint32_t parameter_size = 0;
714         long parameter[64];
715         char buf_cpy[128];
716         char *tmp_str;
717         char *sub_str;
718         const char delimiter[3] = {' ', '\n', '\0'};
719         uint32_t type;
720
721         if (amdgpu_in_reset(adev))
722                 return -EPERM;
723         if (adev->in_suspend && !adev->in_runpm)
724                 return -EPERM;
725
726         if (count > 127)
727                 return -EINVAL;
728
729         if (*buf == 's')
730                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
731         else if (*buf == 'p')
732                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
733         else if (*buf == 'm')
734                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
735         else if (*buf == 'r')
736                 type = PP_OD_RESTORE_DEFAULT_TABLE;
737         else if (*buf == 'c')
738                 type = PP_OD_COMMIT_DPM_TABLE;
739         else if (!strncmp(buf, "vc", 2))
740                 type = PP_OD_EDIT_VDDC_CURVE;
741         else if (!strncmp(buf, "vo", 2))
742                 type = PP_OD_EDIT_VDDGFX_OFFSET;
743         else
744                 return -EINVAL;
745
746         memcpy(buf_cpy, buf, count+1);
747
748         tmp_str = buf_cpy;
749
750         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
751              (type == PP_OD_EDIT_VDDGFX_OFFSET))
752                 tmp_str++;
753         while (isspace(*++tmp_str));
754
755         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
756                 if (strlen(sub_str) == 0)
757                         continue;
758                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
759                 if (ret)
760                         return -EINVAL;
761                 parameter_size++;
762
763                 while (isspace(*tmp_str))
764                         tmp_str++;
765         }
766
767         ret = pm_runtime_get_sync(ddev->dev);
768         if (ret < 0) {
769                 pm_runtime_put_autosuspend(ddev->dev);
770                 return ret;
771         }
772
773         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
774                                               type,
775                                               parameter,
776                                               parameter_size))
777                 goto err_out;
778
779         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
780                                           parameter, parameter_size))
781                 goto err_out;
782
783         if (type == PP_OD_COMMIT_DPM_TABLE) {
784                 if (amdgpu_dpm_dispatch_task(adev,
785                                              AMD_PP_TASK_READJUST_POWER_STATE,
786                                              NULL))
787                         goto err_out;
788         }
789
790         pm_runtime_mark_last_busy(ddev->dev);
791         pm_runtime_put_autosuspend(ddev->dev);
792
793         return count;
794
795 err_out:
796         pm_runtime_mark_last_busy(ddev->dev);
797         pm_runtime_put_autosuspend(ddev->dev);
798         return -EINVAL;
799 }
800
801 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
802                 struct device_attribute *attr,
803                 char *buf)
804 {
805         struct drm_device *ddev = dev_get_drvdata(dev);
806         struct amdgpu_device *adev = drm_to_adev(ddev);
807         int size = 0;
808         int ret;
809         enum pp_clock_type od_clocks[6] = {
810                 OD_SCLK,
811                 OD_MCLK,
812                 OD_VDDC_CURVE,
813                 OD_RANGE,
814                 OD_VDDGFX_OFFSET,
815                 OD_CCLK,
816         };
817         uint clk_index;
818
819         if (amdgpu_in_reset(adev))
820                 return -EPERM;
821         if (adev->in_suspend && !adev->in_runpm)
822                 return -EPERM;
823
824         ret = pm_runtime_get_sync(ddev->dev);
825         if (ret < 0) {
826                 pm_runtime_put_autosuspend(ddev->dev);
827                 return ret;
828         }
829
830         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
831                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
832                 if (ret)
833                         break;
834         }
835         if (ret == -ENOENT) {
836                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
837                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
838                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
839                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
840                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
841                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
842         }
843
844         if (size == 0)
845                 size = sysfs_emit(buf, "\n");
846
847         pm_runtime_mark_last_busy(ddev->dev);
848         pm_runtime_put_autosuspend(ddev->dev);
849
850         return size;
851 }
852
853 /**
854  * DOC: pp_features
855  *
856  * The amdgpu driver provides a sysfs API for adjusting what powerplay
857  * features to be enabled. The file pp_features is used for this. And
858  * this is only available for Vega10 and later dGPUs.
859  *
860  * Reading back the file will show you the followings:
861  * - Current ppfeature masks
862  * - List of the all supported powerplay features with their naming,
863  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
864  *
865  * To manually enable or disable a specific feature, just set or clear
866  * the corresponding bit from original ppfeature masks and input the
867  * new ppfeature masks.
868  */
869 static ssize_t amdgpu_set_pp_features(struct device *dev,
870                                       struct device_attribute *attr,
871                                       const char *buf,
872                                       size_t count)
873 {
874         struct drm_device *ddev = dev_get_drvdata(dev);
875         struct amdgpu_device *adev = drm_to_adev(ddev);
876         uint64_t featuremask;
877         int ret;
878
879         if (amdgpu_in_reset(adev))
880                 return -EPERM;
881         if (adev->in_suspend && !adev->in_runpm)
882                 return -EPERM;
883
884         ret = kstrtou64(buf, 0, &featuremask);
885         if (ret)
886                 return -EINVAL;
887
888         ret = pm_runtime_get_sync(ddev->dev);
889         if (ret < 0) {
890                 pm_runtime_put_autosuspend(ddev->dev);
891                 return ret;
892         }
893
894         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
895
896         pm_runtime_mark_last_busy(ddev->dev);
897         pm_runtime_put_autosuspend(ddev->dev);
898
899         if (ret)
900                 return -EINVAL;
901
902         return count;
903 }
904
905 static ssize_t amdgpu_get_pp_features(struct device *dev,
906                                       struct device_attribute *attr,
907                                       char *buf)
908 {
909         struct drm_device *ddev = dev_get_drvdata(dev);
910         struct amdgpu_device *adev = drm_to_adev(ddev);
911         ssize_t size;
912         int ret;
913
914         if (amdgpu_in_reset(adev))
915                 return -EPERM;
916         if (adev->in_suspend && !adev->in_runpm)
917                 return -EPERM;
918
919         ret = pm_runtime_get_sync(ddev->dev);
920         if (ret < 0) {
921                 pm_runtime_put_autosuspend(ddev->dev);
922                 return ret;
923         }
924
925         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
926         if (size <= 0)
927                 size = sysfs_emit(buf, "\n");
928
929         pm_runtime_mark_last_busy(ddev->dev);
930         pm_runtime_put_autosuspend(ddev->dev);
931
932         return size;
933 }
934
935 /**
936  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
937  *
938  * The amdgpu driver provides a sysfs API for adjusting what power levels
939  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
940  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
941  * this.
942  *
943  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
944  * Vega10 and later ASICs.
945  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
946  *
947  * Reading back the files will show you the available power levels within
948  * the power state and the clock information for those levels.
949  *
950  * To manually adjust these states, first select manual using
951  * power_dpm_force_performance_level.
952  * Secondly, enter a new value for each level by inputing a string that
953  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
954  * E.g.,
955  *
956  * .. code-block:: bash
957  *
958  *      echo "4 5 6" > pp_dpm_sclk
959  *
960  * will enable sclk levels 4, 5, and 6.
961  *
962  * NOTE: change to the dcefclk max dpm level is not supported now
963  */
964
965 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
966                 enum pp_clock_type type,
967                 char *buf)
968 {
969         struct drm_device *ddev = dev_get_drvdata(dev);
970         struct amdgpu_device *adev = drm_to_adev(ddev);
971         int size = 0;
972         int ret = 0;
973
974         if (amdgpu_in_reset(adev))
975                 return -EPERM;
976         if (adev->in_suspend && !adev->in_runpm)
977                 return -EPERM;
978
979         ret = pm_runtime_get_sync(ddev->dev);
980         if (ret < 0) {
981                 pm_runtime_put_autosuspend(ddev->dev);
982                 return ret;
983         }
984
985         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
986         if (ret == -ENOENT)
987                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
988
989         if (size == 0)
990                 size = sysfs_emit(buf, "\n");
991
992         pm_runtime_mark_last_busy(ddev->dev);
993         pm_runtime_put_autosuspend(ddev->dev);
994
995         return size;
996 }
997
998 /*
999  * Worst case: 32 bits individually specified, in octal at 12 characters
1000  * per line (+1 for \n).
1001  */
1002 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1003
1004 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1005 {
1006         int ret;
1007         unsigned long level;
1008         char *sub_str = NULL;
1009         char *tmp;
1010         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1011         const char delimiter[3] = {' ', '\n', '\0'};
1012         size_t bytes;
1013
1014         *mask = 0;
1015
1016         bytes = min(count, sizeof(buf_cpy) - 1);
1017         memcpy(buf_cpy, buf, bytes);
1018         buf_cpy[bytes] = '\0';
1019         tmp = buf_cpy;
1020         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1021                 if (strlen(sub_str)) {
1022                         ret = kstrtoul(sub_str, 0, &level);
1023                         if (ret || level > 31)
1024                                 return -EINVAL;
1025                         *mask |= 1 << level;
1026                 } else
1027                         break;
1028         }
1029
1030         return 0;
1031 }
1032
1033 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1034                 enum pp_clock_type type,
1035                 const char *buf,
1036                 size_t count)
1037 {
1038         struct drm_device *ddev = dev_get_drvdata(dev);
1039         struct amdgpu_device *adev = drm_to_adev(ddev);
1040         int ret;
1041         uint32_t mask = 0;
1042
1043         if (amdgpu_in_reset(adev))
1044                 return -EPERM;
1045         if (adev->in_suspend && !adev->in_runpm)
1046                 return -EPERM;
1047
1048         ret = amdgpu_read_mask(buf, count, &mask);
1049         if (ret)
1050                 return ret;
1051
1052         ret = pm_runtime_get_sync(ddev->dev);
1053         if (ret < 0) {
1054                 pm_runtime_put_autosuspend(ddev->dev);
1055                 return ret;
1056         }
1057
1058         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1059
1060         pm_runtime_mark_last_busy(ddev->dev);
1061         pm_runtime_put_autosuspend(ddev->dev);
1062
1063         if (ret)
1064                 return -EINVAL;
1065
1066         return count;
1067 }
1068
1069 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1070                 struct device_attribute *attr,
1071                 char *buf)
1072 {
1073         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1074 }
1075
1076 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1077                 struct device_attribute *attr,
1078                 const char *buf,
1079                 size_t count)
1080 {
1081         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1082 }
1083
1084 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1085                 struct device_attribute *attr,
1086                 char *buf)
1087 {
1088         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1089 }
1090
1091 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1092                 struct device_attribute *attr,
1093                 const char *buf,
1094                 size_t count)
1095 {
1096         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1097 }
1098
1099 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1100                 struct device_attribute *attr,
1101                 char *buf)
1102 {
1103         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1104 }
1105
1106 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1107                 struct device_attribute *attr,
1108                 const char *buf,
1109                 size_t count)
1110 {
1111         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1112 }
1113
1114 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1115                 struct device_attribute *attr,
1116                 char *buf)
1117 {
1118         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1119 }
1120
1121 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1122                 struct device_attribute *attr,
1123                 const char *buf,
1124                 size_t count)
1125 {
1126         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1127 }
1128
1129 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1130                 struct device_attribute *attr,
1131                 char *buf)
1132 {
1133         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1134 }
1135
1136 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1137                 struct device_attribute *attr,
1138                 const char *buf,
1139                 size_t count)
1140 {
1141         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1142 }
1143
1144 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1145                 struct device_attribute *attr,
1146                 char *buf)
1147 {
1148         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1149 }
1150
1151 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1152                 struct device_attribute *attr,
1153                 const char *buf,
1154                 size_t count)
1155 {
1156         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1157 }
1158
1159 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1160                 struct device_attribute *attr,
1161                 char *buf)
1162 {
1163         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1164 }
1165
1166 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1167                 struct device_attribute *attr,
1168                 const char *buf,
1169                 size_t count)
1170 {
1171         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1172 }
1173
1174 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1175                 struct device_attribute *attr,
1176                 char *buf)
1177 {
1178         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1179 }
1180
1181 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1182                 struct device_attribute *attr,
1183                 const char *buf,
1184                 size_t count)
1185 {
1186         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1187 }
1188
1189 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1190                 struct device_attribute *attr,
1191                 char *buf)
1192 {
1193         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1194 }
1195
1196 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1197                 struct device_attribute *attr,
1198                 const char *buf,
1199                 size_t count)
1200 {
1201         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1202 }
1203
1204 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1205                 struct device_attribute *attr,
1206                 char *buf)
1207 {
1208         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1209 }
1210
1211 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1212                 struct device_attribute *attr,
1213                 const char *buf,
1214                 size_t count)
1215 {
1216         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1217 }
1218
1219 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1220                 struct device_attribute *attr,
1221                 char *buf)
1222 {
1223         struct drm_device *ddev = dev_get_drvdata(dev);
1224         struct amdgpu_device *adev = drm_to_adev(ddev);
1225         uint32_t value = 0;
1226         int ret;
1227
1228         if (amdgpu_in_reset(adev))
1229                 return -EPERM;
1230         if (adev->in_suspend && !adev->in_runpm)
1231                 return -EPERM;
1232
1233         ret = pm_runtime_get_sync(ddev->dev);
1234         if (ret < 0) {
1235                 pm_runtime_put_autosuspend(ddev->dev);
1236                 return ret;
1237         }
1238
1239         value = amdgpu_dpm_get_sclk_od(adev);
1240
1241         pm_runtime_mark_last_busy(ddev->dev);
1242         pm_runtime_put_autosuspend(ddev->dev);
1243
1244         return sysfs_emit(buf, "%d\n", value);
1245 }
1246
1247 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1248                 struct device_attribute *attr,
1249                 const char *buf,
1250                 size_t count)
1251 {
1252         struct drm_device *ddev = dev_get_drvdata(dev);
1253         struct amdgpu_device *adev = drm_to_adev(ddev);
1254         int ret;
1255         long int value;
1256
1257         if (amdgpu_in_reset(adev))
1258                 return -EPERM;
1259         if (adev->in_suspend && !adev->in_runpm)
1260                 return -EPERM;
1261
1262         ret = kstrtol(buf, 0, &value);
1263
1264         if (ret)
1265                 return -EINVAL;
1266
1267         ret = pm_runtime_get_sync(ddev->dev);
1268         if (ret < 0) {
1269                 pm_runtime_put_autosuspend(ddev->dev);
1270                 return ret;
1271         }
1272
1273         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1274
1275         pm_runtime_mark_last_busy(ddev->dev);
1276         pm_runtime_put_autosuspend(ddev->dev);
1277
1278         return count;
1279 }
1280
1281 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1282                 struct device_attribute *attr,
1283                 char *buf)
1284 {
1285         struct drm_device *ddev = dev_get_drvdata(dev);
1286         struct amdgpu_device *adev = drm_to_adev(ddev);
1287         uint32_t value = 0;
1288         int ret;
1289
1290         if (amdgpu_in_reset(adev))
1291                 return -EPERM;
1292         if (adev->in_suspend && !adev->in_runpm)
1293                 return -EPERM;
1294
1295         ret = pm_runtime_get_sync(ddev->dev);
1296         if (ret < 0) {
1297                 pm_runtime_put_autosuspend(ddev->dev);
1298                 return ret;
1299         }
1300
1301         value = amdgpu_dpm_get_mclk_od(adev);
1302
1303         pm_runtime_mark_last_busy(ddev->dev);
1304         pm_runtime_put_autosuspend(ddev->dev);
1305
1306         return sysfs_emit(buf, "%d\n", value);
1307 }
1308
1309 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1310                 struct device_attribute *attr,
1311                 const char *buf,
1312                 size_t count)
1313 {
1314         struct drm_device *ddev = dev_get_drvdata(dev);
1315         struct amdgpu_device *adev = drm_to_adev(ddev);
1316         int ret;
1317         long int value;
1318
1319         if (amdgpu_in_reset(adev))
1320                 return -EPERM;
1321         if (adev->in_suspend && !adev->in_runpm)
1322                 return -EPERM;
1323
1324         ret = kstrtol(buf, 0, &value);
1325
1326         if (ret)
1327                 return -EINVAL;
1328
1329         ret = pm_runtime_get_sync(ddev->dev);
1330         if (ret < 0) {
1331                 pm_runtime_put_autosuspend(ddev->dev);
1332                 return ret;
1333         }
1334
1335         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1336
1337         pm_runtime_mark_last_busy(ddev->dev);
1338         pm_runtime_put_autosuspend(ddev->dev);
1339
1340         return count;
1341 }
1342
1343 /**
1344  * DOC: pp_power_profile_mode
1345  *
1346  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1347  * related to switching between power levels in a power state.  The file
1348  * pp_power_profile_mode is used for this.
1349  *
1350  * Reading this file outputs a list of all of the predefined power profiles
1351  * and the relevant heuristics settings for that profile.
1352  *
1353  * To select a profile or create a custom profile, first select manual using
1354  * power_dpm_force_performance_level.  Writing the number of a predefined
1355  * profile to pp_power_profile_mode will enable those heuristics.  To
1356  * create a custom set of heuristics, write a string of numbers to the file
1357  * starting with the number of the custom profile along with a setting
1358  * for each heuristic parameter.  Due to differences across asic families
1359  * the heuristic parameters vary from family to family.
1360  *
1361  */
1362
1363 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1364                 struct device_attribute *attr,
1365                 char *buf)
1366 {
1367         struct drm_device *ddev = dev_get_drvdata(dev);
1368         struct amdgpu_device *adev = drm_to_adev(ddev);
1369         ssize_t size;
1370         int ret;
1371
1372         if (amdgpu_in_reset(adev))
1373                 return -EPERM;
1374         if (adev->in_suspend && !adev->in_runpm)
1375                 return -EPERM;
1376
1377         ret = pm_runtime_get_sync(ddev->dev);
1378         if (ret < 0) {
1379                 pm_runtime_put_autosuspend(ddev->dev);
1380                 return ret;
1381         }
1382
1383         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1384         if (size <= 0)
1385                 size = sysfs_emit(buf, "\n");
1386
1387         pm_runtime_mark_last_busy(ddev->dev);
1388         pm_runtime_put_autosuspend(ddev->dev);
1389
1390         return size;
1391 }
1392
1393
1394 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1395                 struct device_attribute *attr,
1396                 const char *buf,
1397                 size_t count)
1398 {
1399         int ret;
1400         struct drm_device *ddev = dev_get_drvdata(dev);
1401         struct amdgpu_device *adev = drm_to_adev(ddev);
1402         uint32_t parameter_size = 0;
1403         long parameter[64];
1404         char *sub_str, buf_cpy[128];
1405         char *tmp_str;
1406         uint32_t i = 0;
1407         char tmp[2];
1408         long int profile_mode = 0;
1409         const char delimiter[3] = {' ', '\n', '\0'};
1410
1411         if (amdgpu_in_reset(adev))
1412                 return -EPERM;
1413         if (adev->in_suspend && !adev->in_runpm)
1414                 return -EPERM;
1415
1416         tmp[0] = *(buf);
1417         tmp[1] = '\0';
1418         ret = kstrtol(tmp, 0, &profile_mode);
1419         if (ret)
1420                 return -EINVAL;
1421
1422         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1423                 if (count < 2 || count > 127)
1424                         return -EINVAL;
1425                 while (isspace(*++buf))
1426                         i++;
1427                 memcpy(buf_cpy, buf, count-i);
1428                 tmp_str = buf_cpy;
1429                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1430                         if (strlen(sub_str) == 0)
1431                                 continue;
1432                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1433                         if (ret)
1434                                 return -EINVAL;
1435                         parameter_size++;
1436                         while (isspace(*tmp_str))
1437                                 tmp_str++;
1438                 }
1439         }
1440         parameter[parameter_size] = profile_mode;
1441
1442         ret = pm_runtime_get_sync(ddev->dev);
1443         if (ret < 0) {
1444                 pm_runtime_put_autosuspend(ddev->dev);
1445                 return ret;
1446         }
1447
1448         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1449
1450         pm_runtime_mark_last_busy(ddev->dev);
1451         pm_runtime_put_autosuspend(ddev->dev);
1452
1453         if (!ret)
1454                 return count;
1455
1456         return -EINVAL;
1457 }
1458
1459 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1460                                            enum amd_pp_sensors sensor,
1461                                            void *query)
1462 {
1463         int r, size = sizeof(uint32_t);
1464
1465         if (amdgpu_in_reset(adev))
1466                 return -EPERM;
1467         if (adev->in_suspend && !adev->in_runpm)
1468                 return -EPERM;
1469
1470         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1471         if (r < 0) {
1472                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1473                 return r;
1474         }
1475
1476         /* get the sensor value */
1477         r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1478
1479         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1480         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1481
1482         return r;
1483 }
1484
1485 /**
1486  * DOC: gpu_busy_percent
1487  *
1488  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1489  * is as a percentage.  The file gpu_busy_percent is used for this.
1490  * The SMU firmware computes a percentage of load based on the
1491  * aggregate activity level in the IP cores.
1492  */
1493 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1494                                            struct device_attribute *attr,
1495                                            char *buf)
1496 {
1497         struct drm_device *ddev = dev_get_drvdata(dev);
1498         struct amdgpu_device *adev = drm_to_adev(ddev);
1499         unsigned int value;
1500         int r;
1501
1502         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1503         if (r)
1504                 return r;
1505
1506         return sysfs_emit(buf, "%d\n", value);
1507 }
1508
1509 /**
1510  * DOC: mem_busy_percent
1511  *
1512  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1513  * is as a percentage.  The file mem_busy_percent is used for this.
1514  * The SMU firmware computes a percentage of load based on the
1515  * aggregate activity level in the IP cores.
1516  */
1517 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1518                                            struct device_attribute *attr,
1519                                            char *buf)
1520 {
1521         struct drm_device *ddev = dev_get_drvdata(dev);
1522         struct amdgpu_device *adev = drm_to_adev(ddev);
1523         unsigned int value;
1524         int r;
1525
1526         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1527         if (r)
1528                 return r;
1529
1530         return sysfs_emit(buf, "%d\n", value);
1531 }
1532
1533 /**
1534  * DOC: pcie_bw
1535  *
1536  * The amdgpu driver provides a sysfs API for estimating how much data
1537  * has been received and sent by the GPU in the last second through PCIe.
1538  * The file pcie_bw is used for this.
1539  * The Perf counters count the number of received and sent messages and return
1540  * those values, as well as the maximum payload size of a PCIe packet (mps).
1541  * Note that it is not possible to easily and quickly obtain the size of each
1542  * packet transmitted, so we output the max payload size (mps) to allow for
1543  * quick estimation of the PCIe bandwidth usage
1544  */
1545 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1546                 struct device_attribute *attr,
1547                 char *buf)
1548 {
1549         struct drm_device *ddev = dev_get_drvdata(dev);
1550         struct amdgpu_device *adev = drm_to_adev(ddev);
1551         uint64_t count0 = 0, count1 = 0;
1552         int ret;
1553
1554         if (amdgpu_in_reset(adev))
1555                 return -EPERM;
1556         if (adev->in_suspend && !adev->in_runpm)
1557                 return -EPERM;
1558
1559         if (adev->flags & AMD_IS_APU)
1560                 return -ENODATA;
1561
1562         if (!adev->asic_funcs->get_pcie_usage)
1563                 return -ENODATA;
1564
1565         ret = pm_runtime_get_sync(ddev->dev);
1566         if (ret < 0) {
1567                 pm_runtime_put_autosuspend(ddev->dev);
1568                 return ret;
1569         }
1570
1571         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1572
1573         pm_runtime_mark_last_busy(ddev->dev);
1574         pm_runtime_put_autosuspend(ddev->dev);
1575
1576         return sysfs_emit(buf, "%llu %llu %i\n",
1577                           count0, count1, pcie_get_mps(adev->pdev));
1578 }
1579
1580 /**
1581  * DOC: unique_id
1582  *
1583  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1584  * The file unique_id is used for this.
1585  * This will provide a Unique ID that will persist from machine to machine
1586  *
1587  * NOTE: This will only work for GFX9 and newer. This file will be absent
1588  * on unsupported ASICs (GFX8 and older)
1589  */
1590 static ssize_t amdgpu_get_unique_id(struct device *dev,
1591                 struct device_attribute *attr,
1592                 char *buf)
1593 {
1594         struct drm_device *ddev = dev_get_drvdata(dev);
1595         struct amdgpu_device *adev = drm_to_adev(ddev);
1596
1597         if (amdgpu_in_reset(adev))
1598                 return -EPERM;
1599         if (adev->in_suspend && !adev->in_runpm)
1600                 return -EPERM;
1601
1602         if (adev->unique_id)
1603                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1604
1605         return 0;
1606 }
1607
1608 /**
1609  * DOC: thermal_throttling_logging
1610  *
1611  * Thermal throttling pulls down the clock frequency and thus the performance.
1612  * It's an useful mechanism to protect the chip from overheating. Since it
1613  * impacts performance, the user controls whether it is enabled and if so,
1614  * the log frequency.
1615  *
1616  * Reading back the file shows you the status(enabled or disabled) and
1617  * the interval(in seconds) between each thermal logging.
1618  *
1619  * Writing an integer to the file, sets a new logging interval, in seconds.
1620  * The value should be between 1 and 3600. If the value is less than 1,
1621  * thermal logging is disabled. Values greater than 3600 are ignored.
1622  */
1623 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1624                                                      struct device_attribute *attr,
1625                                                      char *buf)
1626 {
1627         struct drm_device *ddev = dev_get_drvdata(dev);
1628         struct amdgpu_device *adev = drm_to_adev(ddev);
1629
1630         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1631                           adev_to_drm(adev)->unique,
1632                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1633                           adev->throttling_logging_rs.interval / HZ + 1);
1634 }
1635
1636 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1637                                                      struct device_attribute *attr,
1638                                                      const char *buf,
1639                                                      size_t count)
1640 {
1641         struct drm_device *ddev = dev_get_drvdata(dev);
1642         struct amdgpu_device *adev = drm_to_adev(ddev);
1643         long throttling_logging_interval;
1644         unsigned long flags;
1645         int ret = 0;
1646
1647         ret = kstrtol(buf, 0, &throttling_logging_interval);
1648         if (ret)
1649                 return ret;
1650
1651         if (throttling_logging_interval > 3600)
1652                 return -EINVAL;
1653
1654         if (throttling_logging_interval > 0) {
1655                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1656                 /*
1657                  * Reset the ratelimit timer internals.
1658                  * This can effectively restart the timer.
1659                  */
1660                 adev->throttling_logging_rs.interval =
1661                         (throttling_logging_interval - 1) * HZ;
1662                 adev->throttling_logging_rs.begin = 0;
1663                 adev->throttling_logging_rs.printed = 0;
1664                 adev->throttling_logging_rs.missed = 0;
1665                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1666
1667                 atomic_set(&adev->throttling_logging_enabled, 1);
1668         } else {
1669                 atomic_set(&adev->throttling_logging_enabled, 0);
1670         }
1671
1672         return count;
1673 }
1674
1675 /**
1676  * DOC: apu_thermal_cap
1677  *
1678  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1679  * limit temperature in millidegrees Celsius
1680  *
1681  * Reading back the file shows you core limit value
1682  *
1683  * Writing an integer to the file, sets a new thermal limit. The value
1684  * should be between 0 and 100. If the value is less than 0 or greater
1685  * than 100, then the write request will be ignored.
1686  */
1687 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1688                                          struct device_attribute *attr,
1689                                          char *buf)
1690 {
1691         int ret, size;
1692         u32 limit;
1693         struct drm_device *ddev = dev_get_drvdata(dev);
1694         struct amdgpu_device *adev = drm_to_adev(ddev);
1695
1696         ret = pm_runtime_get_sync(ddev->dev);
1697         if (ret < 0) {
1698                 pm_runtime_put_autosuspend(ddev->dev);
1699                 return ret;
1700         }
1701
1702         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1703         if (!ret)
1704                 size = sysfs_emit(buf, "%u\n", limit);
1705         else
1706                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1707
1708         pm_runtime_mark_last_busy(ddev->dev);
1709         pm_runtime_put_autosuspend(ddev->dev);
1710
1711         return size;
1712 }
1713
1714 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1715                                          struct device_attribute *attr,
1716                                          const char *buf,
1717                                          size_t count)
1718 {
1719         int ret;
1720         u32 value;
1721         struct drm_device *ddev = dev_get_drvdata(dev);
1722         struct amdgpu_device *adev = drm_to_adev(ddev);
1723
1724         ret = kstrtou32(buf, 10, &value);
1725         if (ret)
1726                 return ret;
1727
1728         if (value > 100) {
1729                 dev_err(dev, "Invalid argument !\n");
1730                 return -EINVAL;
1731         }
1732
1733         ret = pm_runtime_get_sync(ddev->dev);
1734         if (ret < 0) {
1735                 pm_runtime_put_autosuspend(ddev->dev);
1736                 return ret;
1737         }
1738
1739         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1740         if (ret) {
1741                 dev_err(dev, "failed to update thermal limit\n");
1742                 return ret;
1743         }
1744
1745         pm_runtime_mark_last_busy(ddev->dev);
1746         pm_runtime_put_autosuspend(ddev->dev);
1747
1748         return count;
1749 }
1750
1751 /**
1752  * DOC: gpu_metrics
1753  *
1754  * The amdgpu driver provides a sysfs API for retrieving current gpu
1755  * metrics data. The file gpu_metrics is used for this. Reading the
1756  * file will dump all the current gpu metrics data.
1757  *
1758  * These data include temperature, frequency, engines utilization,
1759  * power consume, throttler status, fan speed and cpu core statistics(
1760  * available for APU only). That's it will give a snapshot of all sensors
1761  * at the same time.
1762  */
1763 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1764                                       struct device_attribute *attr,
1765                                       char *buf)
1766 {
1767         struct drm_device *ddev = dev_get_drvdata(dev);
1768         struct amdgpu_device *adev = drm_to_adev(ddev);
1769         void *gpu_metrics;
1770         ssize_t size = 0;
1771         int ret;
1772
1773         if (amdgpu_in_reset(adev))
1774                 return -EPERM;
1775         if (adev->in_suspend && !adev->in_runpm)
1776                 return -EPERM;
1777
1778         ret = pm_runtime_get_sync(ddev->dev);
1779         if (ret < 0) {
1780                 pm_runtime_put_autosuspend(ddev->dev);
1781                 return ret;
1782         }
1783
1784         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1785         if (size <= 0)
1786                 goto out;
1787
1788         if (size >= PAGE_SIZE)
1789                 size = PAGE_SIZE - 1;
1790
1791         memcpy(buf, gpu_metrics, size);
1792
1793 out:
1794         pm_runtime_mark_last_busy(ddev->dev);
1795         pm_runtime_put_autosuspend(ddev->dev);
1796
1797         return size;
1798 }
1799
1800 static int amdgpu_show_powershift_percent(struct device *dev,
1801                                         char *buf, enum amd_pp_sensors sensor)
1802 {
1803         struct drm_device *ddev = dev_get_drvdata(dev);
1804         struct amdgpu_device *adev = drm_to_adev(ddev);
1805         uint32_t ss_power;
1806         int r = 0, i;
1807
1808         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1809         if (r == -EOPNOTSUPP) {
1810                 /* sensor not available on dGPU, try to read from APU */
1811                 adev = NULL;
1812                 mutex_lock(&mgpu_info.mutex);
1813                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1814                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1815                                 adev = mgpu_info.gpu_ins[i].adev;
1816                                 break;
1817                         }
1818                 }
1819                 mutex_unlock(&mgpu_info.mutex);
1820                 if (adev)
1821                         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1822         }
1823
1824         if (r)
1825                 return r;
1826
1827         return sysfs_emit(buf, "%u%%\n", ss_power);
1828 }
1829
1830 /**
1831  * DOC: smartshift_apu_power
1832  *
1833  * The amdgpu driver provides a sysfs API for reporting APU power
1834  * shift in percentage if platform supports smartshift. Value 0 means that
1835  * there is no powershift and values between [1-100] means that the power
1836  * is shifted to APU, the percentage of boost is with respect to APU power
1837  * limit on the platform.
1838  */
1839
1840 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1841                                                char *buf)
1842 {
1843         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1844 }
1845
1846 /**
1847  * DOC: smartshift_dgpu_power
1848  *
1849  * The amdgpu driver provides a sysfs API for reporting dGPU power
1850  * shift in percentage if platform supports smartshift. Value 0 means that
1851  * there is no powershift and values between [1-100] means that the power is
1852  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1853  * limit on the platform.
1854  */
1855
1856 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1857                                                 char *buf)
1858 {
1859         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1860 }
1861
1862 /**
1863  * DOC: smartshift_bias
1864  *
1865  * The amdgpu driver provides a sysfs API for reporting the
1866  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1867  * and the default is 0. -100 sets maximum preference to APU
1868  * and 100 sets max perference to dGPU.
1869  */
1870
1871 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1872                                           struct device_attribute *attr,
1873                                           char *buf)
1874 {
1875         int r = 0;
1876
1877         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1878
1879         return r;
1880 }
1881
1882 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1883                                           struct device_attribute *attr,
1884                                           const char *buf, size_t count)
1885 {
1886         struct drm_device *ddev = dev_get_drvdata(dev);
1887         struct amdgpu_device *adev = drm_to_adev(ddev);
1888         int r = 0;
1889         int bias = 0;
1890
1891         if (amdgpu_in_reset(adev))
1892                 return -EPERM;
1893         if (adev->in_suspend && !adev->in_runpm)
1894                 return -EPERM;
1895
1896         r = pm_runtime_get_sync(ddev->dev);
1897         if (r < 0) {
1898                 pm_runtime_put_autosuspend(ddev->dev);
1899                 return r;
1900         }
1901
1902         r = kstrtoint(buf, 10, &bias);
1903         if (r)
1904                 goto out;
1905
1906         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1907                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1908         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1909                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1910
1911         amdgpu_smartshift_bias = bias;
1912         r = count;
1913
1914         /* TODO: update bias level with SMU message */
1915
1916 out:
1917         pm_runtime_mark_last_busy(ddev->dev);
1918         pm_runtime_put_autosuspend(ddev->dev);
1919         return r;
1920 }
1921
1922 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1923                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1924 {
1925         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1926                 *states = ATTR_STATE_UNSUPPORTED;
1927
1928         return 0;
1929 }
1930
1931 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1932                                uint32_t mask, enum amdgpu_device_attr_states *states)
1933 {
1934         uint32_t ss_power;
1935
1936         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1937                 *states = ATTR_STATE_UNSUPPORTED;
1938         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1939                  (void *)&ss_power))
1940                 *states = ATTR_STATE_UNSUPPORTED;
1941         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1942                  (void *)&ss_power))
1943                 *states = ATTR_STATE_UNSUPPORTED;
1944
1945         return 0;
1946 }
1947
1948 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1949         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1950         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1951         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1952         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1953         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1954         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1955         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1956         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1957         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1958         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1959         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1960         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1961         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1962         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1963         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1964         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1965         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1966         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1967         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1968         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1969         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1970         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1971         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1972         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1973         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1974         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1975         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1976         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1977         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
1978                               .attr_update = ss_power_attr_update),
1979         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
1980                               .attr_update = ss_power_attr_update),
1981         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
1982                               .attr_update = ss_bias_attr_update),
1983 };
1984
1985 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1986                                uint32_t mask, enum amdgpu_device_attr_states *states)
1987 {
1988         struct device_attribute *dev_attr = &attr->dev_attr;
1989         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
1990         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
1991         const char *attr_name = dev_attr->attr.name;
1992
1993         if (!(attr->flags & mask)) {
1994                 *states = ATTR_STATE_UNSUPPORTED;
1995                 return 0;
1996         }
1997
1998 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
1999
2000         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2001                 if (gc_ver < IP_VERSION(9, 0, 0))
2002                         *states = ATTR_STATE_UNSUPPORTED;
2003         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2004                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2005                     !amdgpu_device_has_display_hardware(adev))
2006                         *states = ATTR_STATE_UNSUPPORTED;
2007         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2008                 if (mp1_ver < IP_VERSION(10, 0, 0))
2009                         *states = ATTR_STATE_UNSUPPORTED;
2010         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2011                 *states = ATTR_STATE_UNSUPPORTED;
2012                 if (amdgpu_dpm_is_overdrive_supported(adev))
2013                         *states = ATTR_STATE_SUPPORTED;
2014         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2015                 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2016                         *states = ATTR_STATE_UNSUPPORTED;
2017         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2018                 /* PCIe Perf counters won't work on APU nodes */
2019                 if (adev->flags & AMD_IS_APU)
2020                         *states = ATTR_STATE_UNSUPPORTED;
2021         } else if (DEVICE_ATTR_IS(unique_id)) {
2022                 switch (gc_ver) {
2023                 case IP_VERSION(9, 0, 1):
2024                 case IP_VERSION(9, 4, 0):
2025                 case IP_VERSION(9, 4, 1):
2026                 case IP_VERSION(9, 4, 2):
2027                 case IP_VERSION(9, 4, 3):
2028                 case IP_VERSION(10, 3, 0):
2029                 case IP_VERSION(11, 0, 0):
2030                 case IP_VERSION(11, 0, 1):
2031                 case IP_VERSION(11, 0, 2):
2032                         *states = ATTR_STATE_SUPPORTED;
2033                         break;
2034                 default:
2035                         *states = ATTR_STATE_UNSUPPORTED;
2036                 }
2037         } else if (DEVICE_ATTR_IS(pp_features)) {
2038                 if ((adev->flags & AMD_IS_APU &&
2039                      gc_ver != IP_VERSION(9, 4, 3)) ||
2040                     gc_ver < IP_VERSION(9, 0, 0))
2041                         *states = ATTR_STATE_UNSUPPORTED;
2042         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2043                 if (gc_ver < IP_VERSION(9, 1, 0))
2044                         *states = ATTR_STATE_UNSUPPORTED;
2045         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2046                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2047                       gc_ver == IP_VERSION(10, 3, 0) ||
2048                       gc_ver == IP_VERSION(10, 1, 2) ||
2049                       gc_ver == IP_VERSION(11, 0, 0) ||
2050                       gc_ver == IP_VERSION(11, 0, 2) ||
2051                       gc_ver == IP_VERSION(11, 0, 3) ||
2052                       gc_ver == IP_VERSION(9, 4, 3)))
2053                         *states = ATTR_STATE_UNSUPPORTED;
2054         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2055                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2056                            gc_ver == IP_VERSION(10, 3, 0) ||
2057                            gc_ver == IP_VERSION(11, 0, 2) ||
2058                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2059                         *states = ATTR_STATE_UNSUPPORTED;
2060         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2061                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2062                       gc_ver == IP_VERSION(10, 3, 0) ||
2063                       gc_ver == IP_VERSION(10, 1, 2) ||
2064                       gc_ver == IP_VERSION(11, 0, 0) ||
2065                       gc_ver == IP_VERSION(11, 0, 2) ||
2066                       gc_ver == IP_VERSION(11, 0, 3) ||
2067                       gc_ver == IP_VERSION(9, 4, 3)))
2068                         *states = ATTR_STATE_UNSUPPORTED;
2069         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2070                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2071                            gc_ver == IP_VERSION(10, 3, 0) ||
2072                            gc_ver == IP_VERSION(11, 0, 2) ||
2073                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2074                         *states = ATTR_STATE_UNSUPPORTED;
2075         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2076                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2077                         *states = ATTR_STATE_UNSUPPORTED;
2078                 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2079                         *states = ATTR_STATE_UNSUPPORTED;
2080         }
2081
2082         switch (gc_ver) {
2083         case IP_VERSION(9, 4, 1):
2084         case IP_VERSION(9, 4, 2):
2085                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2086                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2087                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2088                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2089                         dev_attr->attr.mode &= ~S_IWUGO;
2090                         dev_attr->store = NULL;
2091                 }
2092                 break;
2093         case IP_VERSION(10, 3, 0):
2094                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2095                     amdgpu_sriov_vf(adev)) {
2096                         dev_attr->attr.mode &= ~0222;
2097                         dev_attr->store = NULL;
2098                 }
2099                 break;
2100         default:
2101                 break;
2102         }
2103
2104         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2105                 /* SMU MP1 does not support dcefclk level setting */
2106                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2107                         dev_attr->attr.mode &= ~S_IWUGO;
2108                         dev_attr->store = NULL;
2109                 }
2110         }
2111
2112         /* setting should not be allowed from VF if not in one VF mode */
2113         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2114                 dev_attr->attr.mode &= ~S_IWUGO;
2115                 dev_attr->store = NULL;
2116         }
2117
2118 #undef DEVICE_ATTR_IS
2119
2120         return 0;
2121 }
2122
2123
2124 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2125                                      struct amdgpu_device_attr *attr,
2126                                      uint32_t mask, struct list_head *attr_list)
2127 {
2128         int ret = 0;
2129         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2130         struct amdgpu_device_attr_entry *attr_entry;
2131         struct device_attribute *dev_attr;
2132         const char *name;
2133
2134         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2135                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2136
2137         if (!attr)
2138                 return -EINVAL;
2139
2140         dev_attr = &attr->dev_attr;
2141         name = dev_attr->attr.name;
2142
2143         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2144
2145         ret = attr_update(adev, attr, mask, &attr_states);
2146         if (ret) {
2147                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2148                         name, ret);
2149                 return ret;
2150         }
2151
2152         if (attr_states == ATTR_STATE_UNSUPPORTED)
2153                 return 0;
2154
2155         ret = device_create_file(adev->dev, dev_attr);
2156         if (ret) {
2157                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2158                         name, ret);
2159         }
2160
2161         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2162         if (!attr_entry)
2163                 return -ENOMEM;
2164
2165         attr_entry->attr = attr;
2166         INIT_LIST_HEAD(&attr_entry->entry);
2167
2168         list_add_tail(&attr_entry->entry, attr_list);
2169
2170         return ret;
2171 }
2172
2173 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2174 {
2175         struct device_attribute *dev_attr = &attr->dev_attr;
2176
2177         device_remove_file(adev->dev, dev_attr);
2178 }
2179
2180 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2181                                              struct list_head *attr_list);
2182
2183 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2184                                             struct amdgpu_device_attr *attrs,
2185                                             uint32_t counts,
2186                                             uint32_t mask,
2187                                             struct list_head *attr_list)
2188 {
2189         int ret = 0;
2190         uint32_t i = 0;
2191
2192         for (i = 0; i < counts; i++) {
2193                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2194                 if (ret)
2195                         goto failed;
2196         }
2197
2198         return 0;
2199
2200 failed:
2201         amdgpu_device_attr_remove_groups(adev, attr_list);
2202
2203         return ret;
2204 }
2205
2206 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2207                                              struct list_head *attr_list)
2208 {
2209         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2210
2211         if (list_empty(attr_list))
2212                 return ;
2213
2214         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2215                 amdgpu_device_attr_remove(adev, entry->attr);
2216                 list_del(&entry->entry);
2217                 kfree(entry);
2218         }
2219 }
2220
2221 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2222                                       struct device_attribute *attr,
2223                                       char *buf)
2224 {
2225         struct amdgpu_device *adev = dev_get_drvdata(dev);
2226         int channel = to_sensor_dev_attr(attr)->index;
2227         int r, temp = 0;
2228
2229         if (channel >= PP_TEMP_MAX)
2230                 return -EINVAL;
2231
2232         switch (channel) {
2233         case PP_TEMP_JUNCTION:
2234                 /* get current junction temperature */
2235                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2236                                            (void *)&temp);
2237                 break;
2238         case PP_TEMP_EDGE:
2239                 /* get current edge temperature */
2240                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2241                                            (void *)&temp);
2242                 break;
2243         case PP_TEMP_MEM:
2244                 /* get current memory temperature */
2245                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2246                                            (void *)&temp);
2247                 break;
2248         default:
2249                 r = -EINVAL;
2250                 break;
2251         }
2252
2253         if (r)
2254                 return r;
2255
2256         return sysfs_emit(buf, "%d\n", temp);
2257 }
2258
2259 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2260                                              struct device_attribute *attr,
2261                                              char *buf)
2262 {
2263         struct amdgpu_device *adev = dev_get_drvdata(dev);
2264         int hyst = to_sensor_dev_attr(attr)->index;
2265         int temp;
2266
2267         if (hyst)
2268                 temp = adev->pm.dpm.thermal.min_temp;
2269         else
2270                 temp = adev->pm.dpm.thermal.max_temp;
2271
2272         return sysfs_emit(buf, "%d\n", temp);
2273 }
2274
2275 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2276                                              struct device_attribute *attr,
2277                                              char *buf)
2278 {
2279         struct amdgpu_device *adev = dev_get_drvdata(dev);
2280         int hyst = to_sensor_dev_attr(attr)->index;
2281         int temp;
2282
2283         if (hyst)
2284                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2285         else
2286                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2287
2288         return sysfs_emit(buf, "%d\n", temp);
2289 }
2290
2291 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2292                                              struct device_attribute *attr,
2293                                              char *buf)
2294 {
2295         struct amdgpu_device *adev = dev_get_drvdata(dev);
2296         int hyst = to_sensor_dev_attr(attr)->index;
2297         int temp;
2298
2299         if (hyst)
2300                 temp = adev->pm.dpm.thermal.min_mem_temp;
2301         else
2302                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2303
2304         return sysfs_emit(buf, "%d\n", temp);
2305 }
2306
2307 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2308                                              struct device_attribute *attr,
2309                                              char *buf)
2310 {
2311         int channel = to_sensor_dev_attr(attr)->index;
2312
2313         if (channel >= PP_TEMP_MAX)
2314                 return -EINVAL;
2315
2316         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2317 }
2318
2319 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2320                                              struct device_attribute *attr,
2321                                              char *buf)
2322 {
2323         struct amdgpu_device *adev = dev_get_drvdata(dev);
2324         int channel = to_sensor_dev_attr(attr)->index;
2325         int temp = 0;
2326
2327         if (channel >= PP_TEMP_MAX)
2328                 return -EINVAL;
2329
2330         switch (channel) {
2331         case PP_TEMP_JUNCTION:
2332                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2333                 break;
2334         case PP_TEMP_EDGE:
2335                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2336                 break;
2337         case PP_TEMP_MEM:
2338                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2339                 break;
2340         }
2341
2342         return sysfs_emit(buf, "%d\n", temp);
2343 }
2344
2345 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2346                                             struct device_attribute *attr,
2347                                             char *buf)
2348 {
2349         struct amdgpu_device *adev = dev_get_drvdata(dev);
2350         u32 pwm_mode = 0;
2351         int ret;
2352
2353         if (amdgpu_in_reset(adev))
2354                 return -EPERM;
2355         if (adev->in_suspend && !adev->in_runpm)
2356                 return -EPERM;
2357
2358         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2359         if (ret < 0) {
2360                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2361                 return ret;
2362         }
2363
2364         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2365
2366         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2367         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2368
2369         if (ret)
2370                 return -EINVAL;
2371
2372         return sysfs_emit(buf, "%u\n", pwm_mode);
2373 }
2374
2375 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2376                                             struct device_attribute *attr,
2377                                             const char *buf,
2378                                             size_t count)
2379 {
2380         struct amdgpu_device *adev = dev_get_drvdata(dev);
2381         int err, ret;
2382         int value;
2383
2384         if (amdgpu_in_reset(adev))
2385                 return -EPERM;
2386         if (adev->in_suspend && !adev->in_runpm)
2387                 return -EPERM;
2388
2389         err = kstrtoint(buf, 10, &value);
2390         if (err)
2391                 return err;
2392
2393         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2394         if (ret < 0) {
2395                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2396                 return ret;
2397         }
2398
2399         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2400
2401         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2402         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2403
2404         if (ret)
2405                 return -EINVAL;
2406
2407         return count;
2408 }
2409
2410 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2411                                          struct device_attribute *attr,
2412                                          char *buf)
2413 {
2414         return sysfs_emit(buf, "%i\n", 0);
2415 }
2416
2417 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2418                                          struct device_attribute *attr,
2419                                          char *buf)
2420 {
2421         return sysfs_emit(buf, "%i\n", 255);
2422 }
2423
2424 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2425                                      struct device_attribute *attr,
2426                                      const char *buf, size_t count)
2427 {
2428         struct amdgpu_device *adev = dev_get_drvdata(dev);
2429         int err;
2430         u32 value;
2431         u32 pwm_mode;
2432
2433         if (amdgpu_in_reset(adev))
2434                 return -EPERM;
2435         if (adev->in_suspend && !adev->in_runpm)
2436                 return -EPERM;
2437
2438         err = kstrtou32(buf, 10, &value);
2439         if (err)
2440                 return err;
2441
2442         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2443         if (err < 0) {
2444                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2445                 return err;
2446         }
2447
2448         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2449         if (err)
2450                 goto out;
2451
2452         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2453                 pr_info("manual fan speed control should be enabled first\n");
2454                 err = -EINVAL;
2455                 goto out;
2456         }
2457
2458         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2459
2460 out:
2461         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2462         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2463
2464         if (err)
2465                 return err;
2466
2467         return count;
2468 }
2469
2470 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2471                                      struct device_attribute *attr,
2472                                      char *buf)
2473 {
2474         struct amdgpu_device *adev = dev_get_drvdata(dev);
2475         int err;
2476         u32 speed = 0;
2477
2478         if (amdgpu_in_reset(adev))
2479                 return -EPERM;
2480         if (adev->in_suspend && !adev->in_runpm)
2481                 return -EPERM;
2482
2483         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2484         if (err < 0) {
2485                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2486                 return err;
2487         }
2488
2489         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2490
2491         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2492         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2493
2494         if (err)
2495                 return err;
2496
2497         return sysfs_emit(buf, "%i\n", speed);
2498 }
2499
2500 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2501                                            struct device_attribute *attr,
2502                                            char *buf)
2503 {
2504         struct amdgpu_device *adev = dev_get_drvdata(dev);
2505         int err;
2506         u32 speed = 0;
2507
2508         if (amdgpu_in_reset(adev))
2509                 return -EPERM;
2510         if (adev->in_suspend && !adev->in_runpm)
2511                 return -EPERM;
2512
2513         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2514         if (err < 0) {
2515                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2516                 return err;
2517         }
2518
2519         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2520
2521         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2522         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2523
2524         if (err)
2525                 return err;
2526
2527         return sysfs_emit(buf, "%i\n", speed);
2528 }
2529
2530 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2531                                          struct device_attribute *attr,
2532                                          char *buf)
2533 {
2534         struct amdgpu_device *adev = dev_get_drvdata(dev);
2535         u32 min_rpm = 0;
2536         int r;
2537
2538         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2539                                    (void *)&min_rpm);
2540
2541         if (r)
2542                 return r;
2543
2544         return sysfs_emit(buf, "%d\n", min_rpm);
2545 }
2546
2547 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2548                                          struct device_attribute *attr,
2549                                          char *buf)
2550 {
2551         struct amdgpu_device *adev = dev_get_drvdata(dev);
2552         u32 max_rpm = 0;
2553         int r;
2554
2555         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2556                                    (void *)&max_rpm);
2557
2558         if (r)
2559                 return r;
2560
2561         return sysfs_emit(buf, "%d\n", max_rpm);
2562 }
2563
2564 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2565                                            struct device_attribute *attr,
2566                                            char *buf)
2567 {
2568         struct amdgpu_device *adev = dev_get_drvdata(dev);
2569         int err;
2570         u32 rpm = 0;
2571
2572         if (amdgpu_in_reset(adev))
2573                 return -EPERM;
2574         if (adev->in_suspend && !adev->in_runpm)
2575                 return -EPERM;
2576
2577         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2578         if (err < 0) {
2579                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2580                 return err;
2581         }
2582
2583         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2584
2585         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2586         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2587
2588         if (err)
2589                 return err;
2590
2591         return sysfs_emit(buf, "%i\n", rpm);
2592 }
2593
2594 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2595                                      struct device_attribute *attr,
2596                                      const char *buf, size_t count)
2597 {
2598         struct amdgpu_device *adev = dev_get_drvdata(dev);
2599         int err;
2600         u32 value;
2601         u32 pwm_mode;
2602
2603         if (amdgpu_in_reset(adev))
2604                 return -EPERM;
2605         if (adev->in_suspend && !adev->in_runpm)
2606                 return -EPERM;
2607
2608         err = kstrtou32(buf, 10, &value);
2609         if (err)
2610                 return err;
2611
2612         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2613         if (err < 0) {
2614                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2615                 return err;
2616         }
2617
2618         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2619         if (err)
2620                 goto out;
2621
2622         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2623                 err = -ENODATA;
2624                 goto out;
2625         }
2626
2627         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2628
2629 out:
2630         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2631         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2632
2633         if (err)
2634                 return err;
2635
2636         return count;
2637 }
2638
2639 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2640                                             struct device_attribute *attr,
2641                                             char *buf)
2642 {
2643         struct amdgpu_device *adev = dev_get_drvdata(dev);
2644         u32 pwm_mode = 0;
2645         int ret;
2646
2647         if (amdgpu_in_reset(adev))
2648                 return -EPERM;
2649         if (adev->in_suspend && !adev->in_runpm)
2650                 return -EPERM;
2651
2652         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2653         if (ret < 0) {
2654                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2655                 return ret;
2656         }
2657
2658         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2659
2660         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2661         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2662
2663         if (ret)
2664                 return -EINVAL;
2665
2666         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2667 }
2668
2669 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2670                                             struct device_attribute *attr,
2671                                             const char *buf,
2672                                             size_t count)
2673 {
2674         struct amdgpu_device *adev = dev_get_drvdata(dev);
2675         int err;
2676         int value;
2677         u32 pwm_mode;
2678
2679         if (amdgpu_in_reset(adev))
2680                 return -EPERM;
2681         if (adev->in_suspend && !adev->in_runpm)
2682                 return -EPERM;
2683
2684         err = kstrtoint(buf, 10, &value);
2685         if (err)
2686                 return err;
2687
2688         if (value == 0)
2689                 pwm_mode = AMD_FAN_CTRL_AUTO;
2690         else if (value == 1)
2691                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2692         else
2693                 return -EINVAL;
2694
2695         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2696         if (err < 0) {
2697                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2698                 return err;
2699         }
2700
2701         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2702
2703         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2704         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2705
2706         if (err)
2707                 return -EINVAL;
2708
2709         return count;
2710 }
2711
2712 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2713                                         struct device_attribute *attr,
2714                                         char *buf)
2715 {
2716         struct amdgpu_device *adev = dev_get_drvdata(dev);
2717         u32 vddgfx;
2718         int r;
2719
2720         /* get the voltage */
2721         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2722                                    (void *)&vddgfx);
2723         if (r)
2724                 return r;
2725
2726         return sysfs_emit(buf, "%d\n", vddgfx);
2727 }
2728
2729 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2730                                               struct device_attribute *attr,
2731                                               char *buf)
2732 {
2733         return sysfs_emit(buf, "vddgfx\n");
2734 }
2735
2736 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2737                                        struct device_attribute *attr,
2738                                        char *buf)
2739 {
2740         struct amdgpu_device *adev = dev_get_drvdata(dev);
2741         u32 vddnb;
2742         int r;
2743
2744         /* only APUs have vddnb */
2745         if  (!(adev->flags & AMD_IS_APU))
2746                 return -EINVAL;
2747
2748         /* get the voltage */
2749         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2750                                    (void *)&vddnb);
2751         if (r)
2752                 return r;
2753
2754         return sysfs_emit(buf, "%d\n", vddnb);
2755 }
2756
2757 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2758                                               struct device_attribute *attr,
2759                                               char *buf)
2760 {
2761         return sysfs_emit(buf, "vddnb\n");
2762 }
2763
2764 static int amdgpu_hwmon_get_power(struct device *dev,
2765                                   enum amd_pp_sensors sensor)
2766 {
2767         struct amdgpu_device *adev = dev_get_drvdata(dev);
2768         unsigned int uw;
2769         u32 query = 0;
2770         int r;
2771
2772         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2773         if (r)
2774                 return r;
2775
2776         /* convert to microwatts */
2777         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2778
2779         return uw;
2780 }
2781
2782 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2783                                            struct device_attribute *attr,
2784                                            char *buf)
2785 {
2786         ssize_t val;
2787
2788         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2789         if (val < 0)
2790                 return val;
2791
2792         return sysfs_emit(buf, "%zd\n", val);
2793 }
2794
2795 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2796                                              struct device_attribute *attr,
2797                                              char *buf)
2798 {
2799         ssize_t val;
2800
2801         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2802         if (val < 0)
2803                 return val;
2804
2805         return sysfs_emit(buf, "%zd\n", val);
2806 }
2807
2808 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2809                                          struct device_attribute *attr,
2810                                          char *buf)
2811 {
2812         return sysfs_emit(buf, "%i\n", 0);
2813 }
2814
2815
2816 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2817                                         struct device_attribute *attr,
2818                                         char *buf,
2819                                         enum pp_power_limit_level pp_limit_level)
2820 {
2821         struct amdgpu_device *adev = dev_get_drvdata(dev);
2822         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2823         uint32_t limit;
2824         ssize_t size;
2825         int r;
2826
2827         if (amdgpu_in_reset(adev))
2828                 return -EPERM;
2829         if (adev->in_suspend && !adev->in_runpm)
2830                 return -EPERM;
2831
2832         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2833         if (r < 0) {
2834                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2835                 return r;
2836         }
2837
2838         r = amdgpu_dpm_get_power_limit(adev, &limit,
2839                                       pp_limit_level, power_type);
2840
2841         if (!r)
2842                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2843         else
2844                 size = sysfs_emit(buf, "\n");
2845
2846         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2847         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2848
2849         return size;
2850 }
2851
2852
2853 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2854                                          struct device_attribute *attr,
2855                                          char *buf)
2856 {
2857         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2858
2859 }
2860
2861 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2862                                          struct device_attribute *attr,
2863                                          char *buf)
2864 {
2865         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2866
2867 }
2868
2869 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2870                                          struct device_attribute *attr,
2871                                          char *buf)
2872 {
2873         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2874
2875 }
2876
2877 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2878                                          struct device_attribute *attr,
2879                                          char *buf)
2880 {
2881         struct amdgpu_device *adev = dev_get_drvdata(dev);
2882         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2883
2884         if (gc_ver == IP_VERSION(10, 3, 1))
2885                 return sysfs_emit(buf, "%s\n",
2886                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
2887                                   "fastPPT" : "slowPPT");
2888         else
2889                 return sysfs_emit(buf, "PPT\n");
2890 }
2891
2892 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2893                 struct device_attribute *attr,
2894                 const char *buf,
2895                 size_t count)
2896 {
2897         struct amdgpu_device *adev = dev_get_drvdata(dev);
2898         int limit_type = to_sensor_dev_attr(attr)->index;
2899         int err;
2900         u32 value;
2901
2902         if (amdgpu_in_reset(adev))
2903                 return -EPERM;
2904         if (adev->in_suspend && !adev->in_runpm)
2905                 return -EPERM;
2906
2907         if (amdgpu_sriov_vf(adev))
2908                 return -EINVAL;
2909
2910         err = kstrtou32(buf, 10, &value);
2911         if (err)
2912                 return err;
2913
2914         value = value / 1000000; /* convert to Watt */
2915         value |= limit_type << 24;
2916
2917         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2918         if (err < 0) {
2919                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2920                 return err;
2921         }
2922
2923         err = amdgpu_dpm_set_power_limit(adev, value);
2924
2925         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2926         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2927
2928         if (err)
2929                 return err;
2930
2931         return count;
2932 }
2933
2934 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2935                                       struct device_attribute *attr,
2936                                       char *buf)
2937 {
2938         struct amdgpu_device *adev = dev_get_drvdata(dev);
2939         uint32_t sclk;
2940         int r;
2941
2942         /* get the sclk */
2943         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2944                                    (void *)&sclk);
2945         if (r)
2946                 return r;
2947
2948         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
2949 }
2950
2951 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2952                                             struct device_attribute *attr,
2953                                             char *buf)
2954 {
2955         return sysfs_emit(buf, "sclk\n");
2956 }
2957
2958 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2959                                       struct device_attribute *attr,
2960                                       char *buf)
2961 {
2962         struct amdgpu_device *adev = dev_get_drvdata(dev);
2963         uint32_t mclk;
2964         int r;
2965
2966         /* get the sclk */
2967         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2968                                    (void *)&mclk);
2969         if (r)
2970                 return r;
2971
2972         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
2973 }
2974
2975 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2976                                             struct device_attribute *attr,
2977                                             char *buf)
2978 {
2979         return sysfs_emit(buf, "mclk\n");
2980 }
2981
2982 /**
2983  * DOC: hwmon
2984  *
2985  * The amdgpu driver exposes the following sensor interfaces:
2986  *
2987  * - GPU temperature (via the on-die sensor)
2988  *
2989  * - GPU voltage
2990  *
2991  * - Northbridge voltage (APUs only)
2992  *
2993  * - GPU power
2994  *
2995  * - GPU fan
2996  *
2997  * - GPU gfx/compute engine clock
2998  *
2999  * - GPU memory clock (dGPU only)
3000  *
3001  * hwmon interfaces for GPU temperature:
3002  *
3003  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3004  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3005  *
3006  * - temp[1-3]_label: temperature channel label
3007  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3008  *
3009  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3010  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3011  *
3012  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3013  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3014  *
3015  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3016  *   - these are supported on SOC15 dGPUs only
3017  *
3018  * hwmon interfaces for GPU voltage:
3019  *
3020  * - in0_input: the voltage on the GPU in millivolts
3021  *
3022  * - in1_input: the voltage on the Northbridge in millivolts
3023  *
3024  * hwmon interfaces for GPU power:
3025  *
3026  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3027  *
3028  * - power1_input: instantaneous power used by the SoC in microWatts.  On APUs this includes the CPU.
3029  *
3030  * - power1_cap_min: minimum cap supported in microWatts
3031  *
3032  * - power1_cap_max: maximum cap supported in microWatts
3033  *
3034  * - power1_cap: selected power cap in microWatts
3035  *
3036  * hwmon interfaces for GPU fan:
3037  *
3038  * - pwm1: pulse width modulation fan level (0-255)
3039  *
3040  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3041  *
3042  * - pwm1_min: pulse width modulation fan control minimum level (0)
3043  *
3044  * - pwm1_max: pulse width modulation fan control maximum level (255)
3045  *
3046  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3047  *
3048  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3049  *
3050  * - fan1_input: fan speed in RPM
3051  *
3052  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3053  *
3054  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3055  *
3056  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3057  *       That will get the former one overridden.
3058  *
3059  * hwmon interfaces for GPU clocks:
3060  *
3061  * - freq1_input: the gfx/compute clock in hertz
3062  *
3063  * - freq2_input: the memory clock in hertz
3064  *
3065  * You can use hwmon tools like sensors to view this information on your system.
3066  *
3067  */
3068
3069 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3070 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3071 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3072 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3073 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3074 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3075 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3076 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3077 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3078 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3079 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3080 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3081 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3082 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3083 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3084 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3085 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3086 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3087 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3088 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3089 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3090 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3091 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3092 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3093 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3094 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3095 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3096 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3097 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3098 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3099 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3100 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3101 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3102 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3103 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3104 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3105 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3106 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3107 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3108 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3109 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3110 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3111 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3112 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3113 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3114
3115 static struct attribute *hwmon_attributes[] = {
3116         &sensor_dev_attr_temp1_input.dev_attr.attr,
3117         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3118         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3119         &sensor_dev_attr_temp2_input.dev_attr.attr,
3120         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3121         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3122         &sensor_dev_attr_temp3_input.dev_attr.attr,
3123         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3124         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3125         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3126         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3127         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3128         &sensor_dev_attr_temp1_label.dev_attr.attr,
3129         &sensor_dev_attr_temp2_label.dev_attr.attr,
3130         &sensor_dev_attr_temp3_label.dev_attr.attr,
3131         &sensor_dev_attr_pwm1.dev_attr.attr,
3132         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3133         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3134         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3135         &sensor_dev_attr_fan1_input.dev_attr.attr,
3136         &sensor_dev_attr_fan1_min.dev_attr.attr,
3137         &sensor_dev_attr_fan1_max.dev_attr.attr,
3138         &sensor_dev_attr_fan1_target.dev_attr.attr,
3139         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3140         &sensor_dev_attr_in0_input.dev_attr.attr,
3141         &sensor_dev_attr_in0_label.dev_attr.attr,
3142         &sensor_dev_attr_in1_input.dev_attr.attr,
3143         &sensor_dev_attr_in1_label.dev_attr.attr,
3144         &sensor_dev_attr_power1_average.dev_attr.attr,
3145         &sensor_dev_attr_power1_input.dev_attr.attr,
3146         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3147         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3148         &sensor_dev_attr_power1_cap.dev_attr.attr,
3149         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3150         &sensor_dev_attr_power1_label.dev_attr.attr,
3151         &sensor_dev_attr_power2_average.dev_attr.attr,
3152         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3153         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3154         &sensor_dev_attr_power2_cap.dev_attr.attr,
3155         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3156         &sensor_dev_attr_power2_label.dev_attr.attr,
3157         &sensor_dev_attr_freq1_input.dev_attr.attr,
3158         &sensor_dev_attr_freq1_label.dev_attr.attr,
3159         &sensor_dev_attr_freq2_input.dev_attr.attr,
3160         &sensor_dev_attr_freq2_label.dev_attr.attr,
3161         NULL
3162 };
3163
3164 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3165                                         struct attribute *attr, int index)
3166 {
3167         struct device *dev = kobj_to_dev(kobj);
3168         struct amdgpu_device *adev = dev_get_drvdata(dev);
3169         umode_t effective_mode = attr->mode;
3170         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3171         uint32_t tmp;
3172
3173         /* under multi-vf mode, the hwmon attributes are all not supported */
3174         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3175                 return 0;
3176
3177         /* under pp one vf mode manage of hwmon attributes is not supported */
3178         if (amdgpu_sriov_is_pp_one_vf(adev))
3179                 effective_mode &= ~S_IWUSR;
3180
3181         /* Skip fan attributes if fan is not present */
3182         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3183             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3184             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3185             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3186             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3187             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3188             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3189             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3190             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3191                 return 0;
3192
3193         /* Skip fan attributes on APU */
3194         if ((adev->flags & AMD_IS_APU) &&
3195             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3196              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3197              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3198              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3199              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3200              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3201              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3202              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3203              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3204                 return 0;
3205
3206         /* Skip crit temp on APU */
3207         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3208             (gc_ver == IP_VERSION(9, 4, 3))) &&
3209             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3210              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3211                 return 0;
3212
3213         /* Skip limit attributes if DPM is not enabled */
3214         if (!adev->pm.dpm_enabled &&
3215             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3216              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3217              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3218              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3219              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3220              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3221              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3222              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3223              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3224              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3225              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3226                 return 0;
3227
3228         /* mask fan attributes if we have no bindings for this asic to expose */
3229         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3230               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3231             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3232              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3233                 effective_mode &= ~S_IRUGO;
3234
3235         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3236               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3237               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3238               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3239                 effective_mode &= ~S_IWUSR;
3240
3241         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3242         if (((adev->family == AMDGPU_FAMILY_SI) ||
3243              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3244               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3245             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3246              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3247              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3248              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3249                 return 0;
3250
3251         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3252         if (((adev->family == AMDGPU_FAMILY_SI) ||
3253              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3254             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3255                 return 0;
3256
3257         /* not all products support both average and instantaneous */
3258         if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3259             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3260                 return 0;
3261         if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3262             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3263                 return 0;
3264
3265         /* hide max/min values if we can't both query and manage the fan */
3266         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3267               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3268               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3269               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3270             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3271              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3272                 return 0;
3273
3274         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3275              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3276              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3277              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3278                 return 0;
3279
3280         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3281              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3282              (gc_ver == IP_VERSION(9, 4, 3))) &&
3283             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3284              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3285                 return 0;
3286
3287         /* only APUs other than gc 9,4,3 have vddnb */
3288         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3289             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3290              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3291                 return 0;
3292
3293         /* no mclk on APUs other than gc 9,4,3*/
3294         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3295             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3296              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3297                 return 0;
3298
3299         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3300             (gc_ver != IP_VERSION(9, 4, 3)) &&
3301             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3302              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3303              attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3304              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3305              attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3306              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3307                 return 0;
3308
3309         /* hotspot temperature for gc 9,4,3*/
3310         if ((gc_ver == IP_VERSION(9, 4, 3)) &&
3311             (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3312              attr == &sensor_dev_attr_temp1_label.dev_attr.attr))
3313                 return 0;
3314
3315         /* only SOC15 dGPUs support hotspot and mem temperatures */
3316         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) ||
3317             (gc_ver == IP_VERSION(9, 4, 3))) &&
3318              (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3319              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3320              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3321              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3322              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3323                 return 0;
3324
3325         /* only Vangogh has fast PPT limit and power labels */
3326         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3327             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3328              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3329              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3330              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3331              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3332              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3333                 return 0;
3334
3335         return effective_mode;
3336 }
3337
3338 static const struct attribute_group hwmon_attrgroup = {
3339         .attrs = hwmon_attributes,
3340         .is_visible = hwmon_attributes_visible,
3341 };
3342
3343 static const struct attribute_group *hwmon_groups[] = {
3344         &hwmon_attrgroup,
3345         NULL
3346 };
3347
3348 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3349 {
3350         int ret;
3351         uint32_t mask = 0;
3352
3353         if (adev->pm.sysfs_initialized)
3354                 return 0;
3355
3356         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3357
3358         if (adev->pm.dpm_enabled == 0)
3359                 return 0;
3360
3361         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3362                                                                    DRIVER_NAME, adev,
3363                                                                    hwmon_groups);
3364         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3365                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3366                 dev_err(adev->dev,
3367                         "Unable to register hwmon device: %d\n", ret);
3368                 return ret;
3369         }
3370
3371         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3372         case SRIOV_VF_MODE_ONE_VF:
3373                 mask = ATTR_FLAG_ONEVF;
3374                 break;
3375         case SRIOV_VF_MODE_MULTI_VF:
3376                 mask = 0;
3377                 break;
3378         case SRIOV_VF_MODE_BARE_METAL:
3379         default:
3380                 mask = ATTR_FLAG_MASK_ALL;
3381                 break;
3382         }
3383
3384         ret = amdgpu_device_attr_create_groups(adev,
3385                                                amdgpu_device_attrs,
3386                                                ARRAY_SIZE(amdgpu_device_attrs),
3387                                                mask,
3388                                                &adev->pm.pm_attr_list);
3389         if (ret)
3390                 return ret;
3391
3392         adev->pm.sysfs_initialized = true;
3393
3394         return 0;
3395 }
3396
3397 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3398 {
3399         if (adev->pm.int_hwmon_dev)
3400                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3401
3402         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3403 }
3404
3405 /*
3406  * Debugfs info
3407  */
3408 #if defined(CONFIG_DEBUG_FS)
3409
3410 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3411                                            struct amdgpu_device *adev)
3412 {
3413         uint16_t *p_val;
3414         uint32_t size;
3415         int i;
3416         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3417
3418         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3419                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3420                                 GFP_KERNEL);
3421
3422                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3423                                             (void *)p_val, &size)) {
3424                         for (i = 0; i < num_cpu_cores; i++)
3425                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3426                                            *(p_val + i), i);
3427                 }
3428
3429                 kfree(p_val);
3430         }
3431 }
3432
3433 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3434 {
3435         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3436         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3437         uint32_t value;
3438         uint64_t value64 = 0;
3439         uint32_t query = 0;
3440         int size;
3441
3442         /* GPU Clocks */
3443         size = sizeof(value);
3444         seq_printf(m, "GFX Clocks and Power:\n");
3445
3446         amdgpu_debugfs_prints_cpu_info(m, adev);
3447
3448         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3449                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3450         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3451                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3452         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3453                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3454         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3455                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3456         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3457                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3458         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3459                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3460         size = sizeof(uint32_t);
3461         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size))
3462                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3463         size = sizeof(uint32_t);
3464         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size))
3465                 seq_printf(m, "\t%u.%u W (current GPU)\n", query >> 8, query & 0xff);
3466         size = sizeof(value);
3467         seq_printf(m, "\n");
3468
3469         /* GPU Temp */
3470         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3471                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3472
3473         /* GPU Load */
3474         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3475                 seq_printf(m, "GPU Load: %u %%\n", value);
3476         /* MEM Load */
3477         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3478                 seq_printf(m, "MEM Load: %u %%\n", value);
3479
3480         seq_printf(m, "\n");
3481
3482         /* SMC feature mask */
3483         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3484                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3485
3486         /* ASICs greater than CHIP_VEGA20 supports these sensors */
3487         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3488                 /* VCN clocks */
3489                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3490                         if (!value) {
3491                                 seq_printf(m, "VCN: Disabled\n");
3492                         } else {
3493                                 seq_printf(m, "VCN: Enabled\n");
3494                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3495                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3496                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3497                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3498                         }
3499                 }
3500                 seq_printf(m, "\n");
3501         } else {
3502                 /* UVD clocks */
3503                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3504                         if (!value) {
3505                                 seq_printf(m, "UVD: Disabled\n");
3506                         } else {
3507                                 seq_printf(m, "UVD: Enabled\n");
3508                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3509                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3510                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3511                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3512                         }
3513                 }
3514                 seq_printf(m, "\n");
3515
3516                 /* VCE clocks */
3517                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3518                         if (!value) {
3519                                 seq_printf(m, "VCE: Disabled\n");
3520                         } else {
3521                                 seq_printf(m, "VCE: Enabled\n");
3522                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3523                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3524                         }
3525                 }
3526         }
3527
3528         return 0;
3529 }
3530
3531 static const struct cg_flag_name clocks[] = {
3532         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
3533         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
3534         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
3535         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
3536         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
3537         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
3538         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
3539         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
3540         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
3541         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
3542         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
3543         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
3544         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
3545         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
3546         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
3547         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
3548         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
3549         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
3550         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
3551         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
3552         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
3553         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
3554         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
3555         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
3556         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
3557         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
3558         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
3559         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
3560         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
3561         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
3562         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
3563         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
3564         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
3565         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
3566         {0, NULL},
3567 };
3568
3569 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3570 {
3571         int i;
3572
3573         for (i = 0; clocks[i].flag; i++)
3574                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3575                            (flags & clocks[i].flag) ? "On" : "Off");
3576 }
3577
3578 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3579 {
3580         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3581         struct drm_device *dev = adev_to_drm(adev);
3582         u64 flags = 0;
3583         int r;
3584
3585         if (amdgpu_in_reset(adev))
3586                 return -EPERM;
3587         if (adev->in_suspend && !adev->in_runpm)
3588                 return -EPERM;
3589
3590         r = pm_runtime_get_sync(dev->dev);
3591         if (r < 0) {
3592                 pm_runtime_put_autosuspend(dev->dev);
3593                 return r;
3594         }
3595
3596         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3597                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3598                 if (r)
3599                         goto out;
3600         }
3601
3602         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3603
3604         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3605         amdgpu_parse_cg_state(m, flags);
3606         seq_printf(m, "\n");
3607
3608 out:
3609         pm_runtime_mark_last_busy(dev->dev);
3610         pm_runtime_put_autosuspend(dev->dev);
3611
3612         return r;
3613 }
3614
3615 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3616
3617 /*
3618  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3619  *
3620  * Reads debug memory region allocated to PMFW
3621  */
3622 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3623                                          size_t size, loff_t *pos)
3624 {
3625         struct amdgpu_device *adev = file_inode(f)->i_private;
3626         size_t smu_prv_buf_size;
3627         void *smu_prv_buf;
3628         int ret = 0;
3629
3630         if (amdgpu_in_reset(adev))
3631                 return -EPERM;
3632         if (adev->in_suspend && !adev->in_runpm)
3633                 return -EPERM;
3634
3635         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3636         if (ret)
3637                 return ret;
3638
3639         if (!smu_prv_buf || !smu_prv_buf_size)
3640                 return -EINVAL;
3641
3642         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3643                                        smu_prv_buf_size);
3644 }
3645
3646 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3647         .owner = THIS_MODULE,
3648         .open = simple_open,
3649         .read = amdgpu_pm_prv_buffer_read,
3650         .llseek = default_llseek,
3651 };
3652
3653 #endif
3654
3655 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3656 {
3657 #if defined(CONFIG_DEBUG_FS)
3658         struct drm_minor *minor = adev_to_drm(adev)->primary;
3659         struct dentry *root = minor->debugfs_root;
3660
3661         if (!adev->pm.dpm_enabled)
3662                 return;
3663
3664         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3665                             &amdgpu_debugfs_pm_info_fops);
3666
3667         if (adev->pm.smu_prv_buffer_size > 0)
3668                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3669                                          adev,
3670                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3671                                          adev->pm.smu_prv_buffer_size);
3672
3673         amdgpu_dpm_stb_debug_fs_init(adev);
3674 #endif
3675 }
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