2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/cec.h>
33 #include <linux/hdmi.h>
34 #include <linux/i2c.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
41 #include <drm/drm_displayid.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_encoder.h>
45 #include <drm/drm_print.h>
47 #include "drm_crtc_internal.h"
49 static int oui(u8 first, u8 second, u8 third)
51 return (first << 16) | (second << 8) | third;
54 #define EDID_EST_TIMINGS 16
55 #define EDID_STD_TIMINGS 8
56 #define EDID_DETAILED_TIMINGS 4
59 * EDID blocks out in the wild have a variety of bugs, try to collect
60 * them here (note that userspace may work around broken monitors first,
61 * but fixes should make their way here so that the kernel "just works"
62 * on as many displays as possible).
65 /* First detailed mode wrong, use largest 60Hz mode */
66 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
67 /* Reported 135MHz pixel clock is too high, needs adjustment */
68 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
69 /* Prefer the largest mode at 75 Hz */
70 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
71 /* Detail timing is in cm not mm */
72 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
73 /* Detailed timing descriptors have bogus size values, so just take the
74 * maximum size and use that.
76 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
77 /* use +hsync +vsync for detailed mode */
78 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
79 /* Force reduced-blanking timings for detailed modes */
80 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
82 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
84 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
86 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
88 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
89 /* Non desktop display (i.e. HMD) */
90 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 /* Cap the DSC target bitrate to 15bpp */
92 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
94 #define MICROSOFT_IEEE_OUI 0xca125c
96 struct detailed_mode_closure {
97 struct drm_connector *connector;
98 const struct drm_edid *drm_edid;
108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
115 static const struct edid_quirk {
118 } edid_quirk_list[] = {
120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
128 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
142 /* Belinea 10 15 55 */
143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
146 /* Envision Peripherals, Inc. EN-7100e */
147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
148 /* Envision EN2028 */
149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
151 /* Funai Electronics PM36B */
152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
153 EDID_QUIRK_DETAILED_IN_CM),
156 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
159 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
161 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
162 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
164 /* LG Philips LCD LP154W01-A5 */
165 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
166 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
168 /* Samsung SyncMaster 205BW. Note: irony */
169 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
170 /* Samsung SyncMaster 22[5-6]BW */
171 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
172 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
174 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
175 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
177 /* ViewSonic VA2026w */
178 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
180 /* Medion MD 30217 PG */
181 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
184 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
186 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
187 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
189 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
190 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
192 /* Valve Index Headset */
193 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
211 /* HTC Vive and Vive Pro VR Headsets */
212 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
215 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
216 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
221 /* Windows Mixed Reality Headsets */
222 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
227 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
229 /* Sony PlayStation VR Headset */
230 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
232 /* Sensics VR Headsets */
233 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
235 /* OSVR HDK and HDK2 VR Headsets */
236 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
241 * Autogenerated from the DMT spec.
242 * This table is copied from xfree86/modes/xf86EdidModes.c.
244 static const struct drm_display_mode drm_dmt_modes[] = {
245 /* 0x01 - 640x350@85Hz */
246 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
247 736, 832, 0, 350, 382, 385, 445, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x02 - 640x400@85Hz */
250 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
251 736, 832, 0, 400, 401, 404, 445, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x03 - 720x400@85Hz */
254 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
255 828, 936, 0, 400, 401, 404, 446, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x04 - 640x480@60Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
259 752, 800, 0, 480, 490, 492, 525, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x05 - 640x480@72Hz */
262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
263 704, 832, 0, 480, 489, 492, 520, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x06 - 640x480@75Hz */
266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
267 720, 840, 0, 480, 481, 484, 500, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 0x07 - 640x480@85Hz */
270 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
271 752, 832, 0, 480, 481, 484, 509, 0,
272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
273 /* 0x08 - 800x600@56Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
275 896, 1024, 0, 600, 601, 603, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x09 - 800x600@60Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
279 968, 1056, 0, 600, 601, 605, 628, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0a - 800x600@72Hz */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
283 976, 1040, 0, 600, 637, 643, 666, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x0b - 800x600@75Hz */
286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
287 896, 1056, 0, 600, 601, 604, 625, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0c - 800x600@85Hz */
290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
291 896, 1048, 0, 600, 601, 604, 631, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
293 /* 0x0d - 800x600@120Hz RB */
294 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
295 880, 960, 0, 600, 603, 607, 636, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
297 /* 0x0e - 848x480@60Hz */
298 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
299 976, 1088, 0, 480, 486, 494, 517, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x0f - 1024x768@43Hz, interlace */
302 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
303 1208, 1264, 0, 768, 768, 776, 817, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
305 DRM_MODE_FLAG_INTERLACE) },
306 /* 0x10 - 1024x768@60Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
308 1184, 1344, 0, 768, 771, 777, 806, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 0x11 - 1024x768@70Hz */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
312 1184, 1328, 0, 768, 771, 777, 806, 0,
313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x12 - 1024x768@75Hz */
315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
316 1136, 1312, 0, 768, 769, 772, 800, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x13 - 1024x768@85Hz */
319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
320 1168, 1376, 0, 768, 769, 772, 808, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x14 - 1024x768@120Hz RB */
323 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
324 1104, 1184, 0, 768, 771, 775, 813, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x15 - 1152x864@75Hz */
327 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
328 1344, 1600, 0, 864, 865, 868, 900, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x55 - 1280x720@60Hz */
331 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
332 1430, 1650, 0, 720, 725, 730, 750, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x16 - 1280x768@60Hz RB */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
336 1360, 1440, 0, 768, 771, 778, 790, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x17 - 1280x768@60Hz */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
340 1472, 1664, 0, 768, 771, 778, 798, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x18 - 1280x768@75Hz */
343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
344 1488, 1696, 0, 768, 771, 778, 805, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x19 - 1280x768@85Hz */
347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
348 1496, 1712, 0, 768, 771, 778, 809, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1a - 1280x768@120Hz RB */
351 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
352 1360, 1440, 0, 768, 771, 778, 813, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x1b - 1280x800@60Hz RB */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
356 1360, 1440, 0, 800, 803, 809, 823, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
358 /* 0x1c - 1280x800@60Hz */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
360 1480, 1680, 0, 800, 803, 809, 831, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x1d - 1280x800@75Hz */
363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
364 1488, 1696, 0, 800, 803, 809, 838, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x1e - 1280x800@85Hz */
367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
368 1496, 1712, 0, 800, 803, 809, 843, 0,
369 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x1f - 1280x800@120Hz RB */
371 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
372 1360, 1440, 0, 800, 803, 809, 847, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x20 - 1280x960@60Hz */
375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
376 1488, 1800, 0, 960, 961, 964, 1000, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x21 - 1280x960@85Hz */
379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
380 1504, 1728, 0, 960, 961, 964, 1011, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x22 - 1280x960@120Hz RB */
383 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
384 1360, 1440, 0, 960, 963, 967, 1017, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386 /* 0x23 - 1280x1024@60Hz */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x24 - 1280x1024@75Hz */
391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
392 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x25 - 1280x1024@85Hz */
395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
396 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x26 - 1280x1024@120Hz RB */
399 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
400 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x27 - 1360x768@60Hz */
403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
404 1536, 1792, 0, 768, 771, 777, 795, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x28 - 1360x768@120Hz RB */
407 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
408 1440, 1520, 0, 768, 771, 776, 813, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x51 - 1366x768@60Hz */
411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
412 1579, 1792, 0, 768, 771, 774, 798, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x56 - 1366x768@60Hz */
415 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
416 1436, 1500, 0, 768, 769, 772, 800, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x29 - 1400x1050@60Hz RB */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
420 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x2a - 1400x1050@60Hz */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
424 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x2b - 1400x1050@75Hz */
427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
428 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x2c - 1400x1050@85Hz */
431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
432 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x2d - 1400x1050@120Hz RB */
435 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
436 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x2e - 1440x900@60Hz RB */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
440 1520, 1600, 0, 900, 903, 909, 926, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
442 /* 0x2f - 1440x900@60Hz */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
444 1672, 1904, 0, 900, 903, 909, 934, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x30 - 1440x900@75Hz */
447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
448 1688, 1936, 0, 900, 903, 909, 942, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x31 - 1440x900@85Hz */
451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
452 1696, 1952, 0, 900, 903, 909, 948, 0,
453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x32 - 1440x900@120Hz RB */
455 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
456 1520, 1600, 0, 900, 903, 909, 953, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
458 /* 0x53 - 1600x900@60Hz */
459 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
460 1704, 1800, 0, 900, 901, 904, 1000, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x33 - 1600x1200@60Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x34 - 1600x1200@65Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x35 - 1600x1200@70Hz */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x36 - 1600x1200@75Hz */
475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x37 - 1600x1200@85Hz */
479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
480 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x38 - 1600x1200@120Hz RB */
483 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
484 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x39 - 1680x1050@60Hz RB */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
488 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 0x3a - 1680x1050@60Hz */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
492 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x3b - 1680x1050@75Hz */
495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
496 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3c - 1680x1050@85Hz */
499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
500 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x3d - 1680x1050@120Hz RB */
503 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
504 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x3e - 1792x1344@60Hz */
507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
508 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x3f - 1792x1344@75Hz */
511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
512 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x40 - 1792x1344@120Hz RB */
515 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
516 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x41 - 1856x1392@60Hz */
519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
520 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x42 - 1856x1392@75Hz */
523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
524 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x43 - 1856x1392@120Hz RB */
527 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
528 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x52 - 1920x1080@60Hz */
531 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
532 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x44 - 1920x1200@60Hz RB */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
536 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
538 /* 0x45 - 1920x1200@60Hz */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
540 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x46 - 1920x1200@75Hz */
543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
544 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x47 - 1920x1200@85Hz */
547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
548 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x48 - 1920x1200@120Hz RB */
551 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
552 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x49 - 1920x1440@60Hz */
555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
556 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4a - 1920x1440@75Hz */
559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
560 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4b - 1920x1440@120Hz RB */
563 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
564 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
566 /* 0x54 - 2048x1152@60Hz */
567 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
568 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4c - 2560x1600@60Hz RB */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
572 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x4d - 2560x1600@60Hz */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
576 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
578 /* 0x4e - 2560x1600@75Hz */
579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
580 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
582 /* 0x4f - 2560x1600@85Hz */
583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
584 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
586 /* 0x50 - 2560x1600@120Hz RB */
587 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
588 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
590 /* 0x57 - 4096x2160@60Hz RB */
591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
595 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
596 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 * These more or less come from the DMT spec. The 720x400 modes are
602 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
603 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
604 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
607 * The DMT modes have been fact-checked; the rest are mild guesses.
609 static const struct drm_display_mode edid_est_modes[] = {
610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
611 968, 1056, 0, 600, 601, 605, 628, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
613 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
614 896, 1024, 0, 600, 601, 603, 625, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
616 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
617 720, 840, 0, 480, 481, 484, 500, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
619 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
620 704, 832, 0, 480, 489, 492, 520, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
622 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
623 768, 864, 0, 480, 483, 486, 525, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
625 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
626 752, 800, 0, 480, 490, 492, 525, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
628 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
629 846, 900, 0, 400, 421, 423, 449, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
631 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
632 846, 900, 0, 400, 412, 414, 449, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
634 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
635 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
637 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
638 1136, 1312, 0, 768, 769, 772, 800, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
640 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
641 1184, 1328, 0, 768, 771, 777, 806, 0,
642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
643 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
644 1184, 1344, 0, 768, 771, 777, 806, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
646 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
647 1208, 1264, 0, 768, 768, 776, 817, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
649 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
650 928, 1152, 0, 624, 625, 628, 667, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
652 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
653 896, 1056, 0, 600, 601, 604, 625, 0,
654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
655 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
656 976, 1040, 0, 600, 637, 643, 666, 0,
657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
658 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
659 1344, 1600, 0, 864, 865, 868, 900, 0,
660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
670 static const struct minimode est3_modes[] = {
678 { 1024, 768, 85, 0 },
679 { 1152, 864, 75, 0 },
681 { 1280, 768, 60, 1 },
682 { 1280, 768, 60, 0 },
683 { 1280, 768, 75, 0 },
684 { 1280, 768, 85, 0 },
685 { 1280, 960, 60, 0 },
686 { 1280, 960, 85, 0 },
687 { 1280, 1024, 60, 0 },
688 { 1280, 1024, 85, 0 },
690 { 1360, 768, 60, 0 },
691 { 1440, 900, 60, 1 },
692 { 1440, 900, 60, 0 },
693 { 1440, 900, 75, 0 },
694 { 1440, 900, 85, 0 },
695 { 1400, 1050, 60, 1 },
696 { 1400, 1050, 60, 0 },
697 { 1400, 1050, 75, 0 },
699 { 1400, 1050, 85, 0 },
700 { 1680, 1050, 60, 1 },
701 { 1680, 1050, 60, 0 },
702 { 1680, 1050, 75, 0 },
703 { 1680, 1050, 85, 0 },
704 { 1600, 1200, 60, 0 },
705 { 1600, 1200, 65, 0 },
706 { 1600, 1200, 70, 0 },
708 { 1600, 1200, 75, 0 },
709 { 1600, 1200, 85, 0 },
710 { 1792, 1344, 60, 0 },
711 { 1792, 1344, 75, 0 },
712 { 1856, 1392, 60, 0 },
713 { 1856, 1392, 75, 0 },
714 { 1920, 1200, 60, 1 },
715 { 1920, 1200, 60, 0 },
717 { 1920, 1200, 75, 0 },
718 { 1920, 1200, 85, 0 },
719 { 1920, 1440, 60, 0 },
720 { 1920, 1440, 75, 0 },
723 static const struct minimode extra_modes[] = {
724 { 1024, 576, 60, 0 },
725 { 1366, 768, 60, 0 },
726 { 1600, 900, 60, 0 },
727 { 1680, 945, 60, 0 },
728 { 1920, 1080, 60, 0 },
729 { 2048, 1152, 60, 0 },
730 { 2048, 1536, 60, 0 },
734 * From CEA/CTA-861 spec.
736 * Do not access directly, instead always use cea_mode_for_vic().
738 static const struct drm_display_mode edid_cea_modes_1[] = {
739 /* 1 - 640x480@60Hz 4:3 */
740 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
741 752, 800, 0, 480, 490, 492, 525, 0,
742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
744 /* 2 - 720x480@60Hz 4:3 */
745 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
746 798, 858, 0, 480, 489, 495, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
748 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
749 /* 3 - 720x480@60Hz 16:9 */
750 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
751 798, 858, 0, 480, 489, 495, 525, 0,
752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
753 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
754 /* 4 - 1280x720@60Hz 16:9 */
755 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
756 1430, 1650, 0, 720, 725, 730, 750, 0,
757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 5 - 1920x1080i@60Hz 16:9 */
760 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
761 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
762 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
763 DRM_MODE_FLAG_INTERLACE),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 6 - 720(1440)x480i@60Hz 4:3 */
766 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 480, 488, 494, 525, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 7 - 720(1440)x480i@60Hz 16:9 */
772 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 480, 488, 494, 525, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 8 - 720(1440)x240@60Hz 4:3 */
778 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
779 801, 858, 0, 240, 244, 247, 262, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_DBLCLK),
782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 9 - 720(1440)x240@60Hz 16:9 */
784 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
785 801, 858, 0, 240, 244, 247, 262, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_DBLCLK),
788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 10 - 2880x480i@60Hz 4:3 */
790 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 480, 488, 494, 525, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
793 DRM_MODE_FLAG_INTERLACE),
794 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795 /* 11 - 2880x480i@60Hz 16:9 */
796 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
797 3204, 3432, 0, 480, 488, 494, 525, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
799 DRM_MODE_FLAG_INTERLACE),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 12 - 2880x240@60Hz 4:3 */
802 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
803 3204, 3432, 0, 240, 244, 247, 262, 0,
804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 13 - 2880x240@60Hz 16:9 */
807 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 240, 244, 247, 262, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
811 /* 14 - 1440x480@60Hz 4:3 */
812 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
813 1596, 1716, 0, 480, 489, 495, 525, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
816 /* 15 - 1440x480@60Hz 16:9 */
817 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
818 1596, 1716, 0, 480, 489, 495, 525, 0,
819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 16 - 1920x1080@60Hz 16:9 */
822 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
823 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 17 - 720x576@50Hz 4:3 */
827 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
828 796, 864, 0, 576, 581, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
831 /* 18 - 720x576@50Hz 16:9 */
832 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
833 796, 864, 0, 576, 581, 586, 625, 0,
834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
835 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
836 /* 19 - 1280x720@50Hz 16:9 */
837 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
838 1760, 1980, 0, 720, 725, 730, 750, 0,
839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 20 - 1920x1080i@50Hz 16:9 */
842 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
843 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
845 DRM_MODE_FLAG_INTERLACE),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 21 - 720(1440)x576i@50Hz 4:3 */
848 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 576, 580, 586, 625, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 22 - 720(1440)x576i@50Hz 16:9 */
854 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 576, 580, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 23 - 720(1440)x288@50Hz 4:3 */
860 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
861 795, 864, 0, 288, 290, 293, 312, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_DBLCLK),
864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 24 - 720(1440)x288@50Hz 16:9 */
866 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
867 795, 864, 0, 288, 290, 293, 312, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
869 DRM_MODE_FLAG_DBLCLK),
870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 25 - 2880x576i@50Hz 4:3 */
872 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 576, 580, 586, 625, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
875 DRM_MODE_FLAG_INTERLACE),
876 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877 /* 26 - 2880x576i@50Hz 16:9 */
878 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
879 3180, 3456, 0, 576, 580, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
881 DRM_MODE_FLAG_INTERLACE),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 27 - 2880x288@50Hz 4:3 */
884 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
885 3180, 3456, 0, 288, 290, 293, 312, 0,
886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 28 - 2880x288@50Hz 16:9 */
889 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 288, 290, 293, 312, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 29 - 1440x576@50Hz 4:3 */
894 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
895 1592, 1728, 0, 576, 581, 586, 625, 0,
896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
898 /* 30 - 1440x576@50Hz 16:9 */
899 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
900 1592, 1728, 0, 576, 581, 586, 625, 0,
901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 31 - 1920x1080@50Hz 16:9 */
904 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
905 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 32 - 1920x1080@24Hz 16:9 */
909 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
910 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 33 - 1920x1080@25Hz 16:9 */
914 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
915 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 34 - 1920x1080@30Hz 16:9 */
919 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
920 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 35 - 2880x480@60Hz 4:3 */
924 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
925 3192, 3432, 0, 480, 489, 495, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
928 /* 36 - 2880x480@60Hz 16:9 */
929 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
930 3192, 3432, 0, 480, 489, 495, 525, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
932 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 37 - 2880x576@50Hz 4:3 */
934 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
935 3184, 3456, 0, 576, 581, 586, 625, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
937 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
938 /* 38 - 2880x576@50Hz 16:9 */
939 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
940 3184, 3456, 0, 576, 581, 586, 625, 0,
941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 39 - 1920x1080i@50Hz 16:9 */
944 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
945 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
947 DRM_MODE_FLAG_INTERLACE),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 40 - 1920x1080i@100Hz 16:9 */
950 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
951 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
953 DRM_MODE_FLAG_INTERLACE),
954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 41 - 1280x720@100Hz 16:9 */
956 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
957 1760, 1980, 0, 720, 725, 730, 750, 0,
958 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 42 - 720x576@100Hz 4:3 */
961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
962 796, 864, 0, 576, 581, 586, 625, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
965 /* 43 - 720x576@100Hz 16:9 */
966 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
967 796, 864, 0, 576, 581, 586, 625, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 44 - 720(1440)x576i@100Hz 4:3 */
971 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
972 795, 864, 0, 576, 580, 586, 625, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
974 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 45 - 720(1440)x576i@100Hz 16:9 */
977 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
978 795, 864, 0, 576, 580, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
980 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
981 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 46 - 1920x1080i@120Hz 16:9 */
983 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
984 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
986 DRM_MODE_FLAG_INTERLACE),
987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 47 - 1280x720@120Hz 16:9 */
989 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
990 1430, 1650, 0, 720, 725, 730, 750, 0,
991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 48 - 720x480@120Hz 4:3 */
994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
995 798, 858, 0, 480, 489, 495, 525, 0,
996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
997 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
998 /* 49 - 720x480@120Hz 16:9 */
999 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1000 798, 858, 0, 480, 489, 495, 525, 0,
1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 /* 50 - 720(1440)x480i@120Hz 4:3 */
1004 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1005 801, 858, 0, 480, 488, 494, 525, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1007 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 51 - 720(1440)x480i@120Hz 16:9 */
1010 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1011 801, 858, 0, 480, 488, 494, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1013 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1015 /* 52 - 720x576@200Hz 4:3 */
1016 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1017 796, 864, 0, 576, 581, 586, 625, 0,
1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 53 - 720x576@200Hz 16:9 */
1021 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1022 796, 864, 0, 576, 581, 586, 625, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 54 - 720(1440)x576i@200Hz 4:3 */
1026 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1027 795, 864, 0, 576, 580, 586, 625, 0,
1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1029 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031 /* 55 - 720(1440)x576i@200Hz 16:9 */
1032 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1033 795, 864, 0, 576, 580, 586, 625, 0,
1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1035 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1037 /* 56 - 720x480@240Hz 4:3 */
1038 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1039 798, 858, 0, 480, 489, 495, 525, 0,
1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042 /* 57 - 720x480@240Hz 16:9 */
1043 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1044 798, 858, 0, 480, 489, 495, 525, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047 /* 58 - 720(1440)x480i@240Hz 4:3 */
1048 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1049 801, 858, 0, 480, 488, 494, 525, 0,
1050 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1051 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053 /* 59 - 720(1440)x480i@240Hz 16:9 */
1054 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1055 801, 858, 0, 480, 488, 494, 525, 0,
1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1057 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 60 - 1280x720@24Hz 16:9 */
1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1061 3080, 3300, 0, 720, 725, 730, 750, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 61 - 1280x720@25Hz 16:9 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1066 3740, 3960, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1069 /* 62 - 1280x720@30Hz 16:9 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1071 3080, 3300, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1074 /* 63 - 1920x1080@120Hz 16:9 */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1076 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1079 /* 64 - 1920x1080@100Hz 16:9 */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1081 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1084 /* 65 - 1280x720@24Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1086 3080, 3300, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 66 - 1280x720@25Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1091 3740, 3960, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 67 - 1280x720@30Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1096 3080, 3300, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 68 - 1280x720@50Hz 64:27 */
1100 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1101 1760, 1980, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 69 - 1280x720@60Hz 64:27 */
1105 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1106 1430, 1650, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 70 - 1280x720@100Hz 64:27 */
1110 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1111 1760, 1980, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 71 - 1280x720@120Hz 64:27 */
1115 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1116 1430, 1650, 0, 720, 725, 730, 750, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 72 - 1920x1080@24Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1121 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 73 - 1920x1080@25Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 74 - 1920x1080@30Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 75 - 1920x1080@50Hz 64:27 */
1135 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1136 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 76 - 1920x1080@60Hz 64:27 */
1140 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1141 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 77 - 1920x1080@100Hz 64:27 */
1145 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1146 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 78 - 1920x1080@120Hz 64:27 */
1150 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1151 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 79 - 1680x720@24Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1156 3080, 3300, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 80 - 1680x720@25Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1161 2948, 3168, 0, 720, 725, 730, 750, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 81 - 1680x720@30Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1166 2420, 2640, 0, 720, 725, 730, 750, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 82 - 1680x720@50Hz 64:27 */
1170 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1171 1980, 2200, 0, 720, 725, 730, 750, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 83 - 1680x720@60Hz 64:27 */
1175 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1176 1980, 2200, 0, 720, 725, 730, 750, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 84 - 1680x720@100Hz 64:27 */
1180 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1181 1780, 2000, 0, 720, 725, 730, 825, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 85 - 1680x720@120Hz 64:27 */
1185 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1186 1780, 2000, 0, 720, 725, 730, 825, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 86 - 2560x1080@24Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1191 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 87 - 2560x1080@25Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1196 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 88 - 2560x1080@30Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1201 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 89 - 2560x1080@50Hz 64:27 */
1205 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1206 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1209 /* 90 - 2560x1080@60Hz 64:27 */
1210 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1211 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1214 /* 91 - 2560x1080@100Hz 64:27 */
1215 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1216 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 92 - 2560x1080@120Hz 64:27 */
1220 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1221 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1224 /* 93 - 3840x2160@24Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1226 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 94 - 3840x2160@25Hz 16:9 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1231 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1234 /* 95 - 3840x2160@30Hz 16:9 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1236 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1239 /* 96 - 3840x2160@50Hz 16:9 */
1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1241 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1244 /* 97 - 3840x2160@60Hz 16:9 */
1245 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1246 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1249 /* 98 - 4096x2160@24Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1251 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 99 - 4096x2160@25Hz 256:135 */
1255 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1256 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1259 /* 100 - 4096x2160@30Hz 256:135 */
1260 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1261 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1264 /* 101 - 4096x2160@50Hz 256:135 */
1265 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1266 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1269 /* 102 - 4096x2160@60Hz 256:135 */
1270 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1271 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1274 /* 103 - 3840x2160@24Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1276 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 104 - 3840x2160@25Hz 64:27 */
1280 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1281 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1284 /* 105 - 3840x2160@30Hz 64:27 */
1285 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1286 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 106 - 3840x2160@50Hz 64:27 */
1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1291 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 107 - 3840x2160@60Hz 64:27 */
1295 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1296 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1299 /* 108 - 1280x720@48Hz 16:9 */
1300 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1301 2280, 2500, 0, 720, 725, 730, 750, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1304 /* 109 - 1280x720@48Hz 64:27 */
1305 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1306 2280, 2500, 0, 720, 725, 730, 750, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 110 - 1680x720@48Hz 64:27 */
1310 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1311 2530, 2750, 0, 720, 725, 730, 750, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1314 /* 111 - 1920x1080@48Hz 16:9 */
1315 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1316 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1319 /* 112 - 1920x1080@48Hz 64:27 */
1320 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1321 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 113 - 2560x1080@48Hz 64:27 */
1325 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1326 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1329 /* 114 - 3840x2160@48Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1331 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334 /* 115 - 4096x2160@48Hz 256:135 */
1335 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1336 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1339 /* 116 - 3840x2160@48Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1341 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344 /* 117 - 3840x2160@100Hz 16:9 */
1345 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1346 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1349 /* 118 - 3840x2160@120Hz 16:9 */
1350 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1351 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1354 /* 119 - 3840x2160@100Hz 64:27 */
1355 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1356 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 120 - 3840x2160@120Hz 64:27 */
1360 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1361 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 121 - 5120x2160@24Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1366 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 122 - 5120x2160@25Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1371 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 123 - 5120x2160@30Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1376 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379 /* 124 - 5120x2160@48Hz 64:27 */
1380 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1381 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1383 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1384 /* 125 - 5120x2160@50Hz 64:27 */
1385 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1386 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1388 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1389 /* 126 - 5120x2160@60Hz 64:27 */
1390 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1391 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1393 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1394 /* 127 - 5120x2160@100Hz 64:27 */
1395 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1396 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1398 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1402 * From CEA/CTA-861 spec.
1404 * Do not access directly, instead always use cea_mode_for_vic().
1406 static const struct drm_display_mode edid_cea_modes_193[] = {
1407 /* 193 - 5120x2160@120Hz 64:27 */
1408 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1409 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1412 /* 194 - 7680x4320@24Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1414 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 195 - 7680x4320@25Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1419 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 196 - 7680x4320@30Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1424 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 197 - 7680x4320@48Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1429 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 198 - 7680x4320@50Hz 16:9 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1434 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1437 /* 199 - 7680x4320@60Hz 16:9 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1439 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1442 /* 200 - 7680x4320@100Hz 16:9 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1444 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1447 /* 201 - 7680x4320@120Hz 16:9 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1449 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1452 /* 202 - 7680x4320@24Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1454 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 203 - 7680x4320@25Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1459 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 204 - 7680x4320@30Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1464 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 205 - 7680x4320@48Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1469 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 206 - 7680x4320@50Hz 64:27 */
1473 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1474 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 207 - 7680x4320@60Hz 64:27 */
1478 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1479 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 208 - 7680x4320@100Hz 64:27 */
1483 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1484 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 209 - 7680x4320@120Hz 64:27 */
1488 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1489 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 210 - 10240x4320@24Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1494 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 211 - 10240x4320@25Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1499 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 212 - 10240x4320@30Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1504 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 213 - 10240x4320@48Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1509 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 214 - 10240x4320@50Hz 64:27 */
1513 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1514 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1517 /* 215 - 10240x4320@60Hz 64:27 */
1518 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1519 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1522 /* 216 - 10240x4320@100Hz 64:27 */
1523 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1524 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1526 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1527 /* 217 - 10240x4320@120Hz 64:27 */
1528 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1529 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1531 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1532 /* 218 - 4096x2160@100Hz 256:135 */
1533 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1534 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1537 /* 219 - 4096x2160@120Hz 256:135 */
1538 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1539 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1545 * HDMI 1.4 4k modes. Index using the VIC.
1547 static const struct drm_display_mode edid_4k_modes[] = {
1548 /* 0 - dummy, VICs start at 1 */
1550 /* 1 - 3840x2160@30Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 4016, 4104, 4400, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1556 /* 2 - 3840x2160@25Hz */
1557 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 3840, 4896, 4984, 5280, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1562 /* 3 - 3840x2160@24Hz */
1563 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1564 3840, 5116, 5204, 5500, 0,
1565 2160, 2168, 2178, 2250, 0,
1566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1567 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1568 /* 4 - 4096x2160@24Hz (SMPTE) */
1569 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1570 4096, 5116, 5204, 5500, 0,
1571 2160, 2168, 2178, 2250, 0,
1572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1573 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1576 /*** DDC fetch and block validation ***/
1579 * The opaque EDID type, internal to drm_edid.c.
1582 /* Size allocated for edid */
1584 const struct edid *edid;
1587 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1589 static int edid_hfeeodb_block_count(const struct edid *edid)
1591 int eeodb = edid_hfeeodb_extension_block_count(edid);
1593 return eeodb ? eeodb + 1 : 0;
1596 static int edid_extension_block_count(const struct edid *edid)
1598 return edid->extensions;
1601 static int edid_block_count(const struct edid *edid)
1603 return edid_extension_block_count(edid) + 1;
1606 static int edid_size_by_blocks(int num_blocks)
1608 return num_blocks * EDID_LENGTH;
1611 static int edid_size(const struct edid *edid)
1613 return edid_size_by_blocks(edid_block_count(edid));
1616 static const void *edid_block_data(const struct edid *edid, int index)
1618 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1620 return edid + index;
1623 static const void *edid_extension_block_data(const struct edid *edid, int index)
1625 return edid_block_data(edid, index + 1);
1628 /* EDID block count indicated in EDID, may exceed allocated size */
1629 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1633 /* Starting point */
1634 num_blocks = edid_block_count(drm_edid->edid);
1636 /* HF-EEODB override */
1637 if (drm_edid->size >= edid_size_by_blocks(2)) {
1641 * Note: HF-EEODB may specify a smaller extension count than the
1642 * regular one. Unlike in buffer allocation, here we can use it.
1644 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1652 /* EDID block count, limited by allocated size */
1653 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1655 /* Limit by allocated size */
1656 return min(__drm_edid_block_count(drm_edid),
1657 (int)drm_edid->size / EDID_LENGTH);
1660 /* EDID extension block count, limited by allocated size */
1661 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1663 return drm_edid_block_count(drm_edid) - 1;
1666 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1668 return edid_block_data(drm_edid->edid, index);
1671 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1674 return edid_extension_block_data(drm_edid->edid, index);
1678 * Initializer helper for legacy interfaces, where we have no choice but to
1679 * trust edid size. Not for general purpose use.
1681 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1682 const struct edid *edid)
1687 memset(drm_edid, 0, sizeof(*drm_edid));
1689 drm_edid->edid = edid;
1690 drm_edid->size = edid_size(edid);
1696 * EDID base and extension block iterator.
1698 * struct drm_edid_iter iter;
1701 * drm_edid_iter_begin(drm_edid, &iter);
1702 * drm_edid_iter_for_each(block, &iter) {
1703 * // do stuff with block
1705 * drm_edid_iter_end(&iter);
1707 struct drm_edid_iter {
1708 const struct drm_edid *drm_edid;
1710 /* Current block index. */
1714 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1715 struct drm_edid_iter *iter)
1717 memset(iter, 0, sizeof(*iter));
1719 iter->drm_edid = drm_edid;
1722 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1724 const void *block = NULL;
1726 if (!iter->drm_edid)
1729 if (iter->index < drm_edid_block_count(iter->drm_edid))
1730 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1735 #define drm_edid_iter_for_each(__block, __iter) \
1736 while (((__block) = __drm_edid_iter_next(__iter)))
1738 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1740 memset(iter, 0, sizeof(*iter));
1743 static const u8 edid_header[] = {
1744 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1747 static void edid_header_fix(void *edid)
1749 memcpy(edid, edid_header, sizeof(edid_header));
1753 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1754 * @_edid: pointer to raw base EDID block
1756 * Sanity check the header of the base EDID block.
1758 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1760 int drm_edid_header_is_valid(const void *_edid)
1762 const struct edid *edid = _edid;
1765 for (i = 0; i < sizeof(edid_header); i++) {
1766 if (edid->header[i] == edid_header[i])
1772 EXPORT_SYMBOL(drm_edid_header_is_valid);
1774 static int edid_fixup __read_mostly = 6;
1775 module_param_named(edid_fixup, edid_fixup, int, 0400);
1776 MODULE_PARM_DESC(edid_fixup,
1777 "Minimum number of valid EDID header bytes (0-8, default 6)");
1779 static int edid_block_compute_checksum(const void *_block)
1781 const u8 *block = _block;
1783 u8 csum = 0, crc = 0;
1785 for (i = 0; i < EDID_LENGTH - 1; i++)
1793 static int edid_block_get_checksum(const void *_block)
1795 const struct edid *block = _block;
1797 return block->checksum;
1800 static int edid_block_tag(const void *_block)
1802 const u8 *block = _block;
1807 static bool edid_block_is_zero(const void *edid)
1809 return !memchr_inv(edid, 0, EDID_LENGTH);
1813 * drm_edid_are_equal - compare two edid blobs.
1814 * @edid1: pointer to first blob
1815 * @edid2: pointer to second blob
1816 * This helper can be used during probing to determine if
1819 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1821 int edid1_len, edid2_len;
1822 bool edid1_present = edid1 != NULL;
1823 bool edid2_present = edid2 != NULL;
1825 if (edid1_present != edid2_present)
1829 edid1_len = edid_size(edid1);
1830 edid2_len = edid_size(edid2);
1832 if (edid1_len != edid2_len)
1835 if (memcmp(edid1, edid2, edid1_len))
1841 EXPORT_SYMBOL(drm_edid_are_equal);
1843 enum edid_block_status {
1845 EDID_BLOCK_READ_FAIL,
1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1855 static enum edid_block_status edid_block_check(const void *_block,
1858 const struct edid *block = _block;
1861 return EDID_BLOCK_NULL;
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1870 return EDID_BLOCK_HEADER_CORRUPT;
1874 return EDID_BLOCK_HEADER_REPAIR;
1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1881 return EDID_BLOCK_CHECKSUM;
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1889 return EDID_BLOCK_OK;
1892 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1899 static bool edid_block_valid(const void *block, bool base)
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1905 static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1952 static void edid_block_dump(const char *level, const void *block, int block_num)
1954 enum edid_block_status status;
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 sprintf(prefix, "\t[%02x] BAD ", block_num);
1963 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1970 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1971 * @_block: pointer to raw EDID block
1972 * @block_num: type of block to validate (0 for base, extension otherwise)
1973 * @print_bad_edid: if true, dump bad EDID blocks to the console
1974 * @edid_corrupt: if true, the header or checksum is invalid
1976 * Validate a base or extension EDID block and optionally dump bad blocks to
1979 * Return: True if the block is valid, false otherwise.
1981 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1984 struct edid *block = (struct edid *)_block;
1985 enum edid_block_status status;
1986 bool is_base_block = block_num == 0;
1989 if (WARN_ON(!block))
1992 status = edid_block_check(block, is_base_block);
1993 if (status == EDID_BLOCK_HEADER_REPAIR) {
1994 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1995 edid_header_fix(block);
1997 /* Retry with fixed header, update status if that worked. */
1998 status = edid_block_check(block, is_base_block);
1999 if (status == EDID_BLOCK_OK)
2000 status = EDID_BLOCK_HEADER_FIXED;
2005 * Unknown major version isn't corrupt but we can't use it. Only
2006 * the base block can reset edid_corrupt to false.
2008 if (is_base_block &&
2009 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2010 *edid_corrupt = false;
2011 else if (status != EDID_BLOCK_OK)
2012 *edid_corrupt = true;
2015 edid_block_status_print(status, block, block_num);
2017 /* Determine whether we can use this block with this status. */
2018 valid = edid_block_status_valid(status, edid_block_tag(block));
2020 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2021 pr_notice("Raw EDID:\n");
2022 edid_block_dump(KERN_NOTICE, block, block_num);
2027 EXPORT_SYMBOL(drm_edid_block_valid);
2030 * drm_edid_is_valid - sanity check EDID data
2033 * Sanity-check an entire EDID record (including extensions)
2035 * Return: True if the EDID data is valid, false otherwise.
2037 bool drm_edid_is_valid(struct edid *edid)
2044 for (i = 0; i < edid_block_count(edid); i++) {
2045 void *block = (void *)edid_block_data(edid, i);
2047 if (!drm_edid_block_valid(block, i, true, NULL))
2053 EXPORT_SYMBOL(drm_edid_is_valid);
2056 * drm_edid_valid - sanity check EDID data
2057 * @drm_edid: EDID data
2059 * Sanity check an EDID. Cross check block count against allocated size and
2060 * checksum the blocks.
2062 * Return: True if the EDID data is valid, false otherwise.
2064 bool drm_edid_valid(const struct drm_edid *drm_edid)
2071 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2075 const void *block = drm_edid_block_data(drm_edid, i);
2077 if (!edid_block_valid(block, i == 0))
2083 EXPORT_SYMBOL(drm_edid_valid);
2085 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2089 int i, valid_blocks = 0;
2092 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2093 * back to regular extension count here. We don't want to start
2094 * modifying the HF-EEODB extension too.
2096 for (i = 0; i < edid_block_count(edid); i++) {
2097 const void *src_block = edid_block_data(edid, i);
2099 if (edid_block_valid(src_block, i == 0)) {
2100 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2102 memmove(dst_block, src_block, EDID_LENGTH);
2107 /* We already trusted the base block to be valid here... */
2108 if (WARN_ON(!valid_blocks)) {
2113 edid->extensions = valid_blocks - 1;
2114 edid->checksum = edid_block_compute_checksum(edid);
2116 *alloc_size = edid_size_by_blocks(valid_blocks);
2118 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2125 #define DDC_SEGMENT_ADDR 0x30
2127 * drm_do_probe_ddc_edid() - get EDID information via I2C
2128 * @data: I2C device adapter
2129 * @buf: EDID data buffer to be filled
2130 * @block: 128 byte EDID block to start fetching from
2131 * @len: EDID data buffer length to fetch
2133 * Try to fetch EDID information by calling I2C driver functions.
2135 * Return: 0 on success or -1 on failure.
2138 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2140 struct i2c_adapter *adapter = data;
2141 unsigned char start = block * EDID_LENGTH;
2142 unsigned char segment = block >> 1;
2143 unsigned char xfers = segment ? 3 : 2;
2144 int ret, retries = 5;
2147 * The core I2C driver will automatically retry the transfer if the
2148 * adapter reports EAGAIN. However, we find that bit-banging transfers
2149 * are susceptible to errors under a heavily loaded machine and
2150 * generate spurious NAKs and timeouts. Retrying the transfer
2151 * of the individual block a few times seems to overcome this.
2154 struct i2c_msg msgs[] = {
2156 .addr = DDC_SEGMENT_ADDR,
2174 * Avoid sending the segment addr to not upset non-compliant
2177 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2179 if (ret == -ENXIO) {
2180 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2184 } while (ret != xfers && --retries);
2186 return ret == xfers ? 0 : -1;
2189 static void connector_bad_edid(struct drm_connector *connector,
2190 const struct edid *edid, int num_blocks)
2196 * 0x7e in the EDID is the number of extension blocks. The EDID
2197 * is 1 (base block) + num_ext_blocks big. That means we can think
2198 * of 0x7e in the EDID of the _index_ of the last block in the
2199 * combined chunk of memory.
2201 last_block = edid->extensions;
2203 /* Calculate real checksum for the last edid extension block data */
2204 if (last_block < num_blocks)
2205 connector->real_edid_checksum =
2206 edid_block_compute_checksum(edid + last_block);
2208 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2212 connector->base.id, connector->name);
2213 for (i = 0; i < num_blocks; i++)
2214 edid_block_dump(KERN_DEBUG, edid + i, i);
2217 /* Get override or firmware EDID */
2218 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2220 const struct drm_edid *override = NULL;
2222 mutex_lock(&connector->edid_override_mutex);
2224 if (connector->edid_override)
2225 override = drm_edid_dup(connector->edid_override);
2227 mutex_unlock(&connector->edid_override_mutex);
2230 override = drm_edid_load_firmware(connector);
2232 return IS_ERR(override) ? NULL : override;
2235 /* For debugfs edid_override implementation */
2236 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2238 const struct drm_edid *drm_edid;
2240 mutex_lock(&connector->edid_override_mutex);
2242 drm_edid = connector->edid_override;
2244 seq_write(m, drm_edid->edid, drm_edid->size);
2246 mutex_unlock(&connector->edid_override_mutex);
2251 /* For debugfs edid_override implementation */
2252 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255 const struct drm_edid *drm_edid;
2257 drm_edid = drm_edid_alloc(edid, size);
2258 if (!drm_edid_valid(drm_edid)) {
2259 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2260 connector->base.id, connector->name);
2261 drm_edid_free(drm_edid);
2265 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2266 connector->base.id, connector->name);
2268 mutex_lock(&connector->edid_override_mutex);
2270 drm_edid_free(connector->edid_override);
2271 connector->edid_override = drm_edid;
2273 mutex_unlock(&connector->edid_override_mutex);
2278 /* For debugfs edid_override implementation */
2279 int drm_edid_override_reset(struct drm_connector *connector)
2281 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2282 connector->base.id, connector->name);
2284 mutex_lock(&connector->edid_override_mutex);
2286 drm_edid_free(connector->edid_override);
2287 connector->edid_override = NULL;
2289 mutex_unlock(&connector->edid_override_mutex);
2295 * drm_edid_override_connector_update - add modes from override/firmware EDID
2296 * @connector: connector we're probing
2298 * Add modes from the override/firmware EDID, if available. Only to be used from
2299 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2300 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303 * Return: The number of modes added or 0 if we couldn't find any.
2305 int drm_edid_override_connector_update(struct drm_connector *connector)
2307 const struct drm_edid *override;
2310 override = drm_edid_override_get(connector);
2312 if (drm_edid_connector_update(connector, override) == 0)
2313 num_modes = drm_edid_connector_add_modes(connector);
2315 drm_edid_free(override);
2317 drm_dbg_kms(connector->dev,
2318 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2319 connector->base.id, connector->name, num_modes);
2324 EXPORT_SYMBOL(drm_edid_override_connector_update);
2326 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2328 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2329 read_block_fn read_block,
2332 enum edid_block_status status;
2333 bool is_base_block = block_num == 0;
2336 for (try = 0; try < 4; try++) {
2337 if (read_block(context, block, block_num, EDID_LENGTH))
2338 return EDID_BLOCK_READ_FAIL;
2340 status = edid_block_check(block, is_base_block);
2341 if (status == EDID_BLOCK_HEADER_REPAIR) {
2342 edid_header_fix(block);
2344 /* Retry with fixed header, update status if that worked. */
2345 status = edid_block_check(block, is_base_block);
2346 if (status == EDID_BLOCK_OK)
2347 status = EDID_BLOCK_HEADER_FIXED;
2350 if (edid_block_status_valid(status, edid_block_tag(block)))
2353 /* Fail early for unrepairable base block all zeros. */
2354 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2361 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2362 read_block_fn read_block, void *context,
2365 enum edid_block_status status;
2366 int i, num_blocks, invalid_blocks = 0;
2367 const struct drm_edid *override;
2368 struct edid *edid, *new;
2369 size_t alloc_size = EDID_LENGTH;
2371 override = drm_edid_override_get(connector);
2373 alloc_size = override->size;
2374 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2375 drm_edid_free(override);
2381 edid = kmalloc(alloc_size, GFP_KERNEL);
2385 status = edid_block_read(edid, 0, read_block, context);
2387 edid_block_status_print(status, edid, 0);
2389 if (status == EDID_BLOCK_READ_FAIL)
2392 /* FIXME: Clarify what a corrupt EDID actually means. */
2393 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2394 connector->edid_corrupt = false;
2396 connector->edid_corrupt = true;
2398 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2399 if (status == EDID_BLOCK_ZERO)
2400 connector->null_edid_counter++;
2402 connector_bad_edid(connector, edid, 1);
2406 if (!edid_extension_block_count(edid))
2409 alloc_size = edid_size(edid);
2410 new = krealloc(edid, alloc_size, GFP_KERNEL);
2415 num_blocks = edid_block_count(edid);
2416 for (i = 1; i < num_blocks; i++) {
2417 void *block = (void *)edid_block_data(edid, i);
2419 status = edid_block_read(block, i, read_block, context);
2421 edid_block_status_print(status, block, i);
2423 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2424 if (status == EDID_BLOCK_READ_FAIL)
2427 } else if (i == 1) {
2429 * If the first EDID extension is a CTA extension, and
2430 * the first Data Block is HF-EEODB, override the
2431 * extension block count.
2433 * Note: HF-EEODB could specify a smaller extension
2434 * count too, but we can't risk allocating a smaller
2437 int eeodb = edid_hfeeodb_block_count(edid);
2439 if (eeodb > num_blocks) {
2441 alloc_size = edid_size_by_blocks(num_blocks);
2442 new = krealloc(edid, alloc_size, GFP_KERNEL);
2450 if (invalid_blocks) {
2451 connector_bad_edid(connector, edid, num_blocks);
2453 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2468 * drm_do_get_edid - get EDID data using a custom EDID block read function
2469 * @connector: connector we're probing
2470 * @read_block: EDID block read function
2471 * @context: private data passed to the block read function
2473 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2474 * exposes a different interface to read EDID blocks this function can be used
2475 * to get EDID data using a custom block read function.
2477 * As in the general case the DDC bus is accessible by the kernel at the I2C
2478 * level, drivers must make all reasonable efforts to expose it as an I2C
2479 * adapter and use drm_get_edid() instead of abusing this function.
2481 * The EDID may be overridden using debugfs override_edid or firmware EDID
2482 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2483 * order. Having either of them bypasses actual EDID reads.
2485 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2487 struct edid *drm_do_get_edid(struct drm_connector *connector,
2488 read_block_fn read_block,
2491 return _drm_do_get_edid(connector, read_block, context, NULL);
2493 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2496 * drm_edid_raw - Get a pointer to the raw EDID data.
2497 * @drm_edid: drm_edid container
2499 * Get a pointer to the raw EDID data.
2501 * This is for transition only. Avoid using this like the plague.
2503 * Return: Pointer to raw EDID data.
2505 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2507 if (!drm_edid || !drm_edid->size)
2511 * Do not return pointers where relying on EDID extension count would
2512 * lead to buffer overflow.
2514 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2517 return drm_edid->edid;
2519 EXPORT_SYMBOL(drm_edid_raw);
2521 /* Allocate struct drm_edid container *without* duplicating the edid data */
2522 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2524 struct drm_edid *drm_edid;
2526 if (!edid || !size || size < EDID_LENGTH)
2529 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2531 drm_edid->edid = edid;
2532 drm_edid->size = size;
2539 * drm_edid_alloc - Allocate a new drm_edid container
2540 * @edid: Pointer to raw EDID data
2541 * @size: Size of memory allocated for EDID
2543 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2544 * the actual size that has been allocated for the data. There is no validation
2545 * of the raw EDID data against the size, but at least the EDID base block must
2546 * fit in the buffer.
2548 * The returned pointer must be freed using drm_edid_free().
2550 * Return: drm_edid container, or NULL on errors
2552 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2554 const struct drm_edid *drm_edid;
2556 if (!edid || !size || size < EDID_LENGTH)
2559 edid = kmemdup(edid, size, GFP_KERNEL);
2563 drm_edid = _drm_edid_alloc(edid, size);
2569 EXPORT_SYMBOL(drm_edid_alloc);
2572 * drm_edid_dup - Duplicate a drm_edid container
2573 * @drm_edid: EDID to duplicate
2575 * The returned pointer must be freed using drm_edid_free().
2577 * Returns: drm_edid container copy, or NULL on errors
2579 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2584 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2586 EXPORT_SYMBOL(drm_edid_dup);
2589 * drm_edid_free - Free the drm_edid container
2590 * @drm_edid: EDID to free
2592 void drm_edid_free(const struct drm_edid *drm_edid)
2597 kfree(drm_edid->edid);
2600 EXPORT_SYMBOL(drm_edid_free);
2603 * drm_probe_ddc() - probe DDC presence
2604 * @adapter: I2C adapter to probe
2606 * Return: True on success, false on failure.
2609 drm_probe_ddc(struct i2c_adapter *adapter)
2613 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2615 EXPORT_SYMBOL(drm_probe_ddc);
2618 * drm_get_edid - get EDID data, if available
2619 * @connector: connector we're probing
2620 * @adapter: I2C adapter to use for DDC
2622 * Poke the given I2C channel to grab EDID data if possible. If found,
2623 * attach it to the connector.
2625 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2627 struct edid *drm_get_edid(struct drm_connector *connector,
2628 struct i2c_adapter *adapter)
2632 if (connector->force == DRM_FORCE_OFF)
2635 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2638 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2639 drm_connector_update_edid_property(connector, edid);
2642 EXPORT_SYMBOL(drm_get_edid);
2645 * drm_edid_read_custom - Read EDID data using given EDID block read function
2646 * @connector: Connector to use
2647 * @read_block: EDID block read function
2648 * @context: Private data passed to the block read function
2650 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2651 * exposes a different interface to read EDID blocks this function can be used
2652 * to get EDID data using a custom block read function.
2654 * As in the general case the DDC bus is accessible by the kernel at the I2C
2655 * level, drivers must make all reasonable efforts to expose it as an I2C
2656 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2659 * The EDID may be overridden using debugfs override_edid or firmware EDID
2660 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2661 * order. Having either of them bypasses actual EDID reads.
2663 * The returned pointer must be freed using drm_edid_free().
2665 * Return: Pointer to EDID, or NULL if probe/read failed.
2667 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2668 read_block_fn read_block,
2671 const struct drm_edid *drm_edid;
2675 edid = _drm_do_get_edid(connector, read_block, context, &size);
2679 /* Sanity check for now */
2680 drm_WARN_ON(connector->dev, !size);
2682 drm_edid = _drm_edid_alloc(edid, size);
2688 EXPORT_SYMBOL(drm_edid_read_custom);
2691 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2692 * @connector: Connector to use
2693 * @adapter: I2C adapter to use for DDC
2695 * Read EDID using the given I2C adapter.
2697 * The EDID may be overridden using debugfs override_edid or firmware EDID
2698 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2699 * order. Having either of them bypasses actual EDID reads.
2701 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2702 * using drm_edid_read() instead of this function.
2704 * The returned pointer must be freed using drm_edid_free().
2706 * Return: Pointer to EDID, or NULL if probe/read failed.
2708 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2709 struct i2c_adapter *adapter)
2711 const struct drm_edid *drm_edid;
2713 if (connector->force == DRM_FORCE_OFF)
2716 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2719 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2721 /* Note: Do *not* call connector updates here. */
2725 EXPORT_SYMBOL(drm_edid_read_ddc);
2728 * drm_edid_read - Read EDID data using connector's I2C adapter
2729 * @connector: Connector to use
2731 * Read EDID using the connector's I2C adapter.
2733 * The EDID may be overridden using debugfs override_edid or firmware EDID
2734 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2735 * order. Having either of them bypasses actual EDID reads.
2737 * The returned pointer must be freed using drm_edid_free().
2739 * Return: Pointer to EDID, or NULL if probe/read failed.
2741 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2743 if (drm_WARN_ON(connector->dev, !connector->ddc))
2746 return drm_edid_read_ddc(connector, connector->ddc);
2748 EXPORT_SYMBOL(drm_edid_read);
2750 static u32 edid_extract_panel_id(const struct edid *edid)
2753 * We represent the ID as a 32-bit number so it can easily be compared
2756 * NOTE that we deal with endianness differently for the top half
2757 * of this ID than for the bottom half. The bottom half (the product
2758 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2759 * that's how everyone seems to interpret it. The top half (the mfg_id)
2760 * gets stored as big endian because that makes
2761 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2762 * to write (it's easier to extract the ASCII). It doesn't really
2763 * matter, though, as long as the number here is unique.
2765 return (u32)edid->mfg_id[0] << 24 |
2766 (u32)edid->mfg_id[1] << 16 |
2767 (u32)EDID_PRODUCT_ID(edid);
2771 * drm_edid_get_panel_id - Get a panel's ID through DDC
2772 * @adapter: I2C adapter to use for DDC
2774 * This function reads the first block of the EDID of a panel and (assuming
2775 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2776 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2777 * supposed to be different for each different modem of panel.
2779 * This function is intended to be used during early probing on devices where
2780 * more than one panel might be present. Because of its intended use it must
2781 * assume that the EDID of the panel is correct, at least as far as the ID
2782 * is concerned (in other words, we don't process any overrides here).
2784 * NOTE: it's expected that this function and drm_do_get_edid() will both
2785 * be read the EDID, but there is no caching between them. Since we're only
2786 * reading the first block, hopefully this extra overhead won't be too big.
2788 * Return: A 32-bit ID that should be different for each make/model of panel.
2789 * See the functions drm_edid_encode_panel_id() and
2790 * drm_edid_decode_panel_id() for some details on the structure of this
2794 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2796 enum edid_block_status status;
2801 * There are no manufacturer IDs of 0, so if there is a problem reading
2802 * the EDID then we'll just return 0.
2805 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2809 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2811 edid_block_status_print(status, base_block, 0);
2813 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2814 panel_id = edid_extract_panel_id(base_block);
2816 edid_block_dump(KERN_NOTICE, base_block, 0);
2822 EXPORT_SYMBOL(drm_edid_get_panel_id);
2825 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2826 * @connector: connector we're probing
2827 * @adapter: I2C adapter to use for DDC
2829 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2830 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2831 * switch DDC to the GPU which is retrieving EDID.
2833 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2835 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2836 struct i2c_adapter *adapter)
2838 struct drm_device *dev = connector->dev;
2839 struct pci_dev *pdev = to_pci_dev(dev->dev);
2842 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2845 vga_switcheroo_lock_ddc(pdev);
2846 edid = drm_get_edid(connector, adapter);
2847 vga_switcheroo_unlock_ddc(pdev);
2851 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2854 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2855 * @connector: connector we're probing
2856 * @adapter: I2C adapter to use for DDC
2858 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2859 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2860 * temporarily switch DDC to the GPU which is retrieving EDID.
2862 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2864 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2865 struct i2c_adapter *adapter)
2867 struct drm_device *dev = connector->dev;
2868 struct pci_dev *pdev = to_pci_dev(dev->dev);
2869 const struct drm_edid *drm_edid;
2871 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2874 vga_switcheroo_lock_ddc(pdev);
2875 drm_edid = drm_edid_read_ddc(connector, adapter);
2876 vga_switcheroo_unlock_ddc(pdev);
2880 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2883 * drm_edid_duplicate - duplicate an EDID and the extensions
2884 * @edid: EDID to duplicate
2886 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2888 struct edid *drm_edid_duplicate(const struct edid *edid)
2893 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2895 EXPORT_SYMBOL(drm_edid_duplicate);
2897 /*** EDID parsing ***/
2900 * edid_get_quirks - return quirk flags for a given EDID
2901 * @drm_edid: EDID to process
2903 * This tells subsequent routines what fixes they need to apply.
2905 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2907 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2908 const struct edid_quirk *quirk;
2911 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2912 quirk = &edid_quirk_list[i];
2913 if (quirk->panel_id == panel_id)
2914 return quirk->quirks;
2920 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2921 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2924 * Walk the mode list for connector, clearing the preferred status on existing
2925 * modes and setting it anew for the right mode ala quirks.
2927 static void edid_fixup_preferred(struct drm_connector *connector)
2929 const struct drm_display_info *info = &connector->display_info;
2930 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2931 int target_refresh = 0;
2932 int cur_vrefresh, preferred_vrefresh;
2934 if (list_empty(&connector->probed_modes))
2937 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2938 target_refresh = 60;
2939 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2940 target_refresh = 75;
2942 preferred_mode = list_first_entry(&connector->probed_modes,
2943 struct drm_display_mode, head);
2945 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2946 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2948 if (cur_mode == preferred_mode)
2951 /* Largest mode is preferred */
2952 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2953 preferred_mode = cur_mode;
2955 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2956 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2957 /* At a given size, try to get closest to target refresh */
2958 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2959 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2960 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2961 preferred_mode = cur_mode;
2965 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2969 mode_is_rb(const struct drm_display_mode *mode)
2971 return (mode->htotal - mode->hdisplay == 160) &&
2972 (mode->hsync_end - mode->hdisplay == 80) &&
2973 (mode->hsync_end - mode->hsync_start == 32) &&
2974 (mode->vsync_start - mode->vdisplay == 3);
2978 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2979 * @dev: Device to duplicate against
2980 * @hsize: Mode width
2981 * @vsize: Mode height
2982 * @fresh: Mode refresh rate
2983 * @rb: Mode reduced-blanking-ness
2985 * Walk the DMT mode list looking for a match for the given parameters.
2987 * Return: A newly allocated copy of the mode, or NULL if not found.
2989 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2990 int hsize, int vsize, int fresh,
2995 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2996 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2998 if (hsize != ptr->hdisplay)
3000 if (vsize != ptr->vdisplay)
3002 if (fresh != drm_mode_vrefresh(ptr))
3004 if (rb != mode_is_rb(ptr))
3007 return drm_mode_duplicate(dev, ptr);
3012 EXPORT_SYMBOL(drm_mode_find_dmt);
3014 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3016 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3017 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3018 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3020 return descriptor->pixel_clock == 0 &&
3021 descriptor->data.other_data.pad1 == 0 &&
3022 descriptor->data.other_data.type == type;
3025 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3027 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3029 return descriptor->pixel_clock != 0;
3032 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3035 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3039 const u8 *det_base = ext + d;
3041 if (d < 4 || d > 127)
3045 for (i = 0; i < n; i++)
3046 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3050 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3052 unsigned int i, n = min((int)ext[0x02], 6);
3053 const u8 *det_base = ext + 5;
3056 return; /* unknown version */
3058 for (i = 0; i < n; i++)
3059 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3062 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3063 detailed_cb *cb, void *closure)
3065 struct drm_edid_iter edid_iter;
3072 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3073 cb(&drm_edid->edid->detailed_timings[i], closure);
3075 drm_edid_iter_begin(drm_edid, &edid_iter);
3076 drm_edid_iter_for_each(ext, &edid_iter) {
3079 cea_for_each_detailed_block(ext, cb, closure);
3082 vtb_for_each_detailed_block(ext, cb, closure);
3088 drm_edid_iter_end(&edid_iter);
3092 is_rb(const struct detailed_timing *descriptor, void *data)
3096 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3099 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3100 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3102 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3103 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3107 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3109 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3111 if (drm_edid->edid->revision >= 4) {
3114 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3118 return drm_edid_is_digital(drm_edid);
3122 find_gtf2(const struct detailed_timing *descriptor, void *data)
3124 const struct detailed_timing **res = data;
3126 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3129 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3131 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3135 /* Secondary GTF curve kicks in above some break frequency */
3137 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3139 const struct detailed_timing *descriptor = NULL;
3141 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3143 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3145 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3149 drm_gtf2_2c(const struct drm_edid *drm_edid)
3151 const struct detailed_timing *descriptor = NULL;
3153 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3155 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3157 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3161 drm_gtf2_m(const struct drm_edid *drm_edid)
3163 const struct detailed_timing *descriptor = NULL;
3165 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3167 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3169 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3173 drm_gtf2_k(const struct drm_edid *drm_edid)
3175 const struct detailed_timing *descriptor = NULL;
3177 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3179 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3181 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3185 drm_gtf2_2j(const struct drm_edid *drm_edid)
3187 const struct detailed_timing *descriptor = NULL;
3189 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3191 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3193 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3197 get_timing_level(const struct detailed_timing *descriptor, void *data)
3201 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3204 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3206 switch (descriptor->data.other_data.data.range.flags) {
3207 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3210 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3213 case DRM_EDID_CVT_SUPPORT_FLAG:
3221 /* Get standard timing level (CVT/GTF/DMT). */
3222 static int standard_timing_level(const struct drm_edid *drm_edid)
3224 const struct edid *edid = drm_edid->edid;
3226 if (edid->revision >= 4) {
3228 * If the range descriptor doesn't
3229 * indicate otherwise default to CVT
3231 int ret = LEVEL_CVT;
3233 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3236 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3238 } else if (edid->revision >= 2) {
3246 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3247 * monitors fill with ascii space (0x20) instead.
3250 bad_std_timing(u8 a, u8 b)
3252 return (a == 0x00 && b == 0x00) ||
3253 (a == 0x01 && b == 0x01) ||
3254 (a == 0x20 && b == 0x20);
3257 static int drm_mode_hsync(const struct drm_display_mode *mode)
3259 if (mode->htotal <= 0)
3262 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3265 static struct drm_display_mode *
3266 drm_gtf2_mode(struct drm_device *dev,
3267 const struct drm_edid *drm_edid,
3268 int hsize, int vsize, int vrefresh_rate)
3270 struct drm_display_mode *mode;
3273 * This is potentially wrong if there's ever a monitor with
3274 * more than one ranges section, each claiming a different
3275 * secondary GTF curve. Please don't do that.
3277 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3281 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3282 drm_mode_destroy(dev, mode);
3283 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3284 vrefresh_rate, 0, 0,
3285 drm_gtf2_m(drm_edid),
3286 drm_gtf2_2c(drm_edid),
3287 drm_gtf2_k(drm_edid),
3288 drm_gtf2_2j(drm_edid));
3295 * Take the standard timing params (in this case width, aspect, and refresh)
3296 * and convert them into a real mode using CVT/GTF/DMT.
3298 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3299 const struct drm_edid *drm_edid,
3300 const struct std_timing *t)
3302 struct drm_device *dev = connector->dev;
3303 struct drm_display_mode *m, *mode = NULL;
3306 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3307 >> EDID_TIMING_ASPECT_SHIFT;
3308 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3309 >> EDID_TIMING_VFREQ_SHIFT;
3310 int timing_level = standard_timing_level(drm_edid);
3312 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3315 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3316 hsize = t->hsize * 8 + 248;
3317 /* vrefresh_rate = vfreq + 60 */
3318 vrefresh_rate = vfreq + 60;
3319 /* the vdisplay is calculated based on the aspect ratio */
3320 if (aspect_ratio == 0) {
3321 if (drm_edid->edid->revision < 3)
3324 vsize = (hsize * 10) / 16;
3325 } else if (aspect_ratio == 1)
3326 vsize = (hsize * 3) / 4;
3327 else if (aspect_ratio == 2)
3328 vsize = (hsize * 4) / 5;
3330 vsize = (hsize * 9) / 16;
3332 /* HDTV hack, part 1 */
3333 if (vrefresh_rate == 60 &&
3334 ((hsize == 1360 && vsize == 765) ||
3335 (hsize == 1368 && vsize == 769))) {
3341 * If this connector already has a mode for this size and refresh
3342 * rate (because it came from detailed or CVT info), use that
3343 * instead. This way we don't have to guess at interlace or
3346 list_for_each_entry(m, &connector->probed_modes, head)
3347 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3348 drm_mode_vrefresh(m) == vrefresh_rate)
3351 /* HDTV hack, part 2 */
3352 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3353 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3357 mode->hdisplay = 1366;
3358 mode->hsync_start = mode->hsync_start - 1;
3359 mode->hsync_end = mode->hsync_end - 1;
3363 /* check whether it can be found in default mode table */
3364 if (drm_monitor_supports_rb(drm_edid)) {
3365 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3370 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3374 /* okay, generate it */
3375 switch (timing_level) {
3379 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3382 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3385 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3393 * EDID is delightfully ambiguous about how interlaced modes are to be
3394 * encoded. Our internal representation is of frame height, but some
3395 * HDTV detailed timings are encoded as field height.
3397 * The format list here is from CEA, in frame size. Technically we
3398 * should be checking refresh rate too. Whatever.
3401 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3402 const struct detailed_pixel_timing *pt)
3405 static const struct {
3407 } cea_interlaced[] = {
3417 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3420 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3421 if ((mode->hdisplay == cea_interlaced[i].w) &&
3422 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3423 mode->vdisplay *= 2;
3424 mode->vsync_start *= 2;
3425 mode->vsync_end *= 2;
3431 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3435 * Create a new mode from an EDID detailed timing section. An EDID detailed
3436 * timing block contains enough info for us to create and return a new struct
3439 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3440 const struct drm_edid *drm_edid,
3441 const struct detailed_timing *timing)
3443 const struct drm_display_info *info = &connector->display_info;
3444 struct drm_device *dev = connector->dev;
3445 struct drm_display_mode *mode;
3446 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3447 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3448 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3449 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3450 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3451 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3452 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3453 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3454 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3456 /* ignore tiny modes */
3457 if (hactive < 64 || vactive < 64)
3460 if (pt->misc & DRM_EDID_PT_STEREO) {
3461 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3462 connector->base.id, connector->name);
3465 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3466 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3467 connector->base.id, connector->name);
3470 /* it is incorrect if hsync/vsync width is zero */
3471 if (!hsync_pulse_width || !vsync_pulse_width) {
3472 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3473 connector->base.id, connector->name);
3477 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3478 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3485 mode = drm_mode_create(dev);
3489 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3490 mode->clock = 1088 * 10;
3492 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3494 mode->hdisplay = hactive;
3495 mode->hsync_start = mode->hdisplay + hsync_offset;
3496 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3497 mode->htotal = mode->hdisplay + hblank;
3499 mode->vdisplay = vactive;
3500 mode->vsync_start = mode->vdisplay + vsync_offset;
3501 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3502 mode->vtotal = mode->vdisplay + vblank;
3504 /* Some EDIDs have bogus h/vsync_end values */
3505 if (mode->hsync_end > mode->htotal) {
3506 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3507 connector->base.id, connector->name,
3508 mode->hsync_end, mode->htotal);
3509 mode->hsync_end = mode->htotal;
3511 if (mode->vsync_end > mode->vtotal) {
3512 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3513 connector->base.id, connector->name,
3514 mode->vsync_end, mode->vtotal);
3515 mode->vsync_end = mode->vtotal;
3518 drm_mode_do_interlace_quirk(mode, pt);
3520 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3521 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3523 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3524 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3525 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3526 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3530 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3531 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3533 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3534 mode->width_mm *= 10;
3535 mode->height_mm *= 10;
3538 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3539 mode->width_mm = drm_edid->edid->width_cm * 10;
3540 mode->height_mm = drm_edid->edid->height_cm * 10;
3543 mode->type = DRM_MODE_TYPE_DRIVER;
3544 drm_mode_set_name(mode);
3550 mode_in_hsync_range(const struct drm_display_mode *mode,
3551 const struct edid *edid, const u8 *t)
3553 int hsync, hmin, hmax;
3556 if (edid->revision >= 4)
3557 hmin += ((t[4] & 0x04) ? 255 : 0);
3559 if (edid->revision >= 4)
3560 hmax += ((t[4] & 0x08) ? 255 : 0);
3561 hsync = drm_mode_hsync(mode);
3563 return (hsync <= hmax && hsync >= hmin);
3567 mode_in_vsync_range(const struct drm_display_mode *mode,
3568 const struct edid *edid, const u8 *t)
3570 int vsync, vmin, vmax;
3573 if (edid->revision >= 4)
3574 vmin += ((t[4] & 0x01) ? 255 : 0);
3576 if (edid->revision >= 4)
3577 vmax += ((t[4] & 0x02) ? 255 : 0);
3578 vsync = drm_mode_vrefresh(mode);
3580 return (vsync <= vmax && vsync >= vmin);
3584 range_pixel_clock(const struct edid *edid, const u8 *t)
3587 if (t[9] == 0 || t[9] == 255)
3590 /* 1.4 with CVT support gives us real precision, yay */
3591 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3592 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3594 /* 1.3 is pathetic, so fuzz up a bit */
3595 return t[9] * 10000 + 5001;
3598 static bool mode_in_range(const struct drm_display_mode *mode,
3599 const struct drm_edid *drm_edid,
3600 const struct detailed_timing *timing)
3602 const struct edid *edid = drm_edid->edid;
3604 const u8 *t = (const u8 *)timing;
3606 if (!mode_in_hsync_range(mode, edid, t))
3609 if (!mode_in_vsync_range(mode, edid, t))
3612 if ((max_clock = range_pixel_clock(edid, t)))
3613 if (mode->clock > max_clock)
3616 /* 1.4 max horizontal check */
3617 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3618 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3621 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3627 static bool valid_inferred_mode(const struct drm_connector *connector,
3628 const struct drm_display_mode *mode)
3630 const struct drm_display_mode *m;
3633 list_for_each_entry(m, &connector->probed_modes, head) {
3634 if (mode->hdisplay == m->hdisplay &&
3635 mode->vdisplay == m->vdisplay &&
3636 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3637 return false; /* duplicated */
3638 if (mode->hdisplay <= m->hdisplay &&
3639 mode->vdisplay <= m->vdisplay)
3645 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3646 const struct drm_edid *drm_edid,
3647 const struct detailed_timing *timing)
3650 struct drm_display_mode *newmode;
3651 struct drm_device *dev = connector->dev;
3653 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3654 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3655 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3656 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3658 drm_mode_probed_add(connector, newmode);
3667 /* fix up 1366x768 mode from 1368x768;
3668 * GFT/CVT can't express 1366 width which isn't dividable by 8
3670 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3672 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3673 mode->hdisplay = 1366;
3674 mode->hsync_start--;
3676 drm_mode_set_name(mode);
3680 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3681 const struct drm_edid *drm_edid,
3682 const struct detailed_timing *timing)
3685 struct drm_display_mode *newmode;
3686 struct drm_device *dev = connector->dev;
3688 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3689 const struct minimode *m = &extra_modes[i];
3691 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3695 drm_mode_fixup_1366x768(newmode);
3696 if (!mode_in_range(newmode, drm_edid, timing) ||
3697 !valid_inferred_mode(connector, newmode)) {
3698 drm_mode_destroy(dev, newmode);
3702 drm_mode_probed_add(connector, newmode);
3709 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3710 const struct drm_edid *drm_edid,
3711 const struct detailed_timing *timing)
3714 struct drm_display_mode *newmode;
3715 struct drm_device *dev = connector->dev;
3717 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3718 const struct minimode *m = &extra_modes[i];
3720 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3724 drm_mode_fixup_1366x768(newmode);
3725 if (!mode_in_range(newmode, drm_edid, timing) ||
3726 !valid_inferred_mode(connector, newmode)) {
3727 drm_mode_destroy(dev, newmode);
3731 drm_mode_probed_add(connector, newmode);
3738 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3739 const struct drm_edid *drm_edid,
3740 const struct detailed_timing *timing)
3743 struct drm_display_mode *newmode;
3744 struct drm_device *dev = connector->dev;
3745 bool rb = drm_monitor_supports_rb(drm_edid);
3747 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3748 const struct minimode *m = &extra_modes[i];
3750 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3754 drm_mode_fixup_1366x768(newmode);
3755 if (!mode_in_range(newmode, drm_edid, timing) ||
3756 !valid_inferred_mode(connector, newmode)) {
3757 drm_mode_destroy(dev, newmode);
3761 drm_mode_probed_add(connector, newmode);
3769 do_inferred_modes(const struct detailed_timing *timing, void *c)
3771 struct detailed_mode_closure *closure = c;
3772 const struct detailed_non_pixel *data = &timing->data.other_data;
3773 const struct detailed_data_monitor_range *range = &data->data.range;
3775 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3778 closure->modes += drm_dmt_modes_for_range(closure->connector,
3782 if (closure->drm_edid->edid->revision < 2)
3783 return; /* GTF not defined yet */
3785 switch (range->flags) {
3786 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3787 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3791 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3792 closure->modes += drm_gtf_modes_for_range(closure->connector,
3796 case DRM_EDID_CVT_SUPPORT_FLAG:
3797 if (closure->drm_edid->edid->revision < 4)
3800 closure->modes += drm_cvt_modes_for_range(closure->connector,
3804 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3810 static int add_inferred_modes(struct drm_connector *connector,
3811 const struct drm_edid *drm_edid)
3813 struct detailed_mode_closure closure = {
3814 .connector = connector,
3815 .drm_edid = drm_edid,
3818 if (drm_edid->edid->revision >= 1)
3819 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3821 return closure.modes;
3825 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3827 int i, j, m, modes = 0;
3828 struct drm_display_mode *mode;
3829 const u8 *est = ((const u8 *)timing) + 6;
3831 for (i = 0; i < 6; i++) {
3832 for (j = 7; j >= 0; j--) {
3833 m = (i * 8) + (7 - j);
3834 if (m >= ARRAY_SIZE(est3_modes))
3836 if (est[i] & (1 << j)) {
3837 mode = drm_mode_find_dmt(connector->dev,
3843 drm_mode_probed_add(connector, mode);
3854 do_established_modes(const struct detailed_timing *timing, void *c)
3856 struct detailed_mode_closure *closure = c;
3858 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3861 closure->modes += drm_est3_modes(closure->connector, timing);
3865 * Get established modes from EDID and add them. Each EDID block contains a
3866 * bitmap of the supported "established modes" list (defined above). Tease them
3867 * out and add them to the global modes list.
3869 static int add_established_modes(struct drm_connector *connector,
3870 const struct drm_edid *drm_edid)
3872 struct drm_device *dev = connector->dev;
3873 const struct edid *edid = drm_edid->edid;
3874 unsigned long est_bits = edid->established_timings.t1 |
3875 (edid->established_timings.t2 << 8) |
3876 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3878 struct detailed_mode_closure closure = {
3879 .connector = connector,
3880 .drm_edid = drm_edid,
3883 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3884 if (est_bits & (1<<i)) {
3885 struct drm_display_mode *newmode;
3887 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3889 drm_mode_probed_add(connector, newmode);
3895 if (edid->revision >= 1)
3896 drm_for_each_detailed_block(drm_edid, do_established_modes,
3899 return modes + closure.modes;
3903 do_standard_modes(const struct detailed_timing *timing, void *c)
3905 struct detailed_mode_closure *closure = c;
3906 const struct detailed_non_pixel *data = &timing->data.other_data;
3907 struct drm_connector *connector = closure->connector;
3910 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3913 for (i = 0; i < 6; i++) {
3914 const struct std_timing *std = &data->data.timings[i];
3915 struct drm_display_mode *newmode;
3917 newmode = drm_mode_std(connector, closure->drm_edid, std);
3919 drm_mode_probed_add(connector, newmode);
3926 * Get standard modes from EDID and add them. Standard modes can be calculated
3927 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3928 * add them to the list.
3930 static int add_standard_modes(struct drm_connector *connector,
3931 const struct drm_edid *drm_edid)
3934 struct detailed_mode_closure closure = {
3935 .connector = connector,
3936 .drm_edid = drm_edid,
3939 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3940 struct drm_display_mode *newmode;
3942 newmode = drm_mode_std(connector, drm_edid,
3943 &drm_edid->edid->standard_timings[i]);
3945 drm_mode_probed_add(connector, newmode);
3950 if (drm_edid->edid->revision >= 1)
3951 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3954 /* XXX should also look for standard codes in VTB blocks */
3956 return modes + closure.modes;
3959 static int drm_cvt_modes(struct drm_connector *connector,
3960 const struct detailed_timing *timing)
3962 int i, j, modes = 0;
3963 struct drm_display_mode *newmode;
3964 struct drm_device *dev = connector->dev;
3965 const struct cvt_timing *cvt;
3966 static const int rates[] = { 60, 85, 75, 60, 50 };
3967 const u8 empty[3] = { 0, 0, 0 };
3969 for (i = 0; i < 4; i++) {
3972 cvt = &(timing->data.other_data.data.cvt[i]);
3974 if (!memcmp(cvt->code, empty, 3))
3977 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3978 switch (cvt->code[1] & 0x0c) {
3979 /* default - because compiler doesn't see that we've enumerated all cases */
3982 width = height * 4 / 3;
3985 width = height * 16 / 9;
3988 width = height * 16 / 10;
3991 width = height * 15 / 9;
3995 for (j = 1; j < 5; j++) {
3996 if (cvt->code[2] & (1 << j)) {
3997 newmode = drm_cvt_mode(dev, width, height,
4001 drm_mode_probed_add(connector, newmode);
4012 do_cvt_mode(const struct detailed_timing *timing, void *c)
4014 struct detailed_mode_closure *closure = c;
4016 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4019 closure->modes += drm_cvt_modes(closure->connector, timing);
4023 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4025 struct detailed_mode_closure closure = {
4026 .connector = connector,
4027 .drm_edid = drm_edid,
4030 if (drm_edid->edid->revision >= 3)
4031 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4033 /* XXX should also look for CVT codes in VTB blocks */
4035 return closure.modes;
4038 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4039 struct drm_display_mode *mode);
4042 do_detailed_mode(const struct detailed_timing *timing, void *c)
4044 struct detailed_mode_closure *closure = c;
4045 struct drm_display_mode *newmode;
4047 if (!is_detailed_timing_descriptor(timing))
4050 newmode = drm_mode_detailed(closure->connector,
4051 closure->drm_edid, timing);
4055 if (closure->preferred)
4056 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4059 * Detailed modes are limited to 10kHz pixel clock resolution,
4060 * so fix up anything that looks like CEA/HDMI mode, but the clock
4061 * is just slightly off.
4063 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4065 drm_mode_probed_add(closure->connector, newmode);
4067 closure->preferred = false;
4071 * add_detailed_modes - Add modes from detailed timings
4072 * @connector: attached connector
4073 * @drm_edid: EDID block to scan
4075 static int add_detailed_modes(struct drm_connector *connector,
4076 const struct drm_edid *drm_edid)
4078 struct detailed_mode_closure closure = {
4079 .connector = connector,
4080 .drm_edid = drm_edid,
4083 if (drm_edid->edid->revision >= 4)
4084 closure.preferred = true; /* first detailed timing is always preferred */
4087 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4089 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4091 return closure.modes;
4094 /* CTA-861-H Table 60 - CTA Tag Codes */
4095 #define CTA_DB_AUDIO 1
4096 #define CTA_DB_VIDEO 2
4097 #define CTA_DB_VENDOR 3
4098 #define CTA_DB_SPEAKER 4
4099 #define CTA_DB_EXTENDED_TAG 7
4101 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4102 #define CTA_EXT_DB_VIDEO_CAP 0
4103 #define CTA_EXT_DB_VENDOR 1
4104 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4105 #define CTA_EXT_DB_420_VIDEO_DATA 14
4106 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4107 #define CTA_EXT_DB_HF_EEODB 0x78
4108 #define CTA_EXT_DB_HF_SCDB 0x79
4110 #define EDID_BASIC_AUDIO (1 << 6)
4111 #define EDID_CEA_YCRCB444 (1 << 5)
4112 #define EDID_CEA_YCRCB422 (1 << 4)
4113 #define EDID_CEA_VCDB_QS (1 << 6)
4116 * Search EDID for CEA extension block.
4118 * FIXME: Prefer not returning pointers to raw EDID data.
4120 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4121 int ext_id, int *ext_index)
4123 const u8 *edid_ext = NULL;
4126 /* No EDID or EDID extensions */
4127 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4130 /* Find CEA extension */
4131 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4132 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4133 if (edid_block_tag(edid_ext) == ext_id)
4137 if (i >= drm_edid_extension_block_count(drm_edid))
4145 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4146 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4148 const struct displayid_block *block;
4149 struct displayid_iter iter;
4153 /* Look for a top level CEA extension block */
4154 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4157 /* CEA blocks can also be found embedded in a DisplayID block */
4158 displayid_iter_edid_begin(drm_edid, &iter);
4159 displayid_iter_for_each(block, &iter) {
4160 if (block->tag == DATA_BLOCK_CTA) {
4165 displayid_iter_end(&iter);
4170 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4172 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4173 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4175 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4176 return &edid_cea_modes_1[vic - 1];
4177 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4178 return &edid_cea_modes_193[vic - 193];
4182 static u8 cea_num_vics(void)
4184 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4187 static u8 cea_next_vic(u8 vic)
4189 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4195 * Calculate the alternate clock for the CEA mode
4196 * (60Hz vs. 59.94Hz etc.)
4199 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4201 unsigned int clock = cea_mode->clock;
4203 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4207 * edid_cea_modes contains the 59.94Hz
4208 * variant for 240 and 480 line modes,
4209 * and the 60Hz variant otherwise.
4211 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4212 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4214 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4220 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4223 * For certain VICs the spec allows the vertical
4224 * front porch to vary by one or two lines.
4226 * cea_modes[] stores the variant with the shortest
4227 * vertical front porch. We can adjust the mode to
4228 * get the other variants by simply increasing the
4229 * vertical front porch length.
4231 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4232 cea_mode_for_vic(9)->vtotal != 262 ||
4233 cea_mode_for_vic(12)->vtotal != 262 ||
4234 cea_mode_for_vic(13)->vtotal != 262 ||
4235 cea_mode_for_vic(23)->vtotal != 312 ||
4236 cea_mode_for_vic(24)->vtotal != 312 ||
4237 cea_mode_for_vic(27)->vtotal != 312 ||
4238 cea_mode_for_vic(28)->vtotal != 312);
4240 if (((vic == 8 || vic == 9 ||
4241 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4242 ((vic == 23 || vic == 24 ||
4243 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4244 mode->vsync_start++;
4254 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4255 unsigned int clock_tolerance)
4257 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4260 if (!to_match->clock)
4263 if (to_match->picture_aspect_ratio)
4264 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4266 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4267 struct drm_display_mode cea_mode;
4268 unsigned int clock1, clock2;
4270 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4272 /* Check both 60Hz and 59.94Hz */
4273 clock1 = cea_mode.clock;
4274 clock2 = cea_mode_alternate_clock(&cea_mode);
4276 if (abs(to_match->clock - clock1) > clock_tolerance &&
4277 abs(to_match->clock - clock2) > clock_tolerance)
4281 if (drm_mode_match(to_match, &cea_mode, match_flags))
4283 } while (cea_mode_alternate_timings(vic, &cea_mode));
4290 * drm_match_cea_mode - look for a CEA mode matching given mode
4291 * @to_match: display mode
4293 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4296 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4298 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4301 if (!to_match->clock)
4304 if (to_match->picture_aspect_ratio)
4305 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4307 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4308 struct drm_display_mode cea_mode;
4309 unsigned int clock1, clock2;
4311 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4313 /* Check both 60Hz and 59.94Hz */
4314 clock1 = cea_mode.clock;
4315 clock2 = cea_mode_alternate_clock(&cea_mode);
4317 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4318 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4322 if (drm_mode_match(to_match, &cea_mode, match_flags))
4324 } while (cea_mode_alternate_timings(vic, &cea_mode));
4329 EXPORT_SYMBOL(drm_match_cea_mode);
4331 static bool drm_valid_cea_vic(u8 vic)
4333 return cea_mode_for_vic(vic) != NULL;
4336 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4338 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4341 return mode->picture_aspect_ratio;
4343 return HDMI_PICTURE_ASPECT_NONE;
4346 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4348 return edid_4k_modes[video_code].picture_aspect_ratio;
4352 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4356 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4358 return cea_mode_alternate_clock(hdmi_mode);
4361 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4362 unsigned int clock_tolerance)
4364 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4367 if (!to_match->clock)
4370 if (to_match->picture_aspect_ratio)
4371 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4373 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4374 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4375 unsigned int clock1, clock2;
4377 /* Make sure to also match alternate clocks */
4378 clock1 = hdmi_mode->clock;
4379 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4381 if (abs(to_match->clock - clock1) > clock_tolerance &&
4382 abs(to_match->clock - clock2) > clock_tolerance)
4385 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4393 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4394 * @to_match: display mode
4396 * An HDMI mode is one defined in the HDMI vendor specific block.
4398 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4400 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4402 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4405 if (!to_match->clock)
4408 if (to_match->picture_aspect_ratio)
4409 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4411 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4412 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4413 unsigned int clock1, clock2;
4415 /* Make sure to also match alternate clocks */
4416 clock1 = hdmi_mode->clock;
4417 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4419 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4420 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4421 drm_mode_match(to_match, hdmi_mode, match_flags))
4427 static bool drm_valid_hdmi_vic(u8 vic)
4429 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4432 static int add_alternate_cea_modes(struct drm_connector *connector,
4433 const struct drm_edid *drm_edid)
4435 struct drm_device *dev = connector->dev;
4436 struct drm_display_mode *mode, *tmp;
4440 /* Don't add CTA modes if the CTA extension block is missing */
4441 if (!drm_edid_has_cta_extension(drm_edid))
4445 * Go through all probed modes and create a new mode
4446 * with the alternate clock for certain CEA modes.
4448 list_for_each_entry(mode, &connector->probed_modes, head) {
4449 const struct drm_display_mode *cea_mode = NULL;
4450 struct drm_display_mode *newmode;
4451 u8 vic = drm_match_cea_mode(mode);
4452 unsigned int clock1, clock2;
4454 if (drm_valid_cea_vic(vic)) {
4455 cea_mode = cea_mode_for_vic(vic);
4456 clock2 = cea_mode_alternate_clock(cea_mode);
4458 vic = drm_match_hdmi_mode(mode);
4459 if (drm_valid_hdmi_vic(vic)) {
4460 cea_mode = &edid_4k_modes[vic];
4461 clock2 = hdmi_mode_alternate_clock(cea_mode);
4468 clock1 = cea_mode->clock;
4470 if (clock1 == clock2)
4473 if (mode->clock != clock1 && mode->clock != clock2)
4476 newmode = drm_mode_duplicate(dev, cea_mode);
4480 /* Carry over the stereo flags */
4481 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4484 * The current mode could be either variant. Make
4485 * sure to pick the "other" clock for the new mode.
4487 if (mode->clock != clock1)
4488 newmode->clock = clock1;
4490 newmode->clock = clock2;
4492 list_add_tail(&newmode->head, &list);
4495 list_for_each_entry_safe(mode, tmp, &list, head) {
4496 list_del(&mode->head);
4497 drm_mode_probed_add(connector, mode);
4504 static u8 svd_to_vic(u8 svd)
4506 /* 0-6 bit vic, 7th bit native mode indicator */
4507 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4514 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4515 * the EDID, or NULL on errors.
4517 static struct drm_display_mode *
4518 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4520 const struct drm_display_info *info = &connector->display_info;
4521 struct drm_device *dev = connector->dev;
4523 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4526 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4530 * do_y420vdb_modes - Parse YCBCR 420 only modes
4531 * @connector: connector corresponding to the HDMI sink
4532 * @svds: start of the data block of CEA YCBCR 420 VDB
4533 * @len: length of the CEA YCBCR 420 VDB
4535 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4536 * which contains modes which can be supported in YCBCR 420
4537 * output format only.
4539 static int do_y420vdb_modes(struct drm_connector *connector,
4540 const u8 *svds, u8 svds_len)
4542 struct drm_device *dev = connector->dev;
4545 for (i = 0; i < svds_len; i++) {
4546 u8 vic = svd_to_vic(svds[i]);
4547 struct drm_display_mode *newmode;
4549 if (!drm_valid_cea_vic(vic))
4552 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4555 drm_mode_probed_add(connector, newmode);
4563 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4565 * @video_code: CEA VIC of the mode
4567 * Creates a new mode matching the specified CEA VIC.
4569 * Returns: A new drm_display_mode on success or NULL on failure
4571 struct drm_display_mode *
4572 drm_display_mode_from_cea_vic(struct drm_device *dev,
4575 const struct drm_display_mode *cea_mode;
4576 struct drm_display_mode *newmode;
4578 cea_mode = cea_mode_for_vic(video_code);
4582 newmode = drm_mode_duplicate(dev, cea_mode);
4588 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4590 /* Add modes based on VICs parsed in parse_cta_vdb() */
4591 static int add_cta_vdb_modes(struct drm_connector *connector)
4593 const struct drm_display_info *info = &connector->display_info;
4599 for (i = 0; i < info->vics_len; i++) {
4600 struct drm_display_mode *mode;
4602 mode = drm_display_mode_from_vic_index(connector, i);
4604 drm_mode_probed_add(connector, mode);
4612 struct stereo_mandatory_mode {
4613 int width, height, vrefresh;
4617 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4618 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4619 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4621 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4623 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4624 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4625 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4626 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4627 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4631 stereo_match_mandatory(const struct drm_display_mode *mode,
4632 const struct stereo_mandatory_mode *stereo_mode)
4634 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4636 return mode->hdisplay == stereo_mode->width &&
4637 mode->vdisplay == stereo_mode->height &&
4638 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4639 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4642 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4644 struct drm_device *dev = connector->dev;
4645 const struct drm_display_mode *mode;
4646 struct list_head stereo_modes;
4649 INIT_LIST_HEAD(&stereo_modes);
4651 list_for_each_entry(mode, &connector->probed_modes, head) {
4652 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4653 const struct stereo_mandatory_mode *mandatory;
4654 struct drm_display_mode *new_mode;
4656 if (!stereo_match_mandatory(mode,
4657 &stereo_mandatory_modes[i]))
4660 mandatory = &stereo_mandatory_modes[i];
4661 new_mode = drm_mode_duplicate(dev, mode);
4665 new_mode->flags |= mandatory->flags;
4666 list_add_tail(&new_mode->head, &stereo_modes);
4671 list_splice_tail(&stereo_modes, &connector->probed_modes);
4676 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4678 struct drm_device *dev = connector->dev;
4679 struct drm_display_mode *newmode;
4681 if (!drm_valid_hdmi_vic(vic)) {
4682 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4683 connector->base.id, connector->name, vic);
4687 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4691 drm_mode_probed_add(connector, newmode);
4696 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4699 struct drm_display_mode *newmode;
4702 if (structure & (1 << 0)) {
4703 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4705 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4706 drm_mode_probed_add(connector, newmode);
4710 if (structure & (1 << 6)) {
4711 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4713 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4714 drm_mode_probed_add(connector, newmode);
4718 if (structure & (1 << 8)) {
4719 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4721 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4722 drm_mode_probed_add(connector, newmode);
4730 static bool hdmi_vsdb_latency_present(const u8 *db)
4732 return db[8] & BIT(7);
4735 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4737 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4740 static int hdmi_vsdb_latency_length(const u8 *db)
4742 if (hdmi_vsdb_i_latency_present(db))
4744 else if (hdmi_vsdb_latency_present(db))
4751 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4752 * @connector: connector corresponding to the HDMI sink
4753 * @db: start of the CEA vendor specific block
4754 * @len: length of the CEA block payload, ie. one can access up to db[len]
4756 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4757 * also adds the stereo 3d modes when applicable.
4760 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4762 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4763 u8 vic_len, hdmi_3d_len = 0;
4770 /* no HDMI_Video_Present */
4771 if (!(db[8] & (1 << 5)))
4774 offset += hdmi_vsdb_latency_length(db);
4776 /* the declared length is not long enough for the 2 first bytes
4777 * of additional video format capabilities */
4778 if (len < (8 + offset + 2))
4783 if (db[8 + offset] & (1 << 7)) {
4784 modes += add_hdmi_mandatory_stereo_modes(connector);
4786 /* 3D_Multi_present */
4787 multi_present = (db[8 + offset] & 0x60) >> 5;
4791 vic_len = db[8 + offset] >> 5;
4792 hdmi_3d_len = db[8 + offset] & 0x1f;
4794 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4797 vic = db[9 + offset + i];
4798 modes += add_hdmi_mode(connector, vic);
4800 offset += 1 + vic_len;
4802 if (multi_present == 1)
4804 else if (multi_present == 2)
4809 if (len < (8 + offset + hdmi_3d_len - 1))
4812 if (hdmi_3d_len < multi_len)
4815 if (multi_present == 1 || multi_present == 2) {
4816 /* 3D_Structure_ALL */
4817 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4819 /* check if 3D_MASK is present */
4820 if (multi_present == 2)
4821 mask = (db[10 + offset] << 8) | db[11 + offset];
4825 for (i = 0; i < 16; i++) {
4826 if (mask & (1 << i))
4827 modes += add_3d_struct_modes(connector,
4832 offset += multi_len;
4834 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4836 struct drm_display_mode *newmode = NULL;
4837 unsigned int newflag = 0;
4838 bool detail_present;
4840 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4842 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4845 /* 2D_VIC_order_X */
4846 vic_index = db[8 + offset + i] >> 4;
4848 /* 3D_Structure_X */
4849 switch (db[8 + offset + i] & 0x0f) {
4851 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4854 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4858 if ((db[9 + offset + i] >> 4) == 1)
4859 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4864 newmode = drm_display_mode_from_vic_index(connector,
4868 newmode->flags |= newflag;
4869 drm_mode_probed_add(connector, newmode);
4883 cea_revision(const u8 *cea)
4886 * FIXME is this correct for the DispID variant?
4887 * The DispID spec doesn't really specify whether
4888 * this is the revision of the CEA extension or
4889 * the DispID CEA data block. And the only value
4890 * given as an example is 0.
4896 * CTA Data Block iterator.
4898 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4901 * struct cea_db *db:
4902 * struct cea_db_iter iter;
4904 * cea_db_iter_edid_begin(edid, &iter);
4905 * cea_db_iter_for_each(db, &iter) {
4906 * // do stuff with db
4908 * cea_db_iter_end(&iter);
4910 struct cea_db_iter {
4911 struct drm_edid_iter edid_iter;
4912 struct displayid_iter displayid_iter;
4914 /* Current Data Block Collection. */
4915 const u8 *collection;
4917 /* Current Data Block index in current collection. */
4920 /* End index in current collection. */
4924 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4930 static int cea_db_tag(const struct cea_db *db)
4932 return db->tag_length >> 5;
4935 static int cea_db_payload_len(const void *_db)
4937 /* FIXME: Transition to passing struct cea_db * everywhere. */
4938 const struct cea_db *db = _db;
4940 return db->tag_length & 0x1f;
4943 static const void *cea_db_data(const struct cea_db *db)
4948 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4950 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4951 cea_db_payload_len(db) >= 1 &&
4955 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4957 const u8 *data = cea_db_data(db);
4959 return cea_db_tag(db) == CTA_DB_VENDOR &&
4960 cea_db_payload_len(db) >= 3 &&
4961 oui(data[2], data[1], data[0]) == vendor_oui;
4964 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4965 struct cea_db_iter *iter)
4967 memset(iter, 0, sizeof(*iter));
4969 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4970 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4973 static const struct cea_db *
4974 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4976 const struct cea_db *db;
4978 if (!iter->collection)
4981 db = (const struct cea_db *)&iter->collection[iter->index];
4983 if (iter->index + sizeof(*db) <= iter->end &&
4984 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4992 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4994 static int cea_db_collection_size(const u8 *cta)
4998 if (d < 4 || d > 127)
5006 * - VESA E-EDID v1.4
5007 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5009 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5013 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5016 /* Only support CTA Extension revision 3+ */
5017 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5020 size = cea_db_collection_size(ext);
5025 iter->end = iter->index + size;
5035 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5036 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5038 * Note that the above do not specify any connection between DisplayID Data
5039 * Block revision and CTA Extension versions.
5041 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5043 const struct displayid_block *block;
5045 displayid_iter_for_each(block, &iter->displayid_iter) {
5046 if (block->tag != DATA_BLOCK_CTA)
5050 * The displayid iterator has already verified the block bounds
5051 * in displayid_iter_block().
5053 iter->index = sizeof(*block);
5054 iter->end = iter->index + block->num_bytes;
5062 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5064 const struct cea_db *db;
5066 if (iter->collection) {
5067 /* Current collection should always be valid. */
5068 db = __cea_db_iter_current_block(iter);
5070 iter->collection = NULL;
5074 /* Next block in CTA Data Block Collection */
5075 iter->index += sizeof(*db) + cea_db_payload_len(db);
5077 db = __cea_db_iter_current_block(iter);
5084 * Find the next CTA Data Block Collection. First iterate all
5085 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5087 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5088 * Extension, it's recommended that DisplayID extensions are
5089 * exposed after all of the CTA Extensions.
5091 iter->collection = __cea_db_iter_edid_next(iter);
5092 if (!iter->collection)
5093 iter->collection = __cea_db_iter_displayid_next(iter);
5095 if (!iter->collection)
5098 db = __cea_db_iter_current_block(iter);
5104 #define cea_db_iter_for_each(__db, __iter) \
5105 while (((__db) = __cea_db_iter_next(__iter)))
5107 static void cea_db_iter_end(struct cea_db_iter *iter)
5109 displayid_iter_end(&iter->displayid_iter);
5110 drm_edid_iter_end(&iter->edid_iter);
5112 memset(iter, 0, sizeof(*iter));
5115 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5117 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5118 cea_db_payload_len(db) >= 5;
5121 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5123 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5124 cea_db_payload_len(db) >= 7;
5127 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5129 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5130 cea_db_payload_len(db) >= 2;
5133 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5135 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5136 cea_db_payload_len(db) == 21;
5139 static bool cea_db_is_vcdb(const struct cea_db *db)
5141 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5142 cea_db_payload_len(db) == 2;
5145 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5147 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5148 cea_db_payload_len(db) >= 7;
5151 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5153 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5156 static bool cea_db_is_y420vdb(const struct cea_db *db)
5158 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5161 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5163 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5164 cea_db_payload_len(db) >= 3;
5168 * Get the HF-EEODB override extension block count from EDID.
5170 * The passed in EDID may be partially read, as long as it has at least two
5171 * blocks (base block and one extension block) if EDID extension count is > 0.
5173 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5174 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5175 * iterators instead.
5178 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5180 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5184 /* No extensions according to base block, no HF-EEODB. */
5185 if (!edid_extension_block_count(edid))
5188 /* HF-EEODB is always in the first EDID extension block only */
5189 cta = edid_extension_block_data(edid, 0);
5190 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5193 /* Need to have the data block collection, and at least 3 bytes. */
5194 if (cea_db_collection_size(cta) < 3)
5198 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5199 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5200 * through 6 of Block 1 of the E-EDID.
5202 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5209 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5211 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5212 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5213 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5214 * support YCBCR420 output too.
5216 static void parse_cta_y420cmdb(struct drm_connector *connector,
5217 const struct cea_db *db, u64 *y420cmdb_map)
5219 struct drm_display_info *info = &connector->display_info;
5220 int i, map_len = cea_db_payload_len(db) - 1;
5221 const u8 *data = cea_db_data(db) + 1;
5225 /* All CEA modes support ycbcr420 sampling also.*/
5231 * This map indicates which of the existing CEA block modes
5232 * from VDB can support YCBCR420 output too. So if bit=0 is
5233 * set, first mode from VDB can support YCBCR420 output too.
5234 * We will parse and keep this map, before parsing VDB itself
5235 * to avoid going through the same block again and again.
5237 * Spec is not clear about max possible size of this block.
5238 * Clamping max bitmap block size at 8 bytes. Every byte can
5239 * address 8 CEA modes, in this way this map can address
5240 * 8*8 = first 64 SVDs.
5242 if (WARN_ON_ONCE(map_len > 8))
5245 for (i = 0; i < map_len; i++)
5246 map |= (u64)data[i] << (8 * i);
5250 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5252 *y420cmdb_map = map;
5255 static int add_cea_modes(struct drm_connector *connector,
5256 const struct drm_edid *drm_edid)
5258 const struct cea_db *db;
5259 struct cea_db_iter iter;
5262 /* CTA VDB block VICs parsed earlier */
5263 modes = add_cta_vdb_modes(connector);
5265 cea_db_iter_edid_begin(drm_edid, &iter);
5266 cea_db_iter_for_each(db, &iter) {
5267 if (cea_db_is_hdmi_vsdb(db)) {
5268 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5269 cea_db_payload_len(db));
5270 } else if (cea_db_is_y420vdb(db)) {
5271 const u8 *vdb420 = cea_db_data(db) + 1;
5273 /* Add 4:2:0(only) modes present in EDID */
5274 modes += do_y420vdb_modes(connector, vdb420,
5275 cea_db_payload_len(db) - 1);
5278 cea_db_iter_end(&iter);
5283 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5284 struct drm_display_mode *mode)
5286 const struct drm_display_mode *cea_mode;
5287 int clock1, clock2, clock;
5292 * allow 5kHz clock difference either way to account for
5293 * the 10kHz clock resolution limit of detailed timings.
5295 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5296 if (drm_valid_cea_vic(vic)) {
5298 cea_mode = cea_mode_for_vic(vic);
5299 clock1 = cea_mode->clock;
5300 clock2 = cea_mode_alternate_clock(cea_mode);
5302 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5303 if (drm_valid_hdmi_vic(vic)) {
5305 cea_mode = &edid_4k_modes[vic];
5306 clock1 = cea_mode->clock;
5307 clock2 = hdmi_mode_alternate_clock(cea_mode);
5313 /* pick whichever is closest */
5314 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5319 if (mode->clock == clock)
5322 drm_dbg_kms(connector->dev,
5323 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5324 connector->base.id, connector->name,
5325 type, vic, mode->clock, clock);
5326 mode->clock = clock;
5329 static void drm_calculate_luminance_range(struct drm_connector *connector)
5331 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5332 struct drm_luminance_range_info *luminance_range =
5333 &connector->display_info.luminance_range;
5334 static const u8 pre_computed_values[] = {
5335 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5336 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5338 u32 max_avg, min_cll, max, min, q, r;
5340 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5343 max_avg = hdr_metadata->max_fall;
5344 min_cll = hdr_metadata->min_cll;
5347 * From the specification (CTA-861-G), for calculating the maximum
5348 * luminance we need to use:
5349 * Luminance = 50*2**(CV/32)
5350 * Where CV is a one-byte value.
5351 * For calculating this expression we may need float point precision;
5352 * to avoid this complexity level, we take advantage that CV is divided
5353 * by a constant. From the Euclids division algorithm, we know that CV
5354 * can be written as: CV = 32*q + r. Next, we replace CV in the
5355 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5356 * need to pre-compute the value of r/32. For pre-computing the values
5357 * We just used the following Ruby line:
5358 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5359 * The results of the above expressions can be verified at
5360 * pre_computed_values.
5364 max = (1 << q) * pre_computed_values[r];
5366 /* min luminance: maxLum * (CV/255)^2 / 100 */
5367 q = DIV_ROUND_CLOSEST(min_cll, 255);
5368 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5370 luminance_range->min_luminance = min;
5371 luminance_range->max_luminance = max;
5374 static uint8_t eotf_supported(const u8 *edid_ext)
5376 return edid_ext[2] &
5377 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5378 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5379 BIT(HDMI_EOTF_SMPTE_ST2084) |
5380 BIT(HDMI_EOTF_BT_2100_HLG));
5383 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5385 return edid_ext[3] &
5386 BIT(HDMI_STATIC_METADATA_TYPE1);
5390 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5394 len = cea_db_payload_len(db);
5396 connector->hdr_sink_metadata.hdmi_type1.eotf =
5398 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5399 hdr_metadata_type(db);
5402 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5404 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5406 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5408 /* Calculate only when all values are available */
5409 drm_calculate_luminance_range(connector);
5413 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5415 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5417 u8 len = cea_db_payload_len(db);
5419 if (len >= 6 && (db[6] & (1 << 7)))
5420 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5422 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5423 connector->latency_present[0] = true;
5424 connector->video_latency[0] = db[9];
5425 connector->audio_latency[0] = db[10];
5428 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5429 connector->latency_present[1] = true;
5430 connector->video_latency[1] = db[11];
5431 connector->audio_latency[1] = db[12];
5434 drm_dbg_kms(connector->dev,
5435 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5436 connector->base.id, connector->name,
5437 connector->latency_present[0], connector->latency_present[1],
5438 connector->video_latency[0], connector->video_latency[1],
5439 connector->audio_latency[0], connector->audio_latency[1]);
5443 monitor_name(const struct detailed_timing *timing, void *data)
5445 const char **res = data;
5447 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5450 *res = timing->data.other_data.data.str.str;
5453 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5455 const char *edid_name = NULL;
5458 if (!drm_edid || !name)
5461 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5462 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5463 if (edid_name[mnl] == 0x0a)
5466 name[mnl] = edid_name[mnl];
5473 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5474 * @edid: monitor EDID information
5475 * @name: pointer to a character array to hold the name of the monitor
5476 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5479 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5481 int name_length = 0;
5488 struct drm_edid drm_edid = {
5490 .size = edid_size(edid),
5493 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5494 memcpy(name, buf, name_length);
5497 name[name_length] = '\0';
5499 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5501 static void clear_eld(struct drm_connector *connector)
5503 memset(connector->eld, 0, sizeof(connector->eld));
5505 connector->latency_present[0] = false;
5506 connector->latency_present[1] = false;
5507 connector->video_latency[0] = 0;
5508 connector->audio_latency[0] = 0;
5509 connector->video_latency[1] = 0;
5510 connector->audio_latency[1] = 0;
5514 * drm_edid_to_eld - build ELD from EDID
5515 * @connector: connector corresponding to the HDMI/DP sink
5516 * @drm_edid: EDID to parse
5518 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5519 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5521 static void drm_edid_to_eld(struct drm_connector *connector,
5522 const struct drm_edid *drm_edid)
5524 const struct drm_display_info *info = &connector->display_info;
5525 const struct cea_db *db;
5526 struct cea_db_iter iter;
5527 uint8_t *eld = connector->eld;
5528 int total_sad_count = 0;
5534 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5535 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5536 connector->base.id, connector->name,
5537 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5539 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5540 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5542 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5544 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5545 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5546 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5547 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5549 cea_db_iter_edid_begin(drm_edid, &iter);
5550 cea_db_iter_for_each(db, &iter) {
5551 const u8 *data = cea_db_data(db);
5552 int len = cea_db_payload_len(db);
5555 switch (cea_db_tag(db)) {
5557 /* Audio Data Block, contains SADs */
5558 sad_count = min(len / 3, 15 - total_sad_count);
5560 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5561 data, sad_count * 3);
5562 total_sad_count += sad_count;
5564 case CTA_DB_SPEAKER:
5565 /* Speaker Allocation Data Block */
5567 eld[DRM_ELD_SPEAKER] = data[0];
5570 /* HDMI Vendor-Specific Data Block */
5571 if (cea_db_is_hdmi_vsdb(db))
5572 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5578 cea_db_iter_end(&iter);
5580 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5582 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5583 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5584 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5586 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5588 eld[DRM_ELD_BASELINE_ELD_LEN] =
5589 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5591 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5592 connector->base.id, connector->name,
5593 drm_eld_size(eld), total_sad_count);
5596 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5597 struct cea_sad **sads)
5599 const struct cea_db *db;
5600 struct cea_db_iter iter;
5603 cea_db_iter_edid_begin(drm_edid, &iter);
5604 cea_db_iter_for_each(db, &iter) {
5605 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5608 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5609 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5612 for (j = 0; j < count; j++) {
5613 const u8 *sad = &db->data[j * 3];
5615 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5616 (*sads)[j].channels = sad[0] & 0x7;
5617 (*sads)[j].freq = sad[1] & 0x7F;
5618 (*sads)[j].byte2 = sad[2];
5623 cea_db_iter_end(&iter);
5625 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5631 * drm_edid_to_sad - extracts SADs from EDID
5632 * @edid: EDID to parse
5633 * @sads: pointer that will be set to the extracted SADs
5635 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5637 * Note: The returned pointer needs to be freed using kfree().
5639 * Return: The number of found SADs or negative number on error.
5641 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5643 struct drm_edid drm_edid;
5645 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5647 EXPORT_SYMBOL(drm_edid_to_sad);
5649 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5652 const struct cea_db *db;
5653 struct cea_db_iter iter;
5656 cea_db_iter_edid_begin(drm_edid, &iter);
5657 cea_db_iter_for_each(db, &iter) {
5658 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5659 cea_db_payload_len(db) == 3) {
5660 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5664 count = cea_db_payload_len(db);
5668 cea_db_iter_end(&iter);
5670 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5676 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5677 * @edid: EDID to parse
5678 * @sadb: pointer to the speaker block
5680 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5682 * Note: The returned pointer needs to be freed using kfree().
5684 * Return: The number of found Speaker Allocation Blocks or negative number on
5687 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5689 struct drm_edid drm_edid;
5691 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5694 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5697 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5698 * @connector: connector associated with the HDMI/DP sink
5699 * @mode: the display mode
5701 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5702 * the sink doesn't support audio or video.
5704 int drm_av_sync_delay(struct drm_connector *connector,
5705 const struct drm_display_mode *mode)
5707 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5710 if (!connector->latency_present[0])
5712 if (!connector->latency_present[1])
5715 a = connector->audio_latency[i];
5716 v = connector->video_latency[i];
5719 * HDMI/DP sink doesn't support audio or video?
5721 if (a == 255 || v == 255)
5725 * Convert raw EDID values to millisecond.
5726 * Treat unknown latency as 0ms.
5729 a = min(2 * (a - 1), 500);
5731 v = min(2 * (v - 1), 500);
5733 return max(v - a, 0);
5735 EXPORT_SYMBOL(drm_av_sync_delay);
5737 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5739 const struct cea_db *db;
5740 struct cea_db_iter iter;
5744 * Because HDMI identifier is in Vendor Specific Block,
5745 * search it from all data blocks of CEA extension.
5747 cea_db_iter_edid_begin(drm_edid, &iter);
5748 cea_db_iter_for_each(db, &iter) {
5749 if (cea_db_is_hdmi_vsdb(db)) {
5754 cea_db_iter_end(&iter);
5760 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5761 * @edid: monitor EDID information
5763 * Parse the CEA extension according to CEA-861-B.
5765 * Drivers that have added the modes parsed from EDID to drm_display_info
5766 * should use &drm_display_info.is_hdmi instead of calling this function.
5768 * Return: True if the monitor is HDMI, false if not or unknown.
5770 bool drm_detect_hdmi_monitor(const struct edid *edid)
5772 struct drm_edid drm_edid;
5774 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5776 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5778 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5780 struct drm_edid_iter edid_iter;
5781 const struct cea_db *db;
5782 struct cea_db_iter iter;
5784 bool has_audio = false;
5786 drm_edid_iter_begin(drm_edid, &edid_iter);
5787 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5788 if (edid_ext[0] == CEA_EXT) {
5789 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5794 drm_edid_iter_end(&edid_iter);
5797 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5801 cea_db_iter_edid_begin(drm_edid, &iter);
5802 cea_db_iter_for_each(db, &iter) {
5803 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5804 const u8 *data = cea_db_data(db);
5807 for (i = 0; i < cea_db_payload_len(db); i += 3)
5808 DRM_DEBUG_KMS("CEA audio format %d\n",
5809 (data[i] >> 3) & 0xf);
5814 cea_db_iter_end(&iter);
5821 * drm_detect_monitor_audio - check monitor audio capability
5822 * @edid: EDID block to scan
5824 * Monitor should have CEA extension block.
5825 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5826 * audio' only. If there is any audio extension block and supported
5827 * audio format, assume at least 'basic audio' support, even if 'basic
5828 * audio' is not defined in EDID.
5830 * Return: True if the monitor supports audio, false otherwise.
5832 bool drm_detect_monitor_audio(const struct edid *edid)
5834 struct drm_edid drm_edid;
5836 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5838 EXPORT_SYMBOL(drm_detect_monitor_audio);
5842 * drm_default_rgb_quant_range - default RGB quantization range
5843 * @mode: display mode
5845 * Determine the default RGB quantization range for the mode,
5846 * as specified in CEA-861.
5848 * Return: The default RGB quantization range for the mode
5850 enum hdmi_quantization_range
5851 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5853 /* All CEA modes other than VIC 1 use limited quantization range. */
5854 return drm_match_cea_mode(mode) > 1 ?
5855 HDMI_QUANTIZATION_RANGE_LIMITED :
5856 HDMI_QUANTIZATION_RANGE_FULL;
5858 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5860 /* CTA-861 Video Data Block (CTA VDB) */
5861 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5863 struct drm_display_info *info = &connector->display_info;
5864 int i, vic_index, len = cea_db_payload_len(db);
5865 const u8 *svds = cea_db_data(db);
5871 /* Gracefully handle multiple VDBs, however unlikely that is */
5872 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5876 vic_index = info->vics_len;
5877 info->vics_len += len;
5880 for (i = 0; i < len; i++) {
5881 u8 vic = svd_to_vic(svds[i]);
5883 if (!drm_valid_cea_vic(vic))
5886 info->vics[vic_index++] = vic;
5891 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5893 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5894 * using the VICs themselves.
5896 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5898 struct drm_display_info *info = &connector->display_info;
5899 struct drm_hdmi_info *hdmi = &info->hdmi;
5900 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5902 for (i = 0; i < len; i++) {
5903 u8 vic = info->vics[i];
5905 if (vic && y420cmdb_map & BIT_ULL(i))
5906 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5910 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5912 const struct drm_display_info *info = &connector->display_info;
5915 if (!vic || !info->vics)
5918 for (i = 0; i < info->vics_len; i++) {
5919 if (info->vics[i] == vic)
5926 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5927 static void parse_cta_y420vdb(struct drm_connector *connector,
5928 const struct cea_db *db)
5930 struct drm_display_info *info = &connector->display_info;
5931 struct drm_hdmi_info *hdmi = &info->hdmi;
5932 const u8 *svds = cea_db_data(db) + 1;
5935 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5936 u8 vic = svd_to_vic(svds[i]);
5938 if (!drm_valid_cea_vic(vic))
5941 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5942 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5946 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5948 struct drm_display_info *info = &connector->display_info;
5950 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5951 connector->base.id, connector->name, db[2]);
5953 if (db[2] & EDID_CEA_VCDB_QS)
5954 info->rgb_quant_range_selectable = true;
5958 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5960 switch (max_frl_rate) {
5963 *max_rate_per_lane = 3;
5967 *max_rate_per_lane = 6;
5971 *max_rate_per_lane = 6;
5975 *max_rate_per_lane = 8;
5979 *max_rate_per_lane = 10;
5983 *max_rate_per_lane = 12;
5988 *max_rate_per_lane = 0;
5992 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5996 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5998 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5999 hdmi->y420_dc_modes = dc_mask;
6002 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6005 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6007 if (!hdmi_dsc->v_1p2)
6010 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6011 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6013 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6014 hdmi_dsc->bpc_supported = 16;
6015 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6016 hdmi_dsc->bpc_supported = 12;
6017 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6018 hdmi_dsc->bpc_supported = 10;
6020 /* Supports min 8 BPC if DSC 1.2 is supported*/
6021 hdmi_dsc->bpc_supported = 8;
6023 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6025 u8 dsc_max_frl_rate;
6027 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6028 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6029 &hdmi_dsc->max_frl_rate_per_lane);
6031 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6033 switch (dsc_max_slices) {
6035 hdmi_dsc->max_slices = 1;
6036 hdmi_dsc->clk_per_slice = 340;
6039 hdmi_dsc->max_slices = 2;
6040 hdmi_dsc->clk_per_slice = 340;
6043 hdmi_dsc->max_slices = 4;
6044 hdmi_dsc->clk_per_slice = 340;
6047 hdmi_dsc->max_slices = 8;
6048 hdmi_dsc->clk_per_slice = 340;
6051 hdmi_dsc->max_slices = 8;
6052 hdmi_dsc->clk_per_slice = 400;
6055 hdmi_dsc->max_slices = 12;
6056 hdmi_dsc->clk_per_slice = 400;
6059 hdmi_dsc->max_slices = 16;
6060 hdmi_dsc->clk_per_slice = 400;
6064 hdmi_dsc->max_slices = 0;
6065 hdmi_dsc->clk_per_slice = 0;
6069 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6070 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6073 /* Sink Capability Data Structure */
6074 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6077 struct drm_display_info *info = &connector->display_info;
6078 struct drm_hdmi_info *hdmi = &info->hdmi;
6079 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6080 int max_tmds_clock = 0;
6081 u8 max_frl_rate = 0;
6082 bool dsc_support = false;
6084 info->has_hdmi_infoframe = true;
6086 if (hf_scds[6] & 0x80) {
6087 hdmi->scdc.supported = true;
6088 if (hf_scds[6] & 0x40)
6089 hdmi->scdc.read_request = true;
6093 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6094 * And as per the spec, three factors confirm this:
6095 * * Availability of a HF-VSDB block in EDID (check)
6096 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6097 * * SCDC support available (let's check)
6098 * Lets check it out.
6102 struct drm_scdc *scdc = &hdmi->scdc;
6104 /* max clock is 5000 KHz times block value */
6105 max_tmds_clock = hf_scds[5] * 5000;
6107 if (max_tmds_clock > 340000) {
6108 info->max_tmds_clock = max_tmds_clock;
6111 if (scdc->supported) {
6112 scdc->scrambling.supported = true;
6114 /* Few sinks support scrambling for clocks < 340M */
6115 if ((hf_scds[6] & 0x8))
6116 scdc->scrambling.low_rates = true;
6121 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6122 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6123 &hdmi->max_frl_rate_per_lane);
6126 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6128 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6129 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6133 drm_dbg_kms(connector->dev,
6134 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6135 connector->base.id, connector->name,
6136 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6139 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6142 struct drm_display_info *info = &connector->display_info;
6143 unsigned int dc_bpc = 0;
6145 /* HDMI supports at least 8 bpc */
6148 if (cea_db_payload_len(hdmi) < 6)
6151 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6153 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6154 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6155 connector->base.id, connector->name);
6158 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6160 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6161 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6162 connector->base.id, connector->name);
6165 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6167 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6168 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6169 connector->base.id, connector->name);
6173 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6174 connector->base.id, connector->name);
6178 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6179 connector->base.id, connector->name, dc_bpc);
6182 /* YCRCB444 is optional according to spec. */
6183 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6184 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6185 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6186 connector->base.id, connector->name);
6190 * Spec says that if any deep color mode is supported at all,
6191 * then deep color 36 bit must be supported.
6193 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6194 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6195 connector->base.id, connector->name);
6199 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6201 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6203 struct drm_display_info *info = &connector->display_info;
6204 u8 len = cea_db_payload_len(db);
6206 info->is_hdmi = true;
6208 info->source_physical_address = (db[4] << 8) | db[5];
6211 info->dvi_dual = db[6] & 1;
6213 info->max_tmds_clock = db[7] * 5000;
6216 * Try to infer whether the sink supports HDMI infoframes.
6218 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6219 * supports infoframes if HDMI_Video_present is set.
6221 if (len >= 8 && db[8] & BIT(5))
6222 info->has_hdmi_infoframe = true;
6224 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6225 connector->base.id, connector->name,
6226 info->dvi_dual, info->max_tmds_clock);
6228 drm_parse_hdmi_deep_color_info(connector, db);
6232 * See EDID extension for head-mounted and specialized monitors, specified at:
6233 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6235 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6238 struct drm_display_info *info = &connector->display_info;
6240 bool desktop_usage = db[5] & BIT(6);
6242 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6243 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6244 info->non_desktop = true;
6246 drm_dbg_kms(connector->dev,
6247 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6248 connector->base.id, connector->name, version, db[5]);
6251 static void drm_parse_cea_ext(struct drm_connector *connector,
6252 const struct drm_edid *drm_edid)
6254 struct drm_display_info *info = &connector->display_info;
6255 struct drm_edid_iter edid_iter;
6256 const struct cea_db *db;
6257 struct cea_db_iter iter;
6259 u64 y420cmdb_map = 0;
6261 drm_edid_iter_begin(drm_edid, &edid_iter);
6262 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6263 if (edid_ext[0] != CEA_EXT)
6267 info->cea_rev = edid_ext[1];
6269 if (info->cea_rev != edid_ext[1])
6270 drm_dbg_kms(connector->dev,
6271 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6272 connector->base.id, connector->name,
6273 info->cea_rev, edid_ext[1]);
6275 /* The existence of a CTA extension should imply RGB support */
6276 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6277 if (edid_ext[3] & EDID_CEA_YCRCB444)
6278 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6279 if (edid_ext[3] & EDID_CEA_YCRCB422)
6280 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6281 if (edid_ext[3] & EDID_BASIC_AUDIO)
6282 info->has_audio = true;
6285 drm_edid_iter_end(&edid_iter);
6287 cea_db_iter_edid_begin(drm_edid, &iter);
6288 cea_db_iter_for_each(db, &iter) {
6289 /* FIXME: convert parsers to use struct cea_db */
6290 const u8 *data = (const u8 *)db;
6292 if (cea_db_is_hdmi_vsdb(db))
6293 drm_parse_hdmi_vsdb_video(connector, data);
6294 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6295 cea_db_is_hdmi_forum_scdb(db))
6296 drm_parse_hdmi_forum_scds(connector, data);
6297 else if (cea_db_is_microsoft_vsdb(db))
6298 drm_parse_microsoft_vsdb(connector, data);
6299 else if (cea_db_is_y420cmdb(db))
6300 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6301 else if (cea_db_is_y420vdb(db))
6302 parse_cta_y420vdb(connector, db);
6303 else if (cea_db_is_vcdb(db))
6304 drm_parse_vcdb(connector, data);
6305 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6306 drm_parse_hdr_metadata_block(connector, data);
6307 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6308 parse_cta_vdb(connector, db);
6309 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6310 info->has_audio = true;
6312 cea_db_iter_end(&iter);
6315 update_cta_y420cmdb(connector, y420cmdb_map);
6319 void get_monitor_range(const struct detailed_timing *timing, void *c)
6321 struct detailed_mode_closure *closure = c;
6322 struct drm_display_info *info = &closure->connector->display_info;
6323 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6324 const struct detailed_non_pixel *data = &timing->data.other_data;
6325 const struct detailed_data_monitor_range *range = &data->data.range;
6326 const struct edid *edid = closure->drm_edid->edid;
6328 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6332 * These limits are used to determine the VRR refresh
6333 * rate range. Only the "range limits only" variant
6334 * of the range descriptor seems to guarantee that
6335 * any and all timings are accepted by the sink, as
6336 * opposed to just timings conforming to the indicated
6337 * formula (GTF/GTF2/CVT). Thus other variants of the
6338 * range descriptor are not accepted here.
6340 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6343 monitor_range->min_vfreq = range->min_vfreq;
6344 monitor_range->max_vfreq = range->max_vfreq;
6346 if (edid->revision >= 4) {
6347 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6348 monitor_range->min_vfreq += 255;
6349 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6350 monitor_range->max_vfreq += 255;
6354 static void drm_get_monitor_range(struct drm_connector *connector,
6355 const struct drm_edid *drm_edid)
6357 const struct drm_display_info *info = &connector->display_info;
6358 struct detailed_mode_closure closure = {
6359 .connector = connector,
6360 .drm_edid = drm_edid,
6363 if (drm_edid->edid->revision < 4)
6366 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6369 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6371 drm_dbg_kms(connector->dev,
6372 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6373 connector->base.id, connector->name,
6374 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6377 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6378 const struct displayid_block *block)
6380 struct displayid_vesa_vendor_specific_block *vesa =
6381 (struct displayid_vesa_vendor_specific_block *)block;
6382 struct drm_display_info *info = &connector->display_info;
6384 if (block->num_bytes < 3) {
6385 drm_dbg_kms(connector->dev,
6386 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6387 connector->base.id, connector->name, block->num_bytes);
6391 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6394 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6395 drm_dbg_kms(connector->dev,
6396 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6397 connector->base.id, connector->name);
6401 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6403 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6404 connector->base.id, connector->name);
6407 info->mso_stream_count = 0;
6410 info->mso_stream_count = 2; /* 2 or 4 links */
6413 info->mso_stream_count = 4; /* 4 links */
6417 if (!info->mso_stream_count) {
6418 info->mso_pixel_overlap = 0;
6422 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6423 if (info->mso_pixel_overlap > 8) {
6424 drm_dbg_kms(connector->dev,
6425 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6426 connector->base.id, connector->name,
6427 info->mso_pixel_overlap);
6428 info->mso_pixel_overlap = 8;
6431 drm_dbg_kms(connector->dev,
6432 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6433 connector->base.id, connector->name,
6434 info->mso_stream_count, info->mso_pixel_overlap);
6437 static void drm_update_mso(struct drm_connector *connector,
6438 const struct drm_edid *drm_edid)
6440 const struct displayid_block *block;
6441 struct displayid_iter iter;
6443 displayid_iter_edid_begin(drm_edid, &iter);
6444 displayid_iter_for_each(block, &iter) {
6445 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6446 drm_parse_vesa_mso_data(connector, block);
6448 displayid_iter_end(&iter);
6451 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6452 * all of the values which would have been set from EDID
6454 static void drm_reset_display_info(struct drm_connector *connector)
6456 struct drm_display_info *info = &connector->display_info;
6459 info->height_mm = 0;
6462 info->color_formats = 0;
6464 info->max_tmds_clock = 0;
6465 info->dvi_dual = false;
6466 info->is_hdmi = false;
6467 info->has_audio = false;
6468 info->has_hdmi_infoframe = false;
6469 info->rgb_quant_range_selectable = false;
6470 memset(&info->hdmi, 0, sizeof(info->hdmi));
6472 info->edid_hdmi_rgb444_dc_modes = 0;
6473 info->edid_hdmi_ycbcr444_dc_modes = 0;
6475 info->non_desktop = 0;
6476 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6477 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6479 info->mso_stream_count = 0;
6480 info->mso_pixel_overlap = 0;
6481 info->max_dsc_bpp = 0;
6489 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6492 static void update_displayid_info(struct drm_connector *connector,
6493 const struct drm_edid *drm_edid)
6495 struct drm_display_info *info = &connector->display_info;
6496 const struct displayid_block *block;
6497 struct displayid_iter iter;
6499 displayid_iter_edid_begin(drm_edid, &iter);
6500 displayid_iter_for_each(block, &iter) {
6501 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6502 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6503 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6504 info->non_desktop = true;
6507 * We're only interested in the base section here, no need to
6512 displayid_iter_end(&iter);
6515 static void update_display_info(struct drm_connector *connector,
6516 const struct drm_edid *drm_edid)
6518 struct drm_display_info *info = &connector->display_info;
6519 const struct edid *edid;
6521 drm_reset_display_info(connector);
6522 clear_eld(connector);
6527 edid = drm_edid->edid;
6529 info->quirks = edid_get_quirks(drm_edid);
6531 info->width_mm = edid->width_cm * 10;
6532 info->height_mm = edid->height_cm * 10;
6534 drm_get_monitor_range(connector, drm_edid);
6536 if (edid->revision < 3)
6539 if (!drm_edid_is_digital(drm_edid))
6542 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6543 drm_parse_cea_ext(connector, drm_edid);
6545 update_displayid_info(connector, drm_edid);
6548 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6550 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6551 * tells us to assume 8 bpc color depth if the EDID doesn't have
6552 * extensions which tell otherwise.
6554 if (info->bpc == 0 && edid->revision == 3 &&
6555 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6557 drm_dbg_kms(connector->dev,
6558 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6559 connector->base.id, connector->name, info->bpc);
6562 /* Only defined for 1.4 with digital displays */
6563 if (edid->revision < 4)
6566 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6567 case DRM_EDID_DIGITAL_DEPTH_6:
6570 case DRM_EDID_DIGITAL_DEPTH_8:
6573 case DRM_EDID_DIGITAL_DEPTH_10:
6576 case DRM_EDID_DIGITAL_DEPTH_12:
6579 case DRM_EDID_DIGITAL_DEPTH_14:
6582 case DRM_EDID_DIGITAL_DEPTH_16:
6585 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6591 drm_dbg_kms(connector->dev,
6592 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6593 connector->base.id, connector->name, info->bpc);
6595 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6596 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6597 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6598 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6600 drm_update_mso(connector, drm_edid);
6603 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6604 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6605 connector->base.id, connector->name,
6606 info->non_desktop ? " (redundant quirk)" : "");
6607 info->non_desktop = true;
6610 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6611 info->max_dsc_bpp = 15;
6613 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6616 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6619 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6622 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6625 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6626 drm_edid_to_eld(connector, drm_edid);
6629 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6630 struct displayid_detailed_timings_1 *timings,
6633 struct drm_display_mode *mode;
6634 unsigned pixel_clock = (timings->pixel_clock[0] |
6635 (timings->pixel_clock[1] << 8) |
6636 (timings->pixel_clock[2] << 16)) + 1;
6637 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6638 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6639 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6640 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6641 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6642 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6643 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6644 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6645 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6646 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6648 mode = drm_mode_create(dev);
6652 /* resolution is kHz for type VII, and 10 kHz for type I */
6653 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6654 mode->hdisplay = hactive;
6655 mode->hsync_start = mode->hdisplay + hsync;
6656 mode->hsync_end = mode->hsync_start + hsync_width;
6657 mode->htotal = mode->hdisplay + hblank;
6659 mode->vdisplay = vactive;
6660 mode->vsync_start = mode->vdisplay + vsync;
6661 mode->vsync_end = mode->vsync_start + vsync_width;
6662 mode->vtotal = mode->vdisplay + vblank;
6665 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6666 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6667 mode->type = DRM_MODE_TYPE_DRIVER;
6669 if (timings->flags & 0x80)
6670 mode->type |= DRM_MODE_TYPE_PREFERRED;
6671 drm_mode_set_name(mode);
6676 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6677 const struct displayid_block *block)
6679 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6682 struct drm_display_mode *newmode;
6684 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6685 /* blocks must be multiple of 20 bytes length */
6686 if (block->num_bytes % 20)
6689 num_timings = block->num_bytes / 20;
6690 for (i = 0; i < num_timings; i++) {
6691 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6693 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6697 drm_mode_probed_add(connector, newmode);
6703 static int add_displayid_detailed_modes(struct drm_connector *connector,
6704 const struct drm_edid *drm_edid)
6706 const struct displayid_block *block;
6707 struct displayid_iter iter;
6710 displayid_iter_edid_begin(drm_edid, &iter);
6711 displayid_iter_for_each(block, &iter) {
6712 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6713 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6714 num_modes += add_displayid_detailed_1_modes(connector, block);
6716 displayid_iter_end(&iter);
6721 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6722 const struct drm_edid *drm_edid)
6724 const struct drm_display_info *info = &connector->display_info;
6731 * EDID spec says modes should be preferred in this order:
6732 * - preferred detailed mode
6733 * - other detailed modes from base block
6734 * - detailed modes from extension blocks
6735 * - CVT 3-byte code modes
6736 * - standard timing codes
6737 * - established timing codes
6738 * - modes inferred from GTF or CVT range information
6740 * We get this pretty much right.
6742 * XXX order for additional mode types in extension blocks?
6744 num_modes += add_detailed_modes(connector, drm_edid);
6745 num_modes += add_cvt_modes(connector, drm_edid);
6746 num_modes += add_standard_modes(connector, drm_edid);
6747 num_modes += add_established_modes(connector, drm_edid);
6748 num_modes += add_cea_modes(connector, drm_edid);
6749 num_modes += add_alternate_cea_modes(connector, drm_edid);
6750 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6751 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6752 num_modes += add_inferred_modes(connector, drm_edid);
6754 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6755 edid_fixup_preferred(connector);
6760 static void _drm_update_tile_info(struct drm_connector *connector,
6761 const struct drm_edid *drm_edid);
6763 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6764 const struct drm_edid *drm_edid)
6766 struct drm_device *dev = connector->dev;
6769 if (connector->edid_blob_ptr) {
6770 const struct edid *old_edid = connector->edid_blob_ptr->data;
6773 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6774 connector->epoch_counter++;
6775 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6776 connector->base.id, connector->name,
6777 connector->epoch_counter);
6782 ret = drm_property_replace_global_blob(dev,
6783 &connector->edid_blob_ptr,
6784 drm_edid ? drm_edid->size : 0,
6785 drm_edid ? drm_edid->edid : NULL,
6787 dev->mode_config.edid_property);
6789 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6790 connector->base.id, connector->name, ret);
6794 ret = drm_object_property_set_value(&connector->base,
6795 dev->mode_config.non_desktop_property,
6796 connector->display_info.non_desktop);
6798 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6799 connector->base.id, connector->name, ret);
6803 ret = drm_connector_set_tile_property(connector);
6805 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6806 connector->base.id, connector->name, ret);
6815 * drm_edid_connector_update - Update connector information from EDID
6816 * @connector: Connector
6819 * Update the connector display info, ELD, HDR metadata, relevant properties,
6820 * etc. from the passed in EDID.
6822 * If EDID is NULL, reset the information.
6824 * Must be called before calling drm_edid_connector_add_modes().
6826 * Return: 0 on success, negative error on errors.
6828 int drm_edid_connector_update(struct drm_connector *connector,
6829 const struct drm_edid *drm_edid)
6831 update_display_info(connector, drm_edid);
6833 _drm_update_tile_info(connector, drm_edid);
6835 return _drm_edid_connector_property_update(connector, drm_edid);
6837 EXPORT_SYMBOL(drm_edid_connector_update);
6840 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6841 * @connector: Connector
6843 * Add the modes from the previously updated EDID property to the connector
6844 * probed modes list.
6846 * drm_edid_connector_update() must have been called before this to update the
6849 * Return: The number of modes added, or 0 if we couldn't find any.
6851 int drm_edid_connector_add_modes(struct drm_connector *connector)
6853 const struct drm_edid *drm_edid = NULL;
6856 if (connector->edid_blob_ptr)
6857 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6858 connector->edid_blob_ptr->length);
6860 count = _drm_edid_connector_add_modes(connector, drm_edid);
6862 drm_edid_free(drm_edid);
6866 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6869 * drm_connector_update_edid_property - update the edid property of a connector
6870 * @connector: drm connector
6871 * @edid: new value of the edid property
6873 * This function creates a new blob modeset object and assigns its id to the
6874 * connector's edid property.
6875 * Since we also parse tile information from EDID's displayID block, we also
6876 * set the connector's tile property here. See drm_connector_set_tile_property()
6879 * This function is deprecated. Use drm_edid_connector_update() instead.
6882 * Zero on success, negative errno on failure.
6884 int drm_connector_update_edid_property(struct drm_connector *connector,
6885 const struct edid *edid)
6887 struct drm_edid drm_edid;
6889 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6891 EXPORT_SYMBOL(drm_connector_update_edid_property);
6894 * drm_add_edid_modes - add modes from EDID data, if available
6895 * @connector: connector we're probing
6898 * Add the specified modes to the connector's mode list. Also fills out the
6899 * &drm_display_info structure and ELD in @connector with any information which
6900 * can be derived from the edid.
6902 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6904 * Return: The number of modes added or 0 if we couldn't find any.
6906 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6908 struct drm_edid _drm_edid;
6909 const struct drm_edid *drm_edid;
6911 if (edid && !drm_edid_is_valid(edid)) {
6912 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6913 connector->base.id, connector->name);
6917 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6919 update_display_info(connector, drm_edid);
6921 return _drm_edid_connector_add_modes(connector, drm_edid);
6923 EXPORT_SYMBOL(drm_add_edid_modes);
6926 * drm_add_modes_noedid - add modes for the connectors without EDID
6927 * @connector: connector we're probing
6928 * @hdisplay: the horizontal display limit
6929 * @vdisplay: the vertical display limit
6931 * Add the specified modes to the connector's mode list. Only when the
6932 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6934 * Return: The number of modes added or 0 if we couldn't find any.
6936 int drm_add_modes_noedid(struct drm_connector *connector,
6937 int hdisplay, int vdisplay)
6939 int i, count, num_modes = 0;
6940 struct drm_display_mode *mode;
6941 struct drm_device *dev = connector->dev;
6943 count = ARRAY_SIZE(drm_dmt_modes);
6949 for (i = 0; i < count; i++) {
6950 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6952 if (hdisplay && vdisplay) {
6954 * Only when two are valid, they will be used to check
6955 * whether the mode should be added to the mode list of
6958 if (ptr->hdisplay > hdisplay ||
6959 ptr->vdisplay > vdisplay)
6962 if (drm_mode_vrefresh(ptr) > 61)
6964 mode = drm_mode_duplicate(dev, ptr);
6966 drm_mode_probed_add(connector, mode);
6972 EXPORT_SYMBOL(drm_add_modes_noedid);
6975 * drm_set_preferred_mode - Sets the preferred mode of a connector
6976 * @connector: connector whose mode list should be processed
6977 * @hpref: horizontal resolution of preferred mode
6978 * @vpref: vertical resolution of preferred mode
6980 * Marks a mode as preferred if it matches the resolution specified by @hpref
6983 void drm_set_preferred_mode(struct drm_connector *connector,
6984 int hpref, int vpref)
6986 struct drm_display_mode *mode;
6988 list_for_each_entry(mode, &connector->probed_modes, head) {
6989 if (mode->hdisplay == hpref &&
6990 mode->vdisplay == vpref)
6991 mode->type |= DRM_MODE_TYPE_PREFERRED;
6994 EXPORT_SYMBOL(drm_set_preferred_mode);
6996 static bool is_hdmi2_sink(const struct drm_connector *connector)
6999 * FIXME: sil-sii8620 doesn't have a connector around when
7000 * we need one, so we have to be prepared for a NULL connector.
7005 return connector->display_info.hdmi.scdc.supported ||
7006 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7009 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7010 const struct drm_display_mode *mode)
7012 bool has_hdmi_infoframe = connector ?
7013 connector->display_info.has_hdmi_infoframe : false;
7015 if (!has_hdmi_infoframe)
7018 /* No HDMI VIC when signalling 3D video format */
7019 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7022 return drm_match_hdmi_mode(mode);
7025 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7026 const struct drm_display_mode *mode)
7029 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7030 * we should send its VIC in vendor infoframes, else send the
7031 * VIC in AVI infoframes. Lets check if this mode is present in
7032 * HDMI 1.4b 4K modes
7034 if (drm_mode_hdmi_vic(connector, mode))
7037 return drm_match_cea_mode(mode);
7041 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7042 * conform to HDMI 1.4.
7044 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7045 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7047 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7050 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7052 if (!is_hdmi2_sink(connector) && vic > 64 &&
7053 !cta_vdb_has_vic(connector, vic))
7060 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7061 * data from a DRM display mode
7062 * @frame: HDMI AVI infoframe
7063 * @connector: the connector
7064 * @mode: DRM display mode
7066 * Return: 0 on success or a negative error code on failure.
7069 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7070 const struct drm_connector *connector,
7071 const struct drm_display_mode *mode)
7073 enum hdmi_picture_aspect picture_aspect;
7076 if (!frame || !mode)
7079 hdmi_avi_infoframe_init(frame);
7081 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7082 frame->pixel_repeat = 1;
7084 vic = drm_mode_cea_vic(connector, mode);
7085 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7087 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7090 * As some drivers don't support atomic, we can't use connector state.
7091 * So just initialize the frame with default values, just the same way
7092 * as it's done with other properties here.
7094 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7098 * Populate picture aspect ratio from either
7099 * user input (if specified) or from the CEA/HDMI mode lists.
7101 picture_aspect = mode->picture_aspect_ratio;
7102 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7104 picture_aspect = drm_get_cea_aspect_ratio(vic);
7106 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7110 * The infoframe can't convey anything but none, 4:3
7111 * and 16:9, so if the user has asked for anything else
7112 * we can only satisfy it by specifying the right VIC.
7114 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7116 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7118 } else if (hdmi_vic) {
7119 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7125 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7128 frame->video_code = vic_for_avi_infoframe(connector, vic);
7129 frame->picture_aspect = picture_aspect;
7130 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7131 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7135 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7138 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7139 * quantization range information
7140 * @frame: HDMI AVI infoframe
7141 * @connector: the connector
7142 * @mode: DRM display mode
7143 * @rgb_quant_range: RGB quantization range (Q)
7146 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7147 const struct drm_connector *connector,
7148 const struct drm_display_mode *mode,
7149 enum hdmi_quantization_range rgb_quant_range)
7151 const struct drm_display_info *info = &connector->display_info;
7155 * "A Source shall not send a non-zero Q value that does not correspond
7156 * to the default RGB Quantization Range for the transmitted Picture
7157 * unless the Sink indicates support for the Q bit in a Video
7158 * Capabilities Data Block."
7160 * HDMI 2.0 recommends sending non-zero Q when it does match the
7161 * default RGB quantization range for the mode, even when QS=0.
7163 if (info->rgb_quant_range_selectable ||
7164 rgb_quant_range == drm_default_rgb_quant_range(mode))
7165 frame->quantization_range = rgb_quant_range;
7167 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7171 * "When transmitting any RGB colorimetry, the Source should set the
7172 * YQ-field to match the RGB Quantization Range being transmitted
7173 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7174 * set YQ=1) and the Sink shall ignore the YQ-field."
7176 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7177 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7178 * good way to tell which version of CEA-861 the sink supports, so
7179 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7182 if (!is_hdmi2_sink(connector) ||
7183 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7184 frame->ycc_quantization_range =
7185 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7187 frame->ycc_quantization_range =
7188 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7190 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7192 static enum hdmi_3d_structure
7193 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7195 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7198 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7199 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7200 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7201 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7202 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7203 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7204 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7205 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7206 case DRM_MODE_FLAG_3D_L_DEPTH:
7207 return HDMI_3D_STRUCTURE_L_DEPTH;
7208 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7209 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7210 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7211 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7212 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7213 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7215 return HDMI_3D_STRUCTURE_INVALID;
7220 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7221 * data from a DRM display mode
7222 * @frame: HDMI vendor infoframe
7223 * @connector: the connector
7224 * @mode: DRM display mode
7226 * Note that there's is a need to send HDMI vendor infoframes only when using a
7227 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7228 * function will return -EINVAL, error that can be safely ignored.
7230 * Return: 0 on success or a negative error code on failure.
7233 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7234 const struct drm_connector *connector,
7235 const struct drm_display_mode *mode)
7238 * FIXME: sil-sii8620 doesn't have a connector around when
7239 * we need one, so we have to be prepared for a NULL connector.
7241 bool has_hdmi_infoframe = connector ?
7242 connector->display_info.has_hdmi_infoframe : false;
7245 if (!frame || !mode)
7248 if (!has_hdmi_infoframe)
7251 err = hdmi_vendor_infoframe_init(frame);
7256 * Even if it's not absolutely necessary to send the infoframe
7257 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7258 * know that the sink can handle it. This is based on a
7259 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7260 * have trouble realizing that they should switch from 3D to 2D
7261 * mode if the source simply stops sending the infoframe when
7262 * it wants to switch from 3D to 2D.
7264 frame->vic = drm_mode_hdmi_vic(connector, mode);
7265 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7269 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7271 static void drm_parse_tiled_block(struct drm_connector *connector,
7272 const struct displayid_block *block)
7274 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7276 u8 tile_v_loc, tile_h_loc;
7277 u8 num_v_tile, num_h_tile;
7278 struct drm_tile_group *tg;
7280 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7281 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7283 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7284 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7285 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7286 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7288 connector->has_tile = true;
7289 if (tile->tile_cap & 0x80)
7290 connector->tile_is_single_monitor = true;
7292 connector->num_h_tile = num_h_tile + 1;
7293 connector->num_v_tile = num_v_tile + 1;
7294 connector->tile_h_loc = tile_h_loc;
7295 connector->tile_v_loc = tile_v_loc;
7296 connector->tile_h_size = w + 1;
7297 connector->tile_v_size = h + 1;
7299 drm_dbg_kms(connector->dev,
7300 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7301 connector->base.id, connector->name,
7303 connector->tile_h_size, connector->tile_v_size,
7304 connector->num_h_tile, connector->num_v_tile,
7305 connector->tile_h_loc, connector->tile_v_loc,
7306 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7308 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7310 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7314 if (connector->tile_group != tg) {
7315 /* if we haven't got a pointer,
7316 take the reference, drop ref to old tile group */
7317 if (connector->tile_group)
7318 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7319 connector->tile_group = tg;
7321 /* if same tile group, then release the ref we just took. */
7322 drm_mode_put_tile_group(connector->dev, tg);
7326 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7327 const struct displayid_block *block)
7329 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7330 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7331 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7332 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7335 static void _drm_update_tile_info(struct drm_connector *connector,
7336 const struct drm_edid *drm_edid)
7338 const struct displayid_block *block;
7339 struct displayid_iter iter;
7341 connector->has_tile = false;
7343 displayid_iter_edid_begin(drm_edid, &iter);
7344 displayid_iter_for_each(block, &iter) {
7345 if (displayid_is_tiled_block(&iter, block))
7346 drm_parse_tiled_block(connector, block);
7348 displayid_iter_end(&iter);
7350 if (!connector->has_tile && connector->tile_group) {
7351 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7352 connector->tile_group = NULL;
7357 * drm_edid_is_digital - is digital?
7358 * @drm_edid: The EDID
7360 * Return true if input is digital.
7362 bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7364 return drm_edid && drm_edid->edid &&
7365 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7367 EXPORT_SYMBOL(drm_edid_is_digital);
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