drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "atom.h"
  28 #include "amdgpu_atombios.h"
  29 #include "atombios_crtc.h"
  30 #include "atombios_encoders.h"
  31 #include "amdgpu_pll.h"
  32 #include "amdgpu_connectors.h"
  33 #include "amdgpu_display.h"
  34
  35 #include "bif/bif_3_0_d.h"
  36 #include "bif/bif_3_0_sh_mask.h"
  37 #include "oss/oss_1_0_d.h"
  38 #include "oss/oss_1_0_sh_mask.h"
  39 #include "gca/gfx_6_0_d.h"
  40 #include "gca/gfx_6_0_sh_mask.h"
  41 #include "gmc/gmc_6_0_d.h"
  42 #include "gmc/gmc_6_0_sh_mask.h"
  43 #include "dce/dce_6_0_d.h"
  44 #include "dce/dce_6_0_sh_mask.h"
  45 #include "gca/gfx_7_2_enum.h"
  46 #include "dce_v6_0.h"
  47 #include "si_enums.h"
  48
  49 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
  50 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 static const u32 crtc_offsets[6] =
  53 {
  54         SI_CRTC0_REGISTER_OFFSET,
  55         SI_CRTC1_REGISTER_OFFSET,
  56         SI_CRTC2_REGISTER_OFFSET,
  57         SI_CRTC3_REGISTER_OFFSET,
  58         SI_CRTC4_REGISTER_OFFSET,
  59         SI_CRTC5_REGISTER_OFFSET
  60 };
  61
  62 static const u32 hpd_offsets[] =
  63 {
  64         mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
  65         mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
  66         mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
  67         mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
  68         mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
  69         mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
  70 };
  71
  72 static const uint32_t dig_offsets[] = {
  73         SI_CRTC0_REGISTER_OFFSET,
  74         SI_CRTC1_REGISTER_OFFSET,
  75         SI_CRTC2_REGISTER_OFFSET,
  76         SI_CRTC3_REGISTER_OFFSET,
  77         SI_CRTC4_REGISTER_OFFSET,
  78         SI_CRTC5_REGISTER_OFFSET,
  79         (0x13830 - 0x7030) >> 2,
  80 };
  81
  82 static const struct {
  83         uint32_t        reg;
  84         uint32_t        vblank;
  85         uint32_t        vline;
  86         uint32_t        hpd;
  87
  88 } interrupt_status_offsets[6] = { {
  89         .reg = mmDISP_INTERRUPT_STATUS,
  90         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 113 }, {
 114         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 115         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 116         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 117         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 118 } };
 119
 120 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
 121                                      u32 block_offset, u32 reg)
 122 {
 123         unsigned long flags;
 124         u32 r;
 125
 126         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 127         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 128         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 129         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 130
 131         return r;
 132 }
 133
 134 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
 135                                       u32 block_offset, u32 reg, u32 v)
 136 {
 137         unsigned long flags;
 138
 139         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 140         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
 141                 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
 142         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 143         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 144 }
 145
 146 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 147 {
 148         if (crtc >= adev->mode_info.num_crtc)
 149                 return 0;
 150         else
 151                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 152 }
 153
 154 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 155 {
 156         unsigned i;
 157
 158         /* Enable pflip interrupts */
 159         for (i = 0; i < adev->mode_info.num_crtc; i++)
 160                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 161 }
 162
 163 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 164 {
 165         unsigned i;
 166
 167         /* Disable pflip interrupts */
 168         for (i = 0; i < adev->mode_info.num_crtc; i++)
 169                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 170 }
 171
 172 /**
 173  * dce_v6_0_page_flip - pageflip callback.
 174  *
 175  * @adev: amdgpu_device pointer
 176  * @crtc_id: crtc to cleanup pageflip on
 177  * @crtc_base: new address of the crtc (GPU MC address)
 178  *
 179  * Does the actual pageflip (evergreen+).
 180  * During vblank we take the crtc lock and wait for the update_pending
 181  * bit to go high, when it does, we release the lock, and allow the
 182  * double buffered update to take place.
 183  * Returns the current update pending status.
 184  */
 185 static void dce_v6_0_page_flip(struct amdgpu_device *adev,
 186                                int crtc_id, u64 crtc_base, bool async)
 187 {
 188         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 189
 190         /* flip at hsync for async, default is vsync */
 191         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 192                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 193         /* update the scanout addresses */
 194         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 195                upper_32_bits(crtc_base));
 196         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 197                (u32)crtc_base);
 198
 199         /* post the write */
 200         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 201 }
 202
 203 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 204                                         u32 *vbl, u32 *position)
 205 {
 206         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 207                 return -EINVAL;
 208         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 209         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 210
 211         return 0;
 212
 213 }
 214
 215 /**
 216  * dce_v6_0_hpd_sense - hpd sense callback.
 217  *
 218  * @adev: amdgpu_device pointer
 219  * @hpd: hpd (hotplug detect) pin
 220  *
 221  * Checks if a digital monitor is connected (evergreen+).
 222  * Returns true if connected, false if not connected.
 223  */
 224 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
 225                                enum amdgpu_hpd_id hpd)
 226 {
 227         bool connected = false;
 228
 229         if (hpd >= adev->mode_info.num_hpd)
 230                 return connected;
 231
 232         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 233                 connected = true;
 234
 235         return connected;
 236 }
 237
 238 /**
 239  * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
 240  *
 241  * @adev: amdgpu_device pointer
 242  * @hpd: hpd (hotplug detect) pin
 243  *
 244  * Set the polarity of the hpd pin (evergreen+).
 245  */
 246 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
 247                                       enum amdgpu_hpd_id hpd)
 248 {
 249         u32 tmp;
 250         bool connected = dce_v6_0_hpd_sense(adev, hpd);
 251
 252         if (hpd >= adev->mode_info.num_hpd)
 253                 return;
 254
 255         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 256         if (connected)
 257                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 258         else
 259                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 260         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 261 }
 262
 263 /**
 264  * dce_v6_0_hpd_init - hpd setup callback.
 265  *
 266  * @adev: amdgpu_device pointer
 267  *
 268  * Setup the hpd pins used by the card (evergreen+).
 269  * Enable the pin, set the polarity, and enable the hpd interrupts.
 270  */
 271 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
 272 {
 273         struct drm_device *dev = adev->ddev;
 274         struct drm_connector *connector;
 275         u32 tmp;
 276
 277         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 278                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 279
 280                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 281                         continue;
 282
 283                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 284                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 285                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 286
 287                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 288                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 289                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 290                          * aux dp channel on imac and help (but not completely fix)
 291                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 292                          * also avoid interrupt storms during dpms.
 293                          */
 294                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 295                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 296                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 297                         continue;
 298                 }
 299
 300                 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 301                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 302         }
 303
 304 }
 305
 306 /**
 307  * dce_v6_0_hpd_fini - hpd tear down callback.
 308  *
 309  * @adev: amdgpu_device pointer
 310  *
 311  * Tear down the hpd pins used by the card (evergreen+).
 312  * Disable the hpd interrupts.
 313  */
 314 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 315 {
 316         struct drm_device *dev = adev->ddev;
 317         struct drm_connector *connector;
 318         u32 tmp;
 319
 320         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 321                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 322
 323                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 324                         continue;
 325
 326                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 327                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 328                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 329
 330                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 331         }
 332 }
 333
 334 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 335 {
 336         return mmDC_GPIO_HPD_A;
 337 }
 338
 339 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
 340                                           bool render)
 341 {
 342         if (!render)
 343                 WREG32(mmVGA_RENDER_CONTROL,
 344                         RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
 345
 346 }
 347
 348 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
 349 {
 350         switch (adev->asic_type) {
 351         case CHIP_TAHITI:
 352         case CHIP_PITCAIRN:
 353         case CHIP_VERDE:
 354                 return 6;
 355         case CHIP_OLAND:
 356                 return 2;
 357         default:
 358                 return 0;
 359         }
 360 }
 361
 362 void dce_v6_0_disable_dce(struct amdgpu_device *adev)
 363 {
 364         /*Disable VGA render and enabled crtc, if has DCE engine*/
 365         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 366                 u32 tmp;
 367                 int crtc_enabled, i;
 368
 369                 dce_v6_0_set_vga_render_state(adev, false);
 370
 371                 /*Disable crtc*/
 372                 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
 373                         crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
 374                                 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 375                         if (crtc_enabled) {
 376                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 377                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 378                                 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 379                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 380                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 381                         }
 382                 }
 383         }
 384 }
 385
 386 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 387 {
 388
 389         struct drm_device *dev = encoder->dev;
 390         struct amdgpu_device *adev = dev->dev_private;
 391         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 392         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 393         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 394         int bpc = 0;
 395         u32 tmp = 0;
 396         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 397
 398         if (connector) {
 399                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 400                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 401                 dither = amdgpu_connector->dither;
 402         }
 403
 404         /* LVDS FMT is set up by atom */
 405         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 406                 return;
 407
 408         if (bpc == 0)
 409                 return;
 410
 411
 412         switch (bpc) {
 413         case 6:
 414                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 415                         /* XXX sort out optimal dither settings */
 416                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 417                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 418                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
 419                 else
 420                         tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
 421                 break;
 422         case 8:
 423                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 424                         /* XXX sort out optimal dither settings */
 425                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 426                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 427                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 428                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 429                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
 430                 else
 431                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 432                                 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
 433                 break;
 434         case 10:
 435         default:
 436                 /* not needed */
 437                 break;
 438         }
 439
 440         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 441 }
 442
 443 /**
 444  * cik_get_number_of_dram_channels - get the number of dram channels
 445  *
 446  * @adev: amdgpu_device pointer
 447  *
 448  * Look up the number of video ram channels (CIK).
 449  * Used for display watermark bandwidth calculations
 450  * Returns the number of dram channels
 451  */
 452 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
 453 {
 454         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 455
 456         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 457         case 0:
 458         default:
 459                 return 1;
 460         case 1:
 461                 return 2;
 462         case 2:
 463                 return 4;
 464         case 3:
 465                 return 8;
 466         case 4:
 467                 return 3;
 468         case 5:
 469                 return 6;
 470         case 6:
 471                 return 10;
 472         case 7:
 473                 return 12;
 474         case 8:
 475                 return 16;
 476         }
 477 }
 478
 479 struct dce6_wm_params {
 480         u32 dram_channels; /* number of dram channels */
 481         u32 yclk;          /* bandwidth per dram data pin in kHz */
 482         u32 sclk;          /* engine clock in kHz */
 483         u32 disp_clk;      /* display clock in kHz */
 484         u32 src_width;     /* viewport width */
 485         u32 active_time;   /* active display time in ns */
 486         u32 blank_time;    /* blank time in ns */
 487         bool interlaced;    /* mode is interlaced */
 488         fixed20_12 vsc;    /* vertical scale ratio */
 489         u32 num_heads;     /* number of active crtcs */
 490         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 491         u32 lb_size;       /* line buffer allocated to pipe */
 492         u32 vtaps;         /* vertical scaler taps */
 493 };
 494
 495 /**
 496  * dce_v6_0_dram_bandwidth - get the dram bandwidth
 497  *
 498  * @wm: watermark calculation data
 499  *
 500  * Calculate the raw dram bandwidth (CIK).
 501  * Used for display watermark bandwidth calculations
 502  * Returns the dram bandwidth in MBytes/s
 503  */
 504 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
 505 {
 506         /* Calculate raw DRAM Bandwidth */
 507         fixed20_12 dram_efficiency; /* 0.7 */
 508         fixed20_12 yclk, dram_channels, bandwidth;
 509         fixed20_12 a;
 510
 511         a.full = dfixed_const(1000);
 512         yclk.full = dfixed_const(wm->yclk);
 513         yclk.full = dfixed_div(yclk, a);
 514         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 515         a.full = dfixed_const(10);
 516         dram_efficiency.full = dfixed_const(7);
 517         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 518         bandwidth.full = dfixed_mul(dram_channels, yclk);
 519         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 520
 521         return dfixed_trunc(bandwidth);
 522 }
 523
 524 /**
 525  * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
 526  *
 527  * @wm: watermark calculation data
 528  *
 529  * Calculate the dram bandwidth used for display (CIK).
 530  * Used for display watermark bandwidth calculations
 531  * Returns the dram bandwidth for display in MBytes/s
 532  */
 533 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 534 {
 535         /* Calculate DRAM Bandwidth and the part allocated to display. */
 536         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 537         fixed20_12 yclk, dram_channels, bandwidth;
 538         fixed20_12 a;
 539
 540         a.full = dfixed_const(1000);
 541         yclk.full = dfixed_const(wm->yclk);
 542         yclk.full = dfixed_div(yclk, a);
 543         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 544         a.full = dfixed_const(10);
 545         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 546         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 547         bandwidth.full = dfixed_mul(dram_channels, yclk);
 548         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 549
 550         return dfixed_trunc(bandwidth);
 551 }
 552
 553 /**
 554  * dce_v6_0_data_return_bandwidth - get the data return bandwidth
 555  *
 556  * @wm: watermark calculation data
 557  *
 558  * Calculate the data return bandwidth used for display (CIK).
 559  * Used for display watermark bandwidth calculations
 560  * Returns the data return bandwidth in MBytes/s
 561  */
 562 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
 563 {
 564         /* Calculate the display Data return Bandwidth */
 565         fixed20_12 return_efficiency; /* 0.8 */
 566         fixed20_12 sclk, bandwidth;
 567         fixed20_12 a;
 568
 569         a.full = dfixed_const(1000);
 570         sclk.full = dfixed_const(wm->sclk);
 571         sclk.full = dfixed_div(sclk, a);
 572         a.full = dfixed_const(10);
 573         return_efficiency.full = dfixed_const(8);
 574         return_efficiency.full = dfixed_div(return_efficiency, a);
 575         a.full = dfixed_const(32);
 576         bandwidth.full = dfixed_mul(a, sclk);
 577         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 578
 579         return dfixed_trunc(bandwidth);
 580 }
 581
 582 /**
 583  * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
 584  *
 585  * @wm: watermark calculation data
 586  *
 587  * Calculate the dmif bandwidth used for display (CIK).
 588  * Used for display watermark bandwidth calculations
 589  * Returns the dmif bandwidth in MBytes/s
 590  */
 591 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
 592 {
 593         /* Calculate the DMIF Request Bandwidth */
 594         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 595         fixed20_12 disp_clk, bandwidth;
 596         fixed20_12 a, b;
 597
 598         a.full = dfixed_const(1000);
 599         disp_clk.full = dfixed_const(wm->disp_clk);
 600         disp_clk.full = dfixed_div(disp_clk, a);
 601         a.full = dfixed_const(32);
 602         b.full = dfixed_mul(a, disp_clk);
 603
 604         a.full = dfixed_const(10);
 605         disp_clk_request_efficiency.full = dfixed_const(8);
 606         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 607
 608         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 609
 610         return dfixed_trunc(bandwidth);
 611 }
 612
 613 /**
 614  * dce_v6_0_available_bandwidth - get the min available bandwidth
 615  *
 616  * @wm: watermark calculation data
 617  *
 618  * Calculate the min available bandwidth used for display (CIK).
 619  * Used for display watermark bandwidth calculations
 620  * Returns the min available bandwidth in MBytes/s
 621  */
 622 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
 623 {
 624         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 625         u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
 626         u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
 627         u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
 628
 629         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 630 }
 631
 632 /**
 633  * dce_v6_0_average_bandwidth - get the average available bandwidth
 634  *
 635  * @wm: watermark calculation data
 636  *
 637  * Calculate the average available bandwidth used for display (CIK).
 638  * Used for display watermark bandwidth calculations
 639  * Returns the average available bandwidth in MBytes/s
 640  */
 641 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
 642 {
 643         /* Calculate the display mode Average Bandwidth
 644          * DisplayMode should contain the source and destination dimensions,
 645          * timing, etc.
 646          */
 647         fixed20_12 bpp;
 648         fixed20_12 line_time;
 649         fixed20_12 src_width;
 650         fixed20_12 bandwidth;
 651         fixed20_12 a;
 652
 653         a.full = dfixed_const(1000);
 654         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 655         line_time.full = dfixed_div(line_time, a);
 656         bpp.full = dfixed_const(wm->bytes_per_pixel);
 657         src_width.full = dfixed_const(wm->src_width);
 658         bandwidth.full = dfixed_mul(src_width, bpp);
 659         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 660         bandwidth.full = dfixed_div(bandwidth, line_time);
 661
 662         return dfixed_trunc(bandwidth);
 663 }
 664
 665 /**
 666  * dce_v6_0_latency_watermark - get the latency watermark
 667  *
 668  * @wm: watermark calculation data
 669  *
 670  * Calculate the latency watermark (CIK).
 671  * Used for display watermark bandwidth calculations
 672  * Returns the latency watermark in ns
 673  */
 674 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
 675 {
 676         /* First calculate the latency in ns */
 677         u32 mc_latency = 2000; /* 2000 ns. */
 678         u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
 679         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 680         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 681         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 682         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 683                 (wm->num_heads * cursor_line_pair_return_time);
 684         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 685         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 686         u32 tmp, dmif_size = 12288;
 687         fixed20_12 a, b, c;
 688
 689         if (wm->num_heads == 0)
 690                 return 0;
 691
 692         a.full = dfixed_const(2);
 693         b.full = dfixed_const(1);
 694         if ((wm->vsc.full > a.full) ||
 695             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 696             (wm->vtaps >= 5) ||
 697             ((wm->vsc.full >= a.full) && wm->interlaced))
 698                 max_src_lines_per_dst_line = 4;
 699         else
 700                 max_src_lines_per_dst_line = 2;
 701
 702         a.full = dfixed_const(available_bandwidth);
 703         b.full = dfixed_const(wm->num_heads);
 704         a.full = dfixed_div(a, b);
 705         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 706         tmp = min(dfixed_trunc(a), tmp);
 707
 708         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 709
 710         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 711         b.full = dfixed_const(1000);
 712         c.full = dfixed_const(lb_fill_bw);
 713         b.full = dfixed_div(c, b);
 714         a.full = dfixed_div(a, b);
 715         line_fill_time = dfixed_trunc(a);
 716
 717         if (line_fill_time < wm->active_time)
 718                 return latency;
 719         else
 720                 return latency + (line_fill_time - wm->active_time);
 721
 722 }
 723
 724 /**
 725  * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 726  * average and available dram bandwidth
 727  *
 728  * @wm: watermark calculation data
 729  *
 730  * Check if the display average bandwidth fits in the display
 731  * dram bandwidth (CIK).
 732  * Used for display watermark bandwidth calculations
 733  * Returns true if the display fits, false if not.
 734  */
 735 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 736 {
 737         if (dce_v6_0_average_bandwidth(wm) <=
 738             (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 739                 return true;
 740         else
 741                 return false;
 742 }
 743
 744 /**
 745  * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
 746  * average and available bandwidth
 747  *
 748  * @wm: watermark calculation data
 749  *
 750  * Check if the display average bandwidth fits in the display
 751  * available bandwidth (CIK).
 752  * Used for display watermark bandwidth calculations
 753  * Returns true if the display fits, false if not.
 754  */
 755 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
 756 {
 757         if (dce_v6_0_average_bandwidth(wm) <=
 758             (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
 759                 return true;
 760         else
 761                 return false;
 762 }
 763
 764 /**
 765  * dce_v6_0_check_latency_hiding - check latency hiding
 766  *
 767  * @wm: watermark calculation data
 768  *
 769  * Check latency hiding (CIK).
 770  * Used for display watermark bandwidth calculations
 771  * Returns true if the display fits, false if not.
 772  */
 773 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
 774 {
 775         u32 lb_partitions = wm->lb_size / wm->src_width;
 776         u32 line_time = wm->active_time + wm->blank_time;
 777         u32 latency_tolerant_lines;
 778         u32 latency_hiding;
 779         fixed20_12 a;
 780
 781         a.full = dfixed_const(1);
 782         if (wm->vsc.full > a.full)
 783                 latency_tolerant_lines = 1;
 784         else {
 785                 if (lb_partitions <= (wm->vtaps + 1))
 786                         latency_tolerant_lines = 1;
 787                 else
 788                         latency_tolerant_lines = 2;
 789         }
 790
 791         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 792
 793         if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
 794                 return true;
 795         else
 796                 return false;
 797 }
 798
 799 /**
 800  * dce_v6_0_program_watermarks - program display watermarks
 801  *
 802  * @adev: amdgpu_device pointer
 803  * @amdgpu_crtc: the selected display controller
 804  * @lb_size: line buffer size
 805  * @num_heads: number of display controllers in use
 806  *
 807  * Calculate and program the display watermarks for the
 808  * selected display controller (CIK).
 809  */
 810 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 811                                         struct amdgpu_crtc *amdgpu_crtc,
 812                                         u32 lb_size, u32 num_heads)
 813 {
 814         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 815         struct dce6_wm_params wm_low, wm_high;
 816         u32 dram_channels;
 817         u32 active_time;
 818         u32 line_time = 0;
 819         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 820         u32 priority_a_mark = 0, priority_b_mark = 0;
 821         u32 priority_a_cnt = PRIORITY_OFF;
 822         u32 priority_b_cnt = PRIORITY_OFF;
 823         u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
 824         fixed20_12 a, b, c;
 825
 826         if (amdgpu_crtc->base.enabled && num_heads && mode) {
 827                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
 828                                             (u32)mode->clock);
 829                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
 830                                           (u32)mode->clock);
 831                 line_time = min(line_time, (u32)65535);
 832                 priority_a_cnt = 0;
 833                 priority_b_cnt = 0;
 834
 835                 dram_channels = si_get_number_of_dram_channels(adev);
 836
 837                 /* watermark for high clocks */
 838                 if (adev->pm.dpm_enabled) {
 839                         wm_high.yclk =
 840                                 amdgpu_dpm_get_mclk(adev, false) * 10;
 841                         wm_high.sclk =
 842                                 amdgpu_dpm_get_sclk(adev, false) * 10;
 843                 } else {
 844                         wm_high.yclk = adev->pm.current_mclk * 10;
 845                         wm_high.sclk = adev->pm.current_sclk * 10;
 846                 }
 847
 848                 wm_high.disp_clk = mode->clock;
 849                 wm_high.src_width = mode->crtc_hdisplay;
 850                 wm_high.active_time = active_time;
 851                 wm_high.blank_time = line_time - wm_high.active_time;
 852                 wm_high.interlaced = false;
 853                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 854                         wm_high.interlaced = true;
 855                 wm_high.vsc = amdgpu_crtc->vsc;
 856                 wm_high.vtaps = 1;
 857                 if (amdgpu_crtc->rmx_type != RMX_OFF)
 858                         wm_high.vtaps = 2;
 859                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
 860                 wm_high.lb_size = lb_size;
 861                 wm_high.dram_channels = dram_channels;
 862                 wm_high.num_heads = num_heads;
 863
 864                 if (adev->pm.dpm_enabled) {
 865                 /* watermark for low clocks */
 866                         wm_low.yclk =
 867                                 amdgpu_dpm_get_mclk(adev, true) * 10;
 868                         wm_low.sclk =
 869                                 amdgpu_dpm_get_sclk(adev, true) * 10;
 870                 } else {
 871                         wm_low.yclk = adev->pm.current_mclk * 10;
 872                         wm_low.sclk = adev->pm.current_sclk * 10;
 873                 }
 874
 875                 wm_low.disp_clk = mode->clock;
 876                 wm_low.src_width = mode->crtc_hdisplay;
 877                 wm_low.active_time = active_time;
 878                 wm_low.blank_time = line_time - wm_low.active_time;
 879                 wm_low.interlaced = false;
 880                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 881                         wm_low.interlaced = true;
 882                 wm_low.vsc = amdgpu_crtc->vsc;
 883                 wm_low.vtaps = 1;
 884                 if (amdgpu_crtc->rmx_type != RMX_OFF)
 885                         wm_low.vtaps = 2;
 886                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
 887                 wm_low.lb_size = lb_size;
 888                 wm_low.dram_channels = dram_channels;
 889                 wm_low.num_heads = num_heads;
 890
 891                 /* set for high clocks */
 892                 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
 893                 /* set for low clocks */
 894                 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
 895
 896                 /* possibly force display priority to high */
 897                 /* should really do this at mode validation time... */
 898                 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
 899                     !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
 900                     !dce_v6_0_check_latency_hiding(&wm_high) ||
 901                     (adev->mode_info.disp_priority == 2)) {
 902                         DRM_DEBUG_KMS("force priority to high\n");
 903                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 904                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 905                 }
 906                 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
 907                     !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
 908                     !dce_v6_0_check_latency_hiding(&wm_low) ||
 909                     (adev->mode_info.disp_priority == 2)) {
 910                         DRM_DEBUG_KMS("force priority to high\n");
 911                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 912                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 913                 }
 914
 915                 a.full = dfixed_const(1000);
 916                 b.full = dfixed_const(mode->clock);
 917                 b.full = dfixed_div(b, a);
 918                 c.full = dfixed_const(latency_watermark_a);
 919                 c.full = dfixed_mul(c, b);
 920                 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
 921                 c.full = dfixed_div(c, a);
 922                 a.full = dfixed_const(16);
 923                 c.full = dfixed_div(c, a);
 924                 priority_a_mark = dfixed_trunc(c);
 925                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 926
 927                 a.full = dfixed_const(1000);
 928                 b.full = dfixed_const(mode->clock);
 929                 b.full = dfixed_div(b, a);
 930                 c.full = dfixed_const(latency_watermark_b);
 931                 c.full = dfixed_mul(c, b);
 932                 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
 933                 c.full = dfixed_div(c, a);
 934                 a.full = dfixed_const(16);
 935                 c.full = dfixed_div(c, a);
 936                 priority_b_mark = dfixed_trunc(c);
 937                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 938
 939                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
 940         }
 941
 942         /* select wm A */
 943         arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
 944         tmp = arb_control3;
 945         tmp &= ~LATENCY_WATERMARK_MASK(3);
 946         tmp |= LATENCY_WATERMARK_MASK(1);
 947         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
 948         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
 949                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT)  |
 950                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
 951         /* select wm B */
 952         tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
 953         tmp &= ~LATENCY_WATERMARK_MASK(3);
 954         tmp |= LATENCY_WATERMARK_MASK(2);
 955         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
 956         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
 957                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
 958                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
 959         /* restore original selection */
 960         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
 961
 962         /* write the priority marks */
 963         WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
 964         WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
 965
 966         /* save values for DPM */
 967         amdgpu_crtc->line_time = line_time;
 968         amdgpu_crtc->wm_high = latency_watermark_a;
 969
 970         /* Save number of lines the linebuffer leads before the scanout */
 971         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
 972 }
 973
 974 /* watermark setup */
 975 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
 976                                    struct amdgpu_crtc *amdgpu_crtc,
 977                                    struct drm_display_mode *mode,
 978                                    struct drm_display_mode *other_mode)
 979 {
 980         u32 tmp, buffer_alloc, i;
 981         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 982         /*
 983          * Line Buffer Setup
 984          * There are 3 line buffers, each one shared by 2 display controllers.
 985          * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 986          * the display controllers.  The paritioning is done via one of four
 987          * preset allocations specified in bits 21:20:
 988          *  0 - half lb
 989          *  2 - whole lb, other crtc must be disabled
 990          */
 991         /* this can get tricky if we have two large displays on a paired group
 992          * of crtcs.  Ideally for multiple large displays we'd assign them to
 993          * non-linked crtcs for maximum line buffer allocation.
 994          */
 995         if (amdgpu_crtc->base.enabled && mode) {
 996                 if (other_mode) {
 997                         tmp = 0; /* 1/2 */
 998                         buffer_alloc = 1;
 999                 } else {
1000                         tmp = 2; /* whole */
1001                         buffer_alloc = 2;
1002                 }
1003         } else {
1004                 tmp = 0;
1005                 buffer_alloc = 0;
1006         }
1007
1008         WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1009                DC_LB_MEMORY_CONFIG(tmp));
1010
1011         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1012                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1013         for (i = 0; i < adev->usec_timeout; i++) {
1014                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1015                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1016                         break;
1017                 udelay(1);
1018         }
1019
1020         if (amdgpu_crtc->base.enabled && mode) {
1021                 switch (tmp) {
1022                 case 0:
1023                 default:
1024                         return 4096 * 2;
1025                 case 2:
1026                         return 8192 * 2;
1027                 }
1028         }
1029
1030         /* controller not enabled, so no lb used */
1031         return 0;
1032 }
1033
1034
1035 /**
1036  *
1037  * dce_v6_0_bandwidth_update - program display watermarks
1038  *
1039  * @adev: amdgpu_device pointer
1040  *
1041  * Calculate and program the display watermarks and line
1042  * buffer allocation (CIK).
1043  */
1044 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1045 {
1046         struct drm_display_mode *mode0 = NULL;
1047         struct drm_display_mode *mode1 = NULL;
1048         u32 num_heads = 0, lb_size;
1049         int i;
1050
1051         if (!adev->mode_info.mode_config_initialized)
1052                 return;
1053
1054         amdgpu_display_update_priority(adev);
1055
1056         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1057                 if (adev->mode_info.crtcs[i]->base.enabled)
1058                         num_heads++;
1059         }
1060         for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1061                 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1062                 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1063                 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1064                 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1065                 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1066                 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1067         }
1068 }
1069
1070 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1071 {
1072         int i;
1073         u32 tmp;
1074
1075         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1076                 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
1077                                 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1078                 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1079                                         PORT_CONNECTIVITY))
1080                         adev->mode_info.audio.pin[i].connected = false;
1081                 else
1082                         adev->mode_info.audio.pin[i].connected = true;
1083         }
1084
1085 }
1086
1087 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1088 {
1089         int i;
1090
1091         dce_v6_0_audio_get_connected_pins(adev);
1092
1093         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1094                 if (adev->mode_info.audio.pin[i].connected)
1095                         return &adev->mode_info.audio.pin[i];
1096         }
1097         DRM_ERROR("No connected audio pins found!\n");
1098         return NULL;
1099 }
1100
1101 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
1102 {
1103         struct amdgpu_device *adev = encoder->dev->dev_private;
1104         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1105         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1106
1107         if (!dig || !dig->afmt || !dig->afmt->pin)
1108                 return;
1109
1110         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
1111                REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
1112                              dig->afmt->pin->id));
1113 }
1114
1115 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1116                                                 struct drm_display_mode *mode)
1117 {
1118         struct amdgpu_device *adev = encoder->dev->dev_private;
1119         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1120         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1121         struct drm_connector *connector;
1122         struct amdgpu_connector *amdgpu_connector = NULL;
1123         int interlace = 0;
1124         u32 tmp;
1125
1126         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1127                 if (connector->encoder == encoder) {
1128                         amdgpu_connector = to_amdgpu_connector(connector);
1129                         break;
1130                 }
1131         }
1132
1133         if (!amdgpu_connector) {
1134                 DRM_ERROR("Couldn't find encoder's connector\n");
1135                 return;
1136         }
1137
1138         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1139                 interlace = 1;
1140
1141         if (connector->latency_present[interlace]) {
1142                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1143                                 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1144                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1145                                 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1146         } else {
1147                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1148                                 VIDEO_LIPSYNC, 0);
1149                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1150                                 AUDIO_LIPSYNC, 0);
1151         }
1152         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1153                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1154 }
1155
1156 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1157 {
1158         struct amdgpu_device *adev = encoder->dev->dev_private;
1159         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1160         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1161         struct drm_connector *connector;
1162         struct amdgpu_connector *amdgpu_connector = NULL;
1163         u8 *sadb = NULL;
1164         int sad_count;
1165         u32 tmp;
1166
1167         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1168                 if (connector->encoder == encoder) {
1169                         amdgpu_connector = to_amdgpu_connector(connector);
1170                         break;
1171                 }
1172         }
1173
1174         if (!amdgpu_connector) {
1175                 DRM_ERROR("Couldn't find encoder's connector\n");
1176                 return;
1177         }
1178
1179         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1180         if (sad_count < 0) {
1181                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1182                 sad_count = 0;
1183         }
1184
1185         /* program the speaker allocation */
1186         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1187                         ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1188         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1189                         HDMI_CONNECTION, 0);
1190         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1191                         DP_CONNECTION, 0);
1192
1193         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
1194                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1195                                 DP_CONNECTION, 1);
1196         else
1197                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1198                                 HDMI_CONNECTION, 1);
1199
1200         if (sad_count)
1201                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1202                                 SPEAKER_ALLOCATION, sadb[0]);
1203         else
1204                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1205                                 SPEAKER_ALLOCATION, 5); /* stereo */
1206
1207         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1208                         ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1209
1210         kfree(sadb);
1211 }
1212
1213 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1214 {
1215         struct amdgpu_device *adev = encoder->dev->dev_private;
1216         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1217         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1218         struct drm_connector *connector;
1219         struct amdgpu_connector *amdgpu_connector = NULL;
1220         struct cea_sad *sads;
1221         int i, sad_count;
1222
1223         static const u16 eld_reg_to_type[][2] = {
1224                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1225                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1226                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1227                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1228                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1229                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1230                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1231                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1232                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1233                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1234                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1235                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1236         };
1237
1238         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1239                 if (connector->encoder == encoder) {
1240                         amdgpu_connector = to_amdgpu_connector(connector);
1241                         break;
1242                 }
1243         }
1244
1245         if (!amdgpu_connector) {
1246                 DRM_ERROR("Couldn't find encoder's connector\n");
1247                 return;
1248         }
1249
1250         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1251         if (sad_count <= 0) {
1252                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1253                 return;
1254         }
1255
1256         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1257                 u32 tmp = 0;
1258                 u8 stereo_freqs = 0;
1259                 int max_channels = -1;
1260                 int j;
1261
1262                 for (j = 0; j < sad_count; j++) {
1263                         struct cea_sad *sad = &sads[j];
1264
1265                         if (sad->format == eld_reg_to_type[i][1]) {
1266                                 if (sad->channels > max_channels) {
1267                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1268                                                         MAX_CHANNELS, sad->channels);
1269                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1270                                                         DESCRIPTOR_BYTE_2, sad->byte2);
1271                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1272                                                         SUPPORTED_FREQUENCIES, sad->freq);
1273                                         max_channels = sad->channels;
1274                                 }
1275
1276                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1277                                         stereo_freqs |= sad->freq;
1278                                 else
1279                                         break;
1280                         }
1281                 }
1282
1283                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1284                                 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1285                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1286         }
1287
1288         kfree(sads);
1289
1290 }
1291
1292 static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1293                                   struct amdgpu_audio_pin *pin,
1294                                   bool enable)
1295 {
1296         if (!pin)
1297                 return;
1298
1299         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1300                         enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1301 }
1302
1303 static const u32 pin_offsets[7] =
1304 {
1305         (0x1780 - 0x1780),
1306         (0x1786 - 0x1780),
1307         (0x178c - 0x1780),
1308         (0x1792 - 0x1780),
1309         (0x1798 - 0x1780),
1310         (0x179d - 0x1780),
1311         (0x17a4 - 0x1780),
1312 };
1313
1314 static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1315 {
1316         int i;
1317
1318         if (!amdgpu_audio)
1319                 return 0;
1320
1321         adev->mode_info.audio.enabled = true;
1322
1323         switch (adev->asic_type) {
1324         case CHIP_TAHITI:
1325         case CHIP_PITCAIRN:
1326         case CHIP_VERDE:
1327         default:
1328                 adev->mode_info.audio.num_pins = 6;
1329                 break;
1330         case CHIP_OLAND:
1331                 adev->mode_info.audio.num_pins = 2;
1332                 break;
1333         }
1334
1335         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1336                 adev->mode_info.audio.pin[i].channels = -1;
1337                 adev->mode_info.audio.pin[i].rate = -1;
1338                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1339                 adev->mode_info.audio.pin[i].status_bits = 0;
1340                 adev->mode_info.audio.pin[i].category_code = 0;
1341                 adev->mode_info.audio.pin[i].connected = false;
1342                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1343                 adev->mode_info.audio.pin[i].id = i;
1344                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1345         }
1346
1347         return 0;
1348 }
1349
1350 static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1351 {
1352         int i;
1353
1354         if (!amdgpu_audio)
1355                 return;
1356
1357         if (!adev->mode_info.audio.enabled)
1358                 return;
1359
1360         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1361                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1362
1363         adev->mode_info.audio.enabled = false;
1364 }
1365
1366 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
1367 {
1368         struct drm_device *dev = encoder->dev;
1369         struct amdgpu_device *adev = dev->dev_private;
1370         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1371         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1372         u32 tmp;
1373
1374         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1375         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1376         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
1377         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
1378         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1379 }
1380
1381 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
1382                                    uint32_t clock, int bpc)
1383 {
1384         struct drm_device *dev = encoder->dev;
1385         struct amdgpu_device *adev = dev->dev_private;
1386         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1387         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1388         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1389         u32 tmp;
1390
1391         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1392         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1393         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
1394                         bpc > 8 ? 0 : 1);
1395         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1396
1397         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1398         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1399         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1400         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1401         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1402         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1403
1404         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1405         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1406         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1407         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1408         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1409         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1410
1411         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1412         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1413         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1414         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1415         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1416         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1417 }
1418
1419 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
1420                                                struct drm_display_mode *mode)
1421 {
1422         struct drm_device *dev = encoder->dev;
1423         struct amdgpu_device *adev = dev->dev_private;
1424         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1425         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1426         struct hdmi_avi_infoframe frame;
1427         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1428         uint8_t *payload = buffer + 3;
1429         uint8_t *header = buffer;
1430         ssize_t err;
1431         u32 tmp;
1432
1433         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1434         if (err < 0) {
1435                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1436                 return;
1437         }
1438
1439         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1440         if (err < 0) {
1441                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1442                 return;
1443         }
1444
1445         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1446                payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24));
1447         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1448                payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24));
1449         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1450                payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24));
1451         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1452                payload[0xC] | (payload[0xD] << 8) | (header[1] << 24));
1453
1454         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1455         /* anything other than 0 */
1456         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
1457                         HDMI_AUDIO_INFO_LINE, 2);
1458         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1459 }
1460
1461 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1462 {
1463         struct drm_device *dev = encoder->dev;
1464         struct amdgpu_device *adev = dev->dev_private;
1465         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1466         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1467         u32 tmp;
1468
1469         /*
1470          * Two dtos: generally use dto0 for hdmi, dto1 for dp.
1471          * Express [24MHz / target pixel clock] as an exact rational
1472          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1473          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1474          */
1475         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1476         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1477                         DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
1478         if (em == ATOM_ENCODER_MODE_HDMI) {
1479                 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1480                                 DCCG_AUDIO_DTO_SEL, 0);
1481         } else if (ENCODER_MODE_IS_DP(em)) {
1482                 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1483                                 DCCG_AUDIO_DTO_SEL, 1);
1484         }
1485         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1486         if (em == ATOM_ENCODER_MODE_HDMI) {
1487                 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000);
1488                 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);
1489         } else if (ENCODER_MODE_IS_DP(em)) {
1490                 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
1491                 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
1492         }
1493 }
1494
1495 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
1496 {
1497         struct drm_device *dev = encoder->dev;
1498         struct amdgpu_device *adev = dev->dev_private;
1499         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1500         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1501         u32 tmp;
1502
1503         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1504         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1505         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1506
1507         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1508         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1509         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1510
1511         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1512         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1513         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1514
1515         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1516         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1517         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1518         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1519         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1520         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1521         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1522         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1523
1524         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
1525         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
1526         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
1527
1528         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1529         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1530         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1531         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1532
1533         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1534         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
1535         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1536         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1537 }
1538
1539 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
1540 {
1541         struct drm_device *dev = encoder->dev;
1542         struct amdgpu_device *adev = dev->dev_private;
1543         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1544         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1545         u32 tmp;
1546
1547         tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
1548         tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
1549         WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
1550 }
1551
1552 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
1553 {
1554         struct drm_device *dev = encoder->dev;
1555         struct amdgpu_device *adev = dev->dev_private;
1556         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1557         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1558         u32 tmp;
1559
1560         if (enable) {
1561                 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1562                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1563                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1564                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1565                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1566                 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1567
1568                 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1569                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1570                 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1571
1572                 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1573                 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1574                 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1575         } else {
1576                 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1577                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
1578                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
1579                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
1580                 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
1581                 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1582
1583                 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1584                 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
1585                 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1586         }
1587 }
1588
1589 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
1590 {
1591         struct drm_device *dev = encoder->dev;
1592         struct amdgpu_device *adev = dev->dev_private;
1593         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1594         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1595         u32 tmp;
1596
1597         if (enable) {
1598                 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1599                 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1600                 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1601
1602                 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
1603                 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
1604                 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
1605
1606                 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
1607                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1608                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
1609                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
1610                 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1611                 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
1612         } else {
1613                 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
1614         }
1615 }
1616
1617 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1618                                   struct drm_display_mode *mode)
1619 {
1620         struct drm_device *dev = encoder->dev;
1621         struct amdgpu_device *adev = dev->dev_private;
1622         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1623         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1624         struct drm_connector *connector;
1625         struct amdgpu_connector *amdgpu_connector = NULL;
1626         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1627         int bpc = 8;
1628
1629         if (!dig || !dig->afmt)
1630                 return;
1631
1632         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1633                 if (connector->encoder == encoder) {
1634                         amdgpu_connector = to_amdgpu_connector(connector);
1635                         break;
1636                 }
1637         }
1638
1639         if (!amdgpu_connector) {
1640                 DRM_ERROR("Couldn't find encoder's connector\n");
1641                 return;
1642         }
1643
1644         if (!dig->afmt->enabled)
1645                 return;
1646
1647         dig->afmt->pin = dce_v6_0_audio_get_pin(adev);
1648         if (!dig->afmt->pin)
1649                 return;
1650
1651         if (encoder->crtc) {
1652                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1653                 bpc = amdgpu_crtc->bpc;
1654         }
1655
1656         /* disable audio before setting up hw */
1657         dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1658
1659         dce_v6_0_audio_set_mute(encoder, true);
1660         dce_v6_0_audio_write_speaker_allocation(encoder);
1661         dce_v6_0_audio_write_sad_regs(encoder);
1662         dce_v6_0_audio_write_latency_fields(encoder, mode);
1663         if (em == ATOM_ENCODER_MODE_HDMI) {
1664                 dce_v6_0_audio_set_dto(encoder, mode->clock);
1665                 dce_v6_0_audio_set_vbi_packet(encoder);
1666                 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc);
1667         } else if (ENCODER_MODE_IS_DP(em)) {
1668                 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);
1669         }
1670         dce_v6_0_audio_set_packet(encoder);
1671         dce_v6_0_audio_select_pin(encoder);
1672         dce_v6_0_audio_set_avi_infoframe(encoder, mode);
1673         dce_v6_0_audio_set_mute(encoder, false);
1674         if (em == ATOM_ENCODER_MODE_HDMI) {
1675                 dce_v6_0_audio_hdmi_enable(encoder, 1);
1676         } else if (ENCODER_MODE_IS_DP(em)) {
1677                 dce_v6_0_audio_dp_enable(encoder, 1);
1678         }
1679
1680         /* enable audio after setting up hw */
1681         dce_v6_0_audio_enable(adev, dig->afmt->pin, true);
1682 }
1683
1684 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1685 {
1686         struct drm_device *dev = encoder->dev;
1687         struct amdgpu_device *adev = dev->dev_private;
1688         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1689         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1690
1691         if (!dig || !dig->afmt)
1692                 return;
1693
1694         /* Silent, r600_hdmi_enable will raise WARN for us */
1695         if (enable && dig->afmt->enabled)
1696                 return;
1697
1698         if (!enable && !dig->afmt->enabled)
1699                 return;
1700
1701         if (!enable && dig->afmt->pin) {
1702                 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1703                 dig->afmt->pin = NULL;
1704         }
1705
1706         dig->afmt->enabled = enable;
1707
1708         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1709                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1710 }
1711
1712 static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1713 {
1714         int i, j;
1715
1716         for (i = 0; i < adev->mode_info.num_dig; i++)
1717                 adev->mode_info.afmt[i] = NULL;
1718
1719         /* DCE6 has audio blocks tied to DIG encoders */
1720         for (i = 0; i < adev->mode_info.num_dig; i++) {
1721                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1722                 if (adev->mode_info.afmt[i]) {
1723                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1724                         adev->mode_info.afmt[i]->id = i;
1725                 } else {
1726                         for (j = 0; j < i; j++) {
1727                                 kfree(adev->mode_info.afmt[j]);
1728                                 adev->mode_info.afmt[j] = NULL;
1729                         }
1730                         DRM_ERROR("Out of memory allocating afmt table\n");
1731                         return -ENOMEM;
1732                 }
1733         }
1734         return 0;
1735 }
1736
1737 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1738 {
1739         int i;
1740
1741         for (i = 0; i < adev->mode_info.num_dig; i++) {
1742                 kfree(adev->mode_info.afmt[i]);
1743                 adev->mode_info.afmt[i] = NULL;
1744         }
1745 }
1746
1747 static const u32 vga_control_regs[6] =
1748 {
1749         mmD1VGA_CONTROL,
1750         mmD2VGA_CONTROL,
1751         mmD3VGA_CONTROL,
1752         mmD4VGA_CONTROL,
1753         mmD5VGA_CONTROL,
1754         mmD6VGA_CONTROL,
1755 };
1756
1757 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1758 {
1759         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1760         struct drm_device *dev = crtc->dev;
1761         struct amdgpu_device *adev = dev->dev_private;
1762         u32 vga_control;
1763
1764         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1765         WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1766 }
1767
1768 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1769 {
1770         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1771         struct drm_device *dev = crtc->dev;
1772         struct amdgpu_device *adev = dev->dev_private;
1773
1774         WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1775 }
1776
1777 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1778                                      struct drm_framebuffer *fb,
1779                                      int x, int y, int atomic)
1780 {
1781         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1782         struct drm_device *dev = crtc->dev;
1783         struct amdgpu_device *adev = dev->dev_private;
1784         struct drm_framebuffer *target_fb;
1785         struct drm_gem_object *obj;
1786         struct amdgpu_bo *abo;
1787         uint64_t fb_location, tiling_flags;
1788         uint32_t fb_format, fb_pitch_pixels, pipe_config;
1789         u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1790         u32 viewport_w, viewport_h;
1791         int r;
1792         bool bypass_lut = false;
1793         struct drm_format_name_buf format_name;
1794
1795         /* no fb bound */
1796         if (!atomic && !crtc->primary->fb) {
1797                 DRM_DEBUG_KMS("No FB bound\n");
1798                 return 0;
1799         }
1800
1801         if (atomic)
1802                 target_fb = fb;
1803         else
1804                 target_fb = crtc->primary->fb;
1805
1806         /* If atomic, assume fb object is pinned & idle & fenced and
1807          * just update base pointers
1808          */
1809         obj = target_fb->obj[0];
1810         abo = gem_to_amdgpu_bo(obj);
1811         r = amdgpu_bo_reserve(abo, false);
1812         if (unlikely(r != 0))
1813                 return r;
1814
1815         if (!atomic) {
1816                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1817                 if (unlikely(r != 0)) {
1818                         amdgpu_bo_unreserve(abo);
1819                         return -EINVAL;
1820                 }
1821         }
1822         fb_location = amdgpu_bo_gpu_offset(abo);
1823
1824         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825         amdgpu_bo_unreserve(abo);
1826
1827         switch (target_fb->format->format) {
1828         case DRM_FORMAT_C8:
1829                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1830                              GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1831                 break;
1832         case DRM_FORMAT_XRGB4444:
1833         case DRM_FORMAT_ARGB4444:
1834                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1835                              GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1836 #ifdef __BIG_ENDIAN
1837                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1838 #endif
1839                 break;
1840         case DRM_FORMAT_XRGB1555:
1841         case DRM_FORMAT_ARGB1555:
1842                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1843                              GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1844 #ifdef __BIG_ENDIAN
1845                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1846 #endif
1847                 break;
1848         case DRM_FORMAT_BGRX5551:
1849         case DRM_FORMAT_BGRA5551:
1850                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1851                              GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1852 #ifdef __BIG_ENDIAN
1853                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1854 #endif
1855                 break;
1856         case DRM_FORMAT_RGB565:
1857                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1858                              GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1859 #ifdef __BIG_ENDIAN
1860                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1861 #endif
1862                 break;
1863         case DRM_FORMAT_XRGB8888:
1864         case DRM_FORMAT_ARGB8888:
1865                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1866                              GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1867 #ifdef __BIG_ENDIAN
1868                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1869 #endif
1870                 break;
1871         case DRM_FORMAT_XRGB2101010:
1872         case DRM_FORMAT_ARGB2101010:
1873                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1874                              GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1875 #ifdef __BIG_ENDIAN
1876                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1877 #endif
1878                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1879                 bypass_lut = true;
1880                 break;
1881         case DRM_FORMAT_BGRX1010102:
1882         case DRM_FORMAT_BGRA1010102:
1883                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1884                              GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1885 #ifdef __BIG_ENDIAN
1886                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1887 #endif
1888                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1889                 bypass_lut = true;
1890                 break;
1891         default:
1892                 DRM_ERROR("Unsupported screen format %s\n",
1893                           drm_get_format_name(target_fb->format->format, &format_name));
1894                 return -EINVAL;
1895         }
1896
1897         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1898                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1899
1900                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1901                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1902                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1903                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1904                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1905
1906                 fb_format |= GRPH_NUM_BANKS(num_banks);
1907                 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1908                 fb_format |= GRPH_TILE_SPLIT(tile_split);
1909                 fb_format |= GRPH_BANK_WIDTH(bankw);
1910                 fb_format |= GRPH_BANK_HEIGHT(bankh);
1911                 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1912         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1913                 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1914         }
1915
1916         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1917         fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1918
1919         dce_v6_0_vga_enable(crtc, false);
1920
1921         /* Make sure surface address is updated at vertical blank rather than
1922          * horizontal blank
1923          */
1924         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1925
1926         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1927                upper_32_bits(fb_location));
1928         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1929                upper_32_bits(fb_location));
1930         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1931                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1932         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1933                (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1934         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1935         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1936
1937         /*
1938          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1939          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1940          * retain the full precision throughout the pipeline.
1941          */
1942         WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1943                  (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1944                  ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1945
1946         if (bypass_lut)
1947                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1948
1949         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1950         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1951         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1952         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1953         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1954         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1955
1956         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1957         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1958
1959         dce_v6_0_grph_enable(crtc, true);
1960
1961         WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1962                        target_fb->height);
1963         x &= ~3;
1964         y &= ~1;
1965         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1966                (x << 16) | y);
1967         viewport_w = crtc->mode.hdisplay;
1968         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1969
1970         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1971                (viewport_w << 16) | viewport_h);
1972
1973         /* set pageflip to happen anywhere in vblank interval */
1974         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1975
1976         if (!atomic && fb && fb != crtc->primary->fb) {
1977                 abo = gem_to_amdgpu_bo(fb->obj[0]);
1978                 r = amdgpu_bo_reserve(abo, true);
1979                 if (unlikely(r != 0))
1980                         return r;
1981                 amdgpu_bo_unpin(abo);
1982                 amdgpu_bo_unreserve(abo);
1983         }
1984
1985         /* Bytes per pixel may have changed */
1986         dce_v6_0_bandwidth_update(adev);
1987
1988         return 0;
1989
1990 }
1991
1992 static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1993                                     struct drm_display_mode *mode)
1994 {
1995         struct drm_device *dev = crtc->dev;
1996         struct amdgpu_device *adev = dev->dev_private;
1997         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1998
1999         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2000                 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
2001                        INTERLEAVE_EN);
2002         else
2003                 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2004 }
2005
2006 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
2007 {
2008
2009         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2010         struct drm_device *dev = crtc->dev;
2011         struct amdgpu_device *adev = dev->dev_private;
2012         u16 *r, *g, *b;
2013         int i;
2014
2015         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2016
2017         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2018                ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2019                 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2020         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2021                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2022         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2023                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2024         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2025                ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2026                 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2027
2028         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2029
2030         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2031         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2032         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2033
2034         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2035         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2036         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2037
2038         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2039         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2040
2041         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2042         r = crtc->gamma_store;
2043         g = r + crtc->gamma_size;
2044         b = g + crtc->gamma_size;
2045         for (i = 0; i < 256; i++) {
2046                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2047                        ((*r++ & 0xffc0) << 14) |
2048                        ((*g++ & 0xffc0) << 4) |
2049                        (*b++ >> 6));
2050         }
2051
2052         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2053                ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2054                 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2055                 ICON_DEGAMMA_MODE(0) |
2056                 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2057         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2058                ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2059                 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2060         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2061                ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2062                 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2063         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2064                ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2065                 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2066         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2067         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2068
2069
2070 }
2071
2072 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
2073 {
2074         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2075         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2076
2077         switch (amdgpu_encoder->encoder_id) {
2078         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2079                 return dig->linkb ? 1 : 0;
2080         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2081                 return dig->linkb ? 3 : 2;
2082         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2083                 return dig->linkb ? 5 : 4;
2084         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2085                 return 6;
2086         default:
2087                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2088                 return 0;
2089         }
2090 }
2091
2092 /**
2093  * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2094  *
2095  * @crtc: drm crtc
2096  *
2097  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2098  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2099  * monitors a dedicated PPLL must be used.  If a particular board has
2100  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2101  * as there is no need to program the PLL itself.  If we are not able to
2102  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2103  * avoid messing up an existing monitor.
2104  *
2105  *
2106  */
2107 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
2108 {
2109         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2110         struct drm_device *dev = crtc->dev;
2111         struct amdgpu_device *adev = dev->dev_private;
2112         u32 pll_in_use;
2113         int pll;
2114
2115         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2116                 if (adev->clock.dp_extclk)
2117                         /* skip PPLL programming if using ext clock */
2118                         return ATOM_PPLL_INVALID;
2119                 else
2120                         return ATOM_PPLL0;
2121         } else {
2122                 /* use the same PPLL for all monitors with the same clock */
2123                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2124                 if (pll != ATOM_PPLL_INVALID)
2125                         return pll;
2126         }
2127
2128         /*  PPLL1, and PPLL2 */
2129         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2130         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2131                 return ATOM_PPLL2;
2132         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2133                 return ATOM_PPLL1;
2134         DRM_ERROR("unable to allocate a PPLL\n");
2135         return ATOM_PPLL_INVALID;
2136 }
2137
2138 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2139 {
2140         struct amdgpu_device *adev = crtc->dev->dev_private;
2141         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142         uint32_t cur_lock;
2143
2144         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2145         if (lock)
2146                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2147         else
2148                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2149         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2150 }
2151
2152 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
2153 {
2154         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2155         struct amdgpu_device *adev = crtc->dev->dev_private;
2156
2157         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2158                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2159                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2160
2161
2162 }
2163
2164 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
2165 {
2166         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2167         struct amdgpu_device *adev = crtc->dev->dev_private;
2168
2169         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2170                upper_32_bits(amdgpu_crtc->cursor_addr));
2171         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2172                lower_32_bits(amdgpu_crtc->cursor_addr));
2173
2174         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2175                    CUR_CONTROL__CURSOR_EN_MASK |
2176                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2177                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2178
2179 }
2180
2181 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
2182                                        int x, int y)
2183 {
2184         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2185         struct amdgpu_device *adev = crtc->dev->dev_private;
2186         int xorigin = 0, yorigin = 0;
2187
2188         int w = amdgpu_crtc->cursor_width;
2189
2190         amdgpu_crtc->cursor_x = x;
2191         amdgpu_crtc->cursor_y = y;
2192
2193         /* avivo cursor are offset into the total surface */
2194         x += crtc->x;
2195         y += crtc->y;
2196         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2197
2198         if (x < 0) {
2199                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2200                 x = 0;
2201         }
2202         if (y < 0) {
2203                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2204                 y = 0;
2205         }
2206
2207         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2208         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2209         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2210                ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2211
2212         return 0;
2213 }
2214
2215 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
2216                                      int x, int y)
2217 {
2218         int ret;
2219
2220         dce_v6_0_lock_cursor(crtc, true);
2221         ret = dce_v6_0_cursor_move_locked(crtc, x, y);
2222         dce_v6_0_lock_cursor(crtc, false);
2223
2224         return ret;
2225 }
2226
2227 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
2228                                      struct drm_file *file_priv,
2229                                      uint32_t handle,
2230                                      uint32_t width,
2231                                      uint32_t height,
2232                                      int32_t hot_x,
2233                                      int32_t hot_y)
2234 {
2235         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2236         struct drm_gem_object *obj;
2237         struct amdgpu_bo *aobj;
2238         int ret;
2239
2240         if (!handle) {
2241                 /* turn off cursor */
2242                 dce_v6_0_hide_cursor(crtc);
2243                 obj = NULL;
2244                 goto unpin;
2245         }
2246
2247         if ((width > amdgpu_crtc->max_cursor_width) ||
2248             (height > amdgpu_crtc->max_cursor_height)) {
2249                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2250                 return -EINVAL;
2251         }
2252
2253         obj = drm_gem_object_lookup(file_priv, handle);
2254         if (!obj) {
2255                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2256                 return -ENOENT;
2257         }
2258
2259         aobj = gem_to_amdgpu_bo(obj);
2260         ret = amdgpu_bo_reserve(aobj, false);
2261         if (ret != 0) {
2262                 drm_gem_object_put_unlocked(obj);
2263                 return ret;
2264         }
2265
2266         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2267         amdgpu_bo_unreserve(aobj);
2268         if (ret) {
2269                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2270                 drm_gem_object_put_unlocked(obj);
2271                 return ret;
2272         }
2273         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2274
2275         dce_v6_0_lock_cursor(crtc, true);
2276
2277         if (width != amdgpu_crtc->cursor_width ||
2278             height != amdgpu_crtc->cursor_height ||
2279             hot_x != amdgpu_crtc->cursor_hot_x ||
2280             hot_y != amdgpu_crtc->cursor_hot_y) {
2281                 int x, y;
2282
2283                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2284                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2285
2286                 dce_v6_0_cursor_move_locked(crtc, x, y);
2287
2288                 amdgpu_crtc->cursor_width = width;
2289                 amdgpu_crtc->cursor_height = height;
2290                 amdgpu_crtc->cursor_hot_x = hot_x;
2291                 amdgpu_crtc->cursor_hot_y = hot_y;
2292         }
2293
2294         dce_v6_0_show_cursor(crtc);
2295         dce_v6_0_lock_cursor(crtc, false);
2296
2297 unpin:
2298         if (amdgpu_crtc->cursor_bo) {
2299                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2300                 ret = amdgpu_bo_reserve(aobj, true);
2301                 if (likely(ret == 0)) {
2302                         amdgpu_bo_unpin(aobj);
2303                         amdgpu_bo_unreserve(aobj);
2304                 }
2305                 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2306         }
2307
2308         amdgpu_crtc->cursor_bo = obj;
2309         return 0;
2310 }
2311
2312 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
2313 {
2314         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2315
2316         if (amdgpu_crtc->cursor_bo) {
2317                 dce_v6_0_lock_cursor(crtc, true);
2318
2319                 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2320                                             amdgpu_crtc->cursor_y);
2321
2322                 dce_v6_0_show_cursor(crtc);
2323                 dce_v6_0_lock_cursor(crtc, false);
2324         }
2325 }
2326
2327 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2328                                    u16 *blue, uint32_t size,
2329                                    struct drm_modeset_acquire_ctx *ctx)
2330 {
2331         dce_v6_0_crtc_load_lut(crtc);
2332
2333         return 0;
2334 }
2335
2336 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2337 {
2338         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2339
2340         drm_crtc_cleanup(crtc);
2341         kfree(amdgpu_crtc);
2342 }
2343
2344 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2345         .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2346         .cursor_move = dce_v6_0_crtc_cursor_move,
2347         .gamma_set = dce_v6_0_crtc_gamma_set,
2348         .set_config = amdgpu_display_crtc_set_config,
2349         .destroy = dce_v6_0_crtc_destroy,
2350         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2351 };
2352
2353 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2354 {
2355         struct drm_device *dev = crtc->dev;
2356         struct amdgpu_device *adev = dev->dev_private;
2357         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2358         unsigned type;
2359
2360         switch (mode) {
2361         case DRM_MODE_DPMS_ON:
2362                 amdgpu_crtc->enabled = true;
2363                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2364                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2365                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2366                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2367                                                 amdgpu_crtc->crtc_id);
2368                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2369                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2370                 drm_crtc_vblank_on(crtc);
2371                 dce_v6_0_crtc_load_lut(crtc);
2372                 break;
2373         case DRM_MODE_DPMS_STANDBY:
2374         case DRM_MODE_DPMS_SUSPEND:
2375         case DRM_MODE_DPMS_OFF:
2376                 drm_crtc_vblank_off(crtc);
2377                 if (amdgpu_crtc->enabled)
2378                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2379                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2380                 amdgpu_crtc->enabled = false;
2381                 break;
2382         }
2383         /* adjust pm to dpms */
2384         amdgpu_pm_compute_clocks(adev);
2385 }
2386
2387 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2388 {
2389         /* disable crtc pair power gating before programming */
2390         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2391         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2392         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2393 }
2394
2395 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2396 {
2397         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2398         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2399 }
2400
2401 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2402 {
2403
2404         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405         struct drm_device *dev = crtc->dev;
2406         struct amdgpu_device *adev = dev->dev_private;
2407         struct amdgpu_atom_ss ss;
2408         int i;
2409
2410         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2411         if (crtc->primary->fb) {
2412                 int r;
2413                 struct amdgpu_bo *abo;
2414
2415                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2416                 r = amdgpu_bo_reserve(abo, true);
2417                 if (unlikely(r))
2418                         DRM_ERROR("failed to reserve abo before unpin\n");
2419                 else {
2420                         amdgpu_bo_unpin(abo);
2421                         amdgpu_bo_unreserve(abo);
2422                 }
2423         }
2424         /* disable the GRPH */
2425         dce_v6_0_grph_enable(crtc, false);
2426
2427         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2428
2429         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2430                 if (adev->mode_info.crtcs[i] &&
2431                     adev->mode_info.crtcs[i]->enabled &&
2432                     i != amdgpu_crtc->crtc_id &&
2433                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2434                         /* one other crtc is using this pll don't turn
2435                          * off the pll
2436                          */
2437                         goto done;
2438                 }
2439         }
2440
2441         switch (amdgpu_crtc->pll_id) {
2442         case ATOM_PPLL1:
2443         case ATOM_PPLL2:
2444                 /* disable the ppll */
2445                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2446                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2447                 break;
2448         default:
2449                 break;
2450         }
2451 done:
2452         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2453         amdgpu_crtc->adjusted_clock = 0;
2454         amdgpu_crtc->encoder = NULL;
2455         amdgpu_crtc->connector = NULL;
2456 }
2457
2458 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2459                                   struct drm_display_mode *mode,
2460                                   struct drm_display_mode *adjusted_mode,
2461                                   int x, int y, struct drm_framebuffer *old_fb)
2462 {
2463         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464
2465         if (!amdgpu_crtc->adjusted_clock)
2466                 return -EINVAL;
2467
2468         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2469         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2470         dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2471         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2472         amdgpu_atombios_crtc_scaler_setup(crtc);
2473         dce_v6_0_cursor_reset(crtc);
2474         /* update the hw version fpr dpm */
2475         amdgpu_crtc->hw_mode = *adjusted_mode;
2476
2477         return 0;
2478 }
2479
2480 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2481                                      const struct drm_display_mode *mode,
2482                                      struct drm_display_mode *adjusted_mode)
2483 {
2484
2485         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2486         struct drm_device *dev = crtc->dev;
2487         struct drm_encoder *encoder;
2488
2489         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2490         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2491                 if (encoder->crtc == crtc) {
2492                         amdgpu_crtc->encoder = encoder;
2493                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2494                         break;
2495                 }
2496         }
2497         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2498                 amdgpu_crtc->encoder = NULL;
2499                 amdgpu_crtc->connector = NULL;
2500                 return false;
2501         }
2502         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2503                 return false;
2504         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2505                 return false;
2506         /* pick pll */
2507         amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2508         /* if we can't get a PPLL for a non-DP encoder, fail */
2509         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2510             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2511                 return false;
2512
2513         return true;
2514 }
2515
2516 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2517                                   struct drm_framebuffer *old_fb)
2518 {
2519         return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2520 }
2521
2522 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2523                                          struct drm_framebuffer *fb,
2524                                          int x, int y, enum mode_set_atomic state)
2525 {
2526        return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2527 }
2528
2529 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2530         .dpms = dce_v6_0_crtc_dpms,
2531         .mode_fixup = dce_v6_0_crtc_mode_fixup,
2532         .mode_set = dce_v6_0_crtc_mode_set,
2533         .mode_set_base = dce_v6_0_crtc_set_base,
2534         .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2535         .prepare = dce_v6_0_crtc_prepare,
2536         .commit = dce_v6_0_crtc_commit,
2537         .disable = dce_v6_0_crtc_disable,
2538 };
2539
2540 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2541 {
2542         struct amdgpu_crtc *amdgpu_crtc;
2543
2544         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2545                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2546         if (amdgpu_crtc == NULL)
2547                 return -ENOMEM;
2548
2549         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2550
2551         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2552         amdgpu_crtc->crtc_id = index;
2553         adev->mode_info.crtcs[index] = amdgpu_crtc;
2554
2555         amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2556         amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2557         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2558         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2559
2560         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2561
2562         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2563         amdgpu_crtc->adjusted_clock = 0;
2564         amdgpu_crtc->encoder = NULL;
2565         amdgpu_crtc->connector = NULL;
2566         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2567
2568         return 0;
2569 }
2570
2571 static int dce_v6_0_early_init(void *handle)
2572 {
2573         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2574
2575         adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2576         adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2577
2578         dce_v6_0_set_display_funcs(adev);
2579
2580         adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2581
2582         switch (adev->asic_type) {
2583         case CHIP_TAHITI:
2584         case CHIP_PITCAIRN:
2585         case CHIP_VERDE:
2586                 adev->mode_info.num_hpd = 6;
2587                 adev->mode_info.num_dig = 6;
2588                 break;
2589         case CHIP_OLAND:
2590                 adev->mode_info.num_hpd = 2;
2591                 adev->mode_info.num_dig = 2;
2592                 break;
2593         default:
2594                 return -EINVAL;
2595         }
2596
2597         dce_v6_0_set_irq_funcs(adev);
2598
2599         return 0;
2600 }
2601
2602 static int dce_v6_0_sw_init(void *handle)
2603 {
2604         int r, i;
2605         bool ret;
2606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2607
2608         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2609                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2610                 if (r)
2611                         return r;
2612         }
2613
2614         for (i = 8; i < 20; i += 2) {
2615                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2616                 if (r)
2617                         return r;
2618         }
2619
2620         /* HPD hotplug */
2621         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2622         if (r)
2623                 return r;
2624
2625         adev->mode_info.mode_config_initialized = true;
2626
2627         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2628         adev->ddev->mode_config.async_page_flip = true;
2629         adev->ddev->mode_config.max_width = 16384;
2630         adev->ddev->mode_config.max_height = 16384;
2631         adev->ddev->mode_config.preferred_depth = 24;
2632         adev->ddev->mode_config.prefer_shadow = 1;
2633         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2634
2635         r = amdgpu_display_modeset_create_props(adev);
2636         if (r)
2637                 return r;
2638
2639         adev->ddev->mode_config.max_width = 16384;
2640         adev->ddev->mode_config.max_height = 16384;
2641
2642         /* allocate crtcs */
2643         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2644                 r = dce_v6_0_crtc_init(adev, i);
2645                 if (r)
2646                         return r;
2647         }
2648
2649         ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2650         if (ret)
2651                 amdgpu_display_print_display_setup(adev->ddev);
2652         else
2653                 return -EINVAL;
2654
2655         /* setup afmt */
2656         r = dce_v6_0_afmt_init(adev);
2657         if (r)
2658                 return r;
2659
2660         r = dce_v6_0_audio_init(adev);
2661         if (r)
2662                 return r;
2663
2664         drm_kms_helper_poll_init(adev->ddev);
2665
2666         return r;
2667 }
2668
2669 static int dce_v6_0_sw_fini(void *handle)
2670 {
2671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2672
2673         kfree(adev->mode_info.bios_hardcoded_edid);
2674
2675         drm_kms_helper_poll_fini(adev->ddev);
2676
2677         dce_v6_0_audio_fini(adev);
2678         dce_v6_0_afmt_fini(adev);
2679
2680         drm_mode_config_cleanup(adev->ddev);
2681         adev->mode_info.mode_config_initialized = false;
2682
2683         return 0;
2684 }
2685
2686 static int dce_v6_0_hw_init(void *handle)
2687 {
2688         int i;
2689         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2690
2691         /* disable vga render */
2692         dce_v6_0_set_vga_render_state(adev, false);
2693         /* init dig PHYs, disp eng pll */
2694         amdgpu_atombios_encoder_init_dig(adev);
2695         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2696
2697         /* initialize hpd */
2698         dce_v6_0_hpd_init(adev);
2699
2700         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2701                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2702         }
2703
2704         dce_v6_0_pageflip_interrupt_init(adev);
2705
2706         return 0;
2707 }
2708
2709 static int dce_v6_0_hw_fini(void *handle)
2710 {
2711         int i;
2712         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2713
2714         dce_v6_0_hpd_fini(adev);
2715
2716         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2717                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2718         }
2719
2720         dce_v6_0_pageflip_interrupt_fini(adev);
2721
2722         return 0;
2723 }
2724
2725 static int dce_v6_0_suspend(void *handle)
2726 {
2727         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2728
2729         adev->mode_info.bl_level =
2730                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2731
2732         return dce_v6_0_hw_fini(handle);
2733 }
2734
2735 static int dce_v6_0_resume(void *handle)
2736 {
2737         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2738         int ret;
2739
2740         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2741                                                            adev->mode_info.bl_level);
2742
2743         ret = dce_v6_0_hw_init(handle);
2744
2745         /* turn on the BL */
2746         if (adev->mode_info.bl_encoder) {
2747                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2748                                                                   adev->mode_info.bl_encoder);
2749                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2750                                                     bl_level);
2751         }
2752
2753         return ret;
2754 }
2755
2756 static bool dce_v6_0_is_idle(void *handle)
2757 {
2758         return true;
2759 }
2760
2761 static int dce_v6_0_wait_for_idle(void *handle)
2762 {
2763         return 0;
2764 }
2765
2766 static int dce_v6_0_soft_reset(void *handle)
2767 {
2768         DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2769         return 0;
2770 }
2771
2772 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2773                                                      int crtc,
2774                                                      enum amdgpu_interrupt_state state)
2775 {
2776         u32 reg_block, interrupt_mask;
2777
2778         if (crtc >= adev->mode_info.num_crtc) {
2779                 DRM_DEBUG("invalid crtc %d\n", crtc);
2780                 return;
2781         }
2782
2783         switch (crtc) {
2784         case 0:
2785                 reg_block = SI_CRTC0_REGISTER_OFFSET;
2786                 break;
2787         case 1:
2788                 reg_block = SI_CRTC1_REGISTER_OFFSET;
2789                 break;
2790         case 2:
2791                 reg_block = SI_CRTC2_REGISTER_OFFSET;
2792                 break;
2793         case 3:
2794                 reg_block = SI_CRTC3_REGISTER_OFFSET;
2795                 break;
2796         case 4:
2797                 reg_block = SI_CRTC4_REGISTER_OFFSET;
2798                 break;
2799         case 5:
2800                 reg_block = SI_CRTC5_REGISTER_OFFSET;
2801                 break;
2802         default:
2803                 DRM_DEBUG("invalid crtc %d\n", crtc);
2804                 return;
2805         }
2806
2807         switch (state) {
2808         case AMDGPU_IRQ_STATE_DISABLE:
2809                 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2810                 interrupt_mask &= ~VBLANK_INT_MASK;
2811                 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2812                 break;
2813         case AMDGPU_IRQ_STATE_ENABLE:
2814                 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2815                 interrupt_mask |= VBLANK_INT_MASK;
2816                 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2817                 break;
2818         default:
2819                 break;
2820         }
2821 }
2822
2823 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2824                                                     int crtc,
2825                                                     enum amdgpu_interrupt_state state)
2826 {
2827
2828 }
2829
2830 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2831                                             struct amdgpu_irq_src *src,
2832                                             unsigned type,
2833                                             enum amdgpu_interrupt_state state)
2834 {
2835         u32 dc_hpd_int_cntl;
2836
2837         if (type >= adev->mode_info.num_hpd) {
2838                 DRM_DEBUG("invalid hdp %d\n", type);
2839                 return 0;
2840         }
2841
2842         switch (state) {
2843         case AMDGPU_IRQ_STATE_DISABLE:
2844                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2845                 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2846                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2847                 break;
2848         case AMDGPU_IRQ_STATE_ENABLE:
2849                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2850                 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2851                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2852                 break;
2853         default:
2854                 break;
2855         }
2856
2857         return 0;
2858 }
2859
2860 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2861                                              struct amdgpu_irq_src *src,
2862                                              unsigned type,
2863                                              enum amdgpu_interrupt_state state)
2864 {
2865         switch (type) {
2866         case AMDGPU_CRTC_IRQ_VBLANK1:
2867                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2868                 break;
2869         case AMDGPU_CRTC_IRQ_VBLANK2:
2870                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2871                 break;
2872         case AMDGPU_CRTC_IRQ_VBLANK3:
2873                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2874                 break;
2875         case AMDGPU_CRTC_IRQ_VBLANK4:
2876                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2877                 break;
2878         case AMDGPU_CRTC_IRQ_VBLANK5:
2879                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2880                 break;
2881         case AMDGPU_CRTC_IRQ_VBLANK6:
2882                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2883                 break;
2884         case AMDGPU_CRTC_IRQ_VLINE1:
2885                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2886                 break;
2887         case AMDGPU_CRTC_IRQ_VLINE2:
2888                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2889                 break;
2890         case AMDGPU_CRTC_IRQ_VLINE3:
2891                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2892                 break;
2893         case AMDGPU_CRTC_IRQ_VLINE4:
2894                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2895                 break;
2896         case AMDGPU_CRTC_IRQ_VLINE5:
2897                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2898                 break;
2899         case AMDGPU_CRTC_IRQ_VLINE6:
2900                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2901                 break;
2902         default:
2903                 break;
2904         }
2905         return 0;
2906 }
2907
2908 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2909                              struct amdgpu_irq_src *source,
2910                              struct amdgpu_iv_entry *entry)
2911 {
2912         unsigned crtc = entry->src_id - 1;
2913         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2914         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
2915                                                                     crtc);
2916
2917         switch (entry->src_data[0]) {
2918         case 0: /* vblank */
2919                 if (disp_int & interrupt_status_offsets[crtc].vblank)
2920                         WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2921                 else
2922                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2923
2924                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2925                         drm_handle_vblank(adev->ddev, crtc);
2926                 }
2927                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2928                 break;
2929         case 1: /* vline */
2930                 if (disp_int & interrupt_status_offsets[crtc].vline)
2931                         WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2932                 else
2933                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2934
2935                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2936                 break;
2937         default:
2938                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
2939                 break;
2940         }
2941
2942         return 0;
2943 }
2944
2945 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2946                                                  struct amdgpu_irq_src *src,
2947                                                  unsigned type,
2948                                                  enum amdgpu_interrupt_state state)
2949 {
2950         u32 reg;
2951
2952         if (type >= adev->mode_info.num_crtc) {
2953                 DRM_ERROR("invalid pageflip crtc %d\n", type);
2954                 return -EINVAL;
2955         }
2956
2957         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
2958         if (state == AMDGPU_IRQ_STATE_DISABLE)
2959                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2960                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2961         else
2962                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2963                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2964
2965         return 0;
2966 }
2967
2968 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2969                                  struct amdgpu_irq_src *source,
2970                                  struct amdgpu_iv_entry *entry)
2971 {
2972                 unsigned long flags;
2973         unsigned crtc_id;
2974         struct amdgpu_crtc *amdgpu_crtc;
2975         struct amdgpu_flip_work *works;
2976
2977         crtc_id = (entry->src_id - 8) >> 1;
2978         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
2979
2980         if (crtc_id >= adev->mode_info.num_crtc) {
2981                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
2982                 return -EINVAL;
2983         }
2984
2985         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
2986             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2987                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
2988                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2989
2990         /* IRQ could occur when in initial stage */
2991         if (amdgpu_crtc == NULL)
2992                 return 0;
2993
2994         spin_lock_irqsave(&adev->ddev->event_lock, flags);
2995         works = amdgpu_crtc->pflip_works;
2996         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
2997                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
2998                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
2999                                                 amdgpu_crtc->pflip_status,
3000                                                 AMDGPU_FLIP_SUBMITTED);
3001                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3002                 return 0;
3003         }
3004
3005         /* page flip completed. clean up */
3006         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3007         amdgpu_crtc->pflip_works = NULL;
3008
3009         /* wakeup usersapce */
3010         if (works->event)
3011                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3012
3013         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3014
3015         drm_crtc_vblank_put(&amdgpu_crtc->base);
3016         schedule_work(&works->unpin_work);
3017
3018         return 0;
3019 }
3020
3021 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
3022                             struct amdgpu_irq_src *source,
3023                             struct amdgpu_iv_entry *entry)
3024 {
3025         uint32_t disp_int, mask, tmp;
3026         unsigned hpd;
3027
3028         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3029                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3030                 return 0;
3031         }
3032
3033         hpd = entry->src_data[0];
3034         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3035         mask = interrupt_status_offsets[hpd].hpd;
3036
3037         if (disp_int & mask) {
3038                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3039                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3040                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3041                 schedule_work(&adev->hotplug_work);
3042                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3043         }
3044
3045         return 0;
3046
3047 }
3048
3049 static int dce_v6_0_set_clockgating_state(void *handle,
3050                                           enum amd_clockgating_state state)
3051 {
3052         return 0;
3053 }
3054
3055 static int dce_v6_0_set_powergating_state(void *handle,
3056                                           enum amd_powergating_state state)
3057 {
3058         return 0;
3059 }
3060
3061 static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
3062         .name = "dce_v6_0",
3063         .early_init = dce_v6_0_early_init,
3064         .late_init = NULL,
3065         .sw_init = dce_v6_0_sw_init,
3066         .sw_fini = dce_v6_0_sw_fini,
3067         .hw_init = dce_v6_0_hw_init,
3068         .hw_fini = dce_v6_0_hw_fini,
3069         .suspend = dce_v6_0_suspend,
3070         .resume = dce_v6_0_resume,
3071         .is_idle = dce_v6_0_is_idle,
3072         .wait_for_idle = dce_v6_0_wait_for_idle,
3073         .soft_reset = dce_v6_0_soft_reset,
3074         .set_clockgating_state = dce_v6_0_set_clockgating_state,
3075         .set_powergating_state = dce_v6_0_set_powergating_state,
3076 };
3077
3078 static void
3079 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
3080                           struct drm_display_mode *mode,
3081                           struct drm_display_mode *adjusted_mode)
3082 {
3083
3084         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3085         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3086
3087         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3088
3089         /* need to call this here rather than in prepare() since we need some crtc info */
3090         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3091
3092         /* set scaler clears this on some chips */
3093         dce_v6_0_set_interleave(encoder->crtc, mode);
3094
3095         if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) {
3096                 dce_v6_0_afmt_enable(encoder, true);
3097                 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
3098         }
3099 }
3100
3101 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
3102 {
3103
3104         struct amdgpu_device *adev = encoder->dev->dev_private;
3105         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3106         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3107
3108         if ((amdgpu_encoder->active_device &
3109              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3110             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3111              ENCODER_OBJECT_ID_NONE)) {
3112                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3113                 if (dig) {
3114                         dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
3115                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3116                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3117                 }
3118         }
3119
3120         amdgpu_atombios_scratch_regs_lock(adev, true);
3121
3122         if (connector) {
3123                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3124
3125                 /* select the clock/data port if it uses a router */
3126                 if (amdgpu_connector->router.cd_valid)
3127                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3128
3129                 /* turn eDP panel on for mode set */
3130                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3131                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3132                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3133         }
3134
3135         /* this is needed for the pll/ss setup to work correctly in some cases */
3136         amdgpu_atombios_encoder_set_crtc_source(encoder);
3137         /* set up the FMT blocks */
3138         dce_v6_0_program_fmt(encoder);
3139 }
3140
3141 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
3142 {
3143
3144         struct drm_device *dev = encoder->dev;
3145         struct amdgpu_device *adev = dev->dev_private;
3146
3147         /* need to call this here as we need the crtc set up */
3148         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3149         amdgpu_atombios_scratch_regs_lock(adev, false);
3150 }
3151
3152 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
3153 {
3154
3155         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3156         struct amdgpu_encoder_atom_dig *dig;
3157         int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3158
3159         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3160
3161         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3162                 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em))
3163                         dce_v6_0_afmt_enable(encoder, false);
3164                 dig = amdgpu_encoder->enc_priv;
3165                 dig->dig_encoder = -1;
3166         }
3167         amdgpu_encoder->active_device = 0;
3168 }
3169
3170 /* these are handled by the primary encoders */
3171 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
3172 {
3173
3174 }
3175
3176 static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
3177 {
3178
3179 }
3180
3181 static void
3182 dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
3183                       struct drm_display_mode *mode,
3184                       struct drm_display_mode *adjusted_mode)
3185 {
3186
3187 }
3188
3189 static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
3190 {
3191
3192 }
3193
3194 static void
3195 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
3196 {
3197
3198 }
3199
3200 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
3201                                     const struct drm_display_mode *mode,
3202                                     struct drm_display_mode *adjusted_mode)
3203 {
3204         return true;
3205 }
3206
3207 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
3208         .dpms = dce_v6_0_ext_dpms,
3209         .mode_fixup = dce_v6_0_ext_mode_fixup,
3210         .prepare = dce_v6_0_ext_prepare,
3211         .mode_set = dce_v6_0_ext_mode_set,
3212         .commit = dce_v6_0_ext_commit,
3213         .disable = dce_v6_0_ext_disable,
3214         /* no detect for TMDS/LVDS yet */
3215 };
3216
3217 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
3218         .dpms = amdgpu_atombios_encoder_dpms,
3219         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3220         .prepare = dce_v6_0_encoder_prepare,
3221         .mode_set = dce_v6_0_encoder_mode_set,
3222         .commit = dce_v6_0_encoder_commit,
3223         .disable = dce_v6_0_encoder_disable,
3224         .detect = amdgpu_atombios_encoder_dig_detect,
3225 };
3226
3227 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
3228         .dpms = amdgpu_atombios_encoder_dpms,
3229         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3230         .prepare = dce_v6_0_encoder_prepare,
3231         .mode_set = dce_v6_0_encoder_mode_set,
3232         .commit = dce_v6_0_encoder_commit,
3233         .detect = amdgpu_atombios_encoder_dac_detect,
3234 };
3235
3236 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
3237 {
3238         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3239         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3240                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3241         kfree(amdgpu_encoder->enc_priv);
3242         drm_encoder_cleanup(encoder);
3243         kfree(amdgpu_encoder);
3244 }
3245
3246 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
3247         .destroy = dce_v6_0_encoder_destroy,
3248 };
3249
3250 static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
3251                                  uint32_t encoder_enum,
3252                                  uint32_t supported_device,
3253                                  u16 caps)
3254 {
3255         struct drm_device *dev = adev->ddev;
3256         struct drm_encoder *encoder;
3257         struct amdgpu_encoder *amdgpu_encoder;
3258
3259         /* see if we already added it */
3260         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3261                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3262                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3263                         amdgpu_encoder->devices |= supported_device;
3264                         return;
3265                 }
3266
3267         }
3268
3269         /* add a new one */
3270         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3271         if (!amdgpu_encoder)
3272                 return;
3273
3274         encoder = &amdgpu_encoder->base;
3275         switch (adev->mode_info.num_crtc) {
3276         case 1:
3277                 encoder->possible_crtcs = 0x1;
3278                 break;
3279         case 2:
3280         default:
3281                 encoder->possible_crtcs = 0x3;
3282                 break;
3283         case 4:
3284                 encoder->possible_crtcs = 0xf;
3285                 break;
3286         case 6:
3287                 encoder->possible_crtcs = 0x3f;
3288                 break;
3289         }
3290
3291         amdgpu_encoder->enc_priv = NULL;
3292         amdgpu_encoder->encoder_enum = encoder_enum;
3293         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3294         amdgpu_encoder->devices = supported_device;
3295         amdgpu_encoder->rmx_type = RMX_OFF;
3296         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3297         amdgpu_encoder->is_ext_encoder = false;
3298         amdgpu_encoder->caps = caps;
3299
3300         switch (amdgpu_encoder->encoder_id) {
3301         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3302         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3303                 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3304                                  DRM_MODE_ENCODER_DAC, NULL);
3305                 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
3306                 break;
3307         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3308         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3309         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3310         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3311         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3312                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3313                         amdgpu_encoder->rmx_type = RMX_FULL;
3314                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3315                                          DRM_MODE_ENCODER_LVDS, NULL);
3316                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3317                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3318                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3319                                          DRM_MODE_ENCODER_DAC, NULL);
3320                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3321                 } else {
3322                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3323                                          DRM_MODE_ENCODER_TMDS, NULL);
3324                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3325                 }
3326                 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3327                 break;
3328         case ENCODER_OBJECT_ID_SI170B:
3329         case ENCODER_OBJECT_ID_CH7303:
3330         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3331         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3332         case ENCODER_OBJECT_ID_TITFP513:
3333         case ENCODER_OBJECT_ID_VT1623:
3334         case ENCODER_OBJECT_ID_HDMI_SI1930:
3335         case ENCODER_OBJECT_ID_TRAVIS:
3336         case ENCODER_OBJECT_ID_NUTMEG:
3337                 /* these are handled by the primary encoders */
3338                 amdgpu_encoder->is_ext_encoder = true;
3339                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3340                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3341                                          DRM_MODE_ENCODER_LVDS, NULL);
3342                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3343                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3344                                          DRM_MODE_ENCODER_DAC, NULL);
3345                 else
3346                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3347                                          DRM_MODE_ENCODER_TMDS, NULL);
3348                 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3349                 break;
3350         }
3351 }
3352
3353 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3354         .bandwidth_update = &dce_v6_0_bandwidth_update,
3355         .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3356         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3357         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3358         .hpd_sense = &dce_v6_0_hpd_sense,
3359         .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3360         .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3361         .page_flip = &dce_v6_0_page_flip,
3362         .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3363         .add_encoder = &dce_v6_0_encoder_add,
3364         .add_connector = &amdgpu_connector_add,
3365 };
3366
3367 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3368 {
3369         if (adev->mode_info.funcs == NULL)
3370                 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3371 }
3372
3373 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3374         .set = dce_v6_0_set_crtc_interrupt_state,
3375         .process = dce_v6_0_crtc_irq,
3376 };
3377
3378 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3379         .set = dce_v6_0_set_pageflip_interrupt_state,
3380         .process = dce_v6_0_pageflip_irq,
3381 };
3382
3383 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3384         .set = dce_v6_0_set_hpd_interrupt_state,
3385         .process = dce_v6_0_hpd_irq,
3386 };
3387
3388 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3389 {
3390         if (adev->mode_info.num_crtc > 0)
3391                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3392         else
3393                 adev->crtc_irq.num_types = 0;
3394         adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3395
3396         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3397         adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3398
3399         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3400         adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3401 }
3402
3403 const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3404 {
3405         .type = AMD_IP_BLOCK_TYPE_DCE,
3406         .major = 6,
3407         .minor = 0,
3408         .rev = 0,
3409         .funcs = &dce_v6_0_ip_funcs,
3410 };
3411
3412 const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3413 {
3414         .type = AMD_IP_BLOCK_TYPE_DCE,
3415         .major = 6,
3416         .minor = 4,
3417         .rev = 0,
3418         .funcs = &dce_v6_0_ip_funcs,
3419 };