drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "amdgpu_sdma.h"
  51 #include "bif/bif_4_1_d.h"
  52
  53 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  54
  55 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  56                              struct ttm_mem_reg *mem, unsigned num_pages,
  57                              uint64_t offset, unsigned window,
  58                              struct amdgpu_ring *ring,
  59                              uint64_t *addr);
  60
  61 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  62 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  63
  64 /*
  65  * Global memory.
  66  */
  67
  68 /**
  69  * amdgpu_ttm_mem_global_init - Initialize and acquire reference to
  70  * memory object
  71  *
  72  * @ref: Object for initialization.
  73  *
  74  * This is called by drm_global_item_ref() when an object is being
  75  * initialized.
  76  */
  77 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  78 {
  79         return ttm_mem_global_init(ref->object);
  80 }
  81
  82 /**
  83  * amdgpu_ttm_mem_global_release - Drop reference to a memory object
  84  *
  85  * @ref: Object being removed
  86  *
  87  * This is called by drm_global_item_unref() when an object is being
  88  * released.
  89  */
  90 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  91 {
  92         ttm_mem_global_release(ref->object);
  93 }
  94
  95 /**
  96  * amdgpu_ttm_global_init - Initialize global TTM memory reference structures.
  97  *
  98  * @adev: AMDGPU device for which the global structures need to be registered.
  99  *
 100  * This is called as part of the AMDGPU ttm init from amdgpu_ttm_init()
 101  * during bring up.
 102  */
 103 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
 104 {
 105         struct drm_global_reference *global_ref;
 106         int r;
 107
 108         /* ensure reference is false in case init fails */
 109         adev->mman.mem_global_referenced = false;
 110
 111         global_ref = &adev->mman.mem_global_ref;
 112         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
 113         global_ref->size = sizeof(struct ttm_mem_global);
 114         global_ref->init = &amdgpu_ttm_mem_global_init;
 115         global_ref->release = &amdgpu_ttm_mem_global_release;
 116         r = drm_global_item_ref(global_ref);
 117         if (r) {
 118                 DRM_ERROR("Failed setting up TTM memory accounting "
 119                           "subsystem.\n");
 120                 goto error_mem;
 121         }
 122
 123         adev->mman.bo_global_ref.mem_glob =
 124                 adev->mman.mem_global_ref.object;
 125         global_ref = &adev->mman.bo_global_ref.ref;
 126         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 127         global_ref->size = sizeof(struct ttm_bo_global);
 128         global_ref->init = &ttm_bo_global_init;
 129         global_ref->release = &ttm_bo_global_release;
 130         r = drm_global_item_ref(global_ref);
 131         if (r) {
 132                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 133                 goto error_bo;
 134         }
 135
 136         mutex_init(&adev->mman.gtt_window_lock);
 137
 138         adev->mman.mem_global_referenced = true;
 139
 140         return 0;
 141
 142 error_bo:
 143         drm_global_item_unref(&adev->mman.mem_global_ref);
 144 error_mem:
 145         return r;
 146 }
 147
 148 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 149 {
 150         if (adev->mman.mem_global_referenced) {
 151                 mutex_destroy(&adev->mman.gtt_window_lock);
 152                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 153                 drm_global_item_unref(&adev->mman.mem_global_ref);
 154                 adev->mman.mem_global_referenced = false;
 155         }
 156 }
 157
 158 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 159 {
 160         return 0;
 161 }
 162
 163 /**
 164  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
 165  * memory request.
 166  *
 167  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
 168  * @type: The type of memory requested
 169  * @man: The memory type manager for each domain
 170  *
 171  * This is called by ttm_bo_init_mm() when a buffer object is being
 172  * initialized.
 173  */
 174 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 175                                 struct ttm_mem_type_manager *man)
 176 {
 177         struct amdgpu_device *adev;
 178
 179         adev = amdgpu_ttm_adev(bdev);
 180
 181         switch (type) {
 182         case TTM_PL_SYSTEM:
 183                 /* System memory */
 184                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 185                 man->available_caching = TTM_PL_MASK_CACHING;
 186                 man->default_caching = TTM_PL_FLAG_CACHED;
 187                 break;
 188         case TTM_PL_TT:
 189                 /* GTT memory  */
 190                 man->func = &amdgpu_gtt_mgr_func;
 191                 man->gpu_offset = adev->gmc.gart_start;
 192                 man->available_caching = TTM_PL_MASK_CACHING;
 193                 man->default_caching = TTM_PL_FLAG_CACHED;
 194                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 195                 break;
 196         case TTM_PL_VRAM:
 197                 /* "On-card" video ram */
 198                 man->func = &amdgpu_vram_mgr_func;
 199                 man->gpu_offset = adev->gmc.vram_start;
 200                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 201                              TTM_MEMTYPE_FLAG_MAPPABLE;
 202                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 203                 man->default_caching = TTM_PL_FLAG_WC;
 204                 break;
 205         case AMDGPU_PL_GDS:
 206         case AMDGPU_PL_GWS:
 207         case AMDGPU_PL_OA:
 208                 /* On-chip GDS memory*/
 209                 man->func = &ttm_bo_manager_func;
 210                 man->gpu_offset = 0;
 211                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 212                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 213                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 214                 break;
 215         default:
 216                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 217                 return -EINVAL;
 218         }
 219         return 0;
 220 }
 221
 222 /**
 223  * amdgpu_evict_flags - Compute placement flags
 224  *
 225  * @bo: The buffer object to evict
 226  * @placement: Possible destination(s) for evicted BO
 227  *
 228  * Fill in placement data when ttm_bo_evict() is called
 229  */
 230 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 231                                 struct ttm_placement *placement)
 232 {
 233         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 234         struct amdgpu_bo *abo;
 235         static const struct ttm_place placements = {
 236                 .fpfn = 0,
 237                 .lpfn = 0,
 238                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 239         };
 240
 241         /* Don't handle scatter gather BOs */
 242         if (bo->type == ttm_bo_type_sg) {
 243                 placement->num_placement = 0;
 244                 placement->num_busy_placement = 0;
 245                 return;
 246         }
 247
 248         /* Object isn't an AMDGPU object so ignore */
 249         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 250                 placement->placement = &placements;
 251                 placement->busy_placement = &placements;
 252                 placement->num_placement = 1;
 253                 placement->num_busy_placement = 1;
 254                 return;
 255         }
 256
 257         abo = ttm_to_amdgpu_bo(bo);
 258         switch (bo->mem.mem_type) {
 259         case TTM_PL_VRAM:
 260                 if (!adev->mman.buffer_funcs_enabled) {
 261                         /* Move to system memory */
 262                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 263                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 264                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 265                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 266
 267                         /* Try evicting to the CPU inaccessible part of VRAM
 268                          * first, but only set GTT as busy placement, so this
 269                          * BO will be evicted to GTT rather than causing other
 270                          * BOs to be evicted from VRAM
 271                          */
 272                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 273                                                          AMDGPU_GEM_DOMAIN_GTT);
 274                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 275                         abo->placements[0].lpfn = 0;
 276                         abo->placement.busy_placement = &abo->placements[1];
 277                         abo->placement.num_busy_placement = 1;
 278                 } else {
 279                         /* Move to GTT memory */
 280                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 281                 }
 282                 break;
 283         case TTM_PL_TT:
 284         default:
 285                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 286         }
 287         *placement = abo->placement;
 288 }
 289
 290 /**
 291  * amdgpu_verify_access - Verify access for a mmap call
 292  *
 293  * @bo: The buffer object to map
 294  * @filp: The file pointer from the process performing the mmap
 295  *
 296  * This is called by ttm_bo_mmap() to verify whether a process
 297  * has the right to mmap a BO to their process space.
 298  */
 299 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 300 {
 301         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 302
 303         /*
 304          * Don't verify access for KFD BOs. They don't have a GEM
 305          * object associated with them.
 306          */
 307         if (abo->kfd_bo)
 308                 return 0;
 309
 310         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 311                 return -EPERM;
 312         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 313                                           filp->private_data);
 314 }
 315
 316 /**
 317  * amdgpu_move_null - Register memory for a buffer object
 318  *
 319  * @bo: The bo to assign the memory to
 320  * @new_mem: The memory to be assigned.
 321  *
 322  * Assign the memory from new_mem to the memory of the buffer object bo.
 323  */
 324 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 325                              struct ttm_mem_reg *new_mem)
 326 {
 327         struct ttm_mem_reg *old_mem = &bo->mem;
 328
 329         BUG_ON(old_mem->mm_node != NULL);
 330         *old_mem = *new_mem;
 331         new_mem->mm_node = NULL;
 332 }
 333
 334 /**
 335  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 336  *
 337  * @bo: The bo to assign the memory to.
 338  * @mm_node: Memory manager node for drm allocator.
 339  * @mem: The region where the bo resides.
 340  *
 341  */
 342 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 343                                     struct drm_mm_node *mm_node,
 344                                     struct ttm_mem_reg *mem)
 345 {
 346         uint64_t addr = 0;
 347
 348         if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
 349                 addr = mm_node->start << PAGE_SHIFT;
 350                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 351         }
 352         return addr;
 353 }
 354
 355 /**
 356  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 357  * @offset. It also modifies the offset to be within the drm_mm_node returned
 358  *
 359  * @mem: The region where the bo resides.
 360  * @offset: The offset that drm_mm_node is used for finding.
 361  *
 362  */
 363 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 364                                                unsigned long *offset)
 365 {
 366         struct drm_mm_node *mm_node = mem->mm_node;
 367
 368         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 369                 *offset -= (mm_node->size << PAGE_SHIFT);
 370                 ++mm_node;
 371         }
 372         return mm_node;
 373 }
 374
 375 /**
 376  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 377  *
 378  * The function copies @size bytes from {src->mem + src->offset} to
 379  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 380  * move and different for a BO to BO copy.
 381  *
 382  * @f: Returns the last fence if multiple jobs are submitted.
 383  */
 384 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 385                                struct amdgpu_copy_mem *src,
 386                                struct amdgpu_copy_mem *dst,
 387                                uint64_t size,
 388                                struct reservation_object *resv,
 389                                struct dma_fence **f)
 390 {
 391         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 392         struct drm_mm_node *src_mm, *dst_mm;
 393         uint64_t src_node_start, dst_node_start, src_node_size,
 394                  dst_node_size, src_page_offset, dst_page_offset;
 395         struct dma_fence *fence = NULL;
 396         int r = 0;
 397         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 398                                         AMDGPU_GPU_PAGE_SIZE);
 399
 400         if (!adev->mman.buffer_funcs_enabled) {
 401                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 402                 return -EINVAL;
 403         }
 404
 405         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 406         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 407                                              src->offset;
 408         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 409         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 410
 411         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 412         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 413                                              dst->offset;
 414         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 415         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 416
 417         mutex_lock(&adev->mman.gtt_window_lock);
 418
 419         while (size) {
 420                 unsigned long cur_size;
 421                 uint64_t from = src_node_start, to = dst_node_start;
 422                 struct dma_fence *next;
 423
 424                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 425                  * begins at an offset, then adjust the size accordingly
 426                  */
 427                 cur_size = min3(min(src_node_size, dst_node_size), size,
 428                                 GTT_MAX_BYTES);
 429                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 430                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 431                         cur_size -= max(src_page_offset, dst_page_offset);
 432
 433                 /* Map only what needs to be accessed. Map src to window 0 and
 434                  * dst to window 1
 435                  */
 436                 if (src->mem->mem_type == TTM_PL_TT &&
 437                     !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
 438                         r = amdgpu_map_buffer(src->bo, src->mem,
 439                                         PFN_UP(cur_size + src_page_offset),
 440                                         src_node_start, 0, ring,
 441                                         &from);
 442                         if (r)
 443                                 goto error;
 444                         /* Adjust the offset because amdgpu_map_buffer returns
 445                          * start of mapped page
 446                          */
 447                         from += src_page_offset;
 448                 }
 449
 450                 if (dst->mem->mem_type == TTM_PL_TT &&
 451                     !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
 452                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 453                                         PFN_UP(cur_size + dst_page_offset),
 454                                         dst_node_start, 1, ring,
 455                                         &to);
 456                         if (r)
 457                                 goto error;
 458                         to += dst_page_offset;
 459                 }
 460
 461                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 462                                        resv, &next, false, true);
 463                 if (r)
 464                         goto error;
 465
 466                 dma_fence_put(fence);
 467                 fence = next;
 468
 469                 size -= cur_size;
 470                 if (!size)
 471                         break;
 472
 473                 src_node_size -= cur_size;
 474                 if (!src_node_size) {
 475                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 476                                                              src->mem);
 477                         src_node_size = (src_mm->size << PAGE_SHIFT);
 478                 } else {
 479                         src_node_start += cur_size;
 480                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 481                 }
 482                 dst_node_size -= cur_size;
 483                 if (!dst_node_size) {
 484                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 485                                                              dst->mem);
 486                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 487                 } else {
 488                         dst_node_start += cur_size;
 489                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 490                 }
 491         }
 492 error:
 493         mutex_unlock(&adev->mman.gtt_window_lock);
 494         if (f)
 495                 *f = dma_fence_get(fence);
 496         dma_fence_put(fence);
 497         return r;
 498 }
 499
 500 /**
 501  * amdgpu_move_blit - Copy an entire buffer to another buffer
 502  *
 503  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 504  * help move buffers to and from VRAM.
 505  */
 506 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 507                             bool evict, bool no_wait_gpu,
 508                             struct ttm_mem_reg *new_mem,
 509                             struct ttm_mem_reg *old_mem)
 510 {
 511         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 512         struct amdgpu_copy_mem src, dst;
 513         struct dma_fence *fence = NULL;
 514         int r;
 515
 516         src.bo = bo;
 517         dst.bo = bo;
 518         src.mem = old_mem;
 519         dst.mem = new_mem;
 520         src.offset = 0;
 521         dst.offset = 0;
 522
 523         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 524                                        new_mem->num_pages << PAGE_SHIFT,
 525                                        bo->resv, &fence);
 526         if (r)
 527                 goto error;
 528
 529         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 530         dma_fence_put(fence);
 531         return r;
 532
 533 error:
 534         if (fence)
 535                 dma_fence_wait(fence, false);
 536         dma_fence_put(fence);
 537         return r;
 538 }
 539
 540 /**
 541  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 542  *
 543  * Called by amdgpu_bo_move().
 544  */
 545 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 546                                 struct ttm_operation_ctx *ctx,
 547                                 struct ttm_mem_reg *new_mem)
 548 {
 549         struct amdgpu_device *adev;
 550         struct ttm_mem_reg *old_mem = &bo->mem;
 551         struct ttm_mem_reg tmp_mem;
 552         struct ttm_place placements;
 553         struct ttm_placement placement;
 554         int r;
 555
 556         adev = amdgpu_ttm_adev(bo->bdev);
 557
 558         /* create space/pages for new_mem in GTT space */
 559         tmp_mem = *new_mem;
 560         tmp_mem.mm_node = NULL;
 561         placement.num_placement = 1;
 562         placement.placement = &placements;
 563         placement.num_busy_placement = 1;
 564         placement.busy_placement = &placements;
 565         placements.fpfn = 0;
 566         placements.lpfn = 0;
 567         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 568         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 569         if (unlikely(r)) {
 570                 return r;
 571         }
 572
 573         /* set caching flags */
 574         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 575         if (unlikely(r)) {
 576                 goto out_cleanup;
 577         }
 578
 579         /* Bind the memory to the GTT space */
 580         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 581         if (unlikely(r)) {
 582                 goto out_cleanup;
 583         }
 584
 585         /* blit VRAM to GTT */
 586         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 587         if (unlikely(r)) {
 588                 goto out_cleanup;
 589         }
 590
 591         /* move BO (in tmp_mem) to new_mem */
 592         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 593 out_cleanup:
 594         ttm_bo_mem_put(bo, &tmp_mem);
 595         return r;
 596 }
 597
 598 /**
 599  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 600  *
 601  * Called by amdgpu_bo_move().
 602  */
 603 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 604                                 struct ttm_operation_ctx *ctx,
 605                                 struct ttm_mem_reg *new_mem)
 606 {
 607         struct amdgpu_device *adev;
 608         struct ttm_mem_reg *old_mem = &bo->mem;
 609         struct ttm_mem_reg tmp_mem;
 610         struct ttm_placement placement;
 611         struct ttm_place placements;
 612         int r;
 613
 614         adev = amdgpu_ttm_adev(bo->bdev);
 615
 616         /* make space in GTT for old_mem buffer */
 617         tmp_mem = *new_mem;
 618         tmp_mem.mm_node = NULL;
 619         placement.num_placement = 1;
 620         placement.placement = &placements;
 621         placement.num_busy_placement = 1;
 622         placement.busy_placement = &placements;
 623         placements.fpfn = 0;
 624         placements.lpfn = 0;
 625         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 626         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 627         if (unlikely(r)) {
 628                 return r;
 629         }
 630
 631         /* move/bind old memory to GTT space */
 632         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 633         if (unlikely(r)) {
 634                 goto out_cleanup;
 635         }
 636
 637         /* copy to VRAM */
 638         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 639         if (unlikely(r)) {
 640                 goto out_cleanup;
 641         }
 642 out_cleanup:
 643         ttm_bo_mem_put(bo, &tmp_mem);
 644         return r;
 645 }
 646
 647 /**
 648  * amdgpu_bo_move - Move a buffer object to a new memory location
 649  *
 650  * Called by ttm_bo_handle_move_mem()
 651  */
 652 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 653                           struct ttm_operation_ctx *ctx,
 654                           struct ttm_mem_reg *new_mem)
 655 {
 656         struct amdgpu_device *adev;
 657         struct amdgpu_bo *abo;
 658         struct ttm_mem_reg *old_mem = &bo->mem;
 659         int r;
 660
 661         /* Can't move a pinned BO */
 662         abo = ttm_to_amdgpu_bo(bo);
 663         if (WARN_ON_ONCE(abo->pin_count > 0))
 664                 return -EINVAL;
 665
 666         adev = amdgpu_ttm_adev(bo->bdev);
 667
 668         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 669                 amdgpu_move_null(bo, new_mem);
 670                 return 0;
 671         }
 672         if ((old_mem->mem_type == TTM_PL_TT &&
 673              new_mem->mem_type == TTM_PL_SYSTEM) ||
 674             (old_mem->mem_type == TTM_PL_SYSTEM &&
 675              new_mem->mem_type == TTM_PL_TT)) {
 676                 /* bind is enough */
 677                 amdgpu_move_null(bo, new_mem);
 678                 return 0;
 679         }
 680
 681         if (!adev->mman.buffer_funcs_enabled)
 682                 goto memcpy;
 683
 684         if (old_mem->mem_type == TTM_PL_VRAM &&
 685             new_mem->mem_type == TTM_PL_SYSTEM) {
 686                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 687         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 688                    new_mem->mem_type == TTM_PL_VRAM) {
 689                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 690         } else {
 691                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 692                                      new_mem, old_mem);
 693         }
 694
 695         if (r) {
 696 memcpy:
 697                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 698                 if (r) {
 699                         return r;
 700                 }
 701         }
 702
 703         if (bo->type == ttm_bo_type_device &&
 704             new_mem->mem_type == TTM_PL_VRAM &&
 705             old_mem->mem_type != TTM_PL_VRAM) {
 706                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 707                  * accesses the BO after it's moved.
 708                  */
 709                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 710         }
 711
 712         /* update statistics */
 713         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 714         return 0;
 715 }
 716
 717 /**
 718  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 719  *
 720  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 721  */
 722 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 723 {
 724         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 725         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 726         struct drm_mm_node *mm_node = mem->mm_node;
 727
 728         mem->bus.addr = NULL;
 729         mem->bus.offset = 0;
 730         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 731         mem->bus.base = 0;
 732         mem->bus.is_iomem = false;
 733         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 734                 return -EINVAL;
 735         switch (mem->mem_type) {
 736         case TTM_PL_SYSTEM:
 737                 /* system memory */
 738                 return 0;
 739         case TTM_PL_TT:
 740                 break;
 741         case TTM_PL_VRAM:
 742                 mem->bus.offset = mem->start << PAGE_SHIFT;
 743                 /* check if it's visible */
 744                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 745                         return -EINVAL;
 746                 /* Only physically contiguous buffers apply. In a contiguous
 747                  * buffer, size of the first mm_node would match the number of
 748                  * pages in ttm_mem_reg.
 749                  */
 750                 if (adev->mman.aper_base_kaddr &&
 751                     (mm_node->size == mem->num_pages))
 752                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 753                                         mem->bus.offset;
 754
 755                 mem->bus.base = adev->gmc.aper_base;
 756                 mem->bus.is_iomem = true;
 757                 break;
 758         default:
 759                 return -EINVAL;
 760         }
 761         return 0;
 762 }
 763
 764 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 765 {
 766 }
 767
 768 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 769                                            unsigned long page_offset)
 770 {
 771         struct drm_mm_node *mm;
 772         unsigned long offset = (page_offset << PAGE_SHIFT);
 773
 774         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 775         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 776                 (offset >> PAGE_SHIFT);
 777 }
 778
 779 /*
 780  * TTM backend functions.
 781  */
 782 struct amdgpu_ttm_gup_task_list {
 783         struct list_head        list;
 784         struct task_struct      *task;
 785 };
 786
 787 struct amdgpu_ttm_tt {
 788         struct ttm_dma_tt       ttm;
 789         u64                     offset;
 790         uint64_t                userptr;
 791         struct task_struct      *usertask;
 792         uint32_t                userflags;
 793         spinlock_t              guptasklock;
 794         struct list_head        guptasks;
 795         atomic_t                mmu_invalidations;
 796         uint32_t                last_set_pages;
 797 };
 798
 799 /**
 800  * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR
 801  * pointer to memory
 802  *
 803  * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos().
 804  * This provides a wrapper around the get_user_pages() call to provide
 805  * device accessible pages that back user memory.
 806  */
 807 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 808 {
 809         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 810         struct mm_struct *mm = gtt->usertask->mm;
 811         unsigned int flags = 0;
 812         unsigned pinned = 0;
 813         int r;
 814
 815         if (!mm) /* Happens during process shutdown */
 816                 return -ESRCH;
 817
 818         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 819                 flags |= FOLL_WRITE;
 820
 821         down_read(&mm->mmap_sem);
 822
 823         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 824                 /*
 825                  * check that we only use anonymous memory to prevent problems
 826                  * with writeback
 827                  */
 828                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 829                 struct vm_area_struct *vma;
 830
 831                 vma = find_vma(mm, gtt->userptr);
 832                 if (!vma || vma->vm_file || vma->vm_end < end) {
 833                         up_read(&mm->mmap_sem);
 834                         return -EPERM;
 835                 }
 836         }
 837
 838         /* loop enough times using contiguous pages of memory */
 839         do {
 840                 unsigned num_pages = ttm->num_pages - pinned;
 841                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 842                 struct page **p = pages + pinned;
 843                 struct amdgpu_ttm_gup_task_list guptask;
 844
 845                 guptask.task = current;
 846                 spin_lock(&gtt->guptasklock);
 847                 list_add(&guptask.list, &gtt->guptasks);
 848                 spin_unlock(&gtt->guptasklock);
 849
 850                 if (mm == current->mm)
 851                         r = get_user_pages(userptr, num_pages, flags, p, NULL);
 852                 else
 853                         r = get_user_pages_remote(gtt->usertask,
 854                                         mm, userptr, num_pages,
 855                                         flags, p, NULL, NULL);
 856
 857                 spin_lock(&gtt->guptasklock);
 858                 list_del(&guptask.list);
 859                 spin_unlock(&gtt->guptasklock);
 860
 861                 if (r < 0)
 862                         goto release_pages;
 863
 864                 pinned += r;
 865
 866         } while (pinned < ttm->num_pages);
 867
 868         up_read(&mm->mmap_sem);
 869         return 0;
 870
 871 release_pages:
 872         release_pages(pages, pinned);
 873         up_read(&mm->mmap_sem);
 874         return r;
 875 }
 876
 877 /**
 878  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 879  *
 880  * Called by amdgpu_cs_list_validate(). This creates the page list
 881  * that backs user memory and will ultimately be mapped into the device
 882  * address space.
 883  */
 884 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 885 {
 886         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 887         unsigned i;
 888
 889         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 890         for (i = 0; i < ttm->num_pages; ++i) {
 891                 if (ttm->pages[i])
 892                         put_page(ttm->pages[i]);
 893
 894                 ttm->pages[i] = pages ? pages[i] : NULL;
 895         }
 896 }
 897
 898 /**
 899  * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty
 900  *
 901  * Called while unpinning userptr pages
 902  */
 903 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 904 {
 905         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 906         unsigned i;
 907
 908         for (i = 0; i < ttm->num_pages; ++i) {
 909                 struct page *page = ttm->pages[i];
 910
 911                 if (!page)
 912                         continue;
 913
 914                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 915                         set_page_dirty(page);
 916
 917                 mark_page_accessed(page);
 918         }
 919 }
 920
 921 /**
 922  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 923  *
 924  * Called by amdgpu_ttm_backend_bind()
 925  **/
 926 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 927 {
 928         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 929         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 930         unsigned nents;
 931         int r;
 932
 933         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 934         enum dma_data_direction direction = write ?
 935                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 936
 937         /* Allocate an SG array and squash pages into it */
 938         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 939                                       ttm->num_pages << PAGE_SHIFT,
 940                                       GFP_KERNEL);
 941         if (r)
 942                 goto release_sg;
 943
 944         /* Map SG to device */
 945         r = -ENOMEM;
 946         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 947         if (nents != ttm->sg->nents)
 948                 goto release_sg;
 949
 950         /* convert SG to linear array of pages and dma addresses */
 951         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 952                                          gtt->ttm.dma_address, ttm->num_pages);
 953
 954         return 0;
 955
 956 release_sg:
 957         kfree(ttm->sg);
 958         return r;
 959 }
 960
 961 /**
 962  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 963  */
 964 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 965 {
 966         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 967         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 968
 969         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 970         enum dma_data_direction direction = write ?
 971                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 972
 973         /* double check that we don't free the table twice */
 974         if (!ttm->sg->sgl)
 975                 return;
 976
 977         /* unmap the pages mapped to the device */
 978         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 979
 980         /* mark the pages as dirty */
 981         amdgpu_ttm_tt_mark_user_pages(ttm);
 982
 983         sg_free_table(ttm->sg);
 984 }
 985
 986 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 987                                 struct ttm_buffer_object *tbo,
 988                                 uint64_t flags)
 989 {
 990         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 991         struct ttm_tt *ttm = tbo->ttm;
 992         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 993         int r;
 994
 995         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 996                 uint64_t page_idx = 1;
 997
 998                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 999                                 ttm->pages, gtt->ttm.dma_address, flags);
1000                 if (r)
1001                         goto gart_bind_fail;
1002
1003                 /* Patch mtype of the second part BO */
1004                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
1005                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
1006
1007                 r = amdgpu_gart_bind(adev,
1008                                 gtt->offset + (page_idx << PAGE_SHIFT),
1009                                 ttm->num_pages - page_idx,
1010                                 &ttm->pages[page_idx],
1011                                 &(gtt->ttm.dma_address[page_idx]), flags);
1012         } else {
1013                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1014                                      ttm->pages, gtt->ttm.dma_address, flags);
1015         }
1016
1017 gart_bind_fail:
1018         if (r)
1019                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1020                           ttm->num_pages, gtt->offset);
1021
1022         return r;
1023 }
1024
1025 /**
1026  * amdgpu_ttm_backend_bind - Bind GTT memory
1027  *
1028  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1029  * This handles binding GTT memory to the device address space.
1030  */
1031 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1032                                    struct ttm_mem_reg *bo_mem)
1033 {
1034         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1035         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1036         uint64_t flags;
1037         int r = 0;
1038
1039         if (gtt->userptr) {
1040                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1041                 if (r) {
1042                         DRM_ERROR("failed to pin userptr\n");
1043                         return r;
1044                 }
1045         }
1046         if (!ttm->num_pages) {
1047                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1048                      ttm->num_pages, bo_mem, ttm);
1049         }
1050
1051         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1052             bo_mem->mem_type == AMDGPU_PL_GWS ||
1053             bo_mem->mem_type == AMDGPU_PL_OA)
1054                 return -EINVAL;
1055
1056         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1057                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1058                 return 0;
1059         }
1060
1061         /* compute PTE flags relevant to this BO memory */
1062         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1063
1064         /* bind pages into GART page tables */
1065         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1066         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1067                 ttm->pages, gtt->ttm.dma_address, flags);
1068
1069         if (r)
1070                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1071                           ttm->num_pages, gtt->offset);
1072         return r;
1073 }
1074
1075 /**
1076  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1077  */
1078 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1079 {
1080         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1081         struct ttm_operation_ctx ctx = { false, false };
1082         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1083         struct ttm_mem_reg tmp;
1084         struct ttm_placement placement;
1085         struct ttm_place placements;
1086         uint64_t flags;
1087         int r;
1088
1089         if (bo->mem.mem_type != TTM_PL_TT ||
1090             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
1091                 return 0;
1092
1093         /* allocate GTT space */
1094         tmp = bo->mem;
1095         tmp.mm_node = NULL;
1096         placement.num_placement = 1;
1097         placement.placement = &placements;
1098         placement.num_busy_placement = 1;
1099         placement.busy_placement = &placements;
1100         placements.fpfn = 0;
1101         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1102         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1103                 TTM_PL_FLAG_TT;
1104
1105         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1106         if (unlikely(r))
1107                 return r;
1108
1109         /* compute PTE flags for this buffer object */
1110         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1111
1112         /* Bind pages */
1113         gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1114         r = amdgpu_ttm_gart_bind(adev, bo, flags);
1115         if (unlikely(r)) {
1116                 ttm_bo_mem_put(bo, &tmp);
1117                 return r;
1118         }
1119
1120         ttm_bo_mem_put(bo, &bo->mem);
1121         bo->mem = tmp;
1122         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1123                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1124
1125         return 0;
1126 }
1127
1128 /**
1129  * amdgpu_ttm_recover_gart - Rebind GTT pages
1130  *
1131  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1132  * rebind GTT pages during a GPU reset.
1133  */
1134 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1135 {
1136         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1137         uint64_t flags;
1138         int r;
1139
1140         if (!tbo->ttm)
1141                 return 0;
1142
1143         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1144         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1145
1146         return r;
1147 }
1148
1149 /**
1150  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1151  *
1152  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1153  * ttm_tt_destroy().
1154  */
1155 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1156 {
1157         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1158         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1159         int r;
1160
1161         /* if the pages have userptr pinning then clear that first */
1162         if (gtt->userptr)
1163                 amdgpu_ttm_tt_unpin_userptr(ttm);
1164
1165         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1166                 return 0;
1167
1168         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1169         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1170         if (r)
1171                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1172                           gtt->ttm.ttm.num_pages, gtt->offset);
1173         return r;
1174 }
1175
1176 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1177 {
1178         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1179
1180         if (gtt->usertask)
1181                 put_task_struct(gtt->usertask);
1182
1183         ttm_dma_tt_fini(&gtt->ttm);
1184         kfree(gtt);
1185 }
1186
1187 static struct ttm_backend_func amdgpu_backend_func = {
1188         .bind = &amdgpu_ttm_backend_bind,
1189         .unbind = &amdgpu_ttm_backend_unbind,
1190         .destroy = &amdgpu_ttm_backend_destroy,
1191 };
1192
1193 /**
1194  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1195  *
1196  * @bo: The buffer object to create a GTT ttm_tt object around
1197  *
1198  * Called by ttm_tt_create().
1199  */
1200 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1201                                            uint32_t page_flags)
1202 {
1203         struct amdgpu_device *adev;
1204         struct amdgpu_ttm_tt *gtt;
1205
1206         adev = amdgpu_ttm_adev(bo->bdev);
1207
1208         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1209         if (gtt == NULL) {
1210                 return NULL;
1211         }
1212         gtt->ttm.ttm.func = &amdgpu_backend_func;
1213
1214         /* allocate space for the uninitialized page entries */
1215         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1216                 kfree(gtt);
1217                 return NULL;
1218         }
1219         return &gtt->ttm.ttm;
1220 }
1221
1222 /**
1223  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1224  *
1225  * Map the pages of a ttm_tt object to an address space visible
1226  * to the underlying device.
1227  */
1228 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1229                         struct ttm_operation_ctx *ctx)
1230 {
1231         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1232         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1233         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1234
1235         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1236         if (gtt && gtt->userptr) {
1237                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1238                 if (!ttm->sg)
1239                         return -ENOMEM;
1240
1241                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1242                 ttm->state = tt_unbound;
1243                 return 0;
1244         }
1245
1246         if (slave && ttm->sg) {
1247                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1248                                                  gtt->ttm.dma_address,
1249                                                  ttm->num_pages);
1250                 ttm->state = tt_unbound;
1251                 return 0;
1252         }
1253
1254 #ifdef CONFIG_SWIOTLB
1255         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1256                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1257         }
1258 #endif
1259
1260         /* fall back to generic helper to populate the page array
1261          * and map them to the device */
1262         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1263 }
1264
1265 /**
1266  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1267  *
1268  * Unmaps pages of a ttm_tt object from the device address space and
1269  * unpopulates the page array backing it.
1270  */
1271 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1272 {
1273         struct amdgpu_device *adev;
1274         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1275         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1276
1277         if (gtt && gtt->userptr) {
1278                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1279                 kfree(ttm->sg);
1280                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1281                 return;
1282         }
1283
1284         if (slave)
1285                 return;
1286
1287         adev = amdgpu_ttm_adev(ttm->bdev);
1288
1289 #ifdef CONFIG_SWIOTLB
1290         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1291                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1292                 return;
1293         }
1294 #endif
1295
1296         /* fall back to generic helper to unmap and unpopulate array */
1297         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1298 }
1299
1300 /**
1301  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1302  * task
1303  *
1304  * @ttm: The ttm_tt object to bind this userptr object to
1305  * @addr:  The address in the current tasks VM space to use
1306  * @flags: Requirements of userptr object.
1307  *
1308  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1309  * to current task
1310  */
1311 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1312                               uint32_t flags)
1313 {
1314         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1315
1316         if (gtt == NULL)
1317                 return -EINVAL;
1318
1319         gtt->userptr = addr;
1320         gtt->userflags = flags;
1321
1322         if (gtt->usertask)
1323                 put_task_struct(gtt->usertask);
1324         gtt->usertask = current->group_leader;
1325         get_task_struct(gtt->usertask);
1326
1327         spin_lock_init(&gtt->guptasklock);
1328         INIT_LIST_HEAD(&gtt->guptasks);
1329         atomic_set(&gtt->mmu_invalidations, 0);
1330         gtt->last_set_pages = 0;
1331
1332         return 0;
1333 }
1334
1335 /**
1336  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1337  */
1338 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1339 {
1340         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1341
1342         if (gtt == NULL)
1343                 return NULL;
1344
1345         if (gtt->usertask == NULL)
1346                 return NULL;
1347
1348         return gtt->usertask->mm;
1349 }
1350
1351 /**
1352  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1353  * address range for the current task.
1354  *
1355  */
1356 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1357                                   unsigned long end)
1358 {
1359         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1360         struct amdgpu_ttm_gup_task_list *entry;
1361         unsigned long size;
1362
1363         if (gtt == NULL || !gtt->userptr)
1364                 return false;
1365
1366         /* Return false if no part of the ttm_tt object lies within
1367          * the range
1368          */
1369         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1370         if (gtt->userptr > end || gtt->userptr + size <= start)
1371                 return false;
1372
1373         /* Search the lists of tasks that hold this mapping and see
1374          * if current is one of them.  If it is return false.
1375          */
1376         spin_lock(&gtt->guptasklock);
1377         list_for_each_entry(entry, &gtt->guptasks, list) {
1378                 if (entry->task == current) {
1379                         spin_unlock(&gtt->guptasklock);
1380                         return false;
1381                 }
1382         }
1383         spin_unlock(&gtt->guptasklock);
1384
1385         atomic_inc(&gtt->mmu_invalidations);
1386
1387         return true;
1388 }
1389
1390 /**
1391  * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated?
1392  */
1393 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1394                                        int *last_invalidated)
1395 {
1396         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1397         int prev_invalidated = *last_invalidated;
1398
1399         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1400         return prev_invalidated != *last_invalidated;
1401 }
1402
1403 /**
1404  * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object
1405  * been invalidated since the last time they've been set?
1406  */
1407 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1408 {
1409         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1410
1411         if (gtt == NULL || !gtt->userptr)
1412                 return false;
1413
1414         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1415 }
1416
1417 /**
1418  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1419  */
1420 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1421 {
1422         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1423
1424         if (gtt == NULL)
1425                 return false;
1426
1427         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1428 }
1429
1430 /**
1431  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1432  *
1433  * @ttm: The ttm_tt object to compute the flags for
1434  * @mem: The memory registry backing this ttm_tt object
1435  */
1436 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1437                                  struct ttm_mem_reg *mem)
1438 {
1439         uint64_t flags = 0;
1440
1441         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1442                 flags |= AMDGPU_PTE_VALID;
1443
1444         if (mem && mem->mem_type == TTM_PL_TT) {
1445                 flags |= AMDGPU_PTE_SYSTEM;
1446
1447                 if (ttm->caching_state == tt_cached)
1448                         flags |= AMDGPU_PTE_SNOOPED;
1449         }
1450
1451         flags |= adev->gart.gart_pte_flags;
1452         flags |= AMDGPU_PTE_READABLE;
1453
1454         if (!amdgpu_ttm_tt_is_readonly(ttm))
1455                 flags |= AMDGPU_PTE_WRITEABLE;
1456
1457         return flags;
1458 }
1459
1460 /**
1461  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1462  * object.
1463  *
1464  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1465  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1466  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1467  * used to clean out a memory space.
1468  */
1469 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1470                                             const struct ttm_place *place)
1471 {
1472         unsigned long num_pages = bo->mem.num_pages;
1473         struct drm_mm_node *node = bo->mem.mm_node;
1474         struct reservation_object_list *flist;
1475         struct dma_fence *f;
1476         int i;
1477
1478         /* If bo is a KFD BO, check if the bo belongs to the current process.
1479          * If true, then return false as any KFD process needs all its BOs to
1480          * be resident to run successfully
1481          */
1482         flist = reservation_object_get_list(bo->resv);
1483         if (flist) {
1484                 for (i = 0; i < flist->shared_count; ++i) {
1485                         f = rcu_dereference_protected(flist->shared[i],
1486                                 reservation_object_held(bo->resv));
1487                         if (amdkfd_fence_check_mm(f, current->mm))
1488                                 return false;
1489                 }
1490         }
1491
1492         switch (bo->mem.mem_type) {
1493         case TTM_PL_TT:
1494                 return true;
1495
1496         case TTM_PL_VRAM:
1497                 /* Check each drm MM node individually */
1498                 while (num_pages) {
1499                         if (place->fpfn < (node->start + node->size) &&
1500                             !(place->lpfn && place->lpfn <= node->start))
1501                                 return true;
1502
1503                         num_pages -= node->size;
1504                         ++node;
1505                 }
1506                 return false;
1507
1508         default:
1509                 break;
1510         }
1511
1512         return ttm_bo_eviction_valuable(bo, place);
1513 }
1514
1515 /**
1516  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1517  *
1518  * @bo:  The buffer object to read/write
1519  * @offset:  Offset into buffer object
1520  * @buf:  Secondary buffer to write/read from
1521  * @len: Length in bytes of access
1522  * @write:  true if writing
1523  *
1524  * This is used to access VRAM that backs a buffer object via MMIO
1525  * access for debugging purposes.
1526  */
1527 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1528                                     unsigned long offset,
1529                                     void *buf, int len, int write)
1530 {
1531         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1532         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1533         struct drm_mm_node *nodes;
1534         uint32_t value = 0;
1535         int ret = 0;
1536         uint64_t pos;
1537         unsigned long flags;
1538
1539         if (bo->mem.mem_type != TTM_PL_VRAM)
1540                 return -EIO;
1541
1542         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1543         pos = (nodes->start << PAGE_SHIFT) + offset;
1544
1545         while (len && pos < adev->gmc.mc_vram_size) {
1546                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1547                 uint32_t bytes = 4 - (pos & 3);
1548                 uint32_t shift = (pos & 3) * 8;
1549                 uint32_t mask = 0xffffffff << shift;
1550
1551                 if (len < bytes) {
1552                         mask &= 0xffffffff >> (bytes - len) * 8;
1553                         bytes = len;
1554                 }
1555
1556                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1557                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1558                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1559                 if (!write || mask != 0xffffffff)
1560                         value = RREG32_NO_KIQ(mmMM_DATA);
1561                 if (write) {
1562                         value &= ~mask;
1563                         value |= (*(uint32_t *)buf << shift) & mask;
1564                         WREG32_NO_KIQ(mmMM_DATA, value);
1565                 }
1566                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1567                 if (!write) {
1568                         value = (value & mask) >> shift;
1569                         memcpy(buf, &value, bytes);
1570                 }
1571
1572                 ret += bytes;
1573                 buf = (uint8_t *)buf + bytes;
1574                 pos += bytes;
1575                 len -= bytes;
1576                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1577                         ++nodes;
1578                         pos = (nodes->start << PAGE_SHIFT);
1579                 }
1580         }
1581
1582         return ret;
1583 }
1584
1585 static struct ttm_bo_driver amdgpu_bo_driver = {
1586         .ttm_tt_create = &amdgpu_ttm_tt_create,
1587         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1588         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1589         .invalidate_caches = &amdgpu_invalidate_caches,
1590         .init_mem_type = &amdgpu_init_mem_type,
1591         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1592         .evict_flags = &amdgpu_evict_flags,
1593         .move = &amdgpu_bo_move,
1594         .verify_access = &amdgpu_verify_access,
1595         .move_notify = &amdgpu_bo_move_notify,
1596         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1597         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1598         .io_mem_free = &amdgpu_ttm_io_mem_free,
1599         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1600         .access_memory = &amdgpu_ttm_access_memory
1601 };
1602
1603 /*
1604  * Firmware Reservation functions
1605  */
1606 /**
1607  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1608  *
1609  * @adev: amdgpu_device pointer
1610  *
1611  * free fw reserved vram if it has been reserved.
1612  */
1613 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1614 {
1615         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1616                 NULL, &adev->fw_vram_usage.va);
1617 }
1618
1619 /**
1620  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1621  *
1622  * @adev: amdgpu_device pointer
1623  *
1624  * create bo vram reservation from fw.
1625  */
1626 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1627 {
1628         struct ttm_operation_ctx ctx = { false, false };
1629         struct amdgpu_bo_param bp;
1630         int r = 0;
1631         int i;
1632         u64 vram_size = adev->gmc.visible_vram_size;
1633         u64 offset = adev->fw_vram_usage.start_offset;
1634         u64 size = adev->fw_vram_usage.size;
1635         struct amdgpu_bo *bo;
1636
1637         memset(&bp, 0, sizeof(bp));
1638         bp.size = adev->fw_vram_usage.size;
1639         bp.byte_align = PAGE_SIZE;
1640         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1641         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1642                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1643         bp.type = ttm_bo_type_kernel;
1644         bp.resv = NULL;
1645         adev->fw_vram_usage.va = NULL;
1646         adev->fw_vram_usage.reserved_bo = NULL;
1647
1648         if (adev->fw_vram_usage.size > 0 &&
1649                 adev->fw_vram_usage.size <= vram_size) {
1650
1651                 r = amdgpu_bo_create(adev, &bp,
1652                                      &adev->fw_vram_usage.reserved_bo);
1653                 if (r)
1654                         goto error_create;
1655
1656                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1657                 if (r)
1658                         goto error_reserve;
1659
1660                 /* remove the original mem node and create a new one at the
1661                  * request position
1662                  */
1663                 bo = adev->fw_vram_usage.reserved_bo;
1664                 offset = ALIGN(offset, PAGE_SIZE);
1665                 for (i = 0; i < bo->placement.num_placement; ++i) {
1666                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1667                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1668                 }
1669
1670                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1671                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1672                                      &bo->tbo.mem, &ctx);
1673                 if (r)
1674                         goto error_pin;
1675
1676                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1677                         AMDGPU_GEM_DOMAIN_VRAM,
1678                         adev->fw_vram_usage.start_offset,
1679                         (adev->fw_vram_usage.start_offset +
1680                         adev->fw_vram_usage.size));
1681                 if (r)
1682                         goto error_pin;
1683                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1684                         &adev->fw_vram_usage.va);
1685                 if (r)
1686                         goto error_kmap;
1687
1688                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1689         }
1690         return r;
1691
1692 error_kmap:
1693         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1694 error_pin:
1695         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1696 error_reserve:
1697         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1698 error_create:
1699         adev->fw_vram_usage.va = NULL;
1700         adev->fw_vram_usage.reserved_bo = NULL;
1701         return r;
1702 }
1703 /**
1704  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1705  * gtt/vram related fields.
1706  *
1707  * This initializes all of the memory space pools that the TTM layer
1708  * will need such as the GTT space (system memory mapped to the device),
1709  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1710  * can be mapped per VMID.
1711  */
1712 int amdgpu_ttm_init(struct amdgpu_device *adev)
1713 {
1714         uint64_t gtt_size;
1715         int r;
1716         u64 vis_vram_limit;
1717
1718         /* initialize global references for vram/gtt */
1719         r = amdgpu_ttm_global_init(adev);
1720         if (r) {
1721                 return r;
1722         }
1723         /* No others user of address space so set it to 0 */
1724         r = ttm_bo_device_init(&adev->mman.bdev,
1725                                adev->mman.bo_global_ref.ref.object,
1726                                &amdgpu_bo_driver,
1727                                adev->ddev->anon_inode->i_mapping,
1728                                DRM_FILE_PAGE_OFFSET,
1729                                adev->need_dma32);
1730         if (r) {
1731                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1732                 return r;
1733         }
1734         adev->mman.initialized = true;
1735
1736         /* We opt to avoid OOM on system pages allocations */
1737         adev->mman.bdev.no_retry = true;
1738
1739         /* Initialize VRAM pool with all of VRAM divided into pages */
1740         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1741                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1742         if (r) {
1743                 DRM_ERROR("Failed initializing VRAM heap.\n");
1744                 return r;
1745         }
1746
1747         /* Reduce size of CPU-visible VRAM if requested */
1748         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1749         if (amdgpu_vis_vram_limit > 0 &&
1750             vis_vram_limit <= adev->gmc.visible_vram_size)
1751                 adev->gmc.visible_vram_size = vis_vram_limit;
1752
1753         /* Change the size here instead of the init above so only lpfn is affected */
1754         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1755 #ifdef CONFIG_64BIT
1756         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1757                                                 adev->gmc.visible_vram_size);
1758 #endif
1759
1760         /*
1761          *The reserved vram for firmware must be pinned to the specified
1762          *place on the VRAM, so reserve it early.
1763          */
1764         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1765         if (r) {
1766                 return r;
1767         }
1768
1769         /* allocate memory as required for VGA
1770          * This is used for VGA emulation and pre-OS scanout buffers to
1771          * avoid display artifacts while transitioning between pre-OS
1772          * and driver.  */
1773         if (adev->gmc.stolen_size) {
1774                 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1775                                             AMDGPU_GEM_DOMAIN_VRAM,
1776                                             &adev->stolen_vga_memory,
1777                                             NULL, NULL);
1778                 if (r)
1779                         return r;
1780         }
1781         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1782                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1783
1784         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1785          * or whatever the user passed on module init */
1786         if (amdgpu_gtt_size == -1) {
1787                 struct sysinfo si;
1788
1789                 si_meminfo(&si);
1790                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1791                                adev->gmc.mc_vram_size),
1792                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1793         }
1794         else
1795                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1796
1797         /* Initialize GTT memory pool */
1798         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1799         if (r) {
1800                 DRM_ERROR("Failed initializing GTT heap.\n");
1801                 return r;
1802         }
1803         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1804                  (unsigned)(gtt_size / (1024 * 1024)));
1805
1806         /* Initialize various on-chip memory pools */
1807         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1808         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1809         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1810         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1811         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1812         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1813         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1814         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1815         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1816         /* GDS Memory */
1817         if (adev->gds.mem.total_size) {
1818                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1819                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1820                 if (r) {
1821                         DRM_ERROR("Failed initializing GDS heap.\n");
1822                         return r;
1823                 }
1824         }
1825
1826         /* GWS */
1827         if (adev->gds.gws.total_size) {
1828                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1829                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1830                 if (r) {
1831                         DRM_ERROR("Failed initializing gws heap.\n");
1832                         return r;
1833                 }
1834         }
1835
1836         /* OA */
1837         if (adev->gds.oa.total_size) {
1838                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1839                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1840                 if (r) {
1841                         DRM_ERROR("Failed initializing oa heap.\n");
1842                         return r;
1843                 }
1844         }
1845
1846         /* Register debugfs entries for amdgpu_ttm */
1847         r = amdgpu_ttm_debugfs_init(adev);
1848         if (r) {
1849                 DRM_ERROR("Failed to init debugfs\n");
1850                 return r;
1851         }
1852         return 0;
1853 }
1854
1855 /**
1856  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1857  */
1858 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1859 {
1860         /* return the VGA stolen memory (if any) back to VRAM */
1861         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1862 }
1863
1864 /**
1865  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1866  */
1867 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1868 {
1869         if (!adev->mman.initialized)
1870                 return;
1871
1872         amdgpu_ttm_debugfs_fini(adev);
1873         amdgpu_ttm_fw_reserve_vram_fini(adev);
1874         if (adev->mman.aper_base_kaddr)
1875                 iounmap(adev->mman.aper_base_kaddr);
1876         adev->mman.aper_base_kaddr = NULL;
1877
1878         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1879         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1880         if (adev->gds.mem.total_size)
1881                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1882         if (adev->gds.gws.total_size)
1883                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1884         if (adev->gds.oa.total_size)
1885                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1886         ttm_bo_device_release(&adev->mman.bdev);
1887         amdgpu_ttm_global_fini(adev);
1888         adev->mman.initialized = false;
1889         DRM_INFO("amdgpu: ttm finalized\n");
1890 }
1891
1892 /**
1893  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1894  *
1895  * @adev: amdgpu_device pointer
1896  * @enable: true when we can use buffer functions.
1897  *
1898  * Enable/disable use of buffer functions during suspend/resume. This should
1899  * only be called at bootup or when userspace isn't running.
1900  */
1901 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1902 {
1903         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1904         uint64_t size;
1905         int r;
1906
1907         if (!adev->mman.initialized || adev->in_gpu_reset ||
1908             adev->mman.buffer_funcs_enabled == enable)
1909                 return;
1910
1911         if (enable) {
1912                 struct amdgpu_ring *ring;
1913                 struct drm_sched_rq *rq;
1914
1915                 ring = adev->mman.buffer_funcs_ring;
1916                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1917                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1918                 if (r) {
1919                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1920                                   r);
1921                         return;
1922                 }
1923         } else {
1924                 drm_sched_entity_destroy(&adev->mman.entity);
1925                 dma_fence_put(man->move);
1926                 man->move = NULL;
1927         }
1928
1929         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1930         if (enable)
1931                 size = adev->gmc.real_vram_size;
1932         else
1933                 size = adev->gmc.visible_vram_size;
1934         man->size = size >> PAGE_SHIFT;
1935         adev->mman.buffer_funcs_enabled = enable;
1936 }
1937
1938 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1939 {
1940         struct drm_file *file_priv;
1941         struct amdgpu_device *adev;
1942
1943         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1944                 return -EINVAL;
1945
1946         file_priv = filp->private_data;
1947         adev = file_priv->minor->dev->dev_private;
1948         if (adev == NULL)
1949                 return -EINVAL;
1950
1951         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1952 }
1953
1954 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1955                              struct ttm_mem_reg *mem, unsigned num_pages,
1956                              uint64_t offset, unsigned window,
1957                              struct amdgpu_ring *ring,
1958                              uint64_t *addr)
1959 {
1960         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1961         struct amdgpu_device *adev = ring->adev;
1962         struct ttm_tt *ttm = bo->ttm;
1963         struct amdgpu_job *job;
1964         unsigned num_dw, num_bytes;
1965         dma_addr_t *dma_address;
1966         struct dma_fence *fence;
1967         uint64_t src_addr, dst_addr;
1968         uint64_t flags;
1969         int r;
1970
1971         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1972                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1973
1974         *addr = adev->gmc.gart_start;
1975         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1976                 AMDGPU_GPU_PAGE_SIZE;
1977
1978         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1979         while (num_dw & 0x7)
1980                 num_dw++;
1981
1982         num_bytes = num_pages * 8;
1983
1984         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1985         if (r)
1986                 return r;
1987
1988         src_addr = num_dw * 4;
1989         src_addr += job->ibs[0].gpu_addr;
1990
1991         dst_addr = adev->gart.table_addr;
1992         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1993         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1994                                 dst_addr, num_bytes);
1995
1996         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1997         WARN_ON(job->ibs[0].length_dw > num_dw);
1998
1999         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
2000         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2001         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2002                             &job->ibs[0].ptr[num_dw]);
2003         if (r)
2004                 goto error_free;
2005
2006         r = amdgpu_job_submit(job, &adev->mman.entity,
2007                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2008         if (r)
2009                 goto error_free;
2010
2011         dma_fence_put(fence);
2012
2013         return r;
2014
2015 error_free:
2016         amdgpu_job_free(job);
2017         return r;
2018 }
2019
2020 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2021                        uint64_t dst_offset, uint32_t byte_count,
2022                        struct reservation_object *resv,
2023                        struct dma_fence **fence, bool direct_submit,
2024                        bool vm_needs_flush)
2025 {
2026         struct amdgpu_device *adev = ring->adev;
2027         struct amdgpu_job *job;
2028
2029         uint32_t max_bytes;
2030         unsigned num_loops, num_dw;
2031         unsigned i;
2032         int r;
2033
2034         if (direct_submit && !ring->ready) {
2035                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2036                 return -EINVAL;
2037         }
2038
2039         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2040         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2041         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
2042
2043         /* for IB padding */
2044         while (num_dw & 0x7)
2045                 num_dw++;
2046
2047         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2048         if (r)
2049                 return r;
2050
2051         job->vm_needs_flush = vm_needs_flush;
2052         if (resv) {
2053                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2054                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2055                                      false);
2056                 if (r) {
2057                         DRM_ERROR("sync failed (%d).\n", r);
2058                         goto error_free;
2059                 }
2060         }
2061
2062         for (i = 0; i < num_loops; i++) {
2063                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2064
2065                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2066                                         dst_offset, cur_size_in_bytes);
2067
2068                 src_offset += cur_size_in_bytes;
2069                 dst_offset += cur_size_in_bytes;
2070                 byte_count -= cur_size_in_bytes;
2071         }
2072
2073         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2074         WARN_ON(job->ibs[0].length_dw > num_dw);
2075         if (direct_submit)
2076                 r = amdgpu_job_submit_direct(job, ring, fence);
2077         else
2078                 r = amdgpu_job_submit(job, &adev->mman.entity,
2079                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2080         if (r)
2081                 goto error_free;
2082
2083         return r;
2084
2085 error_free:
2086         amdgpu_job_free(job);
2087         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2088         return r;
2089 }
2090
2091 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2092                        uint32_t src_data,
2093                        struct reservation_object *resv,
2094                        struct dma_fence **fence)
2095 {
2096         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2097         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2098         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2099
2100         struct drm_mm_node *mm_node;
2101         unsigned long num_pages;
2102         unsigned int num_loops, num_dw;
2103
2104         struct amdgpu_job *job;
2105         int r;
2106
2107         if (!adev->mman.buffer_funcs_enabled) {
2108                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2109                 return -EINVAL;
2110         }
2111
2112         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2113                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2114                 if (r)
2115                         return r;
2116         }
2117
2118         num_pages = bo->tbo.num_pages;
2119         mm_node = bo->tbo.mem.mm_node;
2120         num_loops = 0;
2121         while (num_pages) {
2122                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2123
2124                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2125                 num_pages -= mm_node->size;
2126                 ++mm_node;
2127         }
2128         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2129
2130         /* for IB padding */
2131         num_dw += 64;
2132
2133         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2134         if (r)
2135                 return r;
2136
2137         if (resv) {
2138                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2139                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2140                 if (r) {
2141                         DRM_ERROR("sync failed (%d).\n", r);
2142                         goto error_free;
2143                 }
2144         }
2145
2146         num_pages = bo->tbo.num_pages;
2147         mm_node = bo->tbo.mem.mm_node;
2148
2149         while (num_pages) {
2150                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2151                 uint64_t dst_addr;
2152
2153                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2154                 while (byte_count) {
2155                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2156
2157                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2158                                                 dst_addr, cur_size_in_bytes);
2159
2160                         dst_addr += cur_size_in_bytes;
2161                         byte_count -= cur_size_in_bytes;
2162                 }
2163
2164                 num_pages -= mm_node->size;
2165                 ++mm_node;
2166         }
2167
2168         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2169         WARN_ON(job->ibs[0].length_dw > num_dw);
2170         r = amdgpu_job_submit(job, &adev->mman.entity,
2171                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2172         if (r)
2173                 goto error_free;
2174
2175         return 0;
2176
2177 error_free:
2178         amdgpu_job_free(job);
2179         return r;
2180 }
2181
2182 #if defined(CONFIG_DEBUG_FS)
2183
2184 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2185 {
2186         struct drm_info_node *node = (struct drm_info_node *)m->private;
2187         unsigned ttm_pl = *(int *)node->info_ent->data;
2188         struct drm_device *dev = node->minor->dev;
2189         struct amdgpu_device *adev = dev->dev_private;
2190         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2191         struct drm_printer p = drm_seq_file_printer(m);
2192
2193         man->func->debug(man, &p);
2194         return 0;
2195 }
2196
2197 static int ttm_pl_vram = TTM_PL_VRAM;
2198 static int ttm_pl_tt = TTM_PL_TT;
2199
2200 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2201         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
2202         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
2203         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2204 #ifdef CONFIG_SWIOTLB
2205         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2206 #endif
2207 };
2208
2209 /**
2210  * amdgpu_ttm_vram_read - Linear read access to VRAM
2211  *
2212  * Accesses VRAM via MMIO for debugging purposes.
2213  */
2214 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2215                                     size_t size, loff_t *pos)
2216 {
2217         struct amdgpu_device *adev = file_inode(f)->i_private;
2218         ssize_t result = 0;
2219         int r;
2220
2221         if (size & 0x3 || *pos & 0x3)
2222                 return -EINVAL;
2223
2224         if (*pos >= adev->gmc.mc_vram_size)
2225                 return -ENXIO;
2226
2227         while (size) {
2228                 unsigned long flags;
2229                 uint32_t value;
2230
2231                 if (*pos >= adev->gmc.mc_vram_size)
2232                         return result;
2233
2234                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2235                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2236                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2237                 value = RREG32_NO_KIQ(mmMM_DATA);
2238                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2239
2240                 r = put_user(value, (uint32_t *)buf);
2241                 if (r)
2242                         return r;
2243
2244                 result += 4;
2245                 buf += 4;
2246                 *pos += 4;
2247                 size -= 4;
2248         }
2249
2250         return result;
2251 }
2252
2253 /**
2254  * amdgpu_ttm_vram_write - Linear write access to VRAM
2255  *
2256  * Accesses VRAM via MMIO for debugging purposes.
2257  */
2258 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2259                                     size_t size, loff_t *pos)
2260 {
2261         struct amdgpu_device *adev = file_inode(f)->i_private;
2262         ssize_t result = 0;
2263         int r;
2264
2265         if (size & 0x3 || *pos & 0x3)
2266                 return -EINVAL;
2267
2268         if (*pos >= adev->gmc.mc_vram_size)
2269                 return -ENXIO;
2270
2271         while (size) {
2272                 unsigned long flags;
2273                 uint32_t value;
2274
2275                 if (*pos >= adev->gmc.mc_vram_size)
2276                         return result;
2277
2278                 r = get_user(value, (uint32_t *)buf);
2279                 if (r)
2280                         return r;
2281
2282                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2283                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2284                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2285                 WREG32_NO_KIQ(mmMM_DATA, value);
2286                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2287
2288                 result += 4;
2289                 buf += 4;
2290                 *pos += 4;
2291                 size -= 4;
2292         }
2293
2294         return result;
2295 }
2296
2297 static const struct file_operations amdgpu_ttm_vram_fops = {
2298         .owner = THIS_MODULE,
2299         .read = amdgpu_ttm_vram_read,
2300         .write = amdgpu_ttm_vram_write,
2301         .llseek = default_llseek,
2302 };
2303
2304 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2305
2306 /**
2307  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2308  */
2309 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2310                                    size_t size, loff_t *pos)
2311 {
2312         struct amdgpu_device *adev = file_inode(f)->i_private;
2313         ssize_t result = 0;
2314         int r;
2315
2316         while (size) {
2317                 loff_t p = *pos / PAGE_SIZE;
2318                 unsigned off = *pos & ~PAGE_MASK;
2319                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2320                 struct page *page;
2321                 void *ptr;
2322
2323                 if (p >= adev->gart.num_cpu_pages)
2324                         return result;
2325
2326                 page = adev->gart.pages[p];
2327                 if (page) {
2328                         ptr = kmap(page);
2329                         ptr += off;
2330
2331                         r = copy_to_user(buf, ptr, cur_size);
2332                         kunmap(adev->gart.pages[p]);
2333                 } else
2334                         r = clear_user(buf, cur_size);
2335
2336                 if (r)
2337                         return -EFAULT;
2338
2339                 result += cur_size;
2340                 buf += cur_size;
2341                 *pos += cur_size;
2342                 size -= cur_size;
2343         }
2344
2345         return result;
2346 }
2347
2348 static const struct file_operations amdgpu_ttm_gtt_fops = {
2349         .owner = THIS_MODULE,
2350         .read = amdgpu_ttm_gtt_read,
2351         .llseek = default_llseek
2352 };
2353
2354 #endif
2355
2356 /**
2357  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2358  *
2359  * This function is used to read memory that has been mapped to the
2360  * GPU and the known addresses are not physical addresses but instead
2361  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2362  */
2363 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2364                                  size_t size, loff_t *pos)
2365 {
2366         struct amdgpu_device *adev = file_inode(f)->i_private;
2367         struct iommu_domain *dom;
2368         ssize_t result = 0;
2369         int r;
2370
2371         /* retrieve the IOMMU domain if any for this device */
2372         dom = iommu_get_domain_for_dev(adev->dev);
2373
2374         while (size) {
2375                 phys_addr_t addr = *pos & PAGE_MASK;
2376                 loff_t off = *pos & ~PAGE_MASK;
2377                 size_t bytes = PAGE_SIZE - off;
2378                 unsigned long pfn;
2379                 struct page *p;
2380                 void *ptr;
2381
2382                 bytes = bytes < size ? bytes : size;
2383
2384                 /* Translate the bus address to a physical address.  If
2385                  * the domain is NULL it means there is no IOMMU active
2386                  * and the address translation is the identity
2387                  */
2388                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2389
2390                 pfn = addr >> PAGE_SHIFT;
2391                 if (!pfn_valid(pfn))
2392                         return -EPERM;
2393
2394                 p = pfn_to_page(pfn);
2395                 if (p->mapping != adev->mman.bdev.dev_mapping)
2396                         return -EPERM;
2397
2398                 ptr = kmap(p);
2399                 r = copy_to_user(buf, ptr + off, bytes);
2400                 kunmap(p);
2401                 if (r)
2402                         return -EFAULT;
2403
2404                 size -= bytes;
2405                 *pos += bytes;
2406                 result += bytes;
2407         }
2408
2409         return result;
2410 }
2411
2412 /**
2413  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2414  *
2415  * This function is used to write memory that has been mapped to the
2416  * GPU and the known addresses are not physical addresses but instead
2417  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2418  */
2419 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2420                                  size_t size, loff_t *pos)
2421 {
2422         struct amdgpu_device *adev = file_inode(f)->i_private;
2423         struct iommu_domain *dom;
2424         ssize_t result = 0;
2425         int r;
2426
2427         dom = iommu_get_domain_for_dev(adev->dev);
2428
2429         while (size) {
2430                 phys_addr_t addr = *pos & PAGE_MASK;
2431                 loff_t off = *pos & ~PAGE_MASK;
2432                 size_t bytes = PAGE_SIZE - off;
2433                 unsigned long pfn;
2434                 struct page *p;
2435                 void *ptr;
2436
2437                 bytes = bytes < size ? bytes : size;
2438
2439                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2440
2441                 pfn = addr >> PAGE_SHIFT;
2442                 if (!pfn_valid(pfn))
2443                         return -EPERM;
2444
2445                 p = pfn_to_page(pfn);
2446                 if (p->mapping != adev->mman.bdev.dev_mapping)
2447                         return -EPERM;
2448
2449                 ptr = kmap(p);
2450                 r = copy_from_user(ptr + off, buf, bytes);
2451                 kunmap(p);
2452                 if (r)
2453                         return -EFAULT;
2454
2455                 size -= bytes;
2456                 *pos += bytes;
2457                 result += bytes;
2458         }
2459
2460         return result;
2461 }
2462
2463 static const struct file_operations amdgpu_ttm_iomem_fops = {
2464         .owner = THIS_MODULE,
2465         .read = amdgpu_iomem_read,
2466         .write = amdgpu_iomem_write,
2467         .llseek = default_llseek
2468 };
2469
2470 static const struct {
2471         char *name;
2472         const struct file_operations *fops;
2473         int domain;
2474 } ttm_debugfs_entries[] = {
2475         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2476 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2477         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2478 #endif
2479         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2480 };
2481
2482 #endif
2483
2484 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2485 {
2486 #if defined(CONFIG_DEBUG_FS)
2487         unsigned count;
2488
2489         struct drm_minor *minor = adev->ddev->primary;
2490         struct dentry *ent, *root = minor->debugfs_root;
2491
2492         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2493                 ent = debugfs_create_file(
2494                                 ttm_debugfs_entries[count].name,
2495                                 S_IFREG | S_IRUGO, root,
2496                                 adev,
2497                                 ttm_debugfs_entries[count].fops);
2498                 if (IS_ERR(ent))
2499                         return PTR_ERR(ent);
2500                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2501                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2502                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2503                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2504                 adev->mman.debugfs_entries[count] = ent;
2505         }
2506
2507         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2508
2509 #ifdef CONFIG_SWIOTLB
2510         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2511                 --count;
2512 #endif
2513
2514         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2515 #else
2516         return 0;
2517 #endif
2518 }
2519
2520 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2521 {
2522 #if defined(CONFIG_DEBUG_FS)
2523         unsigned i;
2524
2525         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2526                 debugfs_remove(adev->mman.debugfs_entries[i]);
2527 #endif
2528 }