1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for HiSilicon SoCs
5 * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/pci.h>
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
17 #include "../../pci.h"
19 #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
22 void __iomem *reg_base;
25 static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
28 struct pci_config_window *cfg = bus->sysdata;
29 int dev = PCI_SLOT(devfn);
31 if (bus->number == cfg->busr.start) {
32 /* access only one slot on each root port */
34 return PCIBIOS_DEVICE_NOT_FOUND;
36 return pci_generic_config_read32(bus, devfn, where,
40 return pci_generic_config_read(bus, devfn, where, size, val);
43 static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
44 int where, int size, u32 val)
46 struct pci_config_window *cfg = bus->sysdata;
47 int dev = PCI_SLOT(devfn);
49 if (bus->number == cfg->busr.start) {
50 /* access only one slot on each root port */
52 return PCIBIOS_DEVICE_NOT_FOUND;
54 return pci_generic_config_write32(bus, devfn, where,
58 return pci_generic_config_write(bus, devfn, where, size, val);
61 static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
64 struct pci_config_window *cfg = bus->sysdata;
65 struct hisi_pcie *pcie = cfg->priv;
67 if (bus->number == cfg->busr.start)
68 return pcie->reg_base + where;
70 return pci_ecam_map_bus(bus, devfn, where);
73 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
75 static int hisi_pcie_init(struct pci_config_window *cfg)
77 struct device *dev = cfg->parent;
78 struct hisi_pcie *pcie;
79 struct acpi_device *adev = to_acpi_device(dev);
80 struct acpi_pci_root *root = acpi_driver_data(adev);
84 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
89 * Retrieve RC base and size from a HISI0081 device with _UID
90 * matching our segment.
92 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
96 ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
98 dev_err(dev, "can't get rc base address\n");
102 pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
110 const struct pci_ecam_ops hisi_pcie_ops = {
111 .init = hisi_pcie_init,
113 .map_bus = hisi_pcie_map_bus,
114 .read = hisi_pcie_rd_conf,
115 .write = hisi_pcie_wr_conf,
121 #ifdef CONFIG_PCI_HISI
123 static int hisi_pcie_platform_init(struct pci_config_window *cfg)
125 struct device *dev = cfg->parent;
126 struct hisi_pcie *pcie;
127 struct platform_device *pdev = to_platform_device(dev);
128 struct resource *res;
130 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
134 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
136 dev_err(dev, "missing \"reg[1]\"property\n");
140 pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
148 static const struct pci_ecam_ops hisi_pcie_platform_ops = {
149 .init = hisi_pcie_platform_init,
151 .map_bus = hisi_pcie_map_bus,
152 .read = hisi_pcie_rd_conf,
153 .write = hisi_pcie_wr_conf,
157 static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
159 .compatible = "hisilicon,hip06-pcie-ecam",
160 .data = &hisi_pcie_platform_ops,
163 .compatible = "hisilicon,hip07-pcie-ecam",
164 .data = &hisi_pcie_platform_ops,
169 static struct platform_driver hisi_pcie_almost_ecam_driver = {
170 .probe = pci_host_common_probe,
172 .name = "hisi-pcie-almost-ecam",
173 .of_match_table = hisi_pcie_almost_ecam_of_match,
174 .suppress_bind_attrs = true,
177 builtin_platform_driver(hisi_pcie_almost_ecam_driver);