drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <[email protected]>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_helper.h>
  35 #include <drm/display/drm_scdc_helper.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_drv.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_simple_kms_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/i2c.h>
  44 #include <linux/of_address.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/rational.h>
  48 #include <linux/reset.h>
  49 #include <sound/dmaengine_pcm.h>
  50 #include <sound/hdmi-codec.h>
  51 #include <sound/pcm_drm_eld.h>
  52 #include <sound/pcm_params.h>
  53 #include <sound/soc.h>
  54 #include "media/cec.h"
  55 #include "vc4_drv.h"
  56 #include "vc4_hdmi.h"
  57 #include "vc4_hdmi_regs.h"
  58 #include "vc4_regs.h"
  59
  60 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  61 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  62 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  63 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  64 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  65 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  66
  67 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  68 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  69 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  70 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  71
  72 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  73 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  74 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  75 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  76 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  77 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  78
  79 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  80 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  81
  82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  86
  87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  88
  89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  91
  92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  94
  95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  96
  97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  99
 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK   VC4_MASK(7, 0)
 101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE     BIT(0)
 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE   BIT(4)
 103
 104 # define VC4_HD_M_SW_RST                        BIT(2)
 105 # define VC4_HD_M_ENABLE                        BIT(0)
 106
 107 #define HSM_MIN_CLOCK_FREQ      120000000
 108 #define CEC_CLOCK_FREQ 40000
 109
 110 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 111
 112 static const char * const output_format_str[] = {
 113         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 114         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 115         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 116         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 117 };
 118
 119 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 120 {
 121         if (fmt >= ARRAY_SIZE(output_format_str))
 122                 return "invalid";
 123
 124         return output_format_str[fmt];
 125 }
 126
 127 static unsigned long long
 128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 129                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 130
 131 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
 132 {
 133         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 134
 135         lockdep_assert_held(&vc4_hdmi->mutex);
 136
 137         if (!display->is_hdmi)
 138                 return false;
 139
 140         if (!display->hdmi.scdc.supported ||
 141             !display->hdmi.scdc.scrambling.supported)
 142                 return false;
 143
 144         return true;
 145 }
 146
 147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 148                                            unsigned int bpc,
 149                                            enum vc4_hdmi_output_format fmt)
 150 {
 151         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 152
 153         return clock > HDMI_14_MAX_TMDS_CLK;
 154 }
 155
 156 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 157                                        const struct drm_display_mode *mode)
 158 {
 159         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 160
 161         return !display->is_hdmi ||
 162                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 163 }
 164
 165 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 166 {
 167         struct drm_debugfs_entry *entry = m->private;
 168         struct vc4_hdmi *vc4_hdmi = entry->file.data;
 169         struct drm_device *drm = vc4_hdmi->connector.dev;
 170         struct drm_printer p = drm_seq_file_printer(m);
 171         int idx;
 172
 173         if (!drm_dev_enter(drm, &idx))
 174                 return -ENODEV;
 175
 176         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 177         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 178         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 179         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 180         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 181         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 182         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 183         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 184
 185         drm_dev_exit(idx);
 186
 187         return 0;
 188 }
 189
 190 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 191 {
 192         struct drm_device *drm = vc4_hdmi->connector.dev;
 193         unsigned long flags;
 194         int idx;
 195
 196         /*
 197          * We can be called by our bind callback, when the
 198          * connector->dev pointer might not be initialised yet.
 199          */
 200         if (drm && !drm_dev_enter(drm, &idx))
 201                 return;
 202
 203         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 204
 205         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 206         udelay(1);
 207         HDMI_WRITE(HDMI_M_CTL, 0);
 208
 209         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 210
 211         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 212                    VC4_HDMI_SW_RESET_HDMI |
 213                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 214
 215         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 216
 217         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 218
 219         if (drm)
 220                 drm_dev_exit(idx);
 221 }
 222
 223 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 224 {
 225         struct drm_device *drm = vc4_hdmi->connector.dev;
 226         unsigned long flags;
 227         int idx;
 228
 229         /*
 230          * We can be called by our bind callback, when the
 231          * connector->dev pointer might not be initialised yet.
 232          */
 233         if (drm && !drm_dev_enter(drm, &idx))
 234                 return;
 235
 236         reset_control_reset(vc4_hdmi->reset);
 237
 238         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 239
 240         HDMI_WRITE(HDMI_DVP_CTL, 0);
 241
 242         HDMI_WRITE(HDMI_CLOCK_STOP,
 243                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 244
 245         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 246
 247         if (drm)
 248                 drm_dev_exit(idx);
 249 }
 250
 251 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 252 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 253 {
 254         struct drm_device *drm = vc4_hdmi->connector.dev;
 255         unsigned long cec_rate;
 256         unsigned long flags;
 257         u16 clk_cnt;
 258         u32 value;
 259         int idx;
 260
 261         /*
 262          * This function is called by our runtime_resume implementation
 263          * and thus at bind time, when we haven't registered our
 264          * connector yet and thus don't have a pointer to the DRM
 265          * device.
 266          */
 267         if (drm && !drm_dev_enter(drm, &idx))
 268                 return;
 269
 270         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 271
 272         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 273
 274         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 275         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 276
 277         /*
 278          * Set the clock divider: the hsm_clock rate and this divider
 279          * setting will give a 40 kHz CEC clock.
 280          */
 281         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 282         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 283         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 284
 285         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 286
 287         if (drm)
 288                 drm_dev_exit(idx);
 289 }
 290 #else
 291 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 292 #endif
 293
 294 static int reset_pipe(struct drm_crtc *crtc,
 295                         struct drm_modeset_acquire_ctx *ctx)
 296 {
 297         struct drm_atomic_state *state;
 298         struct drm_crtc_state *crtc_state;
 299         int ret;
 300
 301         state = drm_atomic_state_alloc(crtc->dev);
 302         if (!state)
 303                 return -ENOMEM;
 304
 305         state->acquire_ctx = ctx;
 306
 307         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 308         if (IS_ERR(crtc_state)) {
 309                 ret = PTR_ERR(crtc_state);
 310                 goto out;
 311         }
 312
 313         crtc_state->connectors_changed = true;
 314
 315         ret = drm_atomic_commit(state);
 316 out:
 317         drm_atomic_state_put(state);
 318
 319         return ret;
 320 }
 321
 322 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 323                                struct drm_modeset_acquire_ctx *ctx)
 324 {
 325         struct drm_device *drm;
 326         struct vc4_hdmi *vc4_hdmi;
 327         struct drm_connector_state *conn_state;
 328         struct drm_crtc_state *crtc_state;
 329         struct drm_crtc *crtc;
 330         bool scrambling_needed;
 331         u8 config;
 332         int ret;
 333
 334         if (!connector)
 335                 return 0;
 336
 337         drm = connector->dev;
 338         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 339         if (ret)
 340                 return ret;
 341
 342         conn_state = connector->state;
 343         crtc = conn_state->crtc;
 344         if (!crtc)
 345                 return 0;
 346
 347         ret = drm_modeset_lock(&crtc->mutex, ctx);
 348         if (ret)
 349                 return ret;
 350
 351         crtc_state = crtc->state;
 352         if (!crtc_state->active)
 353                 return 0;
 354
 355         vc4_hdmi = connector_to_vc4_hdmi(connector);
 356         mutex_lock(&vc4_hdmi->mutex);
 357
 358         if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
 359                 mutex_unlock(&vc4_hdmi->mutex);
 360                 return 0;
 361         }
 362
 363         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 364                                                            vc4_hdmi->output_bpc,
 365                                                            vc4_hdmi->output_format);
 366         if (!scrambling_needed) {
 367                 mutex_unlock(&vc4_hdmi->mutex);
 368                 return 0;
 369         }
 370
 371         if (conn_state->commit &&
 372             !try_wait_for_completion(&conn_state->commit->hw_done)) {
 373                 mutex_unlock(&vc4_hdmi->mutex);
 374                 return 0;
 375         }
 376
 377         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 378         if (ret < 0) {
 379                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 380                 mutex_unlock(&vc4_hdmi->mutex);
 381                 return 0;
 382         }
 383
 384         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
 385                 mutex_unlock(&vc4_hdmi->mutex);
 386                 return 0;
 387         }
 388
 389         mutex_unlock(&vc4_hdmi->mutex);
 390
 391         /*
 392          * HDMI 2.0 says that one should not send scrambled data
 393          * prior to configuring the sink scrambling, and that
 394          * TMDS clock/data transmission should be suspended when
 395          * changing the TMDS clock rate in the sink. So let's
 396          * just do a full modeset here, even though some sinks
 397          * would be perfectly happy if were to just reconfigure
 398          * the SCDC settings on the fly.
 399          */
 400         return reset_pipe(crtc, ctx);
 401 }
 402
 403 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 404                                     struct drm_modeset_acquire_ctx *ctx,
 405                                     enum drm_connector_status status)
 406 {
 407         struct drm_connector *connector = &vc4_hdmi->connector;
 408         struct edid *edid;
 409         int ret;
 410
 411         /*
 412          * NOTE: This function should really be called with
 413          * vc4_hdmi->mutex held, but doing so results in reentrancy
 414          * issues since cec_s_phys_addr_from_edid might call
 415          * .adap_enable, which leads to that funtion being called with
 416          * our mutex held.
 417          *
 418          * A similar situation occurs with vc4_hdmi_reset_link() that
 419          * will call into our KMS hooks if the scrambling was enabled.
 420          *
 421          * Concurrency isn't an issue at the moment since we don't share
 422          * any state with any of the other frameworks so we can ignore
 423          * the lock for now.
 424          */
 425
 426         if (status == connector_status_disconnected) {
 427                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 428                 return;
 429         }
 430
 431         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 432         if (!edid)
 433                 return;
 434
 435         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 436         kfree(edid);
 437
 438         for (;;) {
 439                 ret = vc4_hdmi_reset_link(connector, ctx);
 440                 if (ret == -EDEADLK) {
 441                         drm_modeset_backoff(ctx);
 442                         continue;
 443                 }
 444
 445                 break;
 446         }
 447 }
 448
 449 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 450                                          struct drm_modeset_acquire_ctx *ctx,
 451                                          bool force)
 452 {
 453         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 454         enum drm_connector_status status = connector_status_disconnected;
 455
 456         /*
 457          * NOTE: This function should really take vc4_hdmi->mutex, but
 458          * doing so results in reentrancy issues since
 459          * vc4_hdmi_handle_hotplug() can call into other functions that
 460          * would take the mutex while it's held here.
 461          *
 462          * Concurrency isn't an issue at the moment since we don't share
 463          * any state with any of the other frameworks so we can ignore
 464          * the lock for now.
 465          */
 466
 467         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 468
 469         if (vc4_hdmi->hpd_gpio) {
 470                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 471                         status = connector_status_connected;
 472         } else {
 473                 if (vc4_hdmi->variant->hp_detect &&
 474                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 475                         status = connector_status_connected;
 476         }
 477
 478         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 479         pm_runtime_put(&vc4_hdmi->pdev->dev);
 480
 481         return status;
 482 }
 483
 484 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 485 {
 486         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 487         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 488         int ret = 0;
 489         struct edid *edid;
 490
 491         /*
 492          * NOTE: This function should really take vc4_hdmi->mutex, but
 493          * doing so results in reentrancy issues since
 494          * cec_s_phys_addr_from_edid might call .adap_enable, which
 495          * leads to that funtion being called with our mutex held.
 496          *
 497          * Concurrency isn't an issue at the moment since we don't share
 498          * any state with any of the other frameworks so we can ignore
 499          * the lock for now.
 500          */
 501
 502         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 503         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 504         if (!edid)
 505                 return -ENODEV;
 506
 507         drm_connector_update_edid_property(connector, edid);
 508         ret = drm_add_edid_modes(connector, edid);
 509         kfree(edid);
 510
 511         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 512                 struct drm_device *drm = connector->dev;
 513                 const struct drm_display_mode *mode;
 514
 515                 list_for_each_entry(mode, &connector->probed_modes, head) {
 516                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 517                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 518                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 519                         }
 520                 }
 521         }
 522
 523         return ret;
 524 }
 525
 526 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 527                                            struct drm_atomic_state *state)
 528 {
 529         struct drm_connector_state *old_state =
 530                 drm_atomic_get_old_connector_state(state, connector);
 531         struct drm_connector_state *new_state =
 532                 drm_atomic_get_new_connector_state(state, connector);
 533         struct drm_crtc *crtc = new_state->crtc;
 534
 535         if (!crtc)
 536                 return 0;
 537
 538         if (old_state->colorspace != new_state->colorspace ||
 539             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 540                 struct drm_crtc_state *crtc_state;
 541
 542                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 543                 if (IS_ERR(crtc_state))
 544                         return PTR_ERR(crtc_state);
 545
 546                 crtc_state->mode_changed = true;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 553 {
 554         struct vc4_hdmi_connector_state *old_state =
 555                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 556         struct vc4_hdmi_connector_state *new_state =
 557                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 558
 559         if (connector->state)
 560                 __drm_atomic_helper_connector_destroy_state(connector->state);
 561
 562         kfree(old_state);
 563         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 564
 565         if (!new_state)
 566                 return;
 567
 568         new_state->base.max_bpc = 8;
 569         new_state->base.max_requested_bpc = 8;
 570         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 571         drm_atomic_helper_connector_tv_margins_reset(connector);
 572 }
 573
 574 static struct drm_connector_state *
 575 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 576 {
 577         struct drm_connector_state *conn_state = connector->state;
 578         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 579         struct vc4_hdmi_connector_state *new_state;
 580
 581         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 582         if (!new_state)
 583                 return NULL;
 584
 585         new_state->tmds_char_rate = vc4_state->tmds_char_rate;
 586         new_state->output_bpc = vc4_state->output_bpc;
 587         new_state->output_format = vc4_state->output_format;
 588         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 589
 590         return &new_state->base;
 591 }
 592
 593 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 594         .fill_modes = drm_helper_probe_single_connector_modes,
 595         .reset = vc4_hdmi_connector_reset,
 596         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 597         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 598 };
 599
 600 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 601         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 602         .get_modes = vc4_hdmi_connector_get_modes,
 603         .atomic_check = vc4_hdmi_connector_atomic_check,
 604 };
 605
 606 static int vc4_hdmi_connector_init(struct drm_device *dev,
 607                                    struct vc4_hdmi *vc4_hdmi)
 608 {
 609         struct drm_connector *connector = &vc4_hdmi->connector;
 610         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 611         int ret;
 612
 613         ret = drmm_connector_init(dev, connector,
 614                                   &vc4_hdmi_connector_funcs,
 615                                   DRM_MODE_CONNECTOR_HDMIA,
 616                                   vc4_hdmi->ddc);
 617         if (ret)
 618                 return ret;
 619
 620         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 621
 622         /*
 623          * Some of the properties below require access to state, like bpc.
 624          * Allocate some default initial connector state with our reset helper.
 625          */
 626         if (connector->funcs->reset)
 627                 connector->funcs->reset(connector);
 628
 629         /* Create and attach TV margin props to this connector. */
 630         ret = drm_mode_create_tv_margin_properties(dev);
 631         if (ret)
 632                 return ret;
 633
 634         ret = drm_mode_create_hdmi_colorspace_property(connector);
 635         if (ret)
 636                 return ret;
 637
 638         drm_connector_attach_colorspace_property(connector);
 639         drm_connector_attach_tv_margin_properties(connector);
 640         drm_connector_attach_max_bpc_property(connector, 8, 12);
 641
 642         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 643                              DRM_CONNECTOR_POLL_DISCONNECT);
 644
 645         connector->interlace_allowed = 1;
 646         connector->doublescan_allowed = 0;
 647         connector->stereo_allowed = 1;
 648
 649         if (vc4_hdmi->variant->supports_hdr)
 650                 drm_connector_attach_hdr_output_metadata_property(connector);
 651
 652         drm_connector_attach_encoder(connector, encoder);
 653
 654         return 0;
 655 }
 656
 657 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 658                                 enum hdmi_infoframe_type type,
 659                                 bool poll)
 660 {
 661         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 662         struct drm_device *drm = vc4_hdmi->connector.dev;
 663         u32 packet_id = type - 0x80;
 664         unsigned long flags;
 665         int ret = 0;
 666         int idx;
 667
 668         if (!drm_dev_enter(drm, &idx))
 669                 return -ENODEV;
 670
 671         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 672         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 673                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 674         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 675
 676         if (poll) {
 677                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 678                                  BIT(packet_id)), 100);
 679         }
 680
 681         drm_dev_exit(idx);
 682         return ret;
 683 }
 684
 685 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 686                                      union hdmi_infoframe *frame)
 687 {
 688         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 689         struct drm_device *drm = vc4_hdmi->connector.dev;
 690         u32 packet_id = frame->any.type - 0x80;
 691         const struct vc4_hdmi_register *ram_packet_start =
 692                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 693         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 694         u32 packet_reg_next = ram_packet_start->offset +
 695                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 696         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 697                                                        ram_packet_start->reg);
 698         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 699         unsigned long flags;
 700         ssize_t len, i;
 701         int ret;
 702         int idx;
 703
 704         if (!drm_dev_enter(drm, &idx))
 705                 return;
 706
 707         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 708                     VC4_HDMI_RAM_PACKET_ENABLE),
 709                   "Packet RAM has to be on to store the packet.");
 710
 711         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 712         if (len < 0)
 713                 goto out;
 714
 715         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 716         if (ret) {
 717                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 718                 goto out;
 719         }
 720
 721         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 722
 723         for (i = 0; i < len; i += 7) {
 724                 writel(buffer[i + 0] << 0 |
 725                        buffer[i + 1] << 8 |
 726                        buffer[i + 2] << 16,
 727                        base + packet_reg);
 728                 packet_reg += 4;
 729
 730                 writel(buffer[i + 3] << 0 |
 731                        buffer[i + 4] << 8 |
 732                        buffer[i + 5] << 16 |
 733                        buffer[i + 6] << 24,
 734                        base + packet_reg);
 735                 packet_reg += 4;
 736         }
 737
 738         /*
 739          * clear remainder of packet ram as it's included in the
 740          * infoframe and triggers a checksum error on hdmi analyser
 741          */
 742         for (; packet_reg < packet_reg_next; packet_reg += 4)
 743                 writel(0, base + packet_reg);
 744
 745         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 746                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 747
 748         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 749
 750         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 751                         BIT(packet_id)), 100);
 752         if (ret)
 753                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 754
 755 out:
 756         drm_dev_exit(idx);
 757 }
 758
 759 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 760                                               enum vc4_hdmi_output_format fmt)
 761 {
 762         switch (fmt) {
 763         case VC4_HDMI_OUTPUT_RGB:
 764                 frame->colorspace = HDMI_COLORSPACE_RGB;
 765                 break;
 766
 767         case VC4_HDMI_OUTPUT_YUV420:
 768                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 769                 break;
 770
 771         case VC4_HDMI_OUTPUT_YUV422:
 772                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 773                 break;
 774
 775         case VC4_HDMI_OUTPUT_YUV444:
 776                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 777                 break;
 778
 779         default:
 780                 break;
 781         }
 782 }
 783
 784 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 785 {
 786         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 787         struct drm_connector *connector = &vc4_hdmi->connector;
 788         struct drm_connector_state *cstate = connector->state;
 789         struct vc4_hdmi_connector_state *vc4_state =
 790                 conn_state_to_vc4_hdmi_conn_state(cstate);
 791         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 792         union hdmi_infoframe frame;
 793         int ret;
 794
 795         lockdep_assert_held(&vc4_hdmi->mutex);
 796
 797         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 798                                                        connector, mode);
 799         if (ret < 0) {
 800                 DRM_ERROR("couldn't fill AVI infoframe\n");
 801                 return;
 802         }
 803
 804         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 805                                            connector, mode,
 806                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 807                                            HDMI_QUANTIZATION_RANGE_FULL :
 808                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 809         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 810         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 811         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 812
 813         vc4_hdmi_write_infoframe(encoder, &frame);
 814 }
 815
 816 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 817 {
 818         union hdmi_infoframe frame;
 819         int ret;
 820
 821         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 822         if (ret < 0) {
 823                 DRM_ERROR("couldn't fill SPD infoframe\n");
 824                 return;
 825         }
 826
 827         frame.spd.sdi = HDMI_SPD_SDI_PC;
 828
 829         vc4_hdmi_write_infoframe(encoder, &frame);
 830 }
 831
 832 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 833 {
 834         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 835         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 836         union hdmi_infoframe frame;
 837
 838         memcpy(&frame.audio, audio, sizeof(*audio));
 839
 840         if (vc4_hdmi->packet_ram_enabled)
 841                 vc4_hdmi_write_infoframe(encoder, &frame);
 842 }
 843
 844 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 845 {
 846         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 847         struct drm_connector *connector = &vc4_hdmi->connector;
 848         struct drm_connector_state *conn_state = connector->state;
 849         union hdmi_infoframe frame;
 850
 851         lockdep_assert_held(&vc4_hdmi->mutex);
 852
 853         if (!vc4_hdmi->variant->supports_hdr)
 854                 return;
 855
 856         if (!conn_state->hdr_output_metadata)
 857                 return;
 858
 859         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 860                 return;
 861
 862         vc4_hdmi_write_infoframe(encoder, &frame);
 863 }
 864
 865 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 866 {
 867         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 868
 869         lockdep_assert_held(&vc4_hdmi->mutex);
 870
 871         vc4_hdmi_set_avi_infoframe(encoder);
 872         vc4_hdmi_set_spd_infoframe(encoder);
 873         /*
 874          * If audio was streaming, then we need to reenabled the audio
 875          * infoframe here during encoder_enable.
 876          */
 877         if (vc4_hdmi->audio.streaming)
 878                 vc4_hdmi_set_audio_infoframe(encoder);
 879
 880         vc4_hdmi_set_hdr_infoframe(encoder);
 881 }
 882
 883 #define SCRAMBLING_POLLING_DELAY_MS     1000
 884
 885 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 886 {
 887         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 888         struct drm_connector *connector = &vc4_hdmi->connector;
 889         struct drm_device *drm = connector->dev;
 890         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 891         unsigned long flags;
 892         int idx;
 893
 894         lockdep_assert_held(&vc4_hdmi->mutex);
 895
 896         if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
 897                 return;
 898
 899         if (!vc4_hdmi_mode_needs_scrambling(mode,
 900                                             vc4_hdmi->output_bpc,
 901                                             vc4_hdmi->output_format))
 902                 return;
 903
 904         if (!drm_dev_enter(drm, &idx))
 905                 return;
 906
 907         drm_scdc_set_high_tmds_clock_ratio(connector, true);
 908         drm_scdc_set_scrambling(connector, true);
 909
 910         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 911         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 912                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 913         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 914
 915         drm_dev_exit(idx);
 916
 917         vc4_hdmi->scdc_enabled = true;
 918
 919         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 920                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 921 }
 922
 923 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 924 {
 925         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 926         struct drm_connector *connector = &vc4_hdmi->connector;
 927         struct drm_device *drm = connector->dev;
 928         unsigned long flags;
 929         int idx;
 930
 931         lockdep_assert_held(&vc4_hdmi->mutex);
 932
 933         if (!vc4_hdmi->scdc_enabled)
 934                 return;
 935
 936         vc4_hdmi->scdc_enabled = false;
 937
 938         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 939                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 940
 941         if (!drm_dev_enter(drm, &idx))
 942                 return;
 943
 944         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 945         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 946                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 947         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 948
 949         drm_scdc_set_scrambling(connector, false);
 950         drm_scdc_set_high_tmds_clock_ratio(connector, false);
 951
 952         drm_dev_exit(idx);
 953 }
 954
 955 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 956 {
 957         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 958                                                  struct vc4_hdmi,
 959                                                  scrambling_work);
 960         struct drm_connector *connector = &vc4_hdmi->connector;
 961
 962         if (drm_scdc_get_scrambling_status(connector))
 963                 return;
 964
 965         drm_scdc_set_high_tmds_clock_ratio(connector, true);
 966         drm_scdc_set_scrambling(connector, true);
 967
 968         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 969                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 970 }
 971
 972 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 973                                                struct drm_atomic_state *state)
 974 {
 975         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 976         struct drm_device *drm = vc4_hdmi->connector.dev;
 977         unsigned long flags;
 978         int idx;
 979
 980         mutex_lock(&vc4_hdmi->mutex);
 981
 982         vc4_hdmi->packet_ram_enabled = false;
 983
 984         if (!drm_dev_enter(drm, &idx))
 985                 goto out;
 986
 987         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 988
 989         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 990
 991         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 992
 993         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 994
 995         mdelay(1);
 996
 997         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 998         HDMI_WRITE(HDMI_VID_CTL,
 999                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
1000         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1001
1002         vc4_hdmi_disable_scrambling(encoder);
1003
1004         drm_dev_exit(idx);
1005
1006 out:
1007         mutex_unlock(&vc4_hdmi->mutex);
1008 }
1009
1010 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1011                                                  struct drm_atomic_state *state)
1012 {
1013         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1014         struct drm_device *drm = vc4_hdmi->connector.dev;
1015         unsigned long flags;
1016         int ret;
1017         int idx;
1018
1019         mutex_lock(&vc4_hdmi->mutex);
1020
1021         if (!drm_dev_enter(drm, &idx))
1022                 goto out;
1023
1024         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1025         HDMI_WRITE(HDMI_VID_CTL,
1026                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1027         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1028
1029         if (vc4_hdmi->variant->phy_disable)
1030                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1031
1032         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1033         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1034
1035         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1036         if (ret < 0)
1037                 DRM_ERROR("Failed to release power domain: %d\n", ret);
1038
1039         drm_dev_exit(idx);
1040
1041 out:
1042         mutex_unlock(&vc4_hdmi->mutex);
1043 }
1044
1045 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1046                                struct drm_connector_state *state,
1047                                const struct drm_display_mode *mode)
1048 {
1049         struct drm_device *drm = vc4_hdmi->connector.dev;
1050         unsigned long flags;
1051         u32 csc_ctl;
1052         int idx;
1053
1054         if (!drm_dev_enter(drm, &idx))
1055                 return;
1056
1057         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1058
1059         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1060                                 VC4_HD_CSC_CTL_ORDER);
1061
1062         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
1063                 /* CEA VICs other than #1 requre limited range RGB
1064                  * output unless overridden by an AVI infoframe.
1065                  * Apply a colorspace conversion to squash 0-255 down
1066                  * to 16-235.  The matrix here is:
1067                  *
1068                  * [ 0      0      0.8594 16]
1069                  * [ 0      0.8594 0      16]
1070                  * [ 0.8594 0      0      16]
1071                  * [ 0      0      0       1]
1072                  */
1073                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1074                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1075                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1076                                          VC4_HD_CSC_CTL_MODE);
1077
1078                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1079                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1080                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1081                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1082                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1083                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1084         }
1085
1086         /* The RGB order applies even when CSC is disabled. */
1087         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1088
1089         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1090
1091         drm_dev_exit(idx);
1092 }
1093
1094 /*
1095  * If we need to output Full Range RGB, then use the unity matrix
1096  *
1097  * [ 1      0      0      0]
1098  * [ 0      1      0      0]
1099  * [ 0      0      1      0]
1100  *
1101  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1102  */
1103 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
1104         { 0x2000, 0x0000, 0x0000, 0x0000 },
1105         { 0x0000, 0x2000, 0x0000, 0x0000 },
1106         { 0x0000, 0x0000, 0x2000, 0x0000 },
1107 };
1108
1109 /*
1110  * CEA VICs other than #1 require limited range RGB output unless
1111  * overridden by an AVI infoframe. Apply a colorspace conversion to
1112  * squash 0-255 down to 16-235. The matrix here is:
1113  *
1114  * [ 0.8594 0      0      16]
1115  * [ 0      0.8594 0      16]
1116  * [ 0      0      0.8594 16]
1117  *
1118  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1119  */
1120 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
1121         { 0x1b80, 0x0000, 0x0000, 0x0400 },
1122         { 0x0000, 0x1b80, 0x0000, 0x0400 },
1123         { 0x0000, 0x0000, 0x1b80, 0x0400 },
1124 };
1125
1126 /*
1127  * Conversion between Full Range RGB and Full Range YUV422 using the
1128  * BT.709 Colorspace
1129  *
1130  *
1131  * [  0.181906  0.611804  0.061758  16  ]
1132  * [ -0.100268 -0.337232  0.437500  128 ]
1133  * [  0.437500 -0.397386 -0.040114  128 ]
1134  *
1135  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1136  */
1137 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
1138         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1139         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1140         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1141 };
1142
1143 /*
1144  * Conversion between Full Range RGB and Full Range YUV444 using the
1145  * BT.709 Colorspace
1146  *
1147  * [ -0.100268 -0.337232  0.437500  128 ]
1148  * [  0.437500 -0.397386 -0.040114  128 ]
1149  * [  0.181906  0.611804  0.061758  16  ]
1150  *
1151  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1152  */
1153 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
1154         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1155         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1156         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1157 };
1158
1159 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1160                                     const u16 coeffs[3][4])
1161 {
1162         lockdep_assert_held(&vc4_hdmi->hw_lock);
1163
1164         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1165         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1166         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1167         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1168         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1169         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1170 }
1171
1172 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1173                                struct drm_connector_state *state,
1174                                const struct drm_display_mode *mode)
1175 {
1176         struct drm_device *drm = vc4_hdmi->connector.dev;
1177         struct vc4_hdmi_connector_state *vc4_state =
1178                 conn_state_to_vc4_hdmi_conn_state(state);
1179         unsigned long flags;
1180         u32 if_cfg = 0;
1181         u32 if_xbar = 0x543210;
1182         u32 csc_chan_ctl = 0;
1183         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1184                                                                VC5_MT_CP_CSC_CTL_MODE);
1185         int idx;
1186
1187         if (!drm_dev_enter(drm, &idx))
1188                 return;
1189
1190         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1191
1192         switch (vc4_state->output_format) {
1193         case VC4_HDMI_OUTPUT_YUV444:
1194                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1195                 break;
1196
1197         case VC4_HDMI_OUTPUT_YUV422:
1198                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1199                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1200                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1201                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1202
1203                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1204                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1205
1206                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1207                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1208
1209                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1210                 break;
1211
1212         case VC4_HDMI_OUTPUT_RGB:
1213                 if_xbar = 0x354021;
1214
1215                 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1216                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1217                 else
1218                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1219                 break;
1220
1221         default:
1222                 break;
1223         }
1224
1225         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1226         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1227         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1228         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1229
1230         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1231
1232         drm_dev_exit(idx);
1233 }
1234
1235 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1236                                  struct drm_connector_state *state,
1237                                  const struct drm_display_mode *mode)
1238 {
1239         struct drm_device *drm = vc4_hdmi->connector.dev;
1240         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1241         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1242         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1243         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1244         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1245                                    VC4_HDMI_VERTA_VSP) |
1246                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1247                                    VC4_HDMI_VERTA_VFP) |
1248                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1249         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1250                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1251                                    interlaced,
1252                                    VC4_HDMI_VERTB_VBP));
1253         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1254                           VC4_SET_FIELD(mode->crtc_vtotal -
1255                                         mode->crtc_vsync_end,
1256                                         VC4_HDMI_VERTB_VBP));
1257         unsigned long flags;
1258         u32 reg;
1259         int idx;
1260
1261         if (!drm_dev_enter(drm, &idx))
1262                 return;
1263
1264         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1265
1266         HDMI_WRITE(HDMI_HORZA,
1267                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1268                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1269                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1270                                  VC4_HDMI_HORZA_HAP));
1271
1272         HDMI_WRITE(HDMI_HORZB,
1273                    VC4_SET_FIELD((mode->htotal -
1274                                   mode->hsync_end) * pixel_rep,
1275                                  VC4_HDMI_HORZB_HBP) |
1276                    VC4_SET_FIELD((mode->hsync_end -
1277                                   mode->hsync_start) * pixel_rep,
1278                                  VC4_HDMI_HORZB_HSP) |
1279                    VC4_SET_FIELD((mode->hsync_start -
1280                                   mode->hdisplay) * pixel_rep,
1281                                  VC4_HDMI_HORZB_HFP));
1282
1283         HDMI_WRITE(HDMI_VERTA0, verta);
1284         HDMI_WRITE(HDMI_VERTA1, verta);
1285
1286         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1287         HDMI_WRITE(HDMI_VERTB1, vertb);
1288
1289         reg = HDMI_READ(HDMI_MISC_CONTROL);
1290         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1291         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1292         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1293
1294         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1295
1296         drm_dev_exit(idx);
1297 }
1298
1299 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1300                                  struct drm_connector_state *state,
1301                                  const struct drm_display_mode *mode)
1302 {
1303         struct drm_device *drm = vc4_hdmi->connector.dev;
1304         const struct vc4_hdmi_connector_state *vc4_state =
1305                 conn_state_to_vc4_hdmi_conn_state(state);
1306         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1307         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1308         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1309         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1310         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1311                                    VC5_HDMI_VERTA_VSP) |
1312                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1313                                    VC5_HDMI_VERTA_VFP) |
1314                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1315         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1316                                    VC5_HDMI_VERTB_VSPO) |
1317                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1318                                    interlaced,
1319                                    VC4_HDMI_VERTB_VBP));
1320         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1321                           VC4_SET_FIELD(mode->crtc_vtotal -
1322                                         mode->crtc_vsync_end,
1323                                         VC4_HDMI_VERTB_VBP));
1324         unsigned long flags;
1325         unsigned char gcp;
1326         u32 reg;
1327         int idx;
1328
1329         if (!drm_dev_enter(drm, &idx))
1330                 return;
1331
1332         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1333
1334         HDMI_WRITE(HDMI_HORZA,
1335                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1336                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1337                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1338                                  VC5_HDMI_HORZA_HAP) |
1339                    VC4_SET_FIELD((mode->hsync_start -
1340                                   mode->hdisplay) * pixel_rep,
1341                                  VC5_HDMI_HORZA_HFP));
1342
1343         HDMI_WRITE(HDMI_HORZB,
1344                    VC4_SET_FIELD((mode->htotal -
1345                                   mode->hsync_end) * pixel_rep,
1346                                  VC5_HDMI_HORZB_HBP) |
1347                    VC4_SET_FIELD((mode->hsync_end -
1348                                   mode->hsync_start) * pixel_rep,
1349                                  VC5_HDMI_HORZB_HSP));
1350
1351         HDMI_WRITE(HDMI_VERTA0, verta);
1352         HDMI_WRITE(HDMI_VERTA1, verta);
1353
1354         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1355         HDMI_WRITE(HDMI_VERTB1, vertb);
1356
1357         switch (vc4_state->output_bpc) {
1358         case 12:
1359                 gcp = 6;
1360                 break;
1361         case 10:
1362                 gcp = 5;
1363                 break;
1364         case 8:
1365         default:
1366                 gcp = 0;
1367                 break;
1368         }
1369
1370         /*
1371          * YCC422 is always 36-bit and not considered deep colour so
1372          * doesn't signal in GCP.
1373          */
1374         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1375                 gcp = 0;
1376         }
1377
1378         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1379         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1380                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1381         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1382                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1383         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1384
1385         reg = HDMI_READ(HDMI_GCP_WORD_1);
1386         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1387         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1388         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1389         reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1390         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1391
1392         reg = HDMI_READ(HDMI_GCP_CONFIG);
1393         reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1394         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1395
1396         reg = HDMI_READ(HDMI_MISC_CONTROL);
1397         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1398         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1399         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1400
1401         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1402
1403         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1404
1405         drm_dev_exit(idx);
1406 }
1407
1408 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1409 {
1410         struct drm_device *drm = vc4_hdmi->connector.dev;
1411         unsigned long flags;
1412         u32 drift;
1413         int ret;
1414         int idx;
1415
1416         if (!drm_dev_enter(drm, &idx))
1417                 return;
1418
1419         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1420
1421         drift = HDMI_READ(HDMI_FIFO_CTL);
1422         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1423
1424         HDMI_WRITE(HDMI_FIFO_CTL,
1425                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1426         HDMI_WRITE(HDMI_FIFO_CTL,
1427                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1428
1429         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1430
1431         usleep_range(1000, 1100);
1432
1433         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1434
1435         HDMI_WRITE(HDMI_FIFO_CTL,
1436                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1437         HDMI_WRITE(HDMI_FIFO_CTL,
1438                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1439
1440         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1441
1442         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1443                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1444         WARN_ONCE(ret, "Timeout waiting for "
1445                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1446
1447         drm_dev_exit(idx);
1448 }
1449
1450 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1451                                                 struct drm_atomic_state *state)
1452 {
1453         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1454         struct drm_device *drm = vc4_hdmi->connector.dev;
1455         struct drm_connector *connector = &vc4_hdmi->connector;
1456         struct drm_connector_state *conn_state =
1457                 drm_atomic_get_new_connector_state(state, connector);
1458         struct vc4_hdmi_connector_state *vc4_conn_state =
1459                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1460         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1461         unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1462         unsigned long bvb_rate, hsm_rate;
1463         unsigned long flags;
1464         int ret;
1465         int idx;
1466
1467         mutex_lock(&vc4_hdmi->mutex);
1468
1469         if (!drm_dev_enter(drm, &idx))
1470                 goto out;
1471
1472         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1473         if (ret < 0) {
1474                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1475                 goto err_dev_exit;
1476         }
1477
1478         /*
1479          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1480          * be faster than pixel clock, infinitesimally faster, tested in
1481          * simulation. Otherwise, exact value is unimportant for HDMI
1482          * operation." This conflicts with bcm2835's vc4 documentation, which
1483          * states HSM's clock has to be at least 108% of the pixel clock.
1484          *
1485          * Real life tests reveal that vc4's firmware statement holds up, and
1486          * users are able to use pixel clocks closer to HSM's, namely for
1487          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1488          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1489          * 162MHz.
1490          *
1491          * Additionally, the AXI clock needs to be at least 25% of
1492          * pixel clock, but HSM ends up being the limiting factor.
1493          */
1494         hsm_rate = max_t(unsigned long,
1495                          HSM_MIN_CLOCK_FREQ,
1496                          (tmds_char_rate / 100) * 101);
1497         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1498         if (ret) {
1499                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1500                 goto err_put_runtime_pm;
1501         }
1502
1503         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1504         if (ret) {
1505                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1506                 goto err_put_runtime_pm;
1507         }
1508
1509         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1510         if (ret) {
1511                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1512                 goto err_put_runtime_pm;
1513         }
1514
1515
1516         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1517
1518         if (tmds_char_rate > 297000000)
1519                 bvb_rate = 300000000;
1520         else if (tmds_char_rate > 148500000)
1521                 bvb_rate = 150000000;
1522         else
1523                 bvb_rate = 75000000;
1524
1525         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1526         if (ret) {
1527                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1528                 goto err_disable_pixel_clock;
1529         }
1530
1531         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1532         if (ret) {
1533                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1534                 goto err_disable_pixel_clock;
1535         }
1536
1537         if (vc4_hdmi->variant->phy_init)
1538                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1539
1540         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1541
1542         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1543                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1544                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1545                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1546
1547         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1548
1549         if (vc4_hdmi->variant->set_timings)
1550                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1551
1552         drm_dev_exit(idx);
1553
1554         mutex_unlock(&vc4_hdmi->mutex);
1555
1556         return;
1557
1558 err_disable_pixel_clock:
1559         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1560 err_put_runtime_pm:
1561         pm_runtime_put(&vc4_hdmi->pdev->dev);
1562 err_dev_exit:
1563         drm_dev_exit(idx);
1564 out:
1565         mutex_unlock(&vc4_hdmi->mutex);
1566         return;
1567 }
1568
1569 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1570                                              struct drm_atomic_state *state)
1571 {
1572         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1573         struct drm_device *drm = vc4_hdmi->connector.dev;
1574         struct drm_connector *connector = &vc4_hdmi->connector;
1575         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1576         struct drm_connector_state *conn_state =
1577                 drm_atomic_get_new_connector_state(state, connector);
1578         unsigned long flags;
1579         int idx;
1580
1581         mutex_lock(&vc4_hdmi->mutex);
1582
1583         if (!drm_dev_enter(drm, &idx))
1584                 goto out;
1585
1586         if (vc4_hdmi->variant->csc_setup)
1587                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1588
1589         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1590         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1591         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1592
1593         drm_dev_exit(idx);
1594
1595 out:
1596         mutex_unlock(&vc4_hdmi->mutex);
1597 }
1598
1599 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1600                                               struct drm_atomic_state *state)
1601 {
1602         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1603         struct drm_device *drm = vc4_hdmi->connector.dev;
1604         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1605         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1606         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1607         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1608         unsigned long flags;
1609         int ret;
1610         int idx;
1611
1612         mutex_lock(&vc4_hdmi->mutex);
1613
1614         if (!drm_dev_enter(drm, &idx))
1615                 goto out;
1616
1617         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1618
1619         HDMI_WRITE(HDMI_VID_CTL,
1620                    VC4_HD_VID_CTL_ENABLE |
1621                    VC4_HD_VID_CTL_CLRRGB |
1622                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1623                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1624                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1625                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1626
1627         HDMI_WRITE(HDMI_VID_CTL,
1628                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1629
1630         if (display->is_hdmi) {
1631                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1632                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1633                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1634
1635                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1636
1637                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1638                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1639                 WARN_ONCE(ret, "Timeout waiting for "
1640                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1641         } else {
1642                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1643                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1644                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1645                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1646                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1647                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1648
1649                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1650
1651                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1652                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1653                 WARN_ONCE(ret, "Timeout waiting for "
1654                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1655         }
1656
1657         if (display->is_hdmi) {
1658                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1659
1660                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1661                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1662
1663                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1664                            VC4_HDMI_RAM_PACKET_ENABLE);
1665
1666                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1667                 vc4_hdmi->packet_ram_enabled = true;
1668
1669                 vc4_hdmi_set_infoframes(encoder);
1670         }
1671
1672         vc4_hdmi_recenter_fifo(vc4_hdmi);
1673         vc4_hdmi_enable_scrambling(encoder);
1674
1675         drm_dev_exit(idx);
1676
1677 out:
1678         mutex_unlock(&vc4_hdmi->mutex);
1679 }
1680
1681 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1682                                              struct drm_crtc_state *crtc_state,
1683                                              struct drm_connector_state *conn_state)
1684 {
1685         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1686         struct vc4_hdmi_connector_state *vc4_state =
1687                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1688
1689         mutex_lock(&vc4_hdmi->mutex);
1690         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1691                       &crtc_state->adjusted_mode);
1692         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1693         vc4_hdmi->output_format = vc4_state->output_format;
1694         mutex_unlock(&vc4_hdmi->mutex);
1695 }
1696
1697 static bool
1698 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1699                                   const struct drm_display_info *info,
1700                                   const struct drm_display_mode *mode,
1701                                   unsigned int format, unsigned int bpc)
1702 {
1703         struct drm_device *dev = vc4_hdmi->connector.dev;
1704         u8 vic = drm_match_cea_mode(mode);
1705
1706         if (vic == 1 && bpc != 8) {
1707                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1708                 return false;
1709         }
1710
1711         if (!info->is_hdmi &&
1712             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1713                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1714                 return false;
1715         }
1716
1717         switch (format) {
1718         case VC4_HDMI_OUTPUT_RGB:
1719                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1720
1721                 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1722                         return false;
1723
1724                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1725                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1726                         return false;
1727                 }
1728
1729                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1730                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1731                         return false;
1732                 }
1733
1734                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1735
1736                 return true;
1737
1738         case VC4_HDMI_OUTPUT_YUV422:
1739                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1740
1741                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1742                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1743                         return false;
1744                 }
1745
1746                 if (bpc != 12) {
1747                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1748                         return false;
1749                 }
1750
1751                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1752
1753                 return true;
1754
1755         case VC4_HDMI_OUTPUT_YUV444:
1756                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1757
1758                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1759                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1760                         return false;
1761                 }
1762
1763                 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1764                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1765                         return false;
1766                 }
1767
1768                 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1769                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1770                         return false;
1771                 }
1772
1773                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1774
1775                 return true;
1776         }
1777
1778         return false;
1779 }
1780
1781 static enum drm_mode_status
1782 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1783                              const struct drm_display_mode *mode,
1784                              unsigned long long clock)
1785 {
1786         const struct drm_connector *connector = &vc4_hdmi->connector;
1787         const struct drm_display_info *info = &connector->display_info;
1788         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1789
1790         if (clock > vc4_hdmi->variant->max_pixel_clock)
1791                 return MODE_CLOCK_HIGH;
1792
1793         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1794                 return MODE_CLOCK_HIGH;
1795
1796         /* 4096x2160@60 is not reliable without overclocking core */
1797         if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1798             mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1799             drm_mode_vrefresh(mode) >= 50)
1800                 return MODE_CLOCK_HIGH;
1801
1802         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1803                 return MODE_CLOCK_HIGH;
1804
1805         return MODE_OK;
1806 }
1807
1808 static unsigned long long
1809 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1810                                     unsigned int bpc,
1811                                     enum vc4_hdmi_output_format fmt)
1812 {
1813         unsigned long long clock = mode->clock * 1000ULL;
1814
1815         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1816                 clock = clock * 2;
1817
1818         if (fmt == VC4_HDMI_OUTPUT_YUV422)
1819                 bpc = 8;
1820
1821         clock = clock * bpc;
1822         do_div(clock, 8);
1823
1824         return clock;
1825 }
1826
1827 static int
1828 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1829                                struct vc4_hdmi_connector_state *vc4_state,
1830                                const struct drm_display_mode *mode,
1831                                unsigned int bpc, unsigned int fmt)
1832 {
1833         unsigned long long clock;
1834
1835         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1836         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
1837                 return -EINVAL;
1838
1839         vc4_state->tmds_char_rate = clock;
1840
1841         return 0;
1842 }
1843
1844 static int
1845 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1846                                 struct vc4_hdmi_connector_state *vc4_state,
1847                                 const struct drm_display_mode *mode,
1848                                 unsigned int bpc)
1849 {
1850         struct drm_device *dev = vc4_hdmi->connector.dev;
1851         const struct drm_connector *connector = &vc4_hdmi->connector;
1852         const struct drm_display_info *info = &connector->display_info;
1853         unsigned int format;
1854
1855         drm_dbg(dev, "Trying with an RGB output\n");
1856
1857         format = VC4_HDMI_OUTPUT_RGB;
1858         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1859                 int ret;
1860
1861                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1862                                                      mode, bpc, format);
1863                 if (!ret) {
1864                         vc4_state->output_format = format;
1865                         return 0;
1866                 }
1867         }
1868
1869         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1870
1871         format = VC4_HDMI_OUTPUT_YUV422;
1872         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1873                 int ret;
1874
1875                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1876                                                      mode, bpc, format);
1877                 if (!ret) {
1878                         vc4_state->output_format = format;
1879                         return 0;
1880                 }
1881         }
1882
1883         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1884
1885         return -EINVAL;
1886 }
1887
1888 static int
1889 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1890                                 struct vc4_hdmi_connector_state *vc4_state,
1891                                 const struct drm_display_mode *mode)
1892 {
1893         struct drm_device *dev = vc4_hdmi->connector.dev;
1894         struct drm_connector_state *conn_state = &vc4_state->base;
1895         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1896         unsigned int bpc;
1897         int ret;
1898
1899         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1900                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1901
1902                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1903                                                       mode, bpc);
1904                 if (ret)
1905                         continue;
1906
1907                 vc4_state->output_bpc = bpc;
1908
1909                 drm_dbg(dev,
1910                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1911                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1912                         vc4_state->output_bpc,
1913                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
1914                         vc4_state->tmds_char_rate);
1915
1916                 break;
1917         }
1918
1919         return ret;
1920 }
1921
1922 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1923 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1924
1925 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1926                                          struct drm_crtc_state *crtc_state,
1927                                          struct drm_connector_state *conn_state)
1928 {
1929         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1930         struct drm_connector *connector = &vc4_hdmi->connector;
1931         struct drm_connector_state *old_conn_state =
1932                 drm_atomic_get_old_connector_state(conn_state->state, connector);
1933         struct vc4_hdmi_connector_state *old_vc4_state =
1934                 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1935         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1936         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1937         unsigned long long tmds_char_rate = mode->clock * 1000;
1938         unsigned long long tmds_bit_rate;
1939         int ret;
1940
1941         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1942                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1943                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1944                          * working.
1945                          * A generic solution for all modes with odd horizontal
1946                          * timing values seems impossible based on trying to
1947                          * solve it for 1366x768 monitors.
1948                          */
1949                         if ((mode->hsync_start - mode->hdisplay) & 1)
1950                                 mode->hsync_start--;
1951                         if ((mode->hsync_end - mode->hsync_start) & 1)
1952                                 mode->hsync_end--;
1953                 }
1954
1955                 /* Now check whether we still have odd values remaining */
1956                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1957                     (mode->hsync_end % 2) || (mode->htotal % 2))
1958                         return -EINVAL;
1959         }
1960
1961         /*
1962          * The 1440p@60 pixel rate is in the same range than the first
1963          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1964          * bandwidth). Slightly lower the frequency to bring it out of
1965          * the WiFi range.
1966          */
1967         tmds_bit_rate = tmds_char_rate * 10;
1968         if (vc4_hdmi->disable_wifi_frequencies &&
1969             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1970              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1971                 mode->clock = 238560;
1972                 tmds_char_rate = mode->clock * 1000;
1973         }
1974
1975         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1976         if (ret)
1977                 return ret;
1978
1979         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1980         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1981             vc4_state->output_format != old_vc4_state->output_format)
1982                 crtc_state->mode_changed = true;
1983
1984         return 0;
1985 }
1986
1987 static enum drm_mode_status
1988 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1989                             const struct drm_display_mode *mode)
1990 {
1991         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1992
1993         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1994             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1995             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1996              (mode->hsync_end % 2) || (mode->htotal % 2)))
1997                 return MODE_H_ILLEGAL;
1998
1999         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2000 }
2001
2002 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2003         .atomic_check = vc4_hdmi_encoder_atomic_check,
2004         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2005         .mode_valid = vc4_hdmi_encoder_mode_valid,
2006 };
2007
2008 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2009 {
2010         struct drm_device *drm = encoder->dev;
2011         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2012         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2013
2014         drm_debugfs_add_file(drm, variant->debugfs_name,
2015                              vc4_hdmi_debugfs_regs, vc4_hdmi);
2016
2017         return 0;
2018 }
2019
2020 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2021         .late_register = vc4_hdmi_late_register,
2022 };
2023
2024 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2025 {
2026         int i;
2027         u32 channel_map = 0;
2028
2029         for (i = 0; i < 8; i++) {
2030                 if (channel_mask & BIT(i))
2031                         channel_map |= i << (3 * i);
2032         }
2033         return channel_map;
2034 }
2035
2036 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2037 {
2038         int i;
2039         u32 channel_map = 0;
2040
2041         for (i = 0; i < 8; i++) {
2042                 if (channel_mask & BIT(i))
2043                         channel_map |= i << (4 * i);
2044         }
2045         return channel_map;
2046 }
2047
2048 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2049 {
2050         struct drm_device *drm = vc4_hdmi->connector.dev;
2051         unsigned long flags;
2052         u32 hotplug;
2053         int idx;
2054
2055         if (!drm_dev_enter(drm, &idx))
2056                 return false;
2057
2058         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2059         hotplug = HDMI_READ(HDMI_HOTPLUG);
2060         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2061
2062         drm_dev_exit(idx);
2063
2064         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2065 }
2066
2067 /* HDMI audio codec callbacks */
2068 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2069                                          unsigned int samplerate)
2070 {
2071         struct drm_device *drm = vc4_hdmi->connector.dev;
2072         u32 hsm_clock;
2073         unsigned long flags;
2074         unsigned long n, m;
2075         int idx;
2076
2077         if (!drm_dev_enter(drm, &idx))
2078                 return;
2079
2080         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2081         rational_best_approximation(hsm_clock, samplerate,
2082                                     VC4_HD_MAI_SMP_N_MASK >>
2083                                     VC4_HD_MAI_SMP_N_SHIFT,
2084                                     (VC4_HD_MAI_SMP_M_MASK >>
2085                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
2086                                     &n, &m);
2087
2088         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2089         HDMI_WRITE(HDMI_MAI_SMP,
2090                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2091                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2092         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2093
2094         drm_dev_exit(idx);
2095 }
2096
2097 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2098 {
2099         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2100         u32 n, cts;
2101         u64 tmp;
2102
2103         lockdep_assert_held(&vc4_hdmi->mutex);
2104         lockdep_assert_held(&vc4_hdmi->hw_lock);
2105
2106         n = 128 * samplerate / 1000;
2107         tmp = (u64)(mode->clock * 1000) * n;
2108         do_div(tmp, 128 * samplerate);
2109         cts = tmp;
2110
2111         HDMI_WRITE(HDMI_CRP_CFG,
2112                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2113                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2114
2115         /*
2116          * We could get slightly more accurate clocks in some cases by
2117          * providing a CTS_1 value.  The two CTS values are alternated
2118          * between based on the period fields
2119          */
2120         HDMI_WRITE(HDMI_CTS_0, cts);
2121         HDMI_WRITE(HDMI_CTS_1, cts);
2122 }
2123
2124 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2125 {
2126         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2127
2128         return snd_soc_card_get_drvdata(card);
2129 }
2130
2131 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2132 {
2133         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2134
2135         lockdep_assert_held(&vc4_hdmi->mutex);
2136
2137         /*
2138          * If the encoder is currently in DVI mode, treat the codec DAI
2139          * as missing.
2140          */
2141         if (!display->is_hdmi)
2142                 return false;
2143
2144         return true;
2145 }
2146
2147 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2148 {
2149         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2150         struct drm_device *drm = vc4_hdmi->connector.dev;
2151         unsigned long flags;
2152         int ret = 0;
2153         int idx;
2154
2155         mutex_lock(&vc4_hdmi->mutex);
2156
2157         if (!drm_dev_enter(drm, &idx)) {
2158                 ret = -ENODEV;
2159                 goto out;
2160         }
2161
2162         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2163                 ret = -ENODEV;
2164                 goto out_dev_exit;
2165         }
2166
2167         vc4_hdmi->audio.streaming = true;
2168
2169         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2170         HDMI_WRITE(HDMI_MAI_CTL,
2171                    VC4_HD_MAI_CTL_RESET |
2172                    VC4_HD_MAI_CTL_FLUSH |
2173                    VC4_HD_MAI_CTL_DLATE |
2174                    VC4_HD_MAI_CTL_ERRORE |
2175                    VC4_HD_MAI_CTL_ERRORF);
2176         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2177
2178         if (vc4_hdmi->variant->phy_rng_enable)
2179                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2180
2181 out_dev_exit:
2182         drm_dev_exit(idx);
2183 out:
2184         mutex_unlock(&vc4_hdmi->mutex);
2185
2186         return ret;
2187 }
2188
2189 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2190 {
2191         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2192         struct device *dev = &vc4_hdmi->pdev->dev;
2193         unsigned long flags;
2194         int ret;
2195
2196         lockdep_assert_held(&vc4_hdmi->mutex);
2197
2198         vc4_hdmi->audio.streaming = false;
2199         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2200         if (ret)
2201                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2202
2203         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2204
2205         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2206         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2207         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2208
2209         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2210 }
2211
2212 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2213 {
2214         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2215         struct drm_device *drm = vc4_hdmi->connector.dev;
2216         unsigned long flags;
2217         int idx;
2218
2219         mutex_lock(&vc4_hdmi->mutex);
2220
2221         if (!drm_dev_enter(drm, &idx))
2222                 goto out;
2223
2224         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2225
2226         HDMI_WRITE(HDMI_MAI_CTL,
2227                    VC4_HD_MAI_CTL_DLATE |
2228                    VC4_HD_MAI_CTL_ERRORE |
2229                    VC4_HD_MAI_CTL_ERRORF);
2230
2231         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2232
2233         if (vc4_hdmi->variant->phy_rng_disable)
2234                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2235
2236         vc4_hdmi->audio.streaming = false;
2237         vc4_hdmi_audio_reset(vc4_hdmi);
2238
2239         drm_dev_exit(idx);
2240
2241 out:
2242         mutex_unlock(&vc4_hdmi->mutex);
2243 }
2244
2245 static int sample_rate_to_mai_fmt(int samplerate)
2246 {
2247         switch (samplerate) {
2248         case 8000:
2249                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2250         case 11025:
2251                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2252         case 12000:
2253                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2254         case 16000:
2255                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2256         case 22050:
2257                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2258         case 24000:
2259                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2260         case 32000:
2261                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2262         case 44100:
2263                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2264         case 48000:
2265                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2266         case 64000:
2267                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2268         case 88200:
2269                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2270         case 96000:
2271                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2272         case 128000:
2273                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2274         case 176400:
2275                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2276         case 192000:
2277                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2278         default:
2279                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2280         }
2281 }
2282
2283 /* HDMI audio codec callbacks */
2284 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2285                                   struct hdmi_codec_daifmt *daifmt,
2286                                   struct hdmi_codec_params *params)
2287 {
2288         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2289         struct drm_device *drm = vc4_hdmi->connector.dev;
2290         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2291         unsigned int sample_rate = params->sample_rate;
2292         unsigned int channels = params->channels;
2293         unsigned long flags;
2294         u32 audio_packet_config, channel_mask;
2295         u32 channel_map;
2296         u32 mai_audio_format;
2297         u32 mai_sample_rate;
2298         int ret = 0;
2299         int idx;
2300
2301         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2302                 sample_rate, params->sample_width, channels);
2303
2304         mutex_lock(&vc4_hdmi->mutex);
2305
2306         if (!drm_dev_enter(drm, &idx)) {
2307                 ret = -ENODEV;
2308                 goto out;
2309         }
2310
2311         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2312                 ret = -EINVAL;
2313                 goto out_dev_exit;
2314         }
2315
2316         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2317
2318         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2319         HDMI_WRITE(HDMI_MAI_CTL,
2320                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2321                    VC4_HD_MAI_CTL_WHOLSMP |
2322                    VC4_HD_MAI_CTL_CHALIGN |
2323                    VC4_HD_MAI_CTL_ENABLE);
2324
2325         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2326         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2327             params->channels == 8)
2328                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2329         else
2330                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2331         HDMI_WRITE(HDMI_MAI_FMT,
2332                    VC4_SET_FIELD(mai_sample_rate,
2333                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2334                    VC4_SET_FIELD(mai_audio_format,
2335                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2336
2337         /* The B frame identifier should match the value used by alsa-lib (8) */
2338         audio_packet_config =
2339                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2340                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2341                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2342
2343         channel_mask = GENMASK(channels - 1, 0);
2344         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2345                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2346
2347         /* Set the MAI threshold */
2348         HDMI_WRITE(HDMI_MAI_THR,
2349                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2350                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2351                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2352                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2353
2354         HDMI_WRITE(HDMI_MAI_CONFIG,
2355                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2356                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2357                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2358
2359         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2360         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2361         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2362
2363         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2364
2365         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2366
2367         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2368         vc4_hdmi_set_audio_infoframe(encoder);
2369
2370 out_dev_exit:
2371         drm_dev_exit(idx);
2372 out:
2373         mutex_unlock(&vc4_hdmi->mutex);
2374
2375         return ret;
2376 }
2377
2378 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2379         .name = "vc4-hdmi-cpu-dai-component",
2380         .legacy_dai_naming = 1,
2381 };
2382
2383 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2384 {
2385         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2386
2387         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2388
2389         return 0;
2390 }
2391
2392 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2393         .name = "vc4-hdmi-cpu-dai",
2394         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2395         .playback = {
2396                 .stream_name = "Playback",
2397                 .channels_min = 1,
2398                 .channels_max = 8,
2399                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2400                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2401                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2402                          SNDRV_PCM_RATE_192000,
2403                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2404         },
2405 };
2406
2407 static const struct snd_dmaengine_pcm_config pcm_conf = {
2408         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2409         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2410 };
2411
2412 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2413                                   uint8_t *buf, size_t len)
2414 {
2415         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2416         struct drm_connector *connector = &vc4_hdmi->connector;
2417
2418         mutex_lock(&vc4_hdmi->mutex);
2419         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2420         mutex_unlock(&vc4_hdmi->mutex);
2421
2422         return 0;
2423 }
2424
2425 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2426         .get_eld = vc4_hdmi_audio_get_eld,
2427         .prepare = vc4_hdmi_audio_prepare,
2428         .audio_shutdown = vc4_hdmi_audio_shutdown,
2429         .audio_startup = vc4_hdmi_audio_startup,
2430 };
2431
2432 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2433         .ops = &vc4_hdmi_codec_ops,
2434         .max_i2s_channels = 8,
2435         .i2s = 1,
2436 };
2437
2438 static void vc4_hdmi_audio_codec_release(void *ptr)
2439 {
2440         struct vc4_hdmi *vc4_hdmi = ptr;
2441
2442         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2443         vc4_hdmi->audio.codec_pdev = NULL;
2444 }
2445
2446 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2447 {
2448         const struct vc4_hdmi_register *mai_data =
2449                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2450         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2451         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2452         struct device *dev = &vc4_hdmi->pdev->dev;
2453         struct platform_device *codec_pdev;
2454         const __be32 *addr;
2455         int index, len;
2456         int ret;
2457
2458         /*
2459          * ASoC makes it a bit hard to retrieve a pointer to the
2460          * vc4_hdmi structure. Registering the card will overwrite our
2461          * device drvdata with a pointer to the snd_soc_card structure,
2462          * which can then be used to retrieve whatever drvdata we want
2463          * to associate.
2464          *
2465          * However, that doesn't fly in the case where we wouldn't
2466          * register an ASoC card (because of an old DT that is missing
2467          * the dmas properties for example), then the card isn't
2468          * registered and the device drvdata wouldn't be set.
2469          *
2470          * We can deal with both cases by making sure a snd_soc_card
2471          * pointer and a vc4_hdmi structure are pointing to the same
2472          * memory address, so we can treat them indistinctly without any
2473          * issue.
2474          */
2475         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2476         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2477
2478         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2479                 dev_warn(dev,
2480                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2481                 return 0;
2482         }
2483
2484         if (mai_data->reg != VC4_HD) {
2485                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2486                 return -EINVAL;
2487         }
2488
2489         /*
2490          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2491          * the bus address specified in the DT, because the physical address
2492          * (the one returned by platform_get_resource()) is not appropriate
2493          * for DMA transfers.
2494          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2495          */
2496         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2497         /* Before BCM2711, we don't have a named register range */
2498         if (index < 0)
2499                 index = 1;
2500
2501         addr = of_get_address(dev->of_node, index, NULL, NULL);
2502
2503         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2504         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2505         vc4_hdmi->audio.dma_data.maxburst = 2;
2506
2507         /*
2508          * NOTE: Strictly speaking, we should probably use a DRM-managed
2509          * registration there to avoid removing all the audio components
2510          * by the time the driver doesn't have any user anymore.
2511          *
2512          * However, the ASoC core uses a number of devm_kzalloc calls
2513          * when registering, even when using non-device-managed
2514          * functions (such as in snd_soc_register_component()).
2515          *
2516          * If we call snd_soc_unregister_component() in a DRM-managed
2517          * action, the device-managed actions have already been executed
2518          * and thus we would access memory that has been freed.
2519          *
2520          * Using device-managed hooks here probably leaves us open to a
2521          * bunch of issues if userspace still has a handle on the ALSA
2522          * device when the device is removed. However, this is mitigated
2523          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2524          * path to prevent the access to the device resources if it
2525          * isn't there anymore.
2526          *
2527          * Then, the vc4_hdmi structure is DRM-managed and thus only
2528          * freed whenever the last user has closed the DRM device file.
2529          * It should thus outlive ALSA in most situations.
2530          */
2531         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2532         if (ret) {
2533                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2534                 return ret;
2535         }
2536
2537         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2538                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2539         if (ret) {
2540                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2541                 return ret;
2542         }
2543
2544         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2545                                                    PLATFORM_DEVID_AUTO,
2546                                                    &vc4_hdmi_codec_pdata,
2547                                                    sizeof(vc4_hdmi_codec_pdata));
2548         if (IS_ERR(codec_pdev)) {
2549                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2550                 return PTR_ERR(codec_pdev);
2551         }
2552         vc4_hdmi->audio.codec_pdev = codec_pdev;
2553
2554         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2555         if (ret)
2556                 return ret;
2557
2558         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2559         dai_link->codecs        = &vc4_hdmi->audio.codec;
2560         dai_link->platforms     = &vc4_hdmi->audio.platform;
2561
2562         dai_link->num_cpus      = 1;
2563         dai_link->num_codecs    = 1;
2564         dai_link->num_platforms = 1;
2565
2566         dai_link->name = "MAI";
2567         dai_link->stream_name = "MAI PCM";
2568         dai_link->codecs->dai_name = "i2s-hifi";
2569         dai_link->cpus->dai_name = dev_name(dev);
2570         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2571         dai_link->platforms->name = dev_name(dev);
2572
2573         card->dai_link = dai_link;
2574         card->num_links = 1;
2575         card->name = vc4_hdmi->variant->card_name;
2576         card->driver_name = "vc4-hdmi";
2577         card->dev = dev;
2578         card->owner = THIS_MODULE;
2579
2580         /*
2581          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2582          * stores a pointer to the snd card object in dev->driver_data. This
2583          * means we cannot use it for something else. The hdmi back-pointer is
2584          * now stored in card->drvdata and should be retrieved with
2585          * snd_soc_card_get_drvdata() if needed.
2586          */
2587         snd_soc_card_set_drvdata(card, vc4_hdmi);
2588         ret = devm_snd_soc_register_card(dev, card);
2589         if (ret)
2590                 dev_err_probe(dev, ret, "Could not register sound card\n");
2591
2592         return ret;
2593
2594 }
2595
2596 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2597 {
2598         struct vc4_hdmi *vc4_hdmi = priv;
2599         struct drm_connector *connector = &vc4_hdmi->connector;
2600         struct drm_device *dev = connector->dev;
2601
2602         if (dev && dev->registered)
2603                 drm_connector_helper_hpd_irq_event(connector);
2604
2605         return IRQ_HANDLED;
2606 }
2607
2608 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2609 {
2610         struct drm_connector *connector = &vc4_hdmi->connector;
2611         struct platform_device *pdev = vc4_hdmi->pdev;
2612         int ret;
2613
2614         if (vc4_hdmi->variant->external_irq_controller) {
2615                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2616                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2617
2618                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2619                                                 NULL,
2620                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2621                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2622                 if (ret)
2623                         return ret;
2624
2625                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2626                                                 NULL,
2627                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2628                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2629                 if (ret)
2630                         return ret;
2631
2632                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2633         }
2634
2635         return 0;
2636 }
2637
2638 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2639 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2640 {
2641         struct vc4_hdmi *vc4_hdmi = priv;
2642
2643         if (vc4_hdmi->cec_rx_msg.len)
2644                 cec_received_msg(vc4_hdmi->cec_adap,
2645                                  &vc4_hdmi->cec_rx_msg);
2646
2647         return IRQ_HANDLED;
2648 }
2649
2650 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2651 {
2652         struct vc4_hdmi *vc4_hdmi = priv;
2653
2654         if (vc4_hdmi->cec_tx_ok) {
2655                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2656                                   0, 0, 0, 0);
2657         } else {
2658                 /*
2659                  * This CEC implementation makes 1 retry, so if we
2660                  * get a NACK, then that means it made 2 attempts.
2661                  */
2662                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2663                                   0, 2, 0, 0);
2664         }
2665         return IRQ_HANDLED;
2666 }
2667
2668 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2669 {
2670         struct vc4_hdmi *vc4_hdmi = priv;
2671         irqreturn_t ret;
2672
2673         if (vc4_hdmi->cec_irq_was_rx)
2674                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2675         else
2676                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2677
2678         return ret;
2679 }
2680
2681 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2682 {
2683         struct drm_device *dev = vc4_hdmi->connector.dev;
2684         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2685         unsigned int i;
2686
2687         lockdep_assert_held(&vc4_hdmi->hw_lock);
2688
2689         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2690                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2691
2692         if (msg->len > 16) {
2693                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2694                 return;
2695         }
2696
2697         for (i = 0; i < msg->len; i += 4) {
2698                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2699
2700                 msg->msg[i] = val & 0xff;
2701                 msg->msg[i + 1] = (val >> 8) & 0xff;
2702                 msg->msg[i + 2] = (val >> 16) & 0xff;
2703                 msg->msg[i + 3] = (val >> 24) & 0xff;
2704         }
2705 }
2706
2707 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2708 {
2709         u32 cntrl1;
2710
2711         /*
2712          * We don't need to protect the register access using
2713          * drm_dev_enter() there because the interrupt handler lifetime
2714          * is tied to the device itself, and not to the DRM device.
2715          *
2716          * So when the device will be gone, one of the first thing we
2717          * will be doing will be to unregister the interrupt handler,
2718          * and then unregister the DRM device. drm_dev_enter() would
2719          * thus always succeed if we are here.
2720          */
2721
2722         lockdep_assert_held(&vc4_hdmi->hw_lock);
2723
2724         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2725         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2726         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2727         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2728
2729         return IRQ_WAKE_THREAD;
2730 }
2731
2732 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2733 {
2734         struct vc4_hdmi *vc4_hdmi = priv;
2735         irqreturn_t ret;
2736
2737         spin_lock(&vc4_hdmi->hw_lock);
2738         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2739         spin_unlock(&vc4_hdmi->hw_lock);
2740
2741         return ret;
2742 }
2743
2744 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2745 {
2746         u32 cntrl1;
2747
2748         lockdep_assert_held(&vc4_hdmi->hw_lock);
2749
2750         /*
2751          * We don't need to protect the register access using
2752          * drm_dev_enter() there because the interrupt handler lifetime
2753          * is tied to the device itself, and not to the DRM device.
2754          *
2755          * So when the device will be gone, one of the first thing we
2756          * will be doing will be to unregister the interrupt handler,
2757          * and then unregister the DRM device. drm_dev_enter() would
2758          * thus always succeed if we are here.
2759          */
2760
2761         vc4_hdmi->cec_rx_msg.len = 0;
2762         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2763         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2764         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2765         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2766         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2767
2768         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2769
2770         return IRQ_WAKE_THREAD;
2771 }
2772
2773 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2774 {
2775         struct vc4_hdmi *vc4_hdmi = priv;
2776         irqreturn_t ret;
2777
2778         spin_lock(&vc4_hdmi->hw_lock);
2779         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2780         spin_unlock(&vc4_hdmi->hw_lock);
2781
2782         return ret;
2783 }
2784
2785 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2786 {
2787         struct vc4_hdmi *vc4_hdmi = priv;
2788         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2789         irqreturn_t ret;
2790         u32 cntrl5;
2791
2792         /*
2793          * We don't need to protect the register access using
2794          * drm_dev_enter() there because the interrupt handler lifetime
2795          * is tied to the device itself, and not to the DRM device.
2796          *
2797          * So when the device will be gone, one of the first thing we
2798          * will be doing will be to unregister the interrupt handler,
2799          * and then unregister the DRM device. drm_dev_enter() would
2800          * thus always succeed if we are here.
2801          */
2802
2803         if (!(stat & VC4_HDMI_CPU_CEC))
2804                 return IRQ_NONE;
2805
2806         spin_lock(&vc4_hdmi->hw_lock);
2807         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2808         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2809         if (vc4_hdmi->cec_irq_was_rx)
2810                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2811         else
2812                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2813
2814         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2815         spin_unlock(&vc4_hdmi->hw_lock);
2816
2817         return ret;
2818 }
2819
2820 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2821 {
2822         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2823         struct drm_device *drm = vc4_hdmi->connector.dev;
2824         /* clock period in microseconds */
2825         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2826         unsigned long flags;
2827         u32 val;
2828         int ret;
2829         int idx;
2830
2831         if (!drm_dev_enter(drm, &idx))
2832                 /*
2833                  * We can't return an error code, because the CEC
2834                  * framework will emit WARN_ON messages at unbind
2835                  * otherwise.
2836                  */
2837                 return 0;
2838
2839         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2840         if (ret) {
2841                 drm_dev_exit(idx);
2842                 return ret;
2843         }
2844
2845         mutex_lock(&vc4_hdmi->mutex);
2846
2847         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2848
2849         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2850         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2851                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2852                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2853         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2854                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2855
2856         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2857                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2858         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2859         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2860                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2861                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2862                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2863                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2864                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2865         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2866                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2867                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2868                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2869                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2870         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2871                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2872                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2873                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2874                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2875
2876         if (!vc4_hdmi->variant->external_irq_controller)
2877                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2878
2879         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2880
2881         mutex_unlock(&vc4_hdmi->mutex);
2882         drm_dev_exit(idx);
2883
2884         return 0;
2885 }
2886
2887 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2888 {
2889         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2890         struct drm_device *drm = vc4_hdmi->connector.dev;
2891         unsigned long flags;
2892         int idx;
2893
2894         if (!drm_dev_enter(drm, &idx))
2895                 /*
2896                  * We can't return an error code, because the CEC
2897                  * framework will emit WARN_ON messages at unbind
2898                  * otherwise.
2899                  */
2900                 return 0;
2901
2902         mutex_lock(&vc4_hdmi->mutex);
2903
2904         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2905
2906         if (!vc4_hdmi->variant->external_irq_controller)
2907                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2908
2909         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2910                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2911
2912         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2913
2914         mutex_unlock(&vc4_hdmi->mutex);
2915
2916         pm_runtime_put(&vc4_hdmi->pdev->dev);
2917
2918         drm_dev_exit(idx);
2919
2920         return 0;
2921 }
2922
2923 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2924 {
2925         if (enable)
2926                 return vc4_hdmi_cec_enable(adap);
2927         else
2928                 return vc4_hdmi_cec_disable(adap);
2929 }
2930
2931 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2932 {
2933         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2934         struct drm_device *drm = vc4_hdmi->connector.dev;
2935         unsigned long flags;
2936         int idx;
2937
2938         if (!drm_dev_enter(drm, &idx))
2939                 /*
2940                  * We can't return an error code, because the CEC
2941                  * framework will emit WARN_ON messages at unbind
2942                  * otherwise.
2943                  */
2944                 return 0;
2945
2946         mutex_lock(&vc4_hdmi->mutex);
2947         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2948         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2949                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2950                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2951         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2952         mutex_unlock(&vc4_hdmi->mutex);
2953
2954         drm_dev_exit(idx);
2955
2956         return 0;
2957 }
2958
2959 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2960                                       u32 signal_free_time, struct cec_msg *msg)
2961 {
2962         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2963         struct drm_device *dev = vc4_hdmi->connector.dev;
2964         unsigned long flags;
2965         u32 val;
2966         unsigned int i;
2967         int idx;
2968
2969         if (!drm_dev_enter(dev, &idx))
2970                 return -ENODEV;
2971
2972         if (msg->len > 16) {
2973                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2974                 drm_dev_exit(idx);
2975                 return -ENOMEM;
2976         }
2977
2978         mutex_lock(&vc4_hdmi->mutex);
2979
2980         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2981
2982         for (i = 0; i < msg->len; i += 4)
2983                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2984                            (msg->msg[i]) |
2985                            (msg->msg[i + 1] << 8) |
2986                            (msg->msg[i + 2] << 16) |
2987                            (msg->msg[i + 3] << 24));
2988
2989         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2990         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2991         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2992         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2993         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2994         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2995
2996         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2997
2998         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2999         mutex_unlock(&vc4_hdmi->mutex);
3000         drm_dev_exit(idx);
3001
3002         return 0;
3003 }
3004
3005 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3006         .adap_enable = vc4_hdmi_cec_adap_enable,
3007         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3008         .adap_transmit = vc4_hdmi_cec_adap_transmit,
3009 };
3010
3011 static void vc4_hdmi_cec_release(void *ptr)
3012 {
3013         struct vc4_hdmi *vc4_hdmi = ptr;
3014
3015         cec_unregister_adapter(vc4_hdmi->cec_adap);
3016         vc4_hdmi->cec_adap = NULL;
3017 }
3018
3019 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3020 {
3021         struct cec_connector_info conn_info;
3022         struct platform_device *pdev = vc4_hdmi->pdev;
3023         struct device *dev = &pdev->dev;
3024         int ret;
3025
3026         if (!of_property_present(dev->of_node, "interrupts")) {
3027                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3028                 return 0;
3029         }
3030
3031         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3032                                                   vc4_hdmi,
3033                                                   vc4_hdmi->variant->card_name,
3034                                                   CEC_CAP_DEFAULTS |
3035                                                   CEC_CAP_CONNECTOR_INFO, 1);
3036         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3037         if (ret < 0)
3038                 return ret;
3039
3040         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3041         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3042
3043         if (vc4_hdmi->variant->external_irq_controller) {
3044                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3045                                                 vc4_cec_irq_handler_rx_bare,
3046                                                 vc4_cec_irq_handler_rx_thread, 0,
3047                                                 "vc4 hdmi cec rx", vc4_hdmi);
3048                 if (ret)
3049                         goto err_delete_cec_adap;
3050
3051                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3052                                                 vc4_cec_irq_handler_tx_bare,
3053                                                 vc4_cec_irq_handler_tx_thread, 0,
3054                                                 "vc4 hdmi cec tx", vc4_hdmi);
3055                 if (ret)
3056                         goto err_delete_cec_adap;
3057         } else {
3058                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3059                                                 vc4_cec_irq_handler,
3060                                                 vc4_cec_irq_handler_thread, 0,
3061                                                 "vc4 hdmi cec", vc4_hdmi);
3062                 if (ret)
3063                         goto err_delete_cec_adap;
3064         }
3065
3066         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3067         if (ret < 0)
3068                 goto err_delete_cec_adap;
3069
3070         /*
3071          * NOTE: Strictly speaking, we should probably use a DRM-managed
3072          * registration there to avoid removing the CEC adapter by the
3073          * time the DRM driver doesn't have any user anymore.
3074          *
3075          * However, the CEC framework already cleans up the CEC adapter
3076          * only when the last user has closed its file descriptor, so we
3077          * don't need to handle it in DRM.
3078          *
3079          * By the time the device-managed hook is executed, we will give
3080          * up our reference to the CEC adapter and therefore don't
3081          * really care when it's actually freed.
3082          *
3083          * There's still a problematic sequence: if we unregister our
3084          * CEC adapter, but the userspace keeps a handle on the CEC
3085          * adapter but not the DRM device for some reason. In such a
3086          * case, our vc4_hdmi structure will be freed, but the
3087          * cec_adapter structure will have a dangling pointer to what
3088          * used to be our HDMI controller. If we get a CEC call at that
3089          * moment, we could end up with a use-after-free. Fortunately,
3090          * the CEC framework already handles this too, by calling
3091          * cec_is_registered() in cec_ioctl() and cec_poll().
3092          */
3093         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3094         if (ret)
3095                 return ret;
3096
3097         return 0;
3098
3099 err_delete_cec_adap:
3100         cec_delete_adapter(vc4_hdmi->cec_adap);
3101
3102         return ret;
3103 }
3104 #else
3105 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3106 {
3107         return 0;
3108 }
3109 #endif
3110
3111 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3112 {
3113         struct debugfs_reg32 *regs = ptr;
3114
3115         kfree(regs);
3116 }
3117
3118 static int vc4_hdmi_build_regset(struct drm_device *drm,
3119                                  struct vc4_hdmi *vc4_hdmi,
3120                                  struct debugfs_regset32 *regset,
3121                                  enum vc4_hdmi_regs reg)
3122 {
3123         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3124         struct debugfs_reg32 *regs, *new_regs;
3125         unsigned int count = 0;
3126         unsigned int i;
3127         int ret;
3128
3129         regs = kcalloc(variant->num_registers, sizeof(*regs),
3130                        GFP_KERNEL);
3131         if (!regs)
3132                 return -ENOMEM;
3133
3134         for (i = 0; i < variant->num_registers; i++) {
3135                 const struct vc4_hdmi_register *field = &variant->registers[i];
3136
3137                 if (field->reg != reg)
3138                         continue;
3139
3140                 regs[count].name = field->name;
3141                 regs[count].offset = field->offset;
3142                 count++;
3143         }
3144
3145         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3146         if (!new_regs)
3147                 return -ENOMEM;
3148
3149         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3150         regset->regs = new_regs;
3151         regset->nregs = count;
3152
3153         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3154         if (ret)
3155                 return ret;
3156
3157         return 0;
3158 }
3159
3160 static int vc4_hdmi_init_resources(struct drm_device *drm,
3161                                    struct vc4_hdmi *vc4_hdmi)
3162 {
3163         struct platform_device *pdev = vc4_hdmi->pdev;
3164         struct device *dev = &pdev->dev;
3165         int ret;
3166
3167         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3168         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3169                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3170
3171         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3172         if (IS_ERR(vc4_hdmi->hd_regs))
3173                 return PTR_ERR(vc4_hdmi->hd_regs);
3174
3175         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3176         if (ret)
3177                 return ret;
3178
3179         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3180         if (ret)
3181                 return ret;
3182
3183         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3184         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3185                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3186                 if (ret != -EPROBE_DEFER)
3187                         DRM_ERROR("Failed to get pixel clock\n");
3188                 return ret;
3189         }
3190
3191         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3192         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3193                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3194                 return PTR_ERR(vc4_hdmi->hsm_clock);
3195         }
3196         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3197         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3198
3199         return 0;
3200 }
3201
3202 static int vc5_hdmi_init_resources(struct drm_device *drm,
3203                                    struct vc4_hdmi *vc4_hdmi)
3204 {
3205         struct platform_device *pdev = vc4_hdmi->pdev;
3206         struct device *dev = &pdev->dev;
3207         struct resource *res;
3208         int ret;
3209
3210         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3211         if (!res)
3212                 return -ENODEV;
3213
3214         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3215                                                resource_size(res));
3216         if (!vc4_hdmi->hdmicore_regs)
3217                 return -ENOMEM;
3218
3219         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3220         if (!res)
3221                 return -ENODEV;
3222
3223         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3224         if (!vc4_hdmi->hd_regs)
3225                 return -ENOMEM;
3226
3227         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3228         if (!res)
3229                 return -ENODEV;
3230
3231         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3232         if (!vc4_hdmi->cec_regs)
3233                 return -ENOMEM;
3234
3235         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3236         if (!res)
3237                 return -ENODEV;
3238
3239         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3240         if (!vc4_hdmi->csc_regs)
3241                 return -ENOMEM;
3242
3243         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3244         if (!res)
3245                 return -ENODEV;
3246
3247         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3248         if (!vc4_hdmi->dvp_regs)
3249                 return -ENOMEM;
3250
3251         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3252         if (!res)
3253                 return -ENODEV;
3254
3255         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3256         if (!vc4_hdmi->phy_regs)
3257                 return -ENOMEM;
3258
3259         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3260         if (!res)
3261                 return -ENODEV;
3262
3263         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3264         if (!vc4_hdmi->ram_regs)
3265                 return -ENOMEM;
3266
3267         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3268         if (!res)
3269                 return -ENODEV;
3270
3271         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3272         if (!vc4_hdmi->rm_regs)
3273                 return -ENOMEM;
3274
3275         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3276         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3277                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3278                 return PTR_ERR(vc4_hdmi->hsm_clock);
3279         }
3280
3281         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3282         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3283                 DRM_ERROR("Failed to get pixel bvb clock\n");
3284                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3285         }
3286
3287         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3288         if (IS_ERR(vc4_hdmi->audio_clock)) {
3289                 DRM_ERROR("Failed to get audio clock\n");
3290                 return PTR_ERR(vc4_hdmi->audio_clock);
3291         }
3292
3293         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3294         if (IS_ERR(vc4_hdmi->cec_clock)) {
3295                 DRM_ERROR("Failed to get CEC clock\n");
3296                 return PTR_ERR(vc4_hdmi->cec_clock);
3297         }
3298
3299         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3300         if (IS_ERR(vc4_hdmi->reset)) {
3301                 DRM_ERROR("Failed to get HDMI reset line\n");
3302                 return PTR_ERR(vc4_hdmi->reset);
3303         }
3304
3305         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3306         if (ret)
3307                 return ret;
3308
3309         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3310         if (ret)
3311                 return ret;
3312
3313         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3314         if (ret)
3315                 return ret;
3316
3317         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3318         if (ret)
3319                 return ret;
3320
3321         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3322         if (ret)
3323                 return ret;
3324
3325         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3326         if (ret)
3327                 return ret;
3328
3329         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3330         if (ret)
3331                 return ret;
3332
3333         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3334         if (ret)
3335                 return ret;
3336
3337         return 0;
3338 }
3339
3340 static int vc4_hdmi_runtime_suspend(struct device *dev)
3341 {
3342         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3343
3344         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3345
3346         return 0;
3347 }
3348
3349 static int vc4_hdmi_runtime_resume(struct device *dev)
3350 {
3351         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3352         unsigned long __maybe_unused flags;
3353         u32 __maybe_unused value;
3354         unsigned long rate;
3355         int ret;
3356
3357         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3358         if (ret)
3359                 return ret;
3360
3361         /*
3362          * Whenever the RaspberryPi boots without an HDMI monitor
3363          * plugged in, the firmware won't have initialized the HSM clock
3364          * rate and it will be reported as 0.
3365          *
3366          * If we try to access a register of the controller in such a
3367          * case, it will lead to a silent CPU stall. Let's make sure we
3368          * prevent such a case.
3369          */
3370         rate = clk_get_rate(vc4_hdmi->hsm_clock);
3371         if (!rate) {
3372                 ret = -EINVAL;
3373                 goto err_disable_clk;
3374         }
3375
3376         if (vc4_hdmi->variant->reset)
3377                 vc4_hdmi->variant->reset(vc4_hdmi);
3378
3379 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3380         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3381         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3382         /* Set the logical address to Unregistered */
3383         value |= VC4_HDMI_CEC_ADDR_MASK;
3384         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3385         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3386
3387         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3388
3389         if (!vc4_hdmi->variant->external_irq_controller) {
3390                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3391                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3392                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3393         }
3394 #endif
3395
3396         return 0;
3397
3398 err_disable_clk:
3399         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3400         return ret;
3401 }
3402
3403 static void vc4_hdmi_put_ddc_device(void *ptr)
3404 {
3405         struct vc4_hdmi *vc4_hdmi = ptr;
3406
3407         put_device(&vc4_hdmi->ddc->dev);
3408 }
3409
3410 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3411 {
3412         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3413         struct platform_device *pdev = to_platform_device(dev);
3414         struct drm_device *drm = dev_get_drvdata(master);
3415         struct vc4_hdmi *vc4_hdmi;
3416         struct drm_encoder *encoder;
3417         struct device_node *ddc_node;
3418         int ret;
3419
3420         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3421         if (!vc4_hdmi)
3422                 return -ENOMEM;
3423
3424         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3425         if (ret)
3426                 return ret;
3427
3428         spin_lock_init(&vc4_hdmi->hw_lock);
3429         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3430
3431         dev_set_drvdata(dev, vc4_hdmi);
3432         encoder = &vc4_hdmi->encoder.base;
3433         vc4_hdmi->encoder.type = variant->encoder_type;
3434         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3435         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3436         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3437         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3438         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3439         vc4_hdmi->pdev = pdev;
3440         vc4_hdmi->variant = variant;
3441
3442         /*
3443          * Since we don't know the state of the controller and its
3444          * display (if any), let's assume it's always enabled.
3445          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3446          * sure it's disabled, and avoid any inconsistency.
3447          */
3448         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3449                 vc4_hdmi->scdc_enabled = true;
3450
3451         ret = variant->init_resources(drm, vc4_hdmi);
3452         if (ret)
3453                 return ret;
3454
3455         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3456         if (!ddc_node) {
3457                 DRM_ERROR("Failed to find ddc node in device tree\n");
3458                 return -ENODEV;
3459         }
3460
3461         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3462         of_node_put(ddc_node);
3463         if (!vc4_hdmi->ddc) {
3464                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3465                 return -EPROBE_DEFER;
3466         }
3467
3468         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3469         if (ret)
3470                 return ret;
3471
3472         /* Only use the GPIO HPD pin if present in the DT, otherwise
3473          * we'll use the HDMI core's register.
3474          */
3475         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3476         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3477                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3478         }
3479
3480         vc4_hdmi->disable_wifi_frequencies =
3481                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3482
3483         ret = devm_pm_runtime_enable(dev);
3484         if (ret)
3485                 return ret;
3486
3487         /*
3488          *  We need to have the device powered up at this point to call
3489          *  our reset hook and for the CEC init.
3490          */
3491         ret = pm_runtime_resume_and_get(dev);
3492         if (ret)
3493                 return ret;
3494
3495         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3496              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3497             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3498                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3499                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3500                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3501         }
3502
3503         ret = drmm_encoder_init(drm, encoder,
3504                                 &vc4_hdmi_encoder_funcs,
3505                                 DRM_MODE_ENCODER_TMDS,
3506                                 NULL);
3507         if (ret)
3508                 goto err_put_runtime_pm;
3509
3510         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3511
3512         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3513         if (ret)
3514                 goto err_put_runtime_pm;
3515
3516         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3517         if (ret)
3518                 goto err_put_runtime_pm;
3519
3520         ret = vc4_hdmi_cec_init(vc4_hdmi);
3521         if (ret)
3522                 goto err_put_runtime_pm;
3523
3524         ret = vc4_hdmi_audio_init(vc4_hdmi);
3525         if (ret)
3526                 goto err_put_runtime_pm;
3527
3528         pm_runtime_put_sync(dev);
3529
3530         return 0;
3531
3532 err_put_runtime_pm:
3533         pm_runtime_put_sync(dev);
3534
3535         return ret;
3536 }
3537
3538 static const struct component_ops vc4_hdmi_ops = {
3539         .bind   = vc4_hdmi_bind,
3540 };
3541
3542 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3543 {
3544         return component_add(&pdev->dev, &vc4_hdmi_ops);
3545 }
3546
3547 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3548 {
3549         component_del(&pdev->dev, &vc4_hdmi_ops);
3550         return 0;
3551 }
3552
3553 static const struct vc4_hdmi_variant bcm2835_variant = {
3554         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3555         .debugfs_name           = "hdmi_regs",
3556         .card_name              = "vc4-hdmi",
3557         .max_pixel_clock        = 162000000,
3558         .registers              = vc4_hdmi_fields,
3559         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3560
3561         .init_resources         = vc4_hdmi_init_resources,
3562         .csc_setup              = vc4_hdmi_csc_setup,
3563         .reset                  = vc4_hdmi_reset,
3564         .set_timings            = vc4_hdmi_set_timings,
3565         .phy_init               = vc4_hdmi_phy_init,
3566         .phy_disable            = vc4_hdmi_phy_disable,
3567         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3568         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3569         .channel_map            = vc4_hdmi_channel_map,
3570         .supports_hdr           = false,
3571 };
3572
3573 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3574         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3575         .debugfs_name           = "hdmi0_regs",
3576         .card_name              = "vc4-hdmi-0",
3577         .max_pixel_clock        = 600000000,
3578         .registers              = vc5_hdmi_hdmi0_fields,
3579         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3580         .phy_lane_mapping       = {
3581                 PHY_LANE_0,
3582                 PHY_LANE_1,
3583                 PHY_LANE_2,
3584                 PHY_LANE_CK,
3585         },
3586         .unsupported_odd_h_timings      = true,
3587         .external_irq_controller        = true,
3588
3589         .init_resources         = vc5_hdmi_init_resources,
3590         .csc_setup              = vc5_hdmi_csc_setup,
3591         .reset                  = vc5_hdmi_reset,
3592         .set_timings            = vc5_hdmi_set_timings,
3593         .phy_init               = vc5_hdmi_phy_init,
3594         .phy_disable            = vc5_hdmi_phy_disable,
3595         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3596         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3597         .channel_map            = vc5_hdmi_channel_map,
3598         .supports_hdr           = true,
3599         .hp_detect              = vc5_hdmi_hp_detect,
3600 };
3601
3602 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3603         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3604         .debugfs_name           = "hdmi1_regs",
3605         .card_name              = "vc4-hdmi-1",
3606         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3607         .registers              = vc5_hdmi_hdmi1_fields,
3608         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3609         .phy_lane_mapping       = {
3610                 PHY_LANE_1,
3611                 PHY_LANE_0,
3612                 PHY_LANE_CK,
3613                 PHY_LANE_2,
3614         },
3615         .unsupported_odd_h_timings      = true,
3616         .external_irq_controller        = true,
3617
3618         .init_resources         = vc5_hdmi_init_resources,
3619         .csc_setup              = vc5_hdmi_csc_setup,
3620         .reset                  = vc5_hdmi_reset,
3621         .set_timings            = vc5_hdmi_set_timings,
3622         .phy_init               = vc5_hdmi_phy_init,
3623         .phy_disable            = vc5_hdmi_phy_disable,
3624         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3625         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3626         .channel_map            = vc5_hdmi_channel_map,
3627         .supports_hdr           = true,
3628         .hp_detect              = vc5_hdmi_hp_detect,
3629 };
3630
3631 static const struct of_device_id vc4_hdmi_dt_match[] = {
3632         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3633         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3634         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3635         {}
3636 };
3637
3638 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3639         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3640                            vc4_hdmi_runtime_resume,
3641                            NULL)
3642 };
3643
3644 struct platform_driver vc4_hdmi_driver = {
3645         .probe = vc4_hdmi_dev_probe,
3646         .remove = vc4_hdmi_dev_remove,
3647         .driver = {
3648                 .name = "vc4_hdmi",
3649                 .of_match_table = vc4_hdmi_dt_match,
3650                 .pm = &vc4_hdmi_pm_ops,
3651         },
3652 };