drivers/spi/spi-cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Driver for Cadence QSPI Controller
   4 //
   5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
   7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
   8
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/reset.h>
  27 #include <linux/sched.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/spi-mem.h>
  30 #include <linux/timer.h>
  31
  32 #define CQSPI_NAME                      "cadence-qspi"
  33 #define CQSPI_MAX_CHIPSELECT            16
  34
  35 /* Quirks */
  36 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  37 #define CQSPI_DISABLE_DAC_MODE          BIT(1)
  38
  39 /* Capabilities */
  40 #define CQSPI_SUPPORTS_OCTAL            BIT(0)
  41
  42 struct cqspi_st;
  43
  44 struct cqspi_flash_pdata {
  45         struct cqspi_st *cqspi;
  46         u32             clk_rate;
  47         u32             read_delay;
  48         u32             tshsl_ns;
  49         u32             tsd2d_ns;
  50         u32             tchsh_ns;
  51         u32             tslch_ns;
  52         u8              inst_width;
  53         u8              addr_width;
  54         u8              data_width;
  55         bool            dtr;
  56         u8              cs;
  57 };
  58
  59 struct cqspi_st {
  60         struct platform_device  *pdev;
  61
  62         struct clk              *clk;
  63         unsigned int            sclk;
  64
  65         void __iomem            *iobase;
  66         void __iomem            *ahb_base;
  67         resource_size_t         ahb_size;
  68         struct completion       transfer_complete;
  69
  70         struct dma_chan         *rx_chan;
  71         struct completion       rx_dma_complete;
  72         dma_addr_t              mmap_phys_base;
  73
  74         int                     current_cs;
  75         unsigned long           master_ref_clk_hz;
  76         bool                    is_decoded_cs;
  77         u32                     fifo_depth;
  78         u32                     fifo_width;
  79         u32                     num_chipselect;
  80         bool                    rclk_en;
  81         u32                     trigger_address;
  82         u32                     wr_delay;
  83         bool                    use_direct_mode;
  84         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  85 };
  86
  87 struct cqspi_driver_platdata {
  88         u32 hwcaps_mask;
  89         u8 quirks;
  90 };
  91
  92 /* Operation timeout value */
  93 #define CQSPI_TIMEOUT_MS                        500
  94 #define CQSPI_READ_TIMEOUT_MS                   10
  95
  96 /* Instruction type */
  97 #define CQSPI_INST_TYPE_SINGLE                  0
  98 #define CQSPI_INST_TYPE_DUAL                    1
  99 #define CQSPI_INST_TYPE_QUAD                    2
 100 #define CQSPI_INST_TYPE_OCTAL                   3
 101
 102 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 103 #define CQSPI_DUMMY_BYTES_MAX                   4
 104 #define CQSPI_DUMMY_CLKS_MAX                    31
 105
 106 #define CQSPI_STIG_DATA_LEN_MAX                 8
 107
 108 /* Register map */
 109 #define CQSPI_REG_CONFIG                        0x00
 110 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 111 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 112 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 113 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 114 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 115 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 116 #define CQSPI_REG_CONFIG_DTR_PROTO              BIT(24)
 117 #define CQSPI_REG_CONFIG_DUAL_OPCODE            BIT(30)
 118 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 119 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 120 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 121
 122 #define CQSPI_REG_RD_INSTR                      0x04
 123 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 124 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 125 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 126 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 127 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 128 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 129 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 130 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 131 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 132 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 133
 134 #define CQSPI_REG_WR_INSTR                      0x08
 135 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 136 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 137 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 138
 139 #define CQSPI_REG_DELAY                         0x0C
 140 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 141 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 142 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 143 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 144 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 145 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 146 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 147 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 148
 149 #define CQSPI_REG_READCAPTURE                   0x10
 150 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 151 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 152 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 153
 154 #define CQSPI_REG_SIZE                          0x14
 155 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 156 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 157 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 158 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 159 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 160 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 161
 162 #define CQSPI_REG_SRAMPARTITION                 0x18
 163 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 164
 165 #define CQSPI_REG_DMA                           0x20
 166 #define CQSPI_REG_DMA_SINGLE_LSB                0
 167 #define CQSPI_REG_DMA_BURST_LSB                 8
 168 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 169 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 170
 171 #define CQSPI_REG_REMAP                         0x24
 172 #define CQSPI_REG_MODE_BIT                      0x28
 173
 174 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 175 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 176 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 177 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 178 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 179
 180 #define CQSPI_REG_WR_COMPLETION_CTRL            0x38
 181 #define CQSPI_REG_WR_DISABLE_AUTO_POLL          BIT(14)
 182
 183 #define CQSPI_REG_IRQSTATUS                     0x40
 184 #define CQSPI_REG_IRQMASK                       0x44
 185
 186 #define CQSPI_REG_INDIRECTRD                    0x60
 187 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 188 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 189 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 190
 191 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 192 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 193 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 194
 195 #define CQSPI_REG_CMDCTRL                       0x90
 196 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 197 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 198 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 199 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 200 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 201 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 202 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 203 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 204 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 205 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 206 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 207 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 208 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 209 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 210
 211 #define CQSPI_REG_INDIRECTWR                    0x70
 212 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 213 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 214 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 215
 216 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 217 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 218 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 219
 220 #define CQSPI_REG_CMDADDRESS                    0x94
 221 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 222 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 223 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 224 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 225
 226 #define CQSPI_REG_POLLING_STATUS                0xB0
 227 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB      16
 228
 229 #define CQSPI_REG_OP_EXT_LOWER                  0xE0
 230 #define CQSPI_REG_OP_EXT_READ_LSB               24
 231 #define CQSPI_REG_OP_EXT_WRITE_LSB              16
 232 #define CQSPI_REG_OP_EXT_STIG_LSB               0
 233
 234 /* Interrupt status bits */
 235 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 236 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 237 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 238 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 239 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 240 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 241 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 242 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 243
 244 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 245                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 246                                          CQSPI_REG_IRQ_IND_COMP)
 247
 248 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 249                                          CQSPI_REG_IRQ_WATERMARK        | \
 250                                          CQSPI_REG_IRQ_UNDERFLOW)
 251
 252 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 253
 254 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 255 {
 256         u32 val;
 257
 258         return readl_relaxed_poll_timeout(reg, val,
 259                                           (((clr ? ~val : val) & mask) == mask),
 260                                           10, CQSPI_TIMEOUT_MS * 1000);
 261 }
 262
 263 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 264 {
 265         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 266
 267         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 268 }
 269
 270 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 271 {
 272         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 273
 274         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 275         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 276 }
 277
 278 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 279 {
 280         struct cqspi_st *cqspi = dev;
 281         unsigned int irq_status;
 282
 283         /* Read interrupt status */
 284         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 285
 286         /* Clear interrupt */
 287         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 288
 289         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 290
 291         if (irq_status)
 292                 complete(&cqspi->transfer_complete);
 293
 294         return IRQ_HANDLED;
 295 }
 296
 297 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
 298 {
 299         u32 rdreg = 0;
 300
 301         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 302         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 303         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 304
 305         return rdreg;
 306 }
 307
 308 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
 309 {
 310         unsigned int dummy_clk;
 311
 312         dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 313         if (dtr)
 314                 dummy_clk /= 2;
 315
 316         return dummy_clk;
 317 }
 318
 319 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
 320                               const struct spi_mem_op *op)
 321 {
 322         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 323         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 324         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 325         f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
 326
 327         switch (op->data.buswidth) {
 328         case 0:
 329                 break;
 330         case 1:
 331                 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 332                 break;
 333         case 2:
 334                 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 335                 break;
 336         case 4:
 337                 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 338                 break;
 339         case 8:
 340                 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 341                 break;
 342         default:
 343                 return -EINVAL;
 344         }
 345
 346         /* Right now we only support 8-8-8 DTR mode. */
 347         if (f_pdata->dtr) {
 348                 switch (op->cmd.buswidth) {
 349                 case 0:
 350                         break;
 351                 case 8:
 352                         f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL;
 353                         break;
 354                 default:
 355                         return -EINVAL;
 356                 }
 357
 358                 switch (op->addr.buswidth) {
 359                 case 0:
 360                         break;
 361                 case 8:
 362                         f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL;
 363                         break;
 364                 default:
 365                         return -EINVAL;
 366                 }
 367
 368                 switch (op->data.buswidth) {
 369                 case 0:
 370                         break;
 371                 case 8:
 372                         f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 373                         break;
 374                 default:
 375                         return -EINVAL;
 376                 }
 377         }
 378
 379         return 0;
 380 }
 381
 382 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 383 {
 384         const unsigned int poll_idle_retry = 3;
 385         unsigned int count = 0;
 386         unsigned long timeout;
 387
 388         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 389         while (1) {
 390                 /*
 391                  * Read few times in succession to ensure the controller
 392                  * is indeed idle, that is, the bit does not transition
 393                  * low again.
 394                  */
 395                 if (cqspi_is_idle(cqspi))
 396                         count++;
 397                 else
 398                         count = 0;
 399
 400                 if (count >= poll_idle_retry)
 401                         return 0;
 402
 403                 if (time_after(jiffies, timeout)) {
 404                         /* Timeout, in busy mode. */
 405                         dev_err(&cqspi->pdev->dev,
 406                                 "QSPI is still busy after %dms timeout.\n",
 407                                 CQSPI_TIMEOUT_MS);
 408                         return -ETIMEDOUT;
 409                 }
 410
 411                 cpu_relax();
 412         }
 413 }
 414
 415 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 416 {
 417         void __iomem *reg_base = cqspi->iobase;
 418         int ret;
 419
 420         /* Write the CMDCTRL without start execution. */
 421         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 422         /* Start execute */
 423         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 424         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 425
 426         /* Polling for completion. */
 427         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 428                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 429         if (ret) {
 430                 dev_err(&cqspi->pdev->dev,
 431                         "Flash command execution timed out.\n");
 432                 return ret;
 433         }
 434
 435         /* Polling QSPI idle status. */
 436         return cqspi_wait_idle(cqspi);
 437 }
 438
 439 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
 440                                   const struct spi_mem_op *op,
 441                                   unsigned int shift)
 442 {
 443         struct cqspi_st *cqspi = f_pdata->cqspi;
 444         void __iomem *reg_base = cqspi->iobase;
 445         unsigned int reg;
 446         u8 ext;
 447
 448         if (op->cmd.nbytes != 2)
 449                 return -EINVAL;
 450
 451         /* Opcode extension is the LSB. */
 452         ext = op->cmd.opcode & 0xff;
 453
 454         reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
 455         reg &= ~(0xff << shift);
 456         reg |= ext << shift;
 457         writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
 458
 459         return 0;
 460 }
 461
 462 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
 463                             const struct spi_mem_op *op, unsigned int shift,
 464                             bool enable)
 465 {
 466         struct cqspi_st *cqspi = f_pdata->cqspi;
 467         void __iomem *reg_base = cqspi->iobase;
 468         unsigned int reg;
 469         int ret;
 470
 471         reg = readl(reg_base + CQSPI_REG_CONFIG);
 472
 473         /*
 474          * We enable dual byte opcode here. The callers have to set up the
 475          * extension opcode based on which type of operation it is.
 476          */
 477         if (enable) {
 478                 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 479                 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 480
 481                 /* Set up command opcode extension. */
 482                 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
 483                 if (ret)
 484                         return ret;
 485         } else {
 486                 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 487                 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 488         }
 489
 490         writel(reg, reg_base + CQSPI_REG_CONFIG);
 491
 492         return cqspi_wait_idle(cqspi);
 493 }
 494
 495 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 496                               const struct spi_mem_op *op)
 497 {
 498         struct cqspi_st *cqspi = f_pdata->cqspi;
 499         void __iomem *reg_base = cqspi->iobase;
 500         u8 *rxbuf = op->data.buf.in;
 501         u8 opcode;
 502         size_t n_rx = op->data.nbytes;
 503         unsigned int rdreg;
 504         unsigned int reg;
 505         unsigned int dummy_clk;
 506         size_t read_len;
 507         int status;
 508
 509         status = cqspi_set_protocol(f_pdata, op);
 510         if (status)
 511                 return status;
 512
 513         status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 514                                   f_pdata->dtr);
 515         if (status)
 516                 return status;
 517
 518         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 519                 dev_err(&cqspi->pdev->dev,
 520                         "Invalid input argument, len %zu rxbuf 0x%p\n",
 521                         n_rx, rxbuf);
 522                 return -EINVAL;
 523         }
 524
 525         if (f_pdata->dtr)
 526                 opcode = op->cmd.opcode >> 8;
 527         else
 528                 opcode = op->cmd.opcode;
 529
 530         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 531
 532         rdreg = cqspi_calc_rdreg(f_pdata);
 533         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 534
 535         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 536         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 537                 return -EOPNOTSUPP;
 538
 539         if (dummy_clk)
 540                 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 541                      << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 542
 543         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 544
 545         /* 0 means 1 byte. */
 546         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 547                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 548         status = cqspi_exec_flash_cmd(cqspi, reg);
 549         if (status)
 550                 return status;
 551
 552         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 553
 554         /* Put the read value into rx_buf */
 555         read_len = (n_rx > 4) ? 4 : n_rx;
 556         memcpy(rxbuf, &reg, read_len);
 557         rxbuf += read_len;
 558
 559         if (n_rx > 4) {
 560                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 561
 562                 read_len = n_rx - read_len;
 563                 memcpy(rxbuf, &reg, read_len);
 564         }
 565
 566         return 0;
 567 }
 568
 569 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
 570                                const struct spi_mem_op *op)
 571 {
 572         struct cqspi_st *cqspi = f_pdata->cqspi;
 573         void __iomem *reg_base = cqspi->iobase;
 574         u8 opcode;
 575         const u8 *txbuf = op->data.buf.out;
 576         size_t n_tx = op->data.nbytes;
 577         unsigned int reg;
 578         unsigned int data;
 579         size_t write_len;
 580         int ret;
 581
 582         ret = cqspi_set_protocol(f_pdata, op);
 583         if (ret)
 584                 return ret;
 585
 586         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 587                                f_pdata->dtr);
 588         if (ret)
 589                 return ret;
 590
 591         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 592                 dev_err(&cqspi->pdev->dev,
 593                         "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
 594                         n_tx, txbuf);
 595                 return -EINVAL;
 596         }
 597
 598         reg = cqspi_calc_rdreg(f_pdata);
 599         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 600
 601         if (f_pdata->dtr)
 602                 opcode = op->cmd.opcode >> 8;
 603         else
 604                 opcode = op->cmd.opcode;
 605
 606         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 607
 608         if (op->addr.nbytes) {
 609                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 610                 reg |= ((op->addr.nbytes - 1) &
 611                         CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 612                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 613
 614                 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 615         }
 616
 617         if (n_tx) {
 618                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 619                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 620                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 621                 data = 0;
 622                 write_len = (n_tx > 4) ? 4 : n_tx;
 623                 memcpy(&data, txbuf, write_len);
 624                 txbuf += write_len;
 625                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 626
 627                 if (n_tx > 4) {
 628                         data = 0;
 629                         write_len = n_tx - 4;
 630                         memcpy(&data, txbuf, write_len);
 631                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 632                 }
 633         }
 634
 635         return cqspi_exec_flash_cmd(cqspi, reg);
 636 }
 637
 638 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 639                             const struct spi_mem_op *op)
 640 {
 641         struct cqspi_st *cqspi = f_pdata->cqspi;
 642         void __iomem *reg_base = cqspi->iobase;
 643         unsigned int dummy_clk = 0;
 644         unsigned int reg;
 645         int ret;
 646         u8 opcode;
 647
 648         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
 649                                f_pdata->dtr);
 650         if (ret)
 651                 return ret;
 652
 653         if (f_pdata->dtr)
 654                 opcode = op->cmd.opcode >> 8;
 655         else
 656                 opcode = op->cmd.opcode;
 657
 658         reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 659         reg |= cqspi_calc_rdreg(f_pdata);
 660
 661         /* Setup dummy clock cycles */
 662         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 663
 664         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 665                 return -EOPNOTSUPP;
 666
 667         if (dummy_clk)
 668                 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 669                        << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 670
 671         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 672
 673         /* Set address width */
 674         reg = readl(reg_base + CQSPI_REG_SIZE);
 675         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 676         reg |= (op->addr.nbytes - 1);
 677         writel(reg, reg_base + CQSPI_REG_SIZE);
 678         return 0;
 679 }
 680
 681 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 682                                        u8 *rxbuf, loff_t from_addr,
 683                                        const size_t n_rx)
 684 {
 685         struct cqspi_st *cqspi = f_pdata->cqspi;
 686         struct device *dev = &cqspi->pdev->dev;
 687         void __iomem *reg_base = cqspi->iobase;
 688         void __iomem *ahb_base = cqspi->ahb_base;
 689         unsigned int remaining = n_rx;
 690         unsigned int mod_bytes = n_rx % 4;
 691         unsigned int bytes_to_read = 0;
 692         u8 *rxbuf_end = rxbuf + n_rx;
 693         int ret = 0;
 694
 695         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 696         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 697
 698         /* Clear all interrupts. */
 699         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 700
 701         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 702
 703         reinit_completion(&cqspi->transfer_complete);
 704         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 705                reg_base + CQSPI_REG_INDIRECTRD);
 706
 707         while (remaining > 0) {
 708                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 709                                                  msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 710                         ret = -ETIMEDOUT;
 711
 712                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 713
 714                 if (ret && bytes_to_read == 0) {
 715                         dev_err(dev, "Indirect read timeout, no bytes\n");
 716                         goto failrd;
 717                 }
 718
 719                 while (bytes_to_read != 0) {
 720                         unsigned int word_remain = round_down(remaining, 4);
 721
 722                         bytes_to_read *= cqspi->fifo_width;
 723                         bytes_to_read = bytes_to_read > remaining ?
 724                                         remaining : bytes_to_read;
 725                         bytes_to_read = round_down(bytes_to_read, 4);
 726                         /* Read 4 byte word chunks then single bytes */
 727                         if (bytes_to_read) {
 728                                 ioread32_rep(ahb_base, rxbuf,
 729                                              (bytes_to_read / 4));
 730                         } else if (!word_remain && mod_bytes) {
 731                                 unsigned int temp = ioread32(ahb_base);
 732
 733                                 bytes_to_read = mod_bytes;
 734                                 memcpy(rxbuf, &temp, min((unsigned int)
 735                                                          (rxbuf_end - rxbuf),
 736                                                          bytes_to_read));
 737                         }
 738                         rxbuf += bytes_to_read;
 739                         remaining -= bytes_to_read;
 740                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 741                 }
 742
 743                 if (remaining > 0)
 744                         reinit_completion(&cqspi->transfer_complete);
 745         }
 746
 747         /* Check indirect done status */
 748         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 749                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 750         if (ret) {
 751                 dev_err(dev, "Indirect read completion error (%i)\n", ret);
 752                 goto failrd;
 753         }
 754
 755         /* Disable interrupt */
 756         writel(0, reg_base + CQSPI_REG_IRQMASK);
 757
 758         /* Clear indirect completion status */
 759         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 760
 761         return 0;
 762
 763 failrd:
 764         /* Disable interrupt */
 765         writel(0, reg_base + CQSPI_REG_IRQMASK);
 766
 767         /* Cancel the indirect read */
 768         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 769                reg_base + CQSPI_REG_INDIRECTRD);
 770         return ret;
 771 }
 772
 773 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 774                              const struct spi_mem_op *op)
 775 {
 776         unsigned int reg;
 777         int ret;
 778         struct cqspi_st *cqspi = f_pdata->cqspi;
 779         void __iomem *reg_base = cqspi->iobase;
 780         u8 opcode;
 781
 782         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
 783                                f_pdata->dtr);
 784         if (ret)
 785                 return ret;
 786
 787         if (f_pdata->dtr)
 788                 opcode = op->cmd.opcode >> 8;
 789         else
 790                 opcode = op->cmd.opcode;
 791
 792         /* Set opcode. */
 793         reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 794         reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 795         reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 796         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 797         reg = cqspi_calc_rdreg(f_pdata);
 798         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 799
 800         if (f_pdata->dtr) {
 801                 /*
 802                  * Some flashes like the cypress Semper flash expect a 4-byte
 803                  * dummy address with the Read SR command in DTR mode, but this
 804                  * controller does not support sending address with the Read SR
 805                  * command. So, disable write completion polling on the
 806                  * controller's side. spi-nor will take care of polling the
 807                  * status register.
 808                  */
 809                 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 810                 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
 811                 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 812         }
 813
 814         reg = readl(reg_base + CQSPI_REG_SIZE);
 815         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 816         reg |= (op->addr.nbytes - 1);
 817         writel(reg, reg_base + CQSPI_REG_SIZE);
 818         return 0;
 819 }
 820
 821 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
 822                                         loff_t to_addr, const u8 *txbuf,
 823                                         const size_t n_tx)
 824 {
 825         struct cqspi_st *cqspi = f_pdata->cqspi;
 826         struct device *dev = &cqspi->pdev->dev;
 827         void __iomem *reg_base = cqspi->iobase;
 828         unsigned int remaining = n_tx;
 829         unsigned int write_bytes;
 830         int ret;
 831
 832         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 833         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 834
 835         /* Clear all interrupts. */
 836         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 837
 838         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 839
 840         reinit_completion(&cqspi->transfer_complete);
 841         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 842                reg_base + CQSPI_REG_INDIRECTWR);
 843         /*
 844          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 845          * Controller programming sequence, couple of cycles of
 846          * QSPI_REF_CLK delay is required for the above bit to
 847          * be internally synchronized by the QSPI module. Provide 5
 848          * cycles of delay.
 849          */
 850         if (cqspi->wr_delay)
 851                 ndelay(cqspi->wr_delay);
 852
 853         while (remaining > 0) {
 854                 size_t write_words, mod_bytes;
 855
 856                 write_bytes = remaining;
 857                 write_words = write_bytes / 4;
 858                 mod_bytes = write_bytes % 4;
 859                 /* Write 4 bytes at a time then single bytes. */
 860                 if (write_words) {
 861                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 862                         txbuf += (write_words * 4);
 863                 }
 864                 if (mod_bytes) {
 865                         unsigned int temp = 0xFFFFFFFF;
 866
 867                         memcpy(&temp, txbuf, mod_bytes);
 868                         iowrite32(temp, cqspi->ahb_base);
 869                         txbuf += mod_bytes;
 870                 }
 871
 872                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 873                                                  msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
 874                         dev_err(dev, "Indirect write timeout\n");
 875                         ret = -ETIMEDOUT;
 876                         goto failwr;
 877                 }
 878
 879                 remaining -= write_bytes;
 880
 881                 if (remaining > 0)
 882                         reinit_completion(&cqspi->transfer_complete);
 883         }
 884
 885         /* Check indirect done status */
 886         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 887                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 888         if (ret) {
 889                 dev_err(dev, "Indirect write completion error (%i)\n", ret);
 890                 goto failwr;
 891         }
 892
 893         /* Disable interrupt. */
 894         writel(0, reg_base + CQSPI_REG_IRQMASK);
 895
 896         /* Clear indirect completion status */
 897         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 898
 899         cqspi_wait_idle(cqspi);
 900
 901         return 0;
 902
 903 failwr:
 904         /* Disable interrupt. */
 905         writel(0, reg_base + CQSPI_REG_IRQMASK);
 906
 907         /* Cancel the indirect write */
 908         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 909                reg_base + CQSPI_REG_INDIRECTWR);
 910         return ret;
 911 }
 912
 913 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
 914 {
 915         struct cqspi_st *cqspi = f_pdata->cqspi;
 916         void __iomem *reg_base = cqspi->iobase;
 917         unsigned int chip_select = f_pdata->cs;
 918         unsigned int reg;
 919
 920         reg = readl(reg_base + CQSPI_REG_CONFIG);
 921         if (cqspi->is_decoded_cs) {
 922                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 923         } else {
 924                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 925
 926                 /* Convert CS if without decoder.
 927                  * CS0 to 4b'1110
 928                  * CS1 to 4b'1101
 929                  * CS2 to 4b'1011
 930                  * CS3 to 4b'0111
 931                  */
 932                 chip_select = 0xF & ~(1 << chip_select);
 933         }
 934
 935         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 936                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 937         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 938             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 939         writel(reg, reg_base + CQSPI_REG_CONFIG);
 940 }
 941
 942 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 943                                            const unsigned int ns_val)
 944 {
 945         unsigned int ticks;
 946
 947         ticks = ref_clk_hz / 1000;      /* kHz */
 948         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 949
 950         return ticks;
 951 }
 952
 953 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
 954 {
 955         struct cqspi_st *cqspi = f_pdata->cqspi;
 956         void __iomem *iobase = cqspi->iobase;
 957         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 958         unsigned int tshsl, tchsh, tslch, tsd2d;
 959         unsigned int reg;
 960         unsigned int tsclk;
 961
 962         /* calculate the number of ref ticks for one sclk tick */
 963         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 964
 965         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 966         /* this particular value must be at least one sclk */
 967         if (tshsl < tsclk)
 968                 tshsl = tsclk;
 969
 970         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 971         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 972         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 973
 974         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 975                << CQSPI_REG_DELAY_TSHSL_LSB;
 976         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 977                 << CQSPI_REG_DELAY_TCHSH_LSB;
 978         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 979                 << CQSPI_REG_DELAY_TSLCH_LSB;
 980         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 981                 << CQSPI_REG_DELAY_TSD2D_LSB;
 982         writel(reg, iobase + CQSPI_REG_DELAY);
 983 }
 984
 985 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 986 {
 987         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 988         void __iomem *reg_base = cqspi->iobase;
 989         u32 reg, div;
 990
 991         /* Recalculate the baudrate divisor based on QSPI specification. */
 992         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 993
 994         reg = readl(reg_base + CQSPI_REG_CONFIG);
 995         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 996         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 997         writel(reg, reg_base + CQSPI_REG_CONFIG);
 998 }
 999
1000 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1001                                    const bool bypass,
1002                                    const unsigned int delay)
1003 {
1004         void __iomem *reg_base = cqspi->iobase;
1005         unsigned int reg;
1006
1007         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1008
1009         if (bypass)
1010                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1011         else
1012                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1013
1014         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1015                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
1016
1017         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1018                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1019
1020         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1021 }
1022
1023 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1024 {
1025         void __iomem *reg_base = cqspi->iobase;
1026         unsigned int reg;
1027
1028         reg = readl(reg_base + CQSPI_REG_CONFIG);
1029
1030         if (enable)
1031                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1032         else
1033                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1034
1035         writel(reg, reg_base + CQSPI_REG_CONFIG);
1036 }
1037
1038 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1039                             unsigned long sclk)
1040 {
1041         struct cqspi_st *cqspi = f_pdata->cqspi;
1042         int switch_cs = (cqspi->current_cs != f_pdata->cs);
1043         int switch_ck = (cqspi->sclk != sclk);
1044
1045         if (switch_cs || switch_ck)
1046                 cqspi_controller_enable(cqspi, 0);
1047
1048         /* Switch chip select. */
1049         if (switch_cs) {
1050                 cqspi->current_cs = f_pdata->cs;
1051                 cqspi_chipselect(f_pdata);
1052         }
1053
1054         /* Setup baudrate divisor and delays */
1055         if (switch_ck) {
1056                 cqspi->sclk = sclk;
1057                 cqspi_config_baudrate_div(cqspi);
1058                 cqspi_delay(f_pdata);
1059                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1060                                        f_pdata->read_delay);
1061         }
1062
1063         if (switch_cs || switch_ck)
1064                 cqspi_controller_enable(cqspi, 1);
1065 }
1066
1067 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1068                            const struct spi_mem_op *op)
1069 {
1070         struct cqspi_st *cqspi = f_pdata->cqspi;
1071         loff_t to = op->addr.val;
1072         size_t len = op->data.nbytes;
1073         const u_char *buf = op->data.buf.out;
1074         int ret;
1075
1076         ret = cqspi_set_protocol(f_pdata, op);
1077         if (ret)
1078                 return ret;
1079
1080         ret = cqspi_write_setup(f_pdata, op);
1081         if (ret)
1082                 return ret;
1083
1084         /*
1085          * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1086          * address (all 0s) with the read status register command in DTR mode.
1087          * But this controller does not support sending dummy address bytes to
1088          * the flash when it is polling the write completion register in DTR
1089          * mode. So, we can not use direct mode when in DTR mode for writing
1090          * data.
1091          */
1092         if (!f_pdata->dtr && cqspi->use_direct_mode &&
1093             ((to + len) <= cqspi->ahb_size)) {
1094                 memcpy_toio(cqspi->ahb_base + to, buf, len);
1095                 return cqspi_wait_idle(cqspi);
1096         }
1097
1098         return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1099 }
1100
1101 static void cqspi_rx_dma_callback(void *param)
1102 {
1103         struct cqspi_st *cqspi = param;
1104
1105         complete(&cqspi->rx_dma_complete);
1106 }
1107
1108 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1109                                      u_char *buf, loff_t from, size_t len)
1110 {
1111         struct cqspi_st *cqspi = f_pdata->cqspi;
1112         struct device *dev = &cqspi->pdev->dev;
1113         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1114         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1115         int ret = 0;
1116         struct dma_async_tx_descriptor *tx;
1117         dma_cookie_t cookie;
1118         dma_addr_t dma_dst;
1119         struct device *ddev;
1120
1121         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1122                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1123                 return 0;
1124         }
1125
1126         ddev = cqspi->rx_chan->device->dev;
1127         dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1128         if (dma_mapping_error(ddev, dma_dst)) {
1129                 dev_err(dev, "dma mapping failed\n");
1130                 return -ENOMEM;
1131         }
1132         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1133                                        len, flags);
1134         if (!tx) {
1135                 dev_err(dev, "device_prep_dma_memcpy error\n");
1136                 ret = -EIO;
1137                 goto err_unmap;
1138         }
1139
1140         tx->callback = cqspi_rx_dma_callback;
1141         tx->callback_param = cqspi;
1142         cookie = tx->tx_submit(tx);
1143         reinit_completion(&cqspi->rx_dma_complete);
1144
1145         ret = dma_submit_error(cookie);
1146         if (ret) {
1147                 dev_err(dev, "dma_submit_error %d\n", cookie);
1148                 ret = -EIO;
1149                 goto err_unmap;
1150         }
1151
1152         dma_async_issue_pending(cqspi->rx_chan);
1153         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1154                                          msecs_to_jiffies(max_t(size_t, len, 500)))) {
1155                 dmaengine_terminate_sync(cqspi->rx_chan);
1156                 dev_err(dev, "DMA wait_for_completion_timeout\n");
1157                 ret = -ETIMEDOUT;
1158                 goto err_unmap;
1159         }
1160
1161 err_unmap:
1162         dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1163
1164         return ret;
1165 }
1166
1167 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1168                           const struct spi_mem_op *op)
1169 {
1170         struct cqspi_st *cqspi = f_pdata->cqspi;
1171         loff_t from = op->addr.val;
1172         size_t len = op->data.nbytes;
1173         u_char *buf = op->data.buf.in;
1174         int ret;
1175
1176         ret = cqspi_set_protocol(f_pdata, op);
1177         if (ret)
1178                 return ret;
1179
1180         ret = cqspi_read_setup(f_pdata, op);
1181         if (ret)
1182                 return ret;
1183
1184         if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1185                 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1186
1187         return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1188 }
1189
1190 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1191 {
1192         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1193         struct cqspi_flash_pdata *f_pdata;
1194
1195         f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1196         cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1197
1198         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1199                 if (!op->addr.nbytes)
1200                         return cqspi_command_read(f_pdata, op);
1201
1202                 return cqspi_read(f_pdata, op);
1203         }
1204
1205         if (!op->addr.nbytes || !op->data.buf.out)
1206                 return cqspi_command_write(f_pdata, op);
1207
1208         return cqspi_write(f_pdata, op);
1209 }
1210
1211 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1212 {
1213         int ret;
1214
1215         ret = cqspi_mem_process(mem, op);
1216         if (ret)
1217                 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1218
1219         return ret;
1220 }
1221
1222 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1223                                   const struct spi_mem_op *op)
1224 {
1225         bool all_true, all_false;
1226
1227         all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
1228                    op->data.dtr;
1229         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1230                     !op->data.dtr;
1231
1232         /* Mixed DTR modes not supported. */
1233         if (!(all_true || all_false))
1234                 return false;
1235
1236         if (all_true)
1237                 return spi_mem_dtr_supports_op(mem, op);
1238         else
1239                 return spi_mem_default_supports_op(mem, op);
1240 }
1241
1242 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1243                                     struct cqspi_flash_pdata *f_pdata,
1244                                     struct device_node *np)
1245 {
1246         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1247                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1248                 return -ENXIO;
1249         }
1250
1251         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1252                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1253                 return -ENXIO;
1254         }
1255
1256         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1257                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1258                 return -ENXIO;
1259         }
1260
1261         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1262                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1263                 return -ENXIO;
1264         }
1265
1266         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1267                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1268                 return -ENXIO;
1269         }
1270
1271         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1272                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1273                 return -ENXIO;
1274         }
1275
1276         return 0;
1277 }
1278
1279 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1280 {
1281         struct device *dev = &cqspi->pdev->dev;
1282         struct device_node *np = dev->of_node;
1283
1284         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1285
1286         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1287                 dev_err(dev, "couldn't determine fifo-depth\n");
1288                 return -ENXIO;
1289         }
1290
1291         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1292                 dev_err(dev, "couldn't determine fifo-width\n");
1293                 return -ENXIO;
1294         }
1295
1296         if (of_property_read_u32(np, "cdns,trigger-address",
1297                                  &cqspi->trigger_address)) {
1298                 dev_err(dev, "couldn't determine trigger-address\n");
1299                 return -ENXIO;
1300         }
1301
1302         if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1303                 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1304
1305         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1306
1307         return 0;
1308 }
1309
1310 static void cqspi_controller_init(struct cqspi_st *cqspi)
1311 {
1312         u32 reg;
1313
1314         cqspi_controller_enable(cqspi, 0);
1315
1316         /* Configure the remap address register, no remap */
1317         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1318
1319         /* Disable all interrupts. */
1320         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1321
1322         /* Configure the SRAM split to 1:1 . */
1323         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1324
1325         /* Load indirect trigger address. */
1326         writel(cqspi->trigger_address,
1327                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1328
1329         /* Program read watermark -- 1/2 of the FIFO. */
1330         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1331                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1332         /* Program write watermark -- 1/8 of the FIFO. */
1333         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1334                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1335
1336         /* Disable direct access controller */
1337         if (!cqspi->use_direct_mode) {
1338                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1339                 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1340                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1341         }
1342
1343         cqspi_controller_enable(cqspi, 1);
1344 }
1345
1346 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1347 {
1348         dma_cap_mask_t mask;
1349
1350         dma_cap_zero(mask);
1351         dma_cap_set(DMA_MEMCPY, mask);
1352
1353         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1354         if (IS_ERR(cqspi->rx_chan)) {
1355                 int ret = PTR_ERR(cqspi->rx_chan);
1356                 cqspi->rx_chan = NULL;
1357                 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1358         }
1359         init_completion(&cqspi->rx_dma_complete);
1360
1361         return 0;
1362 }
1363
1364 static const char *cqspi_get_name(struct spi_mem *mem)
1365 {
1366         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1367         struct device *dev = &cqspi->pdev->dev;
1368
1369         return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1370 }
1371
1372 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1373         .exec_op = cqspi_exec_mem_op,
1374         .get_name = cqspi_get_name,
1375         .supports_op = cqspi_supports_mem_op,
1376 };
1377
1378 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1379 {
1380         struct platform_device *pdev = cqspi->pdev;
1381         struct device *dev = &pdev->dev;
1382         struct device_node *np = dev->of_node;
1383         struct cqspi_flash_pdata *f_pdata;
1384         unsigned int cs;
1385         int ret;
1386
1387         /* Get flash device data */
1388         for_each_available_child_of_node(dev->of_node, np) {
1389                 ret = of_property_read_u32(np, "reg", &cs);
1390                 if (ret) {
1391                         dev_err(dev, "Couldn't determine chip select.\n");
1392                         return ret;
1393                 }
1394
1395                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1396                         dev_err(dev, "Chip select %d out of range.\n", cs);
1397                         return -EINVAL;
1398                 }
1399
1400                 f_pdata = &cqspi->f_pdata[cs];
1401                 f_pdata->cqspi = cqspi;
1402                 f_pdata->cs = cs;
1403
1404                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1405                 if (ret)
1406                         return ret;
1407         }
1408
1409         return 0;
1410 }
1411
1412 static int cqspi_probe(struct platform_device *pdev)
1413 {
1414         const struct cqspi_driver_platdata *ddata;
1415         struct reset_control *rstc, *rstc_ocp;
1416         struct device *dev = &pdev->dev;
1417         struct spi_master *master;
1418         struct resource *res_ahb;
1419         struct cqspi_st *cqspi;
1420         struct resource *res;
1421         int ret;
1422         int irq;
1423
1424         master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1425         if (!master) {
1426                 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1427                 return -ENOMEM;
1428         }
1429         master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1430         master->mem_ops = &cqspi_mem_ops;
1431         master->dev.of_node = pdev->dev.of_node;
1432
1433         cqspi = spi_master_get_devdata(master);
1434
1435         cqspi->pdev = pdev;
1436
1437         /* Obtain configuration from OF. */
1438         ret = cqspi_of_get_pdata(cqspi);
1439         if (ret) {
1440                 dev_err(dev, "Cannot get mandatory OF data.\n");
1441                 ret = -ENODEV;
1442                 goto probe_master_put;
1443         }
1444
1445         /* Obtain QSPI clock. */
1446         cqspi->clk = devm_clk_get(dev, NULL);
1447         if (IS_ERR(cqspi->clk)) {
1448                 dev_err(dev, "Cannot claim QSPI clock.\n");
1449                 ret = PTR_ERR(cqspi->clk);
1450                 goto probe_master_put;
1451         }
1452
1453         /* Obtain and remap controller address. */
1454         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1455         cqspi->iobase = devm_ioremap_resource(dev, res);
1456         if (IS_ERR(cqspi->iobase)) {
1457                 dev_err(dev, "Cannot remap controller address.\n");
1458                 ret = PTR_ERR(cqspi->iobase);
1459                 goto probe_master_put;
1460         }
1461
1462         /* Obtain and remap AHB address. */
1463         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1464         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1465         if (IS_ERR(cqspi->ahb_base)) {
1466                 dev_err(dev, "Cannot remap AHB address.\n");
1467                 ret = PTR_ERR(cqspi->ahb_base);
1468                 goto probe_master_put;
1469         }
1470         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1471         cqspi->ahb_size = resource_size(res_ahb);
1472
1473         init_completion(&cqspi->transfer_complete);
1474
1475         /* Obtain IRQ line. */
1476         irq = platform_get_irq(pdev, 0);
1477         if (irq < 0) {
1478                 ret = -ENXIO;
1479                 goto probe_master_put;
1480         }
1481
1482         pm_runtime_enable(dev);
1483         ret = pm_runtime_get_sync(dev);
1484         if (ret < 0) {
1485                 pm_runtime_put_noidle(dev);
1486                 goto probe_master_put;
1487         }
1488
1489         ret = clk_prepare_enable(cqspi->clk);
1490         if (ret) {
1491                 dev_err(dev, "Cannot enable QSPI clock.\n");
1492                 goto probe_clk_failed;
1493         }
1494
1495         /* Obtain QSPI reset control */
1496         rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1497         if (IS_ERR(rstc)) {
1498                 ret = PTR_ERR(rstc);
1499                 dev_err(dev, "Cannot get QSPI reset.\n");
1500                 goto probe_reset_failed;
1501         }
1502
1503         rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1504         if (IS_ERR(rstc_ocp)) {
1505                 ret = PTR_ERR(rstc_ocp);
1506                 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1507                 goto probe_reset_failed;
1508         }
1509
1510         reset_control_assert(rstc);
1511         reset_control_deassert(rstc);
1512
1513         reset_control_assert(rstc_ocp);
1514         reset_control_deassert(rstc_ocp);
1515
1516         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1517         master->max_speed_hz = cqspi->master_ref_clk_hz;
1518         ddata  = of_device_get_match_data(dev);
1519         if (ddata) {
1520                 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1521                         cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1522                                                 cqspi->master_ref_clk_hz);
1523                 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1524                         master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1525                 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1526                         cqspi->use_direct_mode = true;
1527         }
1528
1529         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1530                                pdev->name, cqspi);
1531         if (ret) {
1532                 dev_err(dev, "Cannot request IRQ.\n");
1533                 goto probe_reset_failed;
1534         }
1535
1536         cqspi_wait_idle(cqspi);
1537         cqspi_controller_init(cqspi);
1538         cqspi->current_cs = -1;
1539         cqspi->sclk = 0;
1540
1541         master->num_chipselect = cqspi->num_chipselect;
1542
1543         ret = cqspi_setup_flash(cqspi);
1544         if (ret) {
1545                 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1546                 goto probe_setup_failed;
1547         }
1548
1549         if (cqspi->use_direct_mode) {
1550                 ret = cqspi_request_mmap_dma(cqspi);
1551                 if (ret == -EPROBE_DEFER)
1552                         goto probe_setup_failed;
1553         }
1554
1555         ret = devm_spi_register_master(dev, master);
1556         if (ret) {
1557                 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1558                 goto probe_setup_failed;
1559         }
1560
1561         return 0;
1562 probe_setup_failed:
1563         cqspi_controller_enable(cqspi, 0);
1564 probe_reset_failed:
1565         clk_disable_unprepare(cqspi->clk);
1566 probe_clk_failed:
1567         pm_runtime_put_sync(dev);
1568         pm_runtime_disable(dev);
1569 probe_master_put:
1570         spi_master_put(master);
1571         return ret;
1572 }
1573
1574 static int cqspi_remove(struct platform_device *pdev)
1575 {
1576         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1577
1578         cqspi_controller_enable(cqspi, 0);
1579
1580         if (cqspi->rx_chan)
1581                 dma_release_channel(cqspi->rx_chan);
1582
1583         clk_disable_unprepare(cqspi->clk);
1584
1585         pm_runtime_put_sync(&pdev->dev);
1586         pm_runtime_disable(&pdev->dev);
1587
1588         return 0;
1589 }
1590
1591 #ifdef CONFIG_PM_SLEEP
1592 static int cqspi_suspend(struct device *dev)
1593 {
1594         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1595
1596         cqspi_controller_enable(cqspi, 0);
1597         return 0;
1598 }
1599
1600 static int cqspi_resume(struct device *dev)
1601 {
1602         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1603
1604         cqspi_controller_enable(cqspi, 1);
1605         return 0;
1606 }
1607
1608 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1609         .suspend = cqspi_suspend,
1610         .resume = cqspi_resume,
1611 };
1612
1613 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1614 #else
1615 #define CQSPI_DEV_PM_OPS        NULL
1616 #endif
1617
1618 static const struct cqspi_driver_platdata cdns_qspi = {
1619         .quirks = CQSPI_DISABLE_DAC_MODE,
1620 };
1621
1622 static const struct cqspi_driver_platdata k2g_qspi = {
1623         .quirks = CQSPI_NEEDS_WR_DELAY,
1624 };
1625
1626 static const struct cqspi_driver_platdata am654_ospi = {
1627         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1628         .quirks = CQSPI_NEEDS_WR_DELAY,
1629 };
1630
1631 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1632         .quirks = CQSPI_DISABLE_DAC_MODE,
1633 };
1634
1635 static const struct of_device_id cqspi_dt_ids[] = {
1636         {
1637                 .compatible = "cdns,qspi-nor",
1638                 .data = &cdns_qspi,
1639         },
1640         {
1641                 .compatible = "ti,k2g-qspi",
1642                 .data = &k2g_qspi,
1643         },
1644         {
1645                 .compatible = "ti,am654-ospi",
1646                 .data = &am654_ospi,
1647         },
1648         {
1649                 .compatible = "intel,lgm-qspi",
1650                 .data = &intel_lgm_qspi,
1651         },
1652         { /* end of table */ }
1653 };
1654
1655 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1656
1657 static struct platform_driver cqspi_platform_driver = {
1658         .probe = cqspi_probe,
1659         .remove = cqspi_remove,
1660         .driver = {
1661                 .name = CQSPI_NAME,
1662                 .pm = CQSPI_DEV_PM_OPS,
1663                 .of_match_table = cqspi_dt_ids,
1664         },
1665 };
1666
1667 module_platform_driver(cqspi_platform_driver);
1668
1669 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1670 MODULE_LICENSE("GPL v2");
1671 MODULE_ALIAS("platform:" CQSPI_NAME);
1672 MODULE_AUTHOR("Ley Foon Tan <[email protected]>");
1673 MODULE_AUTHOR("Graham Moore <[email protected]>");
1674 MODULE_AUTHOR("Vadivel Murugan R <[email protected]>");
1675 MODULE_AUTHOR("Vignesh Raghavendra <[email protected]>");
1676 MODULE_AUTHOR("Pratyush Yadav <[email protected]>");