drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "umc_v6_1.h"
  24 #include "amdgpu_ras.h"
  25 #include "amdgpu.h"
  26
  27 #include "rsmu/rsmu_0_0_2_offset.h"
  28 #include "rsmu/rsmu_0_0_2_sh_mask.h"
  29 #include "umc/umc_6_1_1_offset.h"
  30 #include "umc/umc_6_1_1_sh_mask.h"
  31
  32 static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
  33                                            uint32_t umc_instance)
  34 {
  35         uint32_t rsmu_umc_index;
  36
  37         rsmu_umc_index = RREG32_SOC15(RSMU, 0,
  38                         mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
  39         rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
  40                         RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
  41                         RSMU_UMC_INDEX_MODE_EN, 1);
  42         rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
  43                         RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
  44                         RSMU_UMC_INDEX_INSTANCE, umc_instance);
  45         rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
  46                         RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
  47                         RSMU_UMC_INDEX_WREN, 1 << umc_instance);
  48         WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
  49                                 rsmu_umc_index);
  50 }
  51
  52 static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
  53 {
  54         WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
  55                         RSMU_UMC_INDEX_MODE_EN, 0);
  56 }
  57
  58 static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
  59                                                    uint32_t umc_reg_offset,
  60                                                    unsigned long *error_count)
  61 {
  62         uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
  63         uint32_t ecc_err_cnt, ecc_err_cnt_addr;
  64         uint64_t mc_umc_status;
  65         uint32_t mc_umc_status_addr;
  66
  67         ecc_err_cnt_sel_addr =
  68                 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
  69         ecc_err_cnt_addr =
  70                 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
  71         mc_umc_status_addr =
  72                 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
  73
  74         /* select the lower chip and check the error count */
  75         ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
  76         ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
  77                                         EccErrCntCsSel, 0);
  78         WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
  79         ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
  80         *error_count +=
  81                 REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
  82         /* clear the lower chip err count */
  83         WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
  84
  85         /* select the higher chip and check the err counter */
  86         ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
  87                                         EccErrCntCsSel, 1);
  88         WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
  89         ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
  90         *error_count +=
  91                 REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
  92         /* clear the higher chip err count */
  93         WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
  94
  95         /* check for SRAM correctable error
  96           MCUMC_STATUS is a 64 bit register */
  97         mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
  98         if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
  99             REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
 100             REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
 101                 *error_count += 1;
 102 }
 103
 104 static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev,
 105                                                       uint32_t umc_reg_offset,
 106                                                       unsigned long *error_count)
 107 {
 108         uint64_t mc_umc_status;
 109         uint32_t mc_umc_status_addr;
 110
 111         mc_umc_status_addr =
 112                 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
 113
 114         /* check the MCUMC_STATUS */
 115         mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
 116         if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
 117                 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
 118                 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
 119                 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
 120                 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
 121                 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
 122                 *error_count += 1;
 123 }
 124
 125 static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
 126                                            void *ras_error_status)
 127 {
 128         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 129         uint32_t umc_inst, channel_inst, umc_reg_offset, mc_umc_status_addr;
 130
 131         mc_umc_status_addr =
 132                 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
 133
 134         for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) {
 135                 /* enable the index mode to query eror count per channel */
 136                 umc_v6_1_enable_umc_index_mode(adev, umc_inst);
 137                 for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) {
 138                         /* calc the register offset according to channel instance */
 139                         umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst;
 140                         umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
 141                                                                &(err_data->ce_count));
 142                         umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
 143                                                                   &(err_data->ue_count));
 144                         /* clear umc status */
 145                         WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
 146                 }
 147         }
 148         umc_v6_1_disable_umc_index_mode(adev);
 149 }
 150
 151 const struct amdgpu_umc_funcs umc_v6_1_funcs = {
 152         .query_ras_error_count = umc_v6_1_query_ras_error_count,
 153 };