drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <[email protected]>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "radeon/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "radeon/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_vce.bin"
  54 #define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
  55 #define FIRMWARE_POLARIS12         "amdgpu/polaris12_vce.bin"
  56
  57 #define FIRMWARE_VEGA10         "amdgpu/vega10_vce.bin"
  58
  59 #ifdef CONFIG_DRM_AMDGPU_CIK
  60 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  61 MODULE_FIRMWARE(FIRMWARE_KABINI);
  62 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  63 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  64 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  65 #endif
  66 MODULE_FIRMWARE(FIRMWARE_TONGA);
  67 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  68 MODULE_FIRMWARE(FIRMWARE_FIJI);
  69 MODULE_FIRMWARE(FIRMWARE_STONEY);
  70 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  71 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  72 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
  73
  74 MODULE_FIRMWARE(FIRMWARE_VEGA10);
  75
  76 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  77
  78 /**
  79  * amdgpu_vce_init - allocate memory, load vce firmware
  80  *
  81  * @adev: amdgpu_device pointer
  82  *
  83  * First step to get VCE online, allocate memory and load the firmware
  84  */
  85 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  86 {
  87         struct amdgpu_ring *ring;
  88         struct amd_sched_rq *rq;
  89         const char *fw_name;
  90         const struct common_firmware_header *hdr;
  91         unsigned ucode_version, version_major, version_minor, binary_id;
  92         int i, r;
  93
  94         switch (adev->asic_type) {
  95 #ifdef CONFIG_DRM_AMDGPU_CIK
  96         case CHIP_BONAIRE:
  97                 fw_name = FIRMWARE_BONAIRE;
  98                 break;
  99         case CHIP_KAVERI:
 100                 fw_name = FIRMWARE_KAVERI;
 101                 break;
 102         case CHIP_KABINI:
 103                 fw_name = FIRMWARE_KABINI;
 104                 break;
 105         case CHIP_HAWAII:
 106                 fw_name = FIRMWARE_HAWAII;
 107                 break;
 108         case CHIP_MULLINS:
 109                 fw_name = FIRMWARE_MULLINS;
 110                 break;
 111 #endif
 112         case CHIP_TONGA:
 113                 fw_name = FIRMWARE_TONGA;
 114                 break;
 115         case CHIP_CARRIZO:
 116                 fw_name = FIRMWARE_CARRIZO;
 117                 break;
 118         case CHIP_FIJI:
 119                 fw_name = FIRMWARE_FIJI;
 120                 break;
 121         case CHIP_STONEY:
 122                 fw_name = FIRMWARE_STONEY;
 123                 break;
 124         case CHIP_POLARIS10:
 125                 fw_name = FIRMWARE_POLARIS10;
 126                 break;
 127         case CHIP_POLARIS11:
 128                 fw_name = FIRMWARE_POLARIS11;
 129                 break;
 130         case CHIP_VEGA10:
 131                 fw_name = FIRMWARE_VEGA10;
 132                 break;
 133         case CHIP_POLARIS12:
 134                 fw_name = FIRMWARE_POLARIS12;
 135                 break;
 136
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 142         if (r) {
 143                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 144                         fw_name);
 145                 return r;
 146         }
 147
 148         r = amdgpu_ucode_validate(adev->vce.fw);
 149         if (r) {
 150                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 151                         fw_name);
 152                 release_firmware(adev->vce.fw);
 153                 adev->vce.fw = NULL;
 154                 return r;
 155         }
 156
 157         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 158
 159         ucode_version = le32_to_cpu(hdr->ucode_version);
 160         version_major = (ucode_version >> 20) & 0xfff;
 161         version_minor = (ucode_version >> 8) & 0xfff;
 162         binary_id = ucode_version & 0xff;
 163         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 164                 version_major, version_minor, binary_id);
 165         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 166                                 (binary_id << 8));
 167
 168         /* allocate firmware, stack and heap BO */
 169
 170         r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
 171                              AMDGPU_GEM_DOMAIN_VRAM,
 172                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 173                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 174                              NULL, NULL, &adev->vce.vcpu_bo);
 175         if (r) {
 176                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 177                 return r;
 178         }
 179
 180         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 181         if (r) {
 182                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 183                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 184                 return r;
 185         }
 186
 187         r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 188                           &adev->vce.gpu_addr);
 189         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 190         if (r) {
 191                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 192                 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
 193                 return r;
 194         }
 195
 196
 197         ring = &adev->vce.ring[0];
 198         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 199         r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
 200                                   rq, amdgpu_sched_jobs);
 201         if (r != 0) {
 202                 DRM_ERROR("Failed setting up VCE run queue.\n");
 203                 return r;
 204         }
 205
 206         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 207                 atomic_set(&adev->vce.handles[i], 0);
 208                 adev->vce.filp[i] = NULL;
 209         }
 210
 211         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 212         mutex_init(&adev->vce.idle_mutex);
 213
 214         return 0;
 215 }
 216
 217 /**
 218  * amdgpu_vce_fini - free memory
 219  *
 220  * @adev: amdgpu_device pointer
 221  *
 222  * Last step on VCE teardown, free firmware memory
 223  */
 224 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 225 {
 226         unsigned i;
 227
 228         if (adev->vce.vcpu_bo == NULL)
 229                 return 0;
 230
 231         amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
 232
 233         amdgpu_bo_unref(&adev->vce.vcpu_bo);
 234
 235         for (i = 0; i < adev->vce.num_rings; i++)
 236                 amdgpu_ring_fini(&adev->vce.ring[i]);
 237
 238         release_firmware(adev->vce.fw);
 239         mutex_destroy(&adev->vce.idle_mutex);
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * amdgpu_vce_suspend - unpin VCE fw memory
 246  *
 247  * @adev: amdgpu_device pointer
 248  *
 249  */
 250 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 251 {
 252         int i;
 253
 254         if (adev->vce.vcpu_bo == NULL)
 255                 return 0;
 256
 257         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 258                 if (atomic_read(&adev->vce.handles[i]))
 259                         break;
 260
 261         if (i == AMDGPU_MAX_VCE_HANDLES)
 262                 return 0;
 263
 264         cancel_delayed_work_sync(&adev->vce.idle_work);
 265         /* TODO: suspending running encoding sessions isn't supported */
 266         return -EINVAL;
 267 }
 268
 269 /**
 270  * amdgpu_vce_resume - pin VCE fw memory
 271  *
 272  * @adev: amdgpu_device pointer
 273  *
 274  */
 275 int amdgpu_vce_resume(struct amdgpu_device *adev)
 276 {
 277         void *cpu_addr;
 278         const struct common_firmware_header *hdr;
 279         unsigned offset;
 280         int r;
 281
 282         if (adev->vce.vcpu_bo == NULL)
 283                 return -EINVAL;
 284
 285         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 286         if (r) {
 287                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 288                 return r;
 289         }
 290
 291         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 292         if (r) {
 293                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 294                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 295                 return r;
 296         }
 297
 298         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 299         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 300         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 301                     adev->vce.fw->size - offset);
 302
 303         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 304
 305         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * amdgpu_vce_idle_work_handler - power off VCE
 312  *
 313  * @work: pointer to work structure
 314  *
 315  * power of VCE when it's not used any more
 316  */
 317 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 318 {
 319         struct amdgpu_device *adev =
 320                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 321         unsigned i, count = 0;
 322
 323         if (amdgpu_sriov_vf(adev))
 324                 return;
 325
 326         for (i = 0; i < adev->vce.num_rings; i++)
 327                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 328
 329         if (count == 0) {
 330                 if (adev->pm.dpm_enabled) {
 331                         amdgpu_dpm_enable_vce(adev, false);
 332                 } else {
 333                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 334                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 335                                                             AMD_PG_STATE_GATE);
 336                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 337                                                             AMD_CG_STATE_GATE);
 338                 }
 339         } else {
 340                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 341         }
 342 }
 343
 344 /**
 345  * amdgpu_vce_ring_begin_use - power up VCE
 346  *
 347  * @ring: amdgpu ring
 348  *
 349  * Make sure VCE is powerd up when we want to use it
 350  */
 351 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 352 {
 353         struct amdgpu_device *adev = ring->adev;
 354         bool set_clocks;
 355
 356         if (amdgpu_sriov_vf(adev))
 357                 return;
 358
 359         mutex_lock(&adev->vce.idle_mutex);
 360         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 361         if (set_clocks) {
 362                 if (adev->pm.dpm_enabled) {
 363                         amdgpu_dpm_enable_vce(adev, true);
 364                 } else {
 365                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 366                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 367                                                             AMD_CG_STATE_UNGATE);
 368                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 369                                                             AMD_PG_STATE_UNGATE);
 370
 371                 }
 372         }
 373         mutex_unlock(&adev->vce.idle_mutex);
 374 }
 375
 376 /**
 377  * amdgpu_vce_ring_end_use - power VCE down
 378  *
 379  * @ring: amdgpu ring
 380  *
 381  * Schedule work to power VCE down again
 382  */
 383 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 384 {
 385         schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 386 }
 387
 388 /**
 389  * amdgpu_vce_free_handles - free still open VCE handles
 390  *
 391  * @adev: amdgpu_device pointer
 392  * @filp: drm file pointer
 393  *
 394  * Close all VCE handles still open by this file pointer
 395  */
 396 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 397 {
 398         struct amdgpu_ring *ring = &adev->vce.ring[0];
 399         int i, r;
 400         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 401                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 402
 403                 if (!handle || adev->vce.filp[i] != filp)
 404                         continue;
 405
 406                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 407                 if (r)
 408                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 409
 410                 adev->vce.filp[i] = NULL;
 411                 atomic_set(&adev->vce.handles[i], 0);
 412         }
 413 }
 414
 415 /**
 416  * amdgpu_vce_get_create_msg - generate a VCE create msg
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @ring: ring we should submit the msg to
 420  * @handle: VCE session handle to use
 421  * @fence: optional fence to return
 422  *
 423  * Open up a stream for HW test
 424  */
 425 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 426                               struct dma_fence **fence)
 427 {
 428         const unsigned ib_size_dw = 1024;
 429         struct amdgpu_job *job;
 430         struct amdgpu_ib *ib;
 431         struct dma_fence *f = NULL;
 432         uint64_t dummy;
 433         int i, r;
 434
 435         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 436         if (r)
 437                 return r;
 438
 439         ib = &job->ibs[0];
 440
 441         dummy = ib->gpu_addr + 1024;
 442
 443         /* stitch together an VCE create msg */
 444         ib->length_dw = 0;
 445         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 446         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 447         ib->ptr[ib->length_dw++] = handle;
 448
 449         if ((ring->adev->vce.fw_version >> 24) >= 52)
 450                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 451         else
 452                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 453         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 454         ib->ptr[ib->length_dw++] = 0x00000000;
 455         ib->ptr[ib->length_dw++] = 0x00000042;
 456         ib->ptr[ib->length_dw++] = 0x0000000a;
 457         ib->ptr[ib->length_dw++] = 0x00000001;
 458         ib->ptr[ib->length_dw++] = 0x00000080;
 459         ib->ptr[ib->length_dw++] = 0x00000060;
 460         ib->ptr[ib->length_dw++] = 0x00000100;
 461         ib->ptr[ib->length_dw++] = 0x00000100;
 462         ib->ptr[ib->length_dw++] = 0x0000000c;
 463         ib->ptr[ib->length_dw++] = 0x00000000;
 464         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 465                 ib->ptr[ib->length_dw++] = 0x00000000;
 466                 ib->ptr[ib->length_dw++] = 0x00000000;
 467                 ib->ptr[ib->length_dw++] = 0x00000000;
 468                 ib->ptr[ib->length_dw++] = 0x00000000;
 469         }
 470
 471         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 472         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 473         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 474         ib->ptr[ib->length_dw++] = dummy;
 475         ib->ptr[ib->length_dw++] = 0x00000001;
 476
 477         for (i = ib->length_dw; i < ib_size_dw; ++i)
 478                 ib->ptr[i] = 0x0;
 479
 480         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 481         job->fence = dma_fence_get(f);
 482         if (r)
 483                 goto err;
 484
 485         amdgpu_job_free(job);
 486         if (fence)
 487                 *fence = dma_fence_get(f);
 488         dma_fence_put(f);
 489         return 0;
 490
 491 err:
 492         amdgpu_job_free(job);
 493         return r;
 494 }
 495
 496 /**
 497  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 498  *
 499  * @adev: amdgpu_device pointer
 500  * @ring: ring we should submit the msg to
 501  * @handle: VCE session handle to use
 502  * @fence: optional fence to return
 503  *
 504  * Close up a stream for HW test or if userspace failed to do so
 505  */
 506 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 507                                bool direct, struct dma_fence **fence)
 508 {
 509         const unsigned ib_size_dw = 1024;
 510         struct amdgpu_job *job;
 511         struct amdgpu_ib *ib;
 512         struct dma_fence *f = NULL;
 513         int i, r;
 514
 515         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 516         if (r)
 517                 return r;
 518
 519         ib = &job->ibs[0];
 520
 521         /* stitch together an VCE destroy msg */
 522         ib->length_dw = 0;
 523         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 524         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 525         ib->ptr[ib->length_dw++] = handle;
 526
 527         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 528         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 529         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 530         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 531         ib->ptr[ib->length_dw++] = 0x00000000;
 532         ib->ptr[ib->length_dw++] = 0x00000000;
 533         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 534         ib->ptr[ib->length_dw++] = 0x00000000;
 535
 536         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 537         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 538
 539         for (i = ib->length_dw; i < ib_size_dw; ++i)
 540                 ib->ptr[i] = 0x0;
 541
 542         if (direct) {
 543                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 544                 job->fence = dma_fence_get(f);
 545                 if (r)
 546                         goto err;
 547
 548                 amdgpu_job_free(job);
 549         } else {
 550                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 551                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 552                 if (r)
 553                         goto err;
 554         }
 555
 556         if (fence)
 557                 *fence = dma_fence_get(f);
 558         dma_fence_put(f);
 559         return 0;
 560
 561 err:
 562         amdgpu_job_free(job);
 563         return r;
 564 }
 565
 566 /**
 567  * amdgpu_vce_cs_reloc - command submission relocation
 568  *
 569  * @p: parser context
 570  * @lo: address of lower dword
 571  * @hi: address of higher dword
 572  * @size: minimum size
 573  *
 574  * Patch relocation inside command stream with real buffer address
 575  */
 576 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 577                                int lo, int hi, unsigned size, uint32_t index)
 578 {
 579         struct amdgpu_bo_va_mapping *mapping;
 580         struct amdgpu_bo *bo;
 581         uint64_t addr;
 582
 583         if (index == 0xffffffff)
 584                 index = 0;
 585
 586         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 587                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 588         addr += ((uint64_t)size) * ((uint64_t)index);
 589
 590         mapping = amdgpu_cs_find_mapping(p, addr, &bo);
 591         if (mapping == NULL) {
 592                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 593                           addr, lo, hi, size, index);
 594                 return -EINVAL;
 595         }
 596
 597         if ((addr + (uint64_t)size) >
 598             (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 599                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 600                           addr, lo, hi);
 601                 return -EINVAL;
 602         }
 603
 604         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 605         addr += amdgpu_bo_gpu_offset(bo);
 606         addr -= ((uint64_t)size) * ((uint64_t)index);
 607
 608         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 609         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 610
 611         return 0;
 612 }
 613
 614 /**
 615  * amdgpu_vce_validate_handle - validate stream handle
 616  *
 617  * @p: parser context
 618  * @handle: handle to validate
 619  * @allocated: allocated a new handle?
 620  *
 621  * Validates the handle and return the found session index or -EINVAL
 622  * we we don't have another free session index.
 623  */
 624 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 625                                       uint32_t handle, uint32_t *allocated)
 626 {
 627         unsigned i;
 628
 629         /* validate the handle */
 630         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 631                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 632                         if (p->adev->vce.filp[i] != p->filp) {
 633                                 DRM_ERROR("VCE handle collision detected!\n");
 634                                 return -EINVAL;
 635                         }
 636                         return i;
 637                 }
 638         }
 639
 640         /* handle not found try to alloc a new one */
 641         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 642                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 643                         p->adev->vce.filp[i] = p->filp;
 644                         p->adev->vce.img_size[i] = 0;
 645                         *allocated |= 1 << i;
 646                         return i;
 647                 }
 648         }
 649
 650         DRM_ERROR("No more free VCE handles!\n");
 651         return -EINVAL;
 652 }
 653
 654 /**
 655  * amdgpu_vce_cs_parse - parse and validate the command stream
 656  *
 657  * @p: parser context
 658  *
 659  */
 660 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 661 {
 662         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 663         unsigned fb_idx = 0, bs_idx = 0;
 664         int session_idx = -1;
 665         uint32_t destroyed = 0;
 666         uint32_t created = 0;
 667         uint32_t allocated = 0;
 668         uint32_t tmp, handle = 0;
 669         uint32_t *size = &tmp;
 670         int i, r, idx = 0;
 671
 672         p->job->vm = NULL;
 673         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 674
 675         r = amdgpu_cs_sysvm_access_required(p);
 676         if (r)
 677                 return r;
 678
 679         while (idx < ib->length_dw) {
 680                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 681                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 682
 683                 if ((len < 8) || (len & 3)) {
 684                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 685                         r = -EINVAL;
 686                         goto out;
 687                 }
 688
 689                 switch (cmd) {
 690                 case 0x00000001: /* session */
 691                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 692                         session_idx = amdgpu_vce_validate_handle(p, handle,
 693                                                                  &allocated);
 694                         if (session_idx < 0) {
 695                                 r = session_idx;
 696                                 goto out;
 697                         }
 698                         size = &p->adev->vce.img_size[session_idx];
 699                         break;
 700
 701                 case 0x00000002: /* task info */
 702                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 703                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 704                         break;
 705
 706                 case 0x01000001: /* create */
 707                         created |= 1 << session_idx;
 708                         if (destroyed & (1 << session_idx)) {
 709                                 destroyed &= ~(1 << session_idx);
 710                                 allocated |= 1 << session_idx;
 711
 712                         } else if (!(allocated & (1 << session_idx))) {
 713                                 DRM_ERROR("Handle already in use!\n");
 714                                 r = -EINVAL;
 715                                 goto out;
 716                         }
 717
 718                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 719                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 720                                 8 * 3 / 2;
 721                         break;
 722
 723                 case 0x04000001: /* config extension */
 724                 case 0x04000002: /* pic control */
 725                 case 0x04000005: /* rate control */
 726                 case 0x04000007: /* motion estimation */
 727                 case 0x04000008: /* rdo */
 728                 case 0x04000009: /* vui */
 729                 case 0x05000002: /* auxiliary buffer */
 730                 case 0x05000009: /* clock table */
 731                         break;
 732
 733                 case 0x0500000c: /* hw config */
 734                         switch (p->adev->asic_type) {
 735 #ifdef CONFIG_DRM_AMDGPU_CIK
 736                         case CHIP_KAVERI:
 737                         case CHIP_MULLINS:
 738 #endif
 739                         case CHIP_CARRIZO:
 740                                 break;
 741                         default:
 742                                 r = -EINVAL;
 743                                 goto out;
 744                         }
 745                         break;
 746
 747                 case 0x03000001: /* encode */
 748                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 749                                                 *size, 0);
 750                         if (r)
 751                                 goto out;
 752
 753                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 754                                                 *size / 3, 0);
 755                         if (r)
 756                                 goto out;
 757                         break;
 758
 759                 case 0x02000001: /* destroy */
 760                         destroyed |= 1 << session_idx;
 761                         break;
 762
 763                 case 0x05000001: /* context buffer */
 764                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 765                                                 *size * 2, 0);
 766                         if (r)
 767                                 goto out;
 768                         break;
 769
 770                 case 0x05000004: /* video bitstream buffer */
 771                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 772                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 773                                                 tmp, bs_idx);
 774                         if (r)
 775                                 goto out;
 776                         break;
 777
 778                 case 0x05000005: /* feedback buffer */
 779                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 780                                                 4096, fb_idx);
 781                         if (r)
 782                                 goto out;
 783                         break;
 784
 785                 default:
 786                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 787                         r = -EINVAL;
 788                         goto out;
 789                 }
 790
 791                 if (session_idx == -1) {
 792                         DRM_ERROR("no session command at start of IB\n");
 793                         r = -EINVAL;
 794                         goto out;
 795                 }
 796
 797                 idx += len / 4;
 798         }
 799
 800         if (allocated & ~created) {
 801                 DRM_ERROR("New session without create command!\n");
 802                 r = -ENOENT;
 803         }
 804
 805 out:
 806         if (!r) {
 807                 /* No error, free all destroyed handle slots */
 808                 tmp = destroyed;
 809         } else {
 810                 /* Error during parsing, free all allocated handle slots */
 811                 tmp = allocated;
 812         }
 813
 814         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 815                 if (tmp & (1 << i))
 816                         atomic_set(&p->adev->vce.handles[i], 0);
 817
 818         return r;
 819 }
 820
 821 /**
 822  * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
 823  *
 824  * @p: parser context
 825  *
 826  */
 827 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 828 {
 829         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 830         int session_idx = -1;
 831         uint32_t destroyed = 0;
 832         uint32_t created = 0;
 833         uint32_t allocated = 0;
 834         uint32_t tmp, handle = 0;
 835         int i, r = 0, idx = 0;
 836
 837         while (idx < ib->length_dw) {
 838                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 839                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 840
 841                 if ((len < 8) || (len & 3)) {
 842                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 843                         r = -EINVAL;
 844                         goto out;
 845                 }
 846
 847                 switch (cmd) {
 848                 case 0x00000001: /* session */
 849                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 850                         session_idx = amdgpu_vce_validate_handle(p, handle,
 851                                                                  &allocated);
 852                         if (session_idx < 0) {
 853                                 r = session_idx;
 854                                 goto out;
 855                         }
 856                         break;
 857
 858                 case 0x01000001: /* create */
 859                         created |= 1 << session_idx;
 860                         if (destroyed & (1 << session_idx)) {
 861                                 destroyed &= ~(1 << session_idx);
 862                                 allocated |= 1 << session_idx;
 863
 864                         } else if (!(allocated & (1 << session_idx))) {
 865                                 DRM_ERROR("Handle already in use!\n");
 866                                 r = -EINVAL;
 867                                 goto out;
 868                         }
 869
 870                         break;
 871
 872                 case 0x02000001: /* destroy */
 873                         destroyed |= 1 << session_idx;
 874                         break;
 875
 876                 default:
 877                         break;
 878                 }
 879
 880                 if (session_idx == -1) {
 881                         DRM_ERROR("no session command at start of IB\n");
 882                         r = -EINVAL;
 883                         goto out;
 884                 }
 885
 886                 idx += len / 4;
 887         }
 888
 889         if (allocated & ~created) {
 890                 DRM_ERROR("New session without create command!\n");
 891                 r = -ENOENT;
 892         }
 893
 894 out:
 895         if (!r) {
 896                 /* No error, free all destroyed handle slots */
 897                 tmp = destroyed;
 898                 amdgpu_ib_free(p->adev, ib, NULL);
 899         } else {
 900                 /* Error during parsing, free all allocated handle slots */
 901                 tmp = allocated;
 902         }
 903
 904         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 905                 if (tmp & (1 << i))
 906                         atomic_set(&p->adev->vce.handles[i], 0);
 907
 908         return r;
 909 }
 910
 911 /**
 912  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 913  *
 914  * @ring: engine to use
 915  * @ib: the IB to execute
 916  *
 917  */
 918 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
 919                              unsigned vm_id, bool ctx_switch)
 920 {
 921         amdgpu_ring_write(ring, VCE_CMD_IB);
 922         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 923         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 924         amdgpu_ring_write(ring, ib->length_dw);
 925 }
 926
 927 /**
 928  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
 929  *
 930  * @ring: engine to use
 931  * @fence: the fence
 932  *
 933  */
 934 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 935                                 unsigned flags)
 936 {
 937         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 938
 939         amdgpu_ring_write(ring, VCE_CMD_FENCE);
 940         amdgpu_ring_write(ring, addr);
 941         amdgpu_ring_write(ring, upper_32_bits(addr));
 942         amdgpu_ring_write(ring, seq);
 943         amdgpu_ring_write(ring, VCE_CMD_TRAP);
 944         amdgpu_ring_write(ring, VCE_CMD_END);
 945 }
 946
 947 /**
 948  * amdgpu_vce_ring_test_ring - test if VCE ring is working
 949  *
 950  * @ring: the engine to test on
 951  *
 952  */
 953 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
 954 {
 955         struct amdgpu_device *adev = ring->adev;
 956         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 957         unsigned i;
 958         int r, timeout = adev->usec_timeout;
 959
 960         /* workaround VCE ring test slow issue for sriov*/
 961         if (amdgpu_sriov_vf(adev))
 962                 timeout *= 10;
 963
 964         r = amdgpu_ring_alloc(ring, 16);
 965         if (r) {
 966                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
 967                           ring->idx, r);
 968                 return r;
 969         }
 970         amdgpu_ring_write(ring, VCE_CMD_END);
 971         amdgpu_ring_commit(ring);
 972
 973         for (i = 0; i < timeout; i++) {
 974                 if (amdgpu_ring_get_rptr(ring) != rptr)
 975                         break;
 976                 DRM_UDELAY(1);
 977         }
 978
 979         if (i < timeout) {
 980                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 981                          ring->idx, i);
 982         } else {
 983                 DRM_ERROR("amdgpu: ring %d test failed\n",
 984                           ring->idx);
 985                 r = -ETIMEDOUT;
 986         }
 987
 988         return r;
 989 }
 990
 991 /**
 992  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
 993  *
 994  * @ring: the engine to test on
 995  *
 996  */
 997 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 998 {
 999         struct dma_fence *fence = NULL;
1000         long r;
1001
1002         /* skip vce ring1/2 ib test for now, since it's not reliable */
1003         if (ring != &ring->adev->vce.ring[0])
1004                 return 0;
1005
1006         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1007         if (r) {
1008                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1009                 goto error;
1010         }
1011
1012         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1013         if (r) {
1014                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1015                 goto error;
1016         }
1017
1018         r = dma_fence_wait_timeout(fence, false, timeout);
1019         if (r == 0) {
1020                 DRM_ERROR("amdgpu: IB test timed out.\n");
1021                 r = -ETIMEDOUT;
1022         } else if (r < 0) {
1023                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1024         } else {
1025                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1026                 r = 0;
1027         }
1028 error:
1029         dma_fence_put(fence);
1030         return r;
1031 }