6 * PCI Express I/O Virtualization (IOV) support.
8 * Address Translation Service 1.0
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/mutex.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
18 #define VIRTFN_ID_LEN 16
20 static inline u8 virtfn_bus(struct pci_dev *dev, int id)
22 return dev->bus->number + ((dev->devfn + dev->sriov->offset +
23 dev->sriov->stride * id) >> 8);
26 static inline u8 virtfn_devfn(struct pci_dev *dev, int id)
28 return (dev->devfn + dev->sriov->offset +
29 dev->sriov->stride * id) & 0xff;
32 static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
35 struct pci_bus *child;
37 if (bus->number == busnr)
40 child = pci_find_bus(pci_domain_nr(bus), busnr);
44 child = pci_add_new_bus(bus, NULL, busnr);
48 child->subordinate = busnr;
49 child->dev.parent = bus->bridge;
50 rc = pci_bus_add_child(child);
52 pci_remove_bus(child);
59 static void virtfn_remove_bus(struct pci_bus *bus, int busnr)
61 struct pci_bus *child;
63 if (bus->number == busnr)
66 child = pci_find_bus(pci_domain_nr(bus), busnr);
69 if (list_empty(&child->devices))
70 pci_remove_bus(child);
73 static int virtfn_add(struct pci_dev *dev, int id, int reset)
78 char buf[VIRTFN_ID_LEN];
79 struct pci_dev *virtfn;
81 struct pci_sriov *iov = dev->sriov;
83 virtfn = alloc_pci_dev();
87 mutex_lock(&iov->dev->sriov->lock);
88 virtfn->bus = virtfn_add_bus(dev->bus, virtfn_bus(dev, id));
91 mutex_unlock(&iov->dev->sriov->lock);
94 virtfn->devfn = virtfn_devfn(dev, id);
95 virtfn->vendor = dev->vendor;
96 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_DID, &virtfn->device);
97 pci_setup_device(virtfn);
98 virtfn->dev.parent = dev->dev.parent;
100 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
101 res = dev->resource + PCI_IOV_RESOURCES + i;
104 virtfn->resource[i].name = pci_name(virtfn);
105 virtfn->resource[i].flags = res->flags;
106 size = resource_size(res);
107 do_div(size, iov->total);
108 virtfn->resource[i].start = res->start + size * id;
109 virtfn->resource[i].end = virtfn->resource[i].start + size - 1;
110 rc = request_resource(res, &virtfn->resource[i]);
115 __pci_reset_function(virtfn);
117 pci_device_add(virtfn, virtfn->bus);
118 mutex_unlock(&iov->dev->sriov->lock);
120 virtfn->physfn = pci_dev_get(dev);
121 virtfn->is_virtfn = 1;
123 rc = pci_bus_add_device(virtfn);
126 sprintf(buf, "virtfn%u", id);
127 rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf);
130 rc = sysfs_create_link(&virtfn->dev.kobj, &dev->dev.kobj, "physfn");
134 kobject_uevent(&virtfn->dev.kobj, KOBJ_CHANGE);
139 sysfs_remove_link(&dev->dev.kobj, buf);
142 mutex_lock(&iov->dev->sriov->lock);
143 pci_remove_bus_device(virtfn);
144 virtfn_remove_bus(dev->bus, virtfn_bus(dev, id));
145 mutex_unlock(&iov->dev->sriov->lock);
150 static void virtfn_remove(struct pci_dev *dev, int id, int reset)
152 char buf[VIRTFN_ID_LEN];
154 struct pci_dev *virtfn;
155 struct pci_sriov *iov = dev->sriov;
157 bus = pci_find_bus(pci_domain_nr(dev->bus), virtfn_bus(dev, id));
161 virtfn = pci_get_slot(bus, virtfn_devfn(dev, id));
168 device_release_driver(&virtfn->dev);
169 __pci_reset_function(virtfn);
172 sprintf(buf, "virtfn%u", id);
173 sysfs_remove_link(&dev->dev.kobj, buf);
174 sysfs_remove_link(&virtfn->dev.kobj, "physfn");
176 mutex_lock(&iov->dev->sriov->lock);
177 pci_remove_bus_device(virtfn);
178 virtfn_remove_bus(dev->bus, virtfn_bus(dev, id));
179 mutex_unlock(&iov->dev->sriov->lock);
184 static int sriov_migration(struct pci_dev *dev)
187 struct pci_sriov *iov = dev->sriov;
192 if (!(iov->cap & PCI_SRIOV_CAP_VFM))
195 pci_read_config_word(dev, iov->pos + PCI_SRIOV_STATUS, &status);
196 if (!(status & PCI_SRIOV_STATUS_VFM))
199 schedule_work(&iov->mtask);
204 static void sriov_migration_task(struct work_struct *work)
209 struct pci_sriov *iov = container_of(work, struct pci_sriov, mtask);
211 for (i = iov->initial; i < iov->nr_virtfn; i++) {
212 state = readb(iov->mstate + i);
213 if (state == PCI_SRIOV_VFM_MI) {
214 writeb(PCI_SRIOV_VFM_AV, iov->mstate + i);
215 state = readb(iov->mstate + i);
216 if (state == PCI_SRIOV_VFM_AV)
217 virtfn_add(iov->self, i, 1);
218 } else if (state == PCI_SRIOV_VFM_MO) {
219 virtfn_remove(iov->self, i, 1);
220 writeb(PCI_SRIOV_VFM_UA, iov->mstate + i);
221 state = readb(iov->mstate + i);
222 if (state == PCI_SRIOV_VFM_AV)
223 virtfn_add(iov->self, i, 0);
227 pci_read_config_word(iov->self, iov->pos + PCI_SRIOV_STATUS, &status);
228 status &= ~PCI_SRIOV_STATUS_VFM;
229 pci_write_config_word(iov->self, iov->pos + PCI_SRIOV_STATUS, status);
232 static int sriov_enable_migration(struct pci_dev *dev, int nr_virtfn)
237 struct pci_sriov *iov = dev->sriov;
239 if (nr_virtfn <= iov->initial)
242 pci_read_config_dword(dev, iov->pos + PCI_SRIOV_VFM, &table);
243 bir = PCI_SRIOV_VFM_BIR(table);
244 if (bir > PCI_STD_RESOURCE_END)
247 table = PCI_SRIOV_VFM_OFFSET(table);
248 if (table + nr_virtfn > pci_resource_len(dev, bir))
251 pa = pci_resource_start(dev, bir) + table;
252 iov->mstate = ioremap(pa, nr_virtfn);
256 INIT_WORK(&iov->mtask, sriov_migration_task);
258 iov->ctrl |= PCI_SRIOV_CTRL_VFM | PCI_SRIOV_CTRL_INTR;
259 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
264 static void sriov_disable_migration(struct pci_dev *dev)
266 struct pci_sriov *iov = dev->sriov;
268 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFM | PCI_SRIOV_CTRL_INTR);
269 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
271 cancel_work_sync(&iov->mtask);
272 iounmap(iov->mstate);
275 static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
280 u16 offset, stride, initial;
281 struct resource *res;
282 struct pci_dev *pdev;
283 struct pci_sriov *iov = dev->sriov;
291 pci_read_config_word(dev, iov->pos + PCI_SRIOV_INITIAL_VF, &initial);
292 if (initial > iov->total ||
293 (!(iov->cap & PCI_SRIOV_CAP_VFM) && (initial != iov->total)))
296 if (nr_virtfn < 0 || nr_virtfn > iov->total ||
297 (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))
300 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
301 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset);
302 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride);
303 if (!offset || (nr_virtfn > 1 && !stride))
307 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
308 res = dev->resource + PCI_IOV_RESOURCES + i;
312 if (nres != iov->nres) {
313 dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n");
317 iov->offset = offset;
318 iov->stride = stride;
320 if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->subordinate) {
321 dev_err(&dev->dev, "SR-IOV: bus number out of range\n");
325 if (iov->link != dev->devfn) {
326 pdev = pci_get_slot(dev->bus, iov->link);
332 if (!pdev->is_physfn)
335 rc = sysfs_create_link(&dev->dev.kobj,
336 &pdev->dev.kobj, "dep_link");
341 iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
342 pci_block_user_cfg_access(dev);
343 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
345 pci_unblock_user_cfg_access(dev);
347 iov->initial = initial;
348 if (nr_virtfn < initial)
351 for (i = 0; i < initial; i++) {
352 rc = virtfn_add(dev, i, 0);
357 if (iov->cap & PCI_SRIOV_CAP_VFM) {
358 rc = sriov_enable_migration(dev, nr_virtfn);
363 kobject_uevent(&dev->dev.kobj, KOBJ_CHANGE);
364 iov->nr_virtfn = nr_virtfn;
369 for (j = 0; j < i; j++)
370 virtfn_remove(dev, j, 0);
372 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
373 pci_block_user_cfg_access(dev);
374 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
376 pci_unblock_user_cfg_access(dev);
378 if (iov->link != dev->devfn)
379 sysfs_remove_link(&dev->dev.kobj, "dep_link");
384 static void sriov_disable(struct pci_dev *dev)
387 struct pci_sriov *iov = dev->sriov;
392 if (iov->cap & PCI_SRIOV_CAP_VFM)
393 sriov_disable_migration(dev);
395 for (i = 0; i < iov->nr_virtfn; i++)
396 virtfn_remove(dev, i, 0);
398 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
399 pci_block_user_cfg_access(dev);
400 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
402 pci_unblock_user_cfg_access(dev);
404 if (iov->link != dev->devfn)
405 sysfs_remove_link(&dev->dev.kobj, "dep_link");
410 static int sriov_init(struct pci_dev *dev, int pos)
416 u16 ctrl, total, offset, stride;
417 struct pci_sriov *iov;
418 struct resource *res;
419 struct pci_dev *pdev;
421 if (dev->pcie_type != PCI_EXP_TYPE_RC_END &&
422 dev->pcie_type != PCI_EXP_TYPE_ENDPOINT)
425 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
426 if (ctrl & PCI_SRIOV_CTRL_VFE) {
427 pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, 0);
431 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &total);
436 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
441 if (pci_ari_enabled(dev->bus))
442 ctrl |= PCI_SRIOV_CTRL_ARI;
445 pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
446 pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total);
447 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
448 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
449 if (!offset || (total > 1 && !stride))
452 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &pgsz);
453 i = PAGE_SHIFT > 12 ? PAGE_SHIFT - 12 : 0;
454 pgsz &= ~((1 << i) - 1);
459 pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz);
462 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
463 res = dev->resource + PCI_IOV_RESOURCES + i;
464 i += __pci_read_base(dev, pci_bar_unknown, res,
465 pos + PCI_SRIOV_BAR + i * 4);
468 if (resource_size(res) & (PAGE_SIZE - 1)) {
472 res->end = res->start + resource_size(res) * total - 1;
476 iov = kzalloc(sizeof(*iov), GFP_KERNEL);
486 iov->offset = offset;
487 iov->stride = stride;
490 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
491 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
492 if (dev->pcie_type == PCI_EXP_TYPE_RC_END)
493 iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
496 iov->dev = pci_dev_get(pdev);
500 mutex_init(&iov->lock);
508 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
509 res = dev->resource + PCI_IOV_RESOURCES + i;
516 static void sriov_release(struct pci_dev *dev)
518 BUG_ON(dev->sriov->nr_virtfn);
520 if (dev != dev->sriov->dev)
521 pci_dev_put(dev->sriov->dev);
523 mutex_destroy(&dev->sriov->lock);
529 static void sriov_restore_state(struct pci_dev *dev)
533 struct pci_sriov *iov = dev->sriov;
535 pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &ctrl);
536 if (ctrl & PCI_SRIOV_CTRL_VFE)
539 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
540 pci_update_resource(dev, i);
542 pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
543 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, iov->nr_virtfn);
544 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
545 if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
550 * pci_iov_init - initialize the IOV capability
551 * @dev: the PCI device
553 * Returns 0 on success, or negative on failure.
555 int pci_iov_init(struct pci_dev *dev)
559 if (!pci_is_pcie(dev))
562 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
564 return sriov_init(dev, pos);
570 * pci_iov_release - release resources used by the IOV capability
571 * @dev: the PCI device
573 void pci_iov_release(struct pci_dev *dev)
580 * pci_iov_resource_bar - get position of the SR-IOV BAR
581 * @dev: the PCI device
582 * @resno: the resource number
583 * @type: the BAR type to be filled in
585 * Returns position of the BAR encapsulated in the SR-IOV capability.
587 int pci_iov_resource_bar(struct pci_dev *dev, int resno,
588 enum pci_bar_type *type)
590 if (resno < PCI_IOV_RESOURCES || resno > PCI_IOV_RESOURCE_END)
593 BUG_ON(!dev->is_physfn);
595 *type = pci_bar_unknown;
597 return dev->sriov->pos + PCI_SRIOV_BAR +
598 4 * (resno - PCI_IOV_RESOURCES);
602 * pci_sriov_resource_alignment - get resource alignment for VF BAR
603 * @dev: the PCI device
604 * @resno: the resource number
606 * Returns the alignment of the VF BAR found in the SR-IOV capability.
607 * This is not the same as the resource size which is defined as
608 * the VF BAR size multiplied by the number of VFs. The alignment
609 * is just the VF BAR size.
611 int pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
614 enum pci_bar_type type;
615 int reg = pci_iov_resource_bar(dev, resno, &type);
620 __pci_read_base(dev, type, &tmp, reg);
621 return resource_alignment(&tmp);
625 * pci_restore_iov_state - restore the state of the IOV capability
626 * @dev: the PCI device
628 void pci_restore_iov_state(struct pci_dev *dev)
631 sriov_restore_state(dev);
635 * pci_iov_bus_range - find bus range used by Virtual Function
638 * Returns max number of buses (exclude current one) used by Virtual
641 int pci_iov_bus_range(struct pci_bus *bus)
647 list_for_each_entry(dev, &bus->devices, bus_list) {
650 busnr = virtfn_bus(dev, dev->sriov->total - 1);
655 return max ? max - bus->number : 0;
659 * pci_enable_sriov - enable the SR-IOV capability
660 * @dev: the PCI device
661 * @nr_virtfn: number of virtual functions to enable
663 * Returns 0 on success, or negative on failure.
665 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
672 return sriov_enable(dev, nr_virtfn);
674 EXPORT_SYMBOL_GPL(pci_enable_sriov);
677 * pci_disable_sriov - disable the SR-IOV capability
678 * @dev: the PCI device
680 void pci_disable_sriov(struct pci_dev *dev)
689 EXPORT_SYMBOL_GPL(pci_disable_sriov);
692 * pci_sriov_migration - notify SR-IOV core of Virtual Function Migration
693 * @dev: the PCI device
695 * Returns IRQ_HANDLED if the IRQ is handled, or IRQ_NONE if not.
697 * Physical Function driver is responsible to register IRQ handler using
698 * VF Migration Interrupt Message Number, and call this function when the
699 * interrupt is generated by the hardware.
701 irqreturn_t pci_sriov_migration(struct pci_dev *dev)
706 return sriov_migration(dev) ? IRQ_HANDLED : IRQ_NONE;
708 EXPORT_SYMBOL_GPL(pci_sriov_migration);
711 * pci_num_vf - return number of VFs associated with a PF device_release_driver
712 * @dev: the PCI device
714 * Returns number of VFs, or 0 if SR-IOV is not enabled.
716 int pci_num_vf(struct pci_dev *dev)
718 if (!dev || !dev->is_physfn)
721 return dev->sriov->nr_virtfn;
723 EXPORT_SYMBOL_GPL(pci_num_vf);
725 static int ats_alloc_one(struct pci_dev *dev, int ps)
731 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
735 ats = kzalloc(sizeof(*ats), GFP_KERNEL);
741 pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
742 ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
749 static void ats_free_one(struct pci_dev *dev)
756 * pci_enable_ats - enable the ATS capability
757 * @dev: the PCI device
758 * @ps: the IOMMU page shift
760 * Returns 0 on success, or negative on failure.
762 int pci_enable_ats(struct pci_dev *dev, int ps)
767 BUG_ON(dev->ats && dev->ats->is_enabled);
769 if (ps < PCI_ATS_MIN_STU)
772 if (dev->is_physfn || dev->is_virtfn) {
773 struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
775 mutex_lock(&pdev->sriov->lock);
777 rc = pdev->ats->stu == ps ? 0 : -EINVAL;
779 rc = ats_alloc_one(pdev, ps);
782 pdev->ats->ref_cnt++;
783 mutex_unlock(&pdev->sriov->lock);
788 if (!dev->is_physfn) {
789 rc = ats_alloc_one(dev, ps);
794 ctrl = PCI_ATS_CTRL_ENABLE;
796 ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
797 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
799 dev->ats->is_enabled = 1;
805 * pci_disable_ats - disable the ATS capability
806 * @dev: the PCI device
808 void pci_disable_ats(struct pci_dev *dev)
812 BUG_ON(!dev->ats || !dev->ats->is_enabled);
814 pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
815 ctrl &= ~PCI_ATS_CTRL_ENABLE;
816 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
818 dev->ats->is_enabled = 0;
820 if (dev->is_physfn || dev->is_virtfn) {
821 struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
823 mutex_lock(&pdev->sriov->lock);
824 pdev->ats->ref_cnt--;
825 if (!pdev->ats->ref_cnt)
827 mutex_unlock(&pdev->sriov->lock);
835 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
836 * @dev: the PCI device
838 * Returns the queue depth on success, or negative on failure.
840 * The ATS spec uses 0 in the Invalidate Queue Depth field to
841 * indicate that the function can accept 32 Invalidate Request.
842 * But here we use the `real' values (i.e. 1~32) for the Queue
843 * Depth; and 0 indicates the function shares the Queue with
844 * other functions (doesn't exclusively own a Queue).
846 int pci_ats_queue_depth(struct pci_dev *dev)
855 return dev->ats->qdep;
857 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
861 pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
863 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :