drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 union firmware_info {
  33         struct atom_firmware_info_v3_1 v31;
  34         struct atom_firmware_info_v3_2 v32;
  35         struct atom_firmware_info_v3_3 v33;
  36         struct atom_firmware_info_v3_4 v34;
  37 };
  38
  39 /*
  40  * Helper function to query firmware capability
  41  *
  42  * @adev: amdgpu_device pointer
  43  *
  44  * Return firmware_capability in firmwareinfo table on success or 0 if not
  45  */
  46 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_mode_info *mode_info = &adev->mode_info;
  49         int index;
  50         u16 data_offset, size;
  51         union firmware_info *firmware_info;
  52         u8 frev, crev;
  53         u32 fw_cap = 0;
  54
  55         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  56                         firmwareinfo);
  57
  58         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
  59                                 index, &size, &frev, &crev, &data_offset)) {
  60                 /* support firmware_info 3.1 + */
  61                 if ((frev == 3 && crev >=1) || (frev > 3)) {
  62                         firmware_info = (union firmware_info *)
  63                                 (mode_info->atom_context->bios + data_offset);
  64                         fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
  65                 }
  66         }
  67
  68         return fw_cap;
  69 }
  70
  71 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  72 {
  73         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  74                                                 firmwareinfo);
  75         uint16_t data_offset;
  76
  77         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  78                                           NULL, NULL, &data_offset)) {
  79                 struct atom_firmware_info_v3_1 *firmware_info =
  80                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  81                                                            data_offset);
  82
  83                 if (le32_to_cpu(firmware_info->firmware_capability) &
  84                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  85                         return true;
  86         }
  87         return false;
  88 }
  89
  90 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  91 {
  92         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  93                                                 firmwareinfo);
  94         uint16_t data_offset;
  95
  96         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  97                                           NULL, NULL, &data_offset)) {
  98                 struct atom_firmware_info_v3_1 *firmware_info =
  99                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 100                                                            data_offset);
 101
 102                 adev->bios_scratch_reg_offset =
 103                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
 104         }
 105 }
 106
 107 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 108 {
 109         struct atom_context *ctx = adev->mode_info.atom_context;
 110         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 111                                                 vram_usagebyfirmware);
 112         struct vram_usagebyfirmware_v2_1 *firmware_usage;
 113         uint32_t start_addr, size;
 114         uint16_t data_offset;
 115         int usage_bytes = 0;
 116
 117         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
 118                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
 119                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
 120                           le32_to_cpu(firmware_usage->start_address_in_kb),
 121                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
 122                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
 123
 124                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
 125                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
 126
 127                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
 128                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
 129                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
 130                         /* Firmware request VRAM reservation for SR-IOV */
 131                         adev->mman.fw_vram_usage_start_offset = (start_addr &
 132                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 133                         adev->mman.fw_vram_usage_size = size << 10;
 134                         /* Use the default scratch size */
 135                         usage_bytes = 0;
 136                 } else {
 137                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
 138                 }
 139         }
 140         ctx->scratch_size_bytes = 0;
 141         if (usage_bytes == 0)
 142                 usage_bytes = 20 * 1024;
 143         /* allocate some scratch memory */
 144         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 145         if (!ctx->scratch)
 146                 return -ENOMEM;
 147         ctx->scratch_size_bytes = usage_bytes;
 148         return 0;
 149 }
 150
 151 union igp_info {
 152         struct atom_integrated_system_info_v1_11 v11;
 153         struct atom_integrated_system_info_v1_12 v12;
 154         struct atom_integrated_system_info_v2_1 v21;
 155 };
 156
 157 union umc_info {
 158         struct atom_umc_info_v3_1 v31;
 159         struct atom_umc_info_v3_2 v32;
 160         struct atom_umc_info_v3_3 v33;
 161 };
 162
 163 union vram_info {
 164         struct atom_vram_info_header_v2_3 v23;
 165         struct atom_vram_info_header_v2_4 v24;
 166         struct atom_vram_info_header_v2_5 v25;
 167         struct atom_vram_info_header_v2_6 v26;
 168 };
 169
 170 union vram_module {
 171         struct atom_vram_module_v9 v9;
 172         struct atom_vram_module_v10 v10;
 173         struct atom_vram_module_v11 v11;
 174 };
 175
 176 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 177                                               int atom_mem_type)
 178 {
 179         int vram_type;
 180
 181         if (adev->flags & AMD_IS_APU) {
 182                 switch (atom_mem_type) {
 183                 case Ddr2MemType:
 184                 case LpDdr2MemType:
 185                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 186                         break;
 187                 case Ddr3MemType:
 188                 case LpDdr3MemType:
 189                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 190                         break;
 191                 case Ddr4MemType:
 192                 case LpDdr4MemType:
 193                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 194                         break;
 195                 case Ddr5MemType:
 196                 case LpDdr5MemType:
 197                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 198                         break;
 199                 default:
 200                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 201                         break;
 202                 }
 203         } else {
 204                 switch (atom_mem_type) {
 205                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 206                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 207                         break;
 208                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 209                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 210                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 211                         break;
 212                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 213                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 214                         break;
 215                 default:
 216                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 217                         break;
 218                 }
 219         }
 220
 221         return vram_type;
 222 }
 223
 224
 225 int
 226 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 227                                   int *vram_width, int *vram_type,
 228                                   int *vram_vendor)
 229 {
 230         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 231         int index, i = 0;
 232         u16 data_offset, size;
 233         union igp_info *igp_info;
 234         union vram_info *vram_info;
 235         union vram_module *vram_module;
 236         u8 frev, crev;
 237         u8 mem_type;
 238         u8 mem_vendor;
 239         u32 mem_channel_number;
 240         u32 mem_channel_width;
 241         u32 module_id;
 242
 243         if (adev->flags & AMD_IS_APU)
 244                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 245                                                     integratedsysteminfo);
 246         else
 247                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 248                                                     vram_info);
 249
 250         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 251                                           index, &size,
 252                                           &frev, &crev, &data_offset)) {
 253                 if (adev->flags & AMD_IS_APU) {
 254                         igp_info = (union igp_info *)
 255                                 (mode_info->atom_context->bios + data_offset);
 256                         switch (frev) {
 257                         case 1:
 258                                 switch (crev) {
 259                                 case 11:
 260                                 case 12:
 261                                         mem_channel_number = igp_info->v11.umachannelnumber;
 262                                         if (!mem_channel_number)
 263                                                 mem_channel_number = 1;
 264                                         /* channel width is 64 */
 265                                         if (vram_width)
 266                                                 *vram_width = mem_channel_number * 64;
 267                                         mem_type = igp_info->v11.memorytype;
 268                                         if (vram_type)
 269                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 270                                         break;
 271                                 default:
 272                                         return -EINVAL;
 273                                 }
 274                                 break;
 275                         case 2:
 276                                 switch (crev) {
 277                                 case 1:
 278                                 case 2:
 279                                         mem_channel_number = igp_info->v21.umachannelnumber;
 280                                         if (!mem_channel_number)
 281                                                 mem_channel_number = 1;
 282                                         /* channel width is 64 */
 283                                         if (vram_width)
 284                                                 *vram_width = mem_channel_number * 64;
 285                                         mem_type = igp_info->v21.memorytype;
 286                                         if (vram_type)
 287                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 288                                         break;
 289                                 default:
 290                                         return -EINVAL;
 291                                 }
 292                                 break;
 293                         default:
 294                                 return -EINVAL;
 295                         }
 296                 } else {
 297                         vram_info = (union vram_info *)
 298                                 (mode_info->atom_context->bios + data_offset);
 299                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 300                         switch (crev) {
 301                         case 3:
 302                                 if (module_id > vram_info->v23.vram_module_num)
 303                                         module_id = 0;
 304                                 vram_module = (union vram_module *)vram_info->v23.vram_module;
 305                                 while (i < module_id) {
 306                                         vram_module = (union vram_module *)
 307                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 308                                         i++;
 309                                 }
 310                                 mem_type = vram_module->v9.memory_type;
 311                                 if (vram_type)
 312                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 313                                 mem_channel_number = vram_module->v9.channel_num;
 314                                 mem_channel_width = vram_module->v9.channel_width;
 315                                 if (vram_width)
 316                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 317                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 318                                 if (vram_vendor)
 319                                         *vram_vendor = mem_vendor;
 320                                 break;
 321                         case 4:
 322                                 if (module_id > vram_info->v24.vram_module_num)
 323                                         module_id = 0;
 324                                 vram_module = (union vram_module *)vram_info->v24.vram_module;
 325                                 while (i < module_id) {
 326                                         vram_module = (union vram_module *)
 327                                                 ((u8 *)vram_module + vram_module->v10.vram_module_size);
 328                                         i++;
 329                                 }
 330                                 mem_type = vram_module->v10.memory_type;
 331                                 if (vram_type)
 332                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 333                                 mem_channel_number = vram_module->v10.channel_num;
 334                                 mem_channel_width = vram_module->v10.channel_width;
 335                                 if (vram_width)
 336                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 337                                 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 338                                 if (vram_vendor)
 339                                         *vram_vendor = mem_vendor;
 340                                 break;
 341                         case 5:
 342                                 if (module_id > vram_info->v25.vram_module_num)
 343                                         module_id = 0;
 344                                 vram_module = (union vram_module *)vram_info->v25.vram_module;
 345                                 while (i < module_id) {
 346                                         vram_module = (union vram_module *)
 347                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 348                                         i++;
 349                                 }
 350                                 mem_type = vram_module->v11.memory_type;
 351                                 if (vram_type)
 352                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 353                                 mem_channel_number = vram_module->v11.channel_num;
 354                                 mem_channel_width = vram_module->v11.channel_width;
 355                                 if (vram_width)
 356                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 357                                 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 358                                 if (vram_vendor)
 359                                         *vram_vendor = mem_vendor;
 360                                 break;
 361                         case 6:
 362                                 if (module_id > vram_info->v26.vram_module_num)
 363                                         module_id = 0;
 364                                 vram_module = (union vram_module *)vram_info->v26.vram_module;
 365                                 while (i < module_id) {
 366                                         vram_module = (union vram_module *)
 367                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 368                                         i++;
 369                                 }
 370                                 mem_type = vram_module->v9.memory_type;
 371                                 if (vram_type)
 372                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 373                                 mem_channel_number = vram_module->v9.channel_num;
 374                                 mem_channel_width = vram_module->v9.channel_width;
 375                                 if (vram_width)
 376                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 377                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 378                                 if (vram_vendor)
 379                                         *vram_vendor = mem_vendor;
 380                                 break;
 381                         default:
 382                                 return -EINVAL;
 383                         }
 384                 }
 385
 386         }
 387
 388         return 0;
 389 }
 390
 391 /*
 392  * Return true if vbios enabled ecc by default, if umc info table is available
 393  * or false if ecc is not enabled or umc info table is not available
 394  */
 395 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 396 {
 397         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 398         int index;
 399         u16 data_offset, size;
 400         union umc_info *umc_info;
 401         u8 frev, crev;
 402         bool ecc_default_enabled = false;
 403         u8 umc_config;
 404         u32 umc_config1;
 405
 406         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 407                         umc_info);
 408
 409         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 410                                 index, &size, &frev, &crev, &data_offset)) {
 411                 if (frev == 3) {
 412                         umc_info = (union umc_info *)
 413                                 (mode_info->atom_context->bios + data_offset);
 414                         switch (crev) {
 415                         case 1:
 416                                 umc_config = le32_to_cpu(umc_info->v31.umc_config);
 417                                 ecc_default_enabled =
 418                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 419                                 break;
 420                         case 2:
 421                                 umc_config = le32_to_cpu(umc_info->v32.umc_config);
 422                                 ecc_default_enabled =
 423                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 424                                 break;
 425                         case 3:
 426                                 umc_config = le32_to_cpu(umc_info->v33.umc_config);
 427                                 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
 428                                 ecc_default_enabled =
 429                                         ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
 430                                          (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
 431                                 break;
 432                         default:
 433                                 /* unsupported crev */
 434                                 return false;
 435                         }
 436                 }
 437         }
 438
 439         return ecc_default_enabled;
 440 }
 441
 442 /*
 443  * Return true if vbios supports sram ecc or false if not
 444  */
 445 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 446 {
 447         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 448         int index;
 449         u16 data_offset, size;
 450         union firmware_info *firmware_info;
 451         u8 frev, crev;
 452         bool sram_ecc_supported = false;
 453
 454         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 455                         firmwareinfo);
 456
 457         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 458                                 index, &size, &frev, &crev, &data_offset)) {
 459                 /* support firmware_info 3.1 + */
 460                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 461                         firmware_info = (union firmware_info *)
 462                                 (mode_info->atom_context->bios + data_offset);
 463                         sram_ecc_supported =
 464                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 465                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 466                 }
 467         }
 468
 469         return sram_ecc_supported;
 470 }
 471
 472 union smu_info {
 473         struct atom_smu_info_v3_1 v31;
 474 };
 475
 476 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 477 {
 478         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 479         struct amdgpu_pll *spll = &adev->clock.spll;
 480         struct amdgpu_pll *mpll = &adev->clock.mpll;
 481         uint8_t frev, crev;
 482         uint16_t data_offset;
 483         int ret = -EINVAL, index;
 484
 485         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 486                                             firmwareinfo);
 487         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 488                                    &frev, &crev, &data_offset)) {
 489                 union firmware_info *firmware_info =
 490                         (union firmware_info *)(mode_info->atom_context->bios +
 491                                                 data_offset);
 492
 493                 adev->clock.default_sclk =
 494                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 495                 adev->clock.default_mclk =
 496                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 497
 498                 adev->pm.current_sclk = adev->clock.default_sclk;
 499                 adev->pm.current_mclk = adev->clock.default_mclk;
 500
 501                 ret = 0;
 502         }
 503
 504         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 505                                             smu_info);
 506         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 507                                    &frev, &crev, &data_offset)) {
 508                 union smu_info *smu_info =
 509                         (union smu_info *)(mode_info->atom_context->bios +
 510                                            data_offset);
 511
 512                 /* system clock */
 513                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 514
 515                 spll->reference_div = 0;
 516                 spll->min_post_div = 1;
 517                 spll->max_post_div = 1;
 518                 spll->min_ref_div = 2;
 519                 spll->max_ref_div = 0xff;
 520                 spll->min_feedback_div = 4;
 521                 spll->max_feedback_div = 0xff;
 522                 spll->best_vco = 0;
 523
 524                 ret = 0;
 525         }
 526
 527         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 528                                             umc_info);
 529         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 530                                    &frev, &crev, &data_offset)) {
 531                 union umc_info *umc_info =
 532                         (union umc_info *)(mode_info->atom_context->bios +
 533                                            data_offset);
 534
 535                 /* memory clock */
 536                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 537
 538                 mpll->reference_div = 0;
 539                 mpll->min_post_div = 1;
 540                 mpll->max_post_div = 1;
 541                 mpll->min_ref_div = 2;
 542                 mpll->max_ref_div = 0xff;
 543                 mpll->min_feedback_div = 4;
 544                 mpll->max_feedback_div = 0xff;
 545                 mpll->best_vco = 0;
 546
 547                 ret = 0;
 548         }
 549
 550         return ret;
 551 }
 552
 553 union gfx_info {
 554         struct atom_gfx_info_v2_4 v24;
 555         struct atom_gfx_info_v2_7 v27;
 556 };
 557
 558 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 559 {
 560         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 561         int index;
 562         uint8_t frev, crev;
 563         uint16_t data_offset;
 564
 565         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 566                                             gfx_info);
 567         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 568                                    &frev, &crev, &data_offset)) {
 569                 union gfx_info *gfx_info = (union gfx_info *)
 570                         (mode_info->atom_context->bios + data_offset);
 571                 switch (crev) {
 572                 case 4:
 573                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 574                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 575                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 576                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 577                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 578                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 579                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 580                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 581                         adev->gfx.config.gs_prim_buffer_depth =
 582                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 583                         adev->gfx.config.double_offchip_lds_buf =
 584                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 585                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 586                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 587                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 588                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 589                         return 0;
 590                 case 7:
 591                         adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 592                         adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 593                         adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 594                         adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 595                         adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 596                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 597                         adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 598                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 599                         adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 600                         adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 601                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 602                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 603                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 604                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 605                         return 0;
 606                 default:
 607                         return -EINVAL;
 608                 }
 609
 610         }
 611         return -EINVAL;
 612 }
 613
 614 /*
 615  * Check if VBIOS supports GDDR6 training data save/restore
 616  */
 617 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
 618 {
 619         uint16_t data_offset;
 620         int index;
 621
 622         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 623                                             firmwareinfo);
 624         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
 625                                           NULL, NULL, &data_offset)) {
 626                 struct atom_firmware_info_v3_1 *firmware_info =
 627                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 628                                                            data_offset);
 629
 630                 DRM_DEBUG("atom firmware capability:0x%08x.\n",
 631                           le32_to_cpu(firmware_info->firmware_capability));
 632
 633                 if (le32_to_cpu(firmware_info->firmware_capability) &
 634                     ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
 635                         return true;
 636         }
 637
 638         return false;
 639 }
 640
 641 int amdgpu_mem_train_support(struct amdgpu_device *adev)
 642 {
 643         int ret;
 644         uint32_t major, minor, revision, hw_v;
 645
 646         if (gddr6_mem_train_vbios_support(adev)) {
 647                 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
 648                 hw_v = HW_REV(major, minor, revision);
 649                 /*
 650                  * treat 0 revision as a special case since register for MP0 and MMHUB is missing
 651                  * for some Navi10 A0, preventing driver from discovering the hwip information since
 652                  * none of the functions will be initialized, it should not cause any problems
 653                  */
 654                 switch (hw_v) {
 655                 case HW_REV(11, 0, 0):
 656                 case HW_REV(11, 0, 5):
 657                 case HW_REV(11, 0, 7):
 658                 case HW_REV(11, 0, 11):
 659                 case HW_REV(11, 0, 12):
 660                         ret = 1;
 661                         break;
 662                 default:
 663                         DRM_ERROR("memory training vbios supports but psp hw(%08x)"
 664                                   " doesn't support!\n", hw_v);
 665                         ret = -1;
 666                         break;
 667                 }
 668         } else {
 669                 ret = 0;
 670                 hw_v = -1;
 671         }
 672
 673
 674         DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
 675         return ret;
 676 }
 677
 678 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 679 {
 680         struct atom_context *ctx = adev->mode_info.atom_context;
 681         union firmware_info *firmware_info;
 682         int index;
 683         u16 data_offset, size;
 684         u8 frev, crev;
 685         int fw_reserved_fb_size;
 686
 687         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 688                         firmwareinfo);
 689
 690         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 691                                 &frev, &crev, &data_offset))
 692                 /* fail to parse data_header */
 693                 return 0;
 694
 695         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 696
 697         if (frev !=3)
 698                 return -EINVAL;
 699
 700         switch (crev) {
 701         case 4:
 702                 fw_reserved_fb_size =
 703                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 704                 break;
 705         default:
 706                 fw_reserved_fb_size = 0;
 707                 break;
 708         }
 709
 710         return fw_reserved_fb_size;
 711 }