drivers/irqchip/irq-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370 and Armada XP SoC IRQ handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <[email protected]>
   7  * Gregory CLEMENT <[email protected]>
   8  * Thomas Petazzoni <[email protected]>
   9  * Ben Dooks <[email protected]>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/irqchip/chained_irq.h>
  23 #include <linux/cpu.h>
  24 #include <linux/io.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_pci.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/slab.h>
  30 #include <linux/syscore_ops.h>
  31 #include <linux/msi.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/exception.h>
  34 #include <asm/smp_plat.h>
  35 #include <asm/mach/irq.h>
  36
  37 /*
  38  * Overall diagram of the Armada XP interrupt controller:
  39  *
  40  *    To CPU 0                 To CPU 1
  41  *
  42  *       /\                       /\
  43  *       ||                       ||
  44  * +---------------+     +---------------+
  45  * |               |     |               |
  46  * |    per-CPU    |     |    per-CPU    |
  47  * |  mask/unmask  |     |  mask/unmask  |
  48  * |     CPU0      |     |     CPU1      |
  49  * |               |     |               |
  50  * +---------------+     +---------------+
  51  *        /\                       /\
  52  *        ||                       ||
  53  *        \\_______________________//
  54  *                     ||
  55  *            +-------------------+
  56  *            |                   |
  57  *            | Global interrupt  |
  58  *            |    mask/unmask    |
  59  *            |                   |
  60  *            +-------------------+
  61  *                     /\
  62  *                     ||
  63  *               interrupt from
  64  *                   device
  65  *
  66  * The "global interrupt mask/unmask" is modified using the
  67  * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
  68  * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
  69  * to "main_int_base".
  70  *
  71  * The "per-CPU mask/unmask" is modified using the
  72  * ARMADA_370_XP_INT_SET_MASK_OFFS and
  73  * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
  74  * "per_cpu_int_base". This base address points to a special address,
  75  * which automatically accesses the registers of the current CPU.
  76  *
  77  * The per-CPU mask/unmask can also be adjusted using the global
  78  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
  79  * to configure interrupt affinity.
  80  *
  81  * Due to this model, all interrupts need to be mask/unmasked at two
  82  * different levels: at the global level and at the per-CPU level.
  83  *
  84  * This driver takes the following approach to deal with this:
  85  *
  86  *  - For global interrupts:
  87  *
  88  *    At ->map() time, a global interrupt is unmasked at the per-CPU
  89  *    mask/unmask level. It is therefore unmasked at this level for
  90  *    the current CPU, running the ->map() code. This allows to have
  91  *    the interrupt unmasked at this level in non-SMP
  92  *    configurations. In SMP configurations, the ->set_affinity()
  93  *    callback is called, which using the
  94  *    ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
  95  *    for the interrupt.
  96  *
  97  *    The ->mask() and ->unmask() operations only mask/unmask the
  98  *    interrupt at the "global" level.
  99  *
 100  *    So, a global interrupt is enabled at the per-CPU level as soon
 101  *    as it is mapped. At run time, the masking/unmasking takes place
 102  *    at the global level.
 103  *
 104  *  - For per-CPU interrupts
 105  *
 106  *    At ->map() time, a per-CPU interrupt is unmasked at the global
 107  *    mask/unmask level.
 108  *
 109  *    The ->mask() and ->unmask() operations mask/unmask the interrupt
 110  *    at the per-CPU level.
 111  *
 112  *    So, a per-CPU interrupt is enabled at the global level as soon
 113  *    as it is mapped. At run time, the masking/unmasking takes place
 114  *    at the per-CPU level.
 115  */
 116
 117 /* Registers relative to main_int_base */
 118 #define ARMADA_370_XP_INT_CONTROL               (0x00)
 119 #define ARMADA_370_XP_SW_TRIG_INT_OFFS          (0x04)
 120 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
 121 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
 122 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)       (0x100 + irq*4)
 123 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK       0xF
 124 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)   ((BIT(0) | BIT(8)) << cpuid)
 125
 126 /* Registers relative to per_cpu_int_base */
 127 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS       (0x08)
 128 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS         (0x0c)
 129 #define ARMADA_375_PPI_CAUSE                    (0x10)
 130 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
 131 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
 132 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
 133 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS      (0x54)
 134 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)       (1 << cpu)
 135
 136 #define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
 137
 138 #define IPI_DOORBELL_START                      (0)
 139 #define IPI_DOORBELL_END                        (8)
 140 #define IPI_DOORBELL_MASK                       0xFF
 141 #define PCI_MSI_DOORBELL_START                  (16)
 142 #define PCI_MSI_DOORBELL_NR                     (16)
 143 #define PCI_MSI_DOORBELL_END                    (32)
 144 #define PCI_MSI_DOORBELL_MASK                   0xFFFF0000
 145
 146 static void __iomem *per_cpu_int_base;
 147 static void __iomem *main_int_base;
 148 static struct irq_domain *armada_370_xp_mpic_domain;
 149 static u32 doorbell_mask_reg;
 150 static int parent_irq;
 151 #ifdef CONFIG_PCI_MSI
 152 static struct irq_domain *armada_370_xp_msi_domain;
 153 static struct irq_domain *armada_370_xp_msi_inner_domain;
 154 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
 155 static DEFINE_MUTEX(msi_used_lock);
 156 static phys_addr_t msi_doorbell_addr;
 157 #endif
 158
 159 static inline bool is_percpu_irq(irq_hw_number_t irq)
 160 {
 161         if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
 162                 return true;
 163
 164         return false;
 165 }
 166
 167 /*
 168  * In SMP mode:
 169  * For shared global interrupts, mask/unmask global enable bit
 170  * For CPU interrupts, mask/unmask the calling CPU's bit
 171  */
 172 static void armada_370_xp_irq_mask(struct irq_data *d)
 173 {
 174         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 175
 176         if (!is_percpu_irq(hwirq))
 177                 writel(hwirq, main_int_base +
 178                                 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
 179         else
 180                 writel(hwirq, per_cpu_int_base +
 181                                 ARMADA_370_XP_INT_SET_MASK_OFFS);
 182 }
 183
 184 static void armada_370_xp_irq_unmask(struct irq_data *d)
 185 {
 186         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 187
 188         if (!is_percpu_irq(hwirq))
 189                 writel(hwirq, main_int_base +
 190                                 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 191         else
 192                 writel(hwirq, per_cpu_int_base +
 193                                 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 194 }
 195
 196 #ifdef CONFIG_PCI_MSI
 197
 198 static struct irq_chip armada_370_xp_msi_irq_chip = {
 199         .name = "MPIC MSI",
 200         .irq_mask = pci_msi_mask_irq,
 201         .irq_unmask = pci_msi_unmask_irq,
 202 };
 203
 204 static struct msi_domain_info armada_370_xp_msi_domain_info = {
 205         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 206                    MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
 207         .chip   = &armada_370_xp_msi_irq_chip,
 208 };
 209
 210 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 211 {
 212         msg->address_lo = lower_32_bits(msi_doorbell_addr);
 213         msg->address_hi = upper_32_bits(msi_doorbell_addr);
 214         msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
 215 }
 216
 217 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
 218                                           const struct cpumask *mask, bool force)
 219 {
 220          return -EINVAL;
 221 }
 222
 223 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
 224         .name                   = "MPIC MSI",
 225         .irq_compose_msi_msg    = armada_370_xp_compose_msi_msg,
 226         .irq_set_affinity       = armada_370_xp_msi_set_affinity,
 227 };
 228
 229 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 230                                    unsigned int nr_irqs, void *args)
 231 {
 232         int hwirq, i;
 233
 234         mutex_lock(&msi_used_lock);
 235         hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR,
 236                                         order_base_2(nr_irqs));
 237         mutex_unlock(&msi_used_lock);
 238
 239         if (hwirq < 0)
 240                 return -ENOSPC;
 241
 242         for (i = 0; i < nr_irqs; i++) {
 243                 irq_domain_set_info(domain, virq + i, hwirq + i,
 244                                     &armada_370_xp_msi_bottom_irq_chip,
 245                                     domain->host_data, handle_simple_irq,
 246                                     NULL, NULL);
 247         }
 248
 249         return 0;
 250 }
 251
 252 static void armada_370_xp_msi_free(struct irq_domain *domain,
 253                                    unsigned int virq, unsigned int nr_irqs)
 254 {
 255         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 256
 257         mutex_lock(&msi_used_lock);
 258         bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));
 259         mutex_unlock(&msi_used_lock);
 260 }
 261
 262 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
 263         .alloc  = armada_370_xp_msi_alloc,
 264         .free   = armada_370_xp_msi_free,
 265 };
 266
 267 static int armada_370_xp_msi_init(struct device_node *node,
 268                                   phys_addr_t main_int_phys_base)
 269 {
 270         u32 reg;
 271
 272         msi_doorbell_addr = main_int_phys_base +
 273                 ARMADA_370_XP_SW_TRIG_INT_OFFS;
 274
 275         armada_370_xp_msi_inner_domain =
 276                 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
 277                                       &armada_370_xp_msi_domain_ops, NULL);
 278         if (!armada_370_xp_msi_inner_domain)
 279                 return -ENOMEM;
 280
 281         armada_370_xp_msi_domain =
 282                 pci_msi_create_irq_domain(of_node_to_fwnode(node),
 283                                           &armada_370_xp_msi_domain_info,
 284                                           armada_370_xp_msi_inner_domain);
 285         if (!armada_370_xp_msi_domain) {
 286                 irq_domain_remove(armada_370_xp_msi_inner_domain);
 287                 return -ENOMEM;
 288         }
 289
 290         reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
 291                 | PCI_MSI_DOORBELL_MASK;
 292
 293         writel(reg, per_cpu_int_base +
 294                ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 295
 296         /* Unmask IPI interrupt */
 297         writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 298
 299         return 0;
 300 }
 301 #else
 302 static inline int armada_370_xp_msi_init(struct device_node *node,
 303                                          phys_addr_t main_int_phys_base)
 304 {
 305         return 0;
 306 }
 307 #endif
 308
 309 static void armada_xp_mpic_perf_init(void)
 310 {
 311         unsigned long cpuid = cpu_logical_map(smp_processor_id());
 312
 313         /* Enable Performance Counter Overflow interrupts */
 314         writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
 315                per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
 316 }
 317
 318 #ifdef CONFIG_SMP
 319 static struct irq_domain *ipi_domain;
 320
 321 static void armada_370_xp_ipi_mask(struct irq_data *d)
 322 {
 323         u32 reg;
 324         reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 325         reg &= ~BIT(d->hwirq);
 326         writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 327 }
 328
 329 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 330 {
 331         u32 reg;
 332         reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 333         reg |= BIT(d->hwirq);
 334         writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 335 }
 336
 337 static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 338                                         const struct cpumask *mask)
 339 {
 340         unsigned long map = 0;
 341         int cpu;
 342
 343         /* Convert our logical CPU mask into a physical one. */
 344         for_each_cpu(cpu, mask)
 345                 map |= 1 << cpu_logical_map(cpu);
 346
 347         /*
 348          * Ensure that stores to Normal memory are visible to the
 349          * other CPUs before issuing the IPI.
 350          */
 351         dsb();
 352
 353         /* submit softirq */
 354         writel((map << 8) | d->hwirq, main_int_base +
 355                 ARMADA_370_XP_SW_TRIG_INT_OFFS);
 356 }
 357
 358 static void armada_370_xp_ipi_ack(struct irq_data *d)
 359 {
 360         writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 361 }
 362
 363 static struct irq_chip ipi_irqchip = {
 364         .name           = "IPI",
 365         .irq_ack        = armada_370_xp_ipi_ack,
 366         .irq_mask       = armada_370_xp_ipi_mask,
 367         .irq_unmask     = armada_370_xp_ipi_unmask,
 368         .ipi_send_mask  = armada_370_xp_ipi_send_mask,
 369 };
 370
 371 static int armada_370_xp_ipi_alloc(struct irq_domain *d,
 372                                          unsigned int virq,
 373                                          unsigned int nr_irqs, void *args)
 374 {
 375         int i;
 376
 377         for (i = 0; i < nr_irqs; i++) {
 378                 irq_set_percpu_devid(virq + i);
 379                 irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
 380                                     d->host_data,
 381                                     handle_percpu_devid_irq,
 382                                     NULL, NULL);
 383         }
 384
 385         return 0;
 386 }
 387
 388 static void armada_370_xp_ipi_free(struct irq_domain *d,
 389                                          unsigned int virq,
 390                                          unsigned int nr_irqs)
 391 {
 392         /* Not freeing IPIs */
 393 }
 394
 395 static const struct irq_domain_ops ipi_domain_ops = {
 396         .alloc  = armada_370_xp_ipi_alloc,
 397         .free   = armada_370_xp_ipi_free,
 398 };
 399
 400 static void ipi_resume(void)
 401 {
 402         int i;
 403
 404         for (i = 0; i < IPI_DOORBELL_END; i++) {
 405                 int irq;
 406
 407                 irq = irq_find_mapping(ipi_domain, i);
 408                 if (irq <= 0)
 409                         continue;
 410                 if (irq_percpu_is_enabled(irq)) {
 411                         struct irq_data *d;
 412                         d = irq_domain_get_irq_data(ipi_domain, irq);
 413                         armada_370_xp_ipi_unmask(d);
 414                 }
 415         }
 416 }
 417
 418 static __init void armada_xp_ipi_init(struct device_node *node)
 419 {
 420         int base_ipi;
 421
 422         ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node),
 423                                               IPI_DOORBELL_END,
 424                                               &ipi_domain_ops, NULL);
 425         if (WARN_ON(!ipi_domain))
 426                 return;
 427
 428         irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
 429         base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END,
 430                                            NUMA_NO_NODE, NULL, false, NULL);
 431         if (WARN_ON(!base_ipi))
 432                 return;
 433
 434         set_smp_ipi_range(base_ipi, IPI_DOORBELL_END);
 435 }
 436
 437 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 438
 439 static int armada_xp_set_affinity(struct irq_data *d,
 440                                   const struct cpumask *mask_val, bool force)
 441 {
 442         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 443         unsigned long reg, mask;
 444         int cpu;
 445
 446         /* Select a single core from the affinity mask which is online */
 447         cpu = cpumask_any_and(mask_val, cpu_online_mask);
 448         mask = 1UL << cpu_logical_map(cpu);
 449
 450         raw_spin_lock(&irq_controller_lock);
 451         reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 452         reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
 453         writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 454         raw_spin_unlock(&irq_controller_lock);
 455
 456         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 457
 458         return IRQ_SET_MASK_OK;
 459 }
 460
 461 static void armada_xp_mpic_smp_cpu_init(void)
 462 {
 463         u32 control;
 464         int nr_irqs, i;
 465
 466         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 467         nr_irqs = (control >> 2) & 0x3ff;
 468
 469         for (i = 0; i < nr_irqs; i++)
 470                 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
 471
 472         /* Disable all IPIs */
 473         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 474
 475         /* Clear pending IPIs */
 476         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 477
 478         /* Unmask IPI interrupt */
 479         writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 480 }
 481
 482 static void armada_xp_mpic_reenable_percpu(void)
 483 {
 484         unsigned int irq;
 485
 486         /* Re-enable per-CPU interrupts that were enabled before suspend */
 487         for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
 488                 struct irq_data *data;
 489                 int virq;
 490
 491                 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
 492                 if (virq == 0)
 493                         continue;
 494
 495                 data = irq_get_irq_data(virq);
 496
 497                 if (!irq_percpu_is_enabled(virq))
 498                         continue;
 499
 500                 armada_370_xp_irq_unmask(data);
 501         }
 502
 503         ipi_resume();
 504 }
 505
 506 static int armada_xp_mpic_starting_cpu(unsigned int cpu)
 507 {
 508         armada_xp_mpic_perf_init();
 509         armada_xp_mpic_smp_cpu_init();
 510         armada_xp_mpic_reenable_percpu();
 511         return 0;
 512 }
 513
 514 static int mpic_cascaded_starting_cpu(unsigned int cpu)
 515 {
 516         armada_xp_mpic_perf_init();
 517         armada_xp_mpic_reenable_percpu();
 518         enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
 519         return 0;
 520 }
 521 #else
 522 static void armada_xp_mpic_smp_cpu_init(void) {}
 523 static void ipi_resume(void) {}
 524 #endif
 525
 526 static struct irq_chip armada_370_xp_irq_chip = {
 527         .name           = "MPIC",
 528         .irq_mask       = armada_370_xp_irq_mask,
 529         .irq_mask_ack   = armada_370_xp_irq_mask,
 530         .irq_unmask     = armada_370_xp_irq_unmask,
 531 #ifdef CONFIG_SMP
 532         .irq_set_affinity = armada_xp_set_affinity,
 533 #endif
 534         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
 535 };
 536
 537 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 538                                       unsigned int virq, irq_hw_number_t hw)
 539 {
 540         armada_370_xp_irq_mask(irq_get_irq_data(virq));
 541         if (!is_percpu_irq(hw))
 542                 writel(hw, per_cpu_int_base +
 543                         ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 544         else
 545                 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 546         irq_set_status_flags(virq, IRQ_LEVEL);
 547
 548         if (is_percpu_irq(hw)) {
 549                 irq_set_percpu_devid(virq);
 550                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 551                                         handle_percpu_devid_irq);
 552         } else {
 553                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 554                                         handle_level_irq);
 555                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 556         }
 557         irq_set_probe(virq);
 558
 559         return 0;
 560 }
 561
 562 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 563         .map = armada_370_xp_mpic_irq_map,
 564         .xlate = irq_domain_xlate_onecell,
 565 };
 566
 567 #ifdef CONFIG_PCI_MSI
 568 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 569 {
 570         u32 msimask, msinr;
 571
 572         msimask = readl_relaxed(per_cpu_int_base +
 573                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 574                 & PCI_MSI_DOORBELL_MASK;
 575
 576         writel(~msimask, per_cpu_int_base +
 577                ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 578
 579         for (msinr = PCI_MSI_DOORBELL_START;
 580              msinr < PCI_MSI_DOORBELL_END; msinr++) {
 581                 unsigned int irq;
 582
 583                 if (!(msimask & BIT(msinr)))
 584                         continue;
 585
 586                 irq = msinr - PCI_MSI_DOORBELL_START;
 587
 588                 generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq);
 589         }
 590 }
 591 #else
 592 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
 593 #endif
 594
 595 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
 596 {
 597         struct irq_chip *chip = irq_desc_get_chip(desc);
 598         unsigned long irqmap, irqn, irqsrc, cpuid;
 599
 600         chained_irq_enter(chip, desc);
 601
 602         irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
 603         cpuid = cpu_logical_map(smp_processor_id());
 604
 605         for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
 606                 irqsrc = readl_relaxed(main_int_base +
 607                                        ARMADA_370_XP_INT_SOURCE_CTL(irqn));
 608
 609                 /* Check if the interrupt is not masked on current CPU.
 610                  * Test IRQ (0-1) and FIQ (8-9) mask bits.
 611                  */
 612                 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
 613                         continue;
 614
 615                 if (irqn == 1) {
 616                         armada_370_xp_handle_msi_irq(NULL, true);
 617                         continue;
 618                 }
 619
 620                 generic_handle_domain_irq(armada_370_xp_mpic_domain, irqn);
 621         }
 622
 623         chained_irq_exit(chip, desc);
 624 }
 625
 626 static void __exception_irq_entry
 627 armada_370_xp_handle_irq(struct pt_regs *regs)
 628 {
 629         u32 irqstat, irqnr;
 630
 631         do {
 632                 irqstat = readl_relaxed(per_cpu_int_base +
 633                                         ARMADA_370_XP_CPU_INTACK_OFFS);
 634                 irqnr = irqstat & 0x3FF;
 635
 636                 if (irqnr > 1022)
 637                         break;
 638
 639                 if (irqnr > 1) {
 640                         generic_handle_domain_irq(armada_370_xp_mpic_domain,
 641                                                   irqnr);
 642                         continue;
 643                 }
 644
 645                 /* MSI handling */
 646                 if (irqnr == 1)
 647                         armada_370_xp_handle_msi_irq(regs, false);
 648
 649 #ifdef CONFIG_SMP
 650                 /* IPI Handling */
 651                 if (irqnr == 0) {
 652                         unsigned long ipimask;
 653                         int ipi;
 654
 655                         ipimask = readl_relaxed(per_cpu_int_base +
 656                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 657                                 & IPI_DOORBELL_MASK;
 658
 659                         for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
 660                                 generic_handle_domain_irq(ipi_domain, ipi);
 661                 }
 662 #endif
 663
 664         } while (1);
 665 }
 666
 667 static int armada_370_xp_mpic_suspend(void)
 668 {
 669         doorbell_mask_reg = readl(per_cpu_int_base +
 670                                   ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 671         return 0;
 672 }
 673
 674 static void armada_370_xp_mpic_resume(void)
 675 {
 676         int nirqs;
 677         irq_hw_number_t irq;
 678
 679         /* Re-enable interrupts */
 680         nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
 681         for (irq = 0; irq < nirqs; irq++) {
 682                 struct irq_data *data;
 683                 int virq;
 684
 685                 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
 686                 if (virq == 0)
 687                         continue;
 688
 689                 data = irq_get_irq_data(virq);
 690
 691                 if (!is_percpu_irq(irq)) {
 692                         /* Non per-CPU interrupts */
 693                         writel(irq, per_cpu_int_base +
 694                                ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 695                         if (!irqd_irq_disabled(data))
 696                                 armada_370_xp_irq_unmask(data);
 697                 } else {
 698                         /* Per-CPU interrupts */
 699                         writel(irq, main_int_base +
 700                                ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 701
 702                         /*
 703                          * Re-enable on the current CPU,
 704                          * armada_xp_mpic_reenable_percpu() will take
 705                          * care of secondary CPUs when they come up.
 706                          */
 707                         if (irq_percpu_is_enabled(virq))
 708                                 armada_370_xp_irq_unmask(data);
 709                 }
 710         }
 711
 712         /* Reconfigure doorbells for IPIs and MSIs */
 713         writel(doorbell_mask_reg,
 714                per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 715         if (doorbell_mask_reg & IPI_DOORBELL_MASK)
 716                 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 717         if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
 718                 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 719
 720         ipi_resume();
 721 }
 722
 723 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
 724         .suspend        = armada_370_xp_mpic_suspend,
 725         .resume         = armada_370_xp_mpic_resume,
 726 };
 727
 728 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 729                                              struct device_node *parent)
 730 {
 731         struct resource main_int_res, per_cpu_int_res;
 732         int nr_irqs, i;
 733         u32 control;
 734
 735         BUG_ON(of_address_to_resource(node, 0, &main_int_res));
 736         BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
 737
 738         BUG_ON(!request_mem_region(main_int_res.start,
 739                                    resource_size(&main_int_res),
 740                                    node->full_name));
 741         BUG_ON(!request_mem_region(per_cpu_int_res.start,
 742                                    resource_size(&per_cpu_int_res),
 743                                    node->full_name));
 744
 745         main_int_base = ioremap(main_int_res.start,
 746                                 resource_size(&main_int_res));
 747         BUG_ON(!main_int_base);
 748
 749         per_cpu_int_base = ioremap(per_cpu_int_res.start,
 750                                    resource_size(&per_cpu_int_res));
 751         BUG_ON(!per_cpu_int_base);
 752
 753         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 754         nr_irqs = (control >> 2) & 0x3ff;
 755
 756         for (i = 0; i < nr_irqs; i++)
 757                 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
 758
 759         armada_370_xp_mpic_domain =
 760                 irq_domain_add_linear(node, nr_irqs,
 761                                 &armada_370_xp_mpic_irq_ops, NULL);
 762         BUG_ON(!armada_370_xp_mpic_domain);
 763         irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
 764
 765         /* Setup for the boot CPU */
 766         armada_xp_mpic_perf_init();
 767         armada_xp_mpic_smp_cpu_init();
 768
 769         armada_370_xp_msi_init(node, main_int_res.start);
 770
 771         parent_irq = irq_of_parse_and_map(node, 0);
 772         if (parent_irq <= 0) {
 773                 irq_set_default_host(armada_370_xp_mpic_domain);
 774                 set_handle_irq(armada_370_xp_handle_irq);
 775 #ifdef CONFIG_SMP
 776                 armada_xp_ipi_init(node);
 777                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
 778                                           "irqchip/armada/ipi:starting",
 779                                           armada_xp_mpic_starting_cpu, NULL);
 780 #endif
 781         } else {
 782 #ifdef CONFIG_SMP
 783                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
 784                                           "irqchip/armada/cascade:starting",
 785                                           mpic_cascaded_starting_cpu, NULL);
 786 #endif
 787                 irq_set_chained_handler(parent_irq,
 788                                         armada_370_xp_mpic_handle_cascade_irq);
 789         }
 790
 791         register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
 792
 793         return 0;
 794 }
 795
 796 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);