drivers/clk/ux500/clk.h

   1 /*
   2  * Clocks for ux500 platforms
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <[email protected]>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #ifndef __UX500_CLK_H
  11 #define __UX500_CLK_H
  12
  13 #include <linux/device.h>
  14 #include <linux/types.h>
  15
  16 struct clk;
  17
  18 struct clk *clk_reg_prcc_pclk(const char *name,
  19                               const char *parent_name,
  20                               resource_size_t phy_base,
  21                               u32 cg_sel,
  22                               unsigned long flags);
  23
  24 struct clk *clk_reg_prcc_kclk(const char *name,
  25                               const char *parent_name,
  26                               resource_size_t phy_base,
  27                               u32 cg_sel,
  28                               unsigned long flags);
  29
  30 struct clk *clk_reg_prcmu_scalable(const char *name,
  31                                    const char *parent_name,
  32                                    u8 cg_sel,
  33                                    unsigned long rate,
  34                                    unsigned long flags);
  35
  36 struct clk *clk_reg_prcmu_gate(const char *name,
  37                                const char *parent_name,
  38                                u8 cg_sel,
  39                                unsigned long flags);
  40
  41 struct clk *clk_reg_prcmu_scalable_rate(const char *name,
  42                                         const char *parent_name,
  43                                         u8 cg_sel,
  44                                         unsigned long rate,
  45                                         unsigned long flags);
  46
  47 struct clk *clk_reg_prcmu_rate(const char *name,
  48                                const char *parent_name,
  49                                u8 cg_sel,
  50                                unsigned long flags);
  51
  52 struct clk *clk_reg_prcmu_opp_gate(const char *name,
  53                                    const char *parent_name,
  54                                    u8 cg_sel,
  55                                    unsigned long flags);
  56
  57 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
  58                                             const char *parent_name,
  59                                             u8 cg_sel,
  60                                             unsigned long rate,
  61                                             unsigned long flags);
  62
  63 struct clk *clk_reg_sysctrl_gate(struct device *dev,
  64                                  const char *name,
  65                                  const char *parent_name,
  66                                  u16 reg_sel,
  67                                  u8 reg_mask,
  68                                  u8 reg_bits,
  69                                  unsigned long enable_delay_us,
  70                                  unsigned long flags);
  71
  72 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
  73                                             const char *name,
  74                                             const char *parent_name,
  75                                             u16 reg_sel,
  76                                             u8 reg_mask,
  77                                             u8 reg_bits,
  78                                             unsigned long rate,
  79                                             unsigned long enable_delay_us,
  80                                             unsigned long flags);
  81
  82 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
  83                                        const char *name,
  84                                        const char **parent_names,
  85                                        u8 num_parents,
  86                                        u16 *reg_sel,
  87                                        u8 *reg_mask,
  88                                        u8 *reg_bits,
  89                                        unsigned long flags);
  90
  91 #endif /* __UX500_CLK_H */