drivers/clk/davinci/psc-da850.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PSC clock descriptions for TI DA850/OMAP-L138/AM18XX
   4  *
   5  * Copyright (C) 2018 David Lechner <[email protected]>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/reset-controller.h>
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/of.h>
  15 #include <linux/types.h>
  16
  17 #include "psc.h"
  18
  19 LPSC_CLKDEV2(emifa_clkdev,      NULL,           "ti-aemif",
  20                                 "aemif",        "davinci_nand.0");
  21 LPSC_CLKDEV1(spi0_clkdev,       NULL,           "spi_davinci.0");
  22 LPSC_CLKDEV1(mmcsd0_clkdev,     NULL,           "da830-mmc.0");
  23 LPSC_CLKDEV1(uart0_clkdev,      NULL,           "serial8250.0");
  24 /* REVISIT: used dev_id instead of con_id */
  25 LPSC_CLKDEV1(arm_clkdev,        "arm",          NULL);
  26 LPSC_CLKDEV1(dsp_clkdev,        NULL,           "davinci-rproc.0");
  27
  28 static const struct davinci_lpsc_clk_info da850_psc0_info[] = {
  29         LPSC(0,  0, tpcc0,   pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
  30         LPSC(1,  0, tptc0,   pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
  31         LPSC(2,  0, tptc1,   pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
  32         LPSC(3,  0, emifa,   async1,       emifa_clkdev,  0),
  33         LPSC(4,  0, spi0,    pll0_sysclk2, spi0_clkdev,   0),
  34         LPSC(5,  0, mmcsd0,  pll0_sysclk2, mmcsd0_clkdev, 0),
  35         LPSC(6,  0, aintc,   pll0_sysclk4, NULL,          LPSC_ALWAYS_ENABLED),
  36         LPSC(7,  0, arm_rom, pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
  37         LPSC(9,  0, uart0,   pll0_sysclk2, uart0_clkdev,  0),
  38         LPSC(13, 0, pruss,   pll0_sysclk2, NULL,          0),
  39         LPSC(14, 0, arm,     pll0_sysclk6, arm_clkdev,    LPSC_ALWAYS_ENABLED | LPSC_SET_RATE_PARENT),
  40         LPSC(15, 1, dsp,     pll0_sysclk1, dsp_clkdev,    LPSC_FORCE | LPSC_LOCAL_RESET),
  41         { }
  42 };
  43
  44 LPSC_CLKDEV3(usb0_clkdev,       "fck",  "da830-usb-phy-clks",
  45                                 NULL,   "musb-da8xx",
  46                                 NULL,   "cppi41-dmaengine");
  47 LPSC_CLKDEV1(usb1_clkdev,       NULL,   "ohci-da8xx");
  48 /* REVISIT: gpio-davinci.c should be modified to drop con_id */
  49 LPSC_CLKDEV1(gpio_clkdev,       "gpio", NULL);
  50 LPSC_CLKDEV2(emac_clkdev,       NULL,   "davinci_emac.1",
  51                                 "fck",  "davinci_mdio.0");
  52 LPSC_CLKDEV1(mcasp0_clkdev,     NULL,   "davinci-mcasp.0");
  53 LPSC_CLKDEV1(sata_clkdev,       "fck",  "ahci_da850");
  54 LPSC_CLKDEV1(vpif_clkdev,       NULL,   "vpif");
  55 LPSC_CLKDEV1(spi1_clkdev,       NULL,   "spi_davinci.1");
  56 LPSC_CLKDEV1(i2c1_clkdev,       NULL,   "i2c_davinci.2");
  57 LPSC_CLKDEV1(uart1_clkdev,      NULL,   "serial8250.1");
  58 LPSC_CLKDEV1(uart2_clkdev,      NULL,   "serial8250.2");
  59 LPSC_CLKDEV1(mcbsp0_clkdev,     NULL,   "davinci-mcbsp.0");
  60 LPSC_CLKDEV1(mcbsp1_clkdev,     NULL,   "davinci-mcbsp.1");
  61 LPSC_CLKDEV1(lcdc_clkdev,       "fck",  "da8xx_lcdc.0");
  62 LPSC_CLKDEV3(ehrpwm_clkdev,     "fck",  "ehrpwm.0",
  63                                 "fck",  "ehrpwm.1",
  64                                 NULL,   "da830-tbclksync");
  65 LPSC_CLKDEV1(mmcsd1_clkdev,     NULL,   "da830-mmc.1");
  66 LPSC_CLKDEV3(ecap_clkdev,       "fck",  "ecap.0",
  67                                 "fck",  "ecap.1",
  68                                 "fck",  "ecap.2");
  69
  70 static struct reset_control_lookup da850_psc0_reset_lookup_table[] = {
  71         RESET_LOOKUP("da850-psc0", 15, "davinci-rproc.0", NULL),
  72 };
  73
  74 static int da850_psc0_init(struct device *dev, void __iomem *base)
  75 {
  76         reset_controller_add_lookup(da850_psc0_reset_lookup_table,
  77                                     ARRAY_SIZE(da850_psc0_reset_lookup_table));
  78         return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base);
  79 }
  80
  81 static int of_da850_psc0_init(struct device *dev, void __iomem *base)
  82 {
  83         return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base);
  84 }
  85
  86 static struct clk_bulk_data da850_psc0_parent_clks[] = {
  87         { .id = "pll0_sysclk1" },
  88         { .id = "pll0_sysclk2" },
  89         { .id = "pll0_sysclk4" },
  90         { .id = "pll0_sysclk6" },
  91         { .id = "async1"       },
  92 };
  93
  94 const struct davinci_psc_init_data da850_psc0_init_data = {
  95         .parent_clks            = da850_psc0_parent_clks,
  96         .num_parent_clks        = ARRAY_SIZE(da850_psc0_parent_clks),
  97         .psc_init               = &da850_psc0_init,
  98 };
  99
 100 const struct davinci_psc_init_data of_da850_psc0_init_data = {
 101         .parent_clks            = da850_psc0_parent_clks,
 102         .num_parent_clks        = ARRAY_SIZE(da850_psc0_parent_clks),
 103         .psc_init               = &of_da850_psc0_init,
 104 };
 105
 106 static const struct davinci_lpsc_clk_info da850_psc1_info[] = {
 107         LPSC(0,  0, tpcc1,  pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
 108         LPSC(1,  0, usb0,   pll0_sysclk2, usb0_clkdev,   0),
 109         LPSC(2,  0, usb1,   pll0_sysclk4, usb1_clkdev,   0),
 110         LPSC(3,  0, gpio,   pll0_sysclk4, gpio_clkdev,   0),
 111         LPSC(5,  0, emac,   pll0_sysclk4, emac_clkdev,   0),
 112         LPSC(6,  0, ddr,    pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
 113         LPSC(7,  0, mcasp0, async3,       mcasp0_clkdev, 0),
 114         LPSC(8,  0, sata,   pll0_sysclk2, sata_clkdev,   LPSC_FORCE),
 115         LPSC(9,  0, vpif,   pll0_sysclk2, vpif_clkdev,   0),
 116         LPSC(10, 0, spi1,   async3,       spi1_clkdev,   0),
 117         LPSC(11, 0, i2c1,   pll0_sysclk4, i2c1_clkdev,   0),
 118         LPSC(12, 0, uart1,  async3,       uart1_clkdev,  0),
 119         LPSC(13, 0, uart2,  async3,       uart2_clkdev,  0),
 120         LPSC(14, 0, mcbsp0, async3,       mcbsp0_clkdev, 0),
 121         LPSC(15, 0, mcbsp1, async3,       mcbsp1_clkdev, 0),
 122         LPSC(16, 0, lcdc,   pll0_sysclk2, lcdc_clkdev,   0),
 123         LPSC(17, 0, ehrpwm, async3,       ehrpwm_clkdev, 0),
 124         LPSC(18, 0, mmcsd1, pll0_sysclk2, mmcsd1_clkdev, 0),
 125         LPSC(20, 0, ecap,   async3,       ecap_clkdev,   0),
 126         LPSC(21, 0, tptc2,  pll0_sysclk2, NULL,          LPSC_ALWAYS_ENABLED),
 127         { }
 128 };
 129
 130 static int da850_psc1_init(struct device *dev, void __iomem *base)
 131 {
 132         return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base);
 133 }
 134
 135 static int of_da850_psc1_init(struct device *dev, void __iomem *base)
 136 {
 137         return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base);
 138 }
 139
 140 static struct clk_bulk_data da850_psc1_parent_clks[] = {
 141         { .id = "pll0_sysclk2" },
 142         { .id = "pll0_sysclk4" },
 143         { .id = "async3"       },
 144 };
 145
 146 const struct davinci_psc_init_data da850_psc1_init_data = {
 147         .parent_clks            = da850_psc1_parent_clks,
 148         .num_parent_clks        = ARRAY_SIZE(da850_psc1_parent_clks),
 149         .psc_init               = &da850_psc1_init,
 150 };
 151
 152 const struct davinci_psc_init_data of_da850_psc1_init_data = {
 153         .parent_clks            = da850_psc1_parent_clks,
 154         .num_parent_clks        = ARRAY_SIZE(da850_psc1_parent_clks),
 155         .psc_init               = &of_da850_psc1_init,
 156 };