drivers/base/regmap/regmap-irq.c

   1 /*
   2  * regmap based irq_chip
   3  *
   4  * Copyright 2011 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <[email protected]>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/export.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/slab.h>
  21
  22 #include "internal.h"
  23
  24 struct regmap_irq_chip_data {
  25         struct mutex lock;
  26         struct irq_chip irq_chip;
  27
  28         struct regmap *map;
  29         const struct regmap_irq_chip *chip;
  30
  31         int irq_base;
  32         struct irq_domain *domain;
  33
  34         int irq;
  35         int wake_count;
  36
  37         void *status_reg_buf;
  38         unsigned int *status_buf;
  39         unsigned int *mask_buf;
  40         unsigned int *mask_buf_def;
  41         unsigned int *wake_buf;
  42         unsigned int *type_buf;
  43         unsigned int *type_buf_def;
  44
  45         unsigned int irq_reg_stride;
  46         unsigned int type_reg_stride;
  47 };
  48
  49 static inline const
  50 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  51                                      int irq)
  52 {
  53         return &data->chip->irqs[irq];
  54 }
  55
  56 static void regmap_irq_lock(struct irq_data *data)
  57 {
  58         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  59
  60         mutex_lock(&d->lock);
  61 }
  62
  63 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
  64                                   unsigned int reg, unsigned int mask,
  65                                   unsigned int val)
  66 {
  67         if (d->chip->mask_writeonly)
  68                 return regmap_write_bits(d->map, reg, mask, val);
  69         else
  70                 return regmap_update_bits(d->map, reg, mask, val);
  71 }
  72
  73 static void regmap_irq_sync_unlock(struct irq_data *data)
  74 {
  75         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  76         struct regmap *map = d->map;
  77         int i, ret;
  78         u32 reg;
  79         u32 unmask_offset;
  80
  81         if (d->chip->runtime_pm) {
  82                 ret = pm_runtime_get_sync(map->dev);
  83                 if (ret < 0)
  84                         dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  85                                 ret);
  86         }
  87
  88         /*
  89          * If there's been a change in the mask write it back to the
  90          * hardware.  We rely on the use of the regmap core cache to
  91          * suppress pointless writes.
  92          */
  93         for (i = 0; i < d->chip->num_regs; i++) {
  94                 reg = d->chip->mask_base +
  95                         (i * map->reg_stride * d->irq_reg_stride);
  96                 if (d->chip->mask_invert) {
  97                         ret = regmap_irq_update_bits(d, reg,
  98                                          d->mask_buf_def[i], ~d->mask_buf[i]);
  99                 } else if (d->chip->unmask_base) {
 100                         /* set mask with mask_base register */
 101                         ret = regmap_irq_update_bits(d, reg,
 102                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 103                         if (ret < 0)
 104                                 dev_err(d->map->dev,
 105                                         "Failed to sync unmasks in %x\n",
 106                                         reg);
 107                         unmask_offset = d->chip->unmask_base -
 108                                                         d->chip->mask_base;
 109                         /* clear mask with unmask_base register */
 110                         ret = regmap_irq_update_bits(d,
 111                                         reg + unmask_offset,
 112                                         d->mask_buf_def[i],
 113                                         d->mask_buf[i]);
 114                 } else {
 115                         ret = regmap_irq_update_bits(d, reg,
 116                                          d->mask_buf_def[i], d->mask_buf[i]);
 117                 }
 118                 if (ret != 0)
 119                         dev_err(d->map->dev, "Failed to sync masks in %x\n",
 120                                 reg);
 121
 122                 reg = d->chip->wake_base +
 123                         (i * map->reg_stride * d->irq_reg_stride);
 124                 if (d->wake_buf) {
 125                         if (d->chip->wake_invert)
 126                                 ret = regmap_irq_update_bits(d, reg,
 127                                                          d->mask_buf_def[i],
 128                                                          ~d->wake_buf[i]);
 129                         else
 130                                 ret = regmap_irq_update_bits(d, reg,
 131                                                          d->mask_buf_def[i],
 132                                                          d->wake_buf[i]);
 133                         if (ret != 0)
 134                                 dev_err(d->map->dev,
 135                                         "Failed to sync wakes in %x: %d\n",
 136                                         reg, ret);
 137                 }
 138
 139                 if (!d->chip->init_ack_masked)
 140                         continue;
 141                 /*
 142                  * Ack all the masked interrupts unconditionally,
 143                  * OR if there is masked interrupt which hasn't been Acked,
 144                  * it'll be ignored in irq handler, then may introduce irq storm
 145                  */
 146                 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 147                         reg = d->chip->ack_base +
 148                                 (i * map->reg_stride * d->irq_reg_stride);
 149                         /* some chips ack by write 0 */
 150                         if (d->chip->ack_invert)
 151                                 ret = regmap_write(map, reg, ~d->mask_buf[i]);
 152                         else
 153                                 ret = regmap_write(map, reg, d->mask_buf[i]);
 154                         if (ret != 0)
 155                                 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 156                                         reg, ret);
 157                 }
 158         }
 159
 160         for (i = 0; i < d->chip->num_type_reg; i++) {
 161                 if (!d->type_buf_def[i])
 162                         continue;
 163                 reg = d->chip->type_base +
 164                         (i * map->reg_stride * d->type_reg_stride);
 165                 if (d->chip->type_invert)
 166                         ret = regmap_irq_update_bits(d, reg,
 167                                 d->type_buf_def[i], ~d->type_buf[i]);
 168                 else
 169                         ret = regmap_irq_update_bits(d, reg,
 170                                 d->type_buf_def[i], d->type_buf[i]);
 171                 if (ret != 0)
 172                         dev_err(d->map->dev, "Failed to sync type in %x\n",
 173                                 reg);
 174         }
 175
 176         if (d->chip->runtime_pm)
 177                 pm_runtime_put(map->dev);
 178
 179         /* If we've changed our wakeup count propagate it to the parent */
 180         if (d->wake_count < 0)
 181                 for (i = d->wake_count; i < 0; i++)
 182                         irq_set_irq_wake(d->irq, 0);
 183         else if (d->wake_count > 0)
 184                 for (i = 0; i < d->wake_count; i++)
 185                         irq_set_irq_wake(d->irq, 1);
 186
 187         d->wake_count = 0;
 188
 189         mutex_unlock(&d->lock);
 190 }
 191
 192 static void regmap_irq_enable(struct irq_data *data)
 193 {
 194         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 195         struct regmap *map = d->map;
 196         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 197
 198         d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
 199 }
 200
 201 static void regmap_irq_disable(struct irq_data *data)
 202 {
 203         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 204         struct regmap *map = d->map;
 205         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 206
 207         d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 208 }
 209
 210 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 211 {
 212         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 213         struct regmap *map = d->map;
 214         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 215         int reg = irq_data->type_reg_offset / map->reg_stride;
 216
 217         if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
 218                 return 0;
 219
 220         d->type_buf[reg] &= ~(irq_data->type_falling_mask |
 221                                         irq_data->type_rising_mask);
 222         switch (type) {
 223         case IRQ_TYPE_EDGE_FALLING:
 224                 d->type_buf[reg] |= irq_data->type_falling_mask;
 225                 break;
 226
 227         case IRQ_TYPE_EDGE_RISING:
 228                 d->type_buf[reg] |= irq_data->type_rising_mask;
 229                 break;
 230
 231         case IRQ_TYPE_EDGE_BOTH:
 232                 d->type_buf[reg] |= (irq_data->type_falling_mask |
 233                                         irq_data->type_rising_mask);
 234                 break;
 235
 236         default:
 237                 return -EINVAL;
 238         }
 239         return 0;
 240 }
 241
 242 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 243 {
 244         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 245         struct regmap *map = d->map;
 246         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 247
 248         if (on) {
 249                 if (d->wake_buf)
 250                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 251                                 &= ~irq_data->mask;
 252                 d->wake_count++;
 253         } else {
 254                 if (d->wake_buf)
 255                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 256                                 |= irq_data->mask;
 257                 d->wake_count--;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static const struct irq_chip regmap_irq_chip = {
 264         .irq_bus_lock           = regmap_irq_lock,
 265         .irq_bus_sync_unlock    = regmap_irq_sync_unlock,
 266         .irq_disable            = regmap_irq_disable,
 267         .irq_enable             = regmap_irq_enable,
 268         .irq_set_type           = regmap_irq_set_type,
 269         .irq_set_wake           = regmap_irq_set_wake,
 270 };
 271
 272 static irqreturn_t regmap_irq_thread(int irq, void *d)
 273 {
 274         struct regmap_irq_chip_data *data = d;
 275         const struct regmap_irq_chip *chip = data->chip;
 276         struct regmap *map = data->map;
 277         int ret, i;
 278         bool handled = false;
 279         u32 reg;
 280
 281         if (chip->handle_pre_irq)
 282                 chip->handle_pre_irq(chip->irq_drv_data);
 283
 284         if (chip->runtime_pm) {
 285                 ret = pm_runtime_get_sync(map->dev);
 286                 if (ret < 0) {
 287                         dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 288                                 ret);
 289                         pm_runtime_put(map->dev);
 290                         goto exit;
 291                 }
 292         }
 293
 294         /*
 295          * Read in the statuses, using a single bulk read if possible
 296          * in order to reduce the I/O overheads.
 297          */
 298         if (!map->use_single_read && map->reg_stride == 1 &&
 299             data->irq_reg_stride == 1) {
 300                 u8 *buf8 = data->status_reg_buf;
 301                 u16 *buf16 = data->status_reg_buf;
 302                 u32 *buf32 = data->status_reg_buf;
 303
 304                 BUG_ON(!data->status_reg_buf);
 305
 306                 ret = regmap_bulk_read(map, chip->status_base,
 307                                        data->status_reg_buf,
 308                                        chip->num_regs);
 309                 if (ret != 0) {
 310                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 311                                 ret);
 312                         goto exit;
 313                 }
 314
 315                 for (i = 0; i < data->chip->num_regs; i++) {
 316                         switch (map->format.val_bytes) {
 317                         case 1:
 318                                 data->status_buf[i] = buf8[i];
 319                                 break;
 320                         case 2:
 321                                 data->status_buf[i] = buf16[i];
 322                                 break;
 323                         case 4:
 324                                 data->status_buf[i] = buf32[i];
 325                                 break;
 326                         default:
 327                                 BUG();
 328                                 goto exit;
 329                         }
 330                 }
 331
 332         } else {
 333                 for (i = 0; i < data->chip->num_regs; i++) {
 334                         ret = regmap_read(map, chip->status_base +
 335                                           (i * map->reg_stride
 336                                            * data->irq_reg_stride),
 337                                           &data->status_buf[i]);
 338
 339                         if (ret != 0) {
 340                                 dev_err(map->dev,
 341                                         "Failed to read IRQ status: %d\n",
 342                                         ret);
 343                                 if (chip->runtime_pm)
 344                                         pm_runtime_put(map->dev);
 345                                 goto exit;
 346                         }
 347                 }
 348         }
 349
 350         /*
 351          * Ignore masked IRQs and ack if we need to; we ack early so
 352          * there is no race between handling and acknowleding the
 353          * interrupt.  We assume that typically few of the interrupts
 354          * will fire simultaneously so don't worry about overhead from
 355          * doing a write per register.
 356          */
 357         for (i = 0; i < data->chip->num_regs; i++) {
 358                 data->status_buf[i] &= ~data->mask_buf[i];
 359
 360                 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 361                         reg = chip->ack_base +
 362                                 (i * map->reg_stride * data->irq_reg_stride);
 363                         ret = regmap_write(map, reg, data->status_buf[i]);
 364                         if (ret != 0)
 365                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 366                                         reg, ret);
 367                 }
 368         }
 369
 370         for (i = 0; i < chip->num_irqs; i++) {
 371                 if (data->status_buf[chip->irqs[i].reg_offset /
 372                                      map->reg_stride] & chip->irqs[i].mask) {
 373                         handle_nested_irq(irq_find_mapping(data->domain, i));
 374                         handled = true;
 375                 }
 376         }
 377
 378         if (chip->runtime_pm)
 379                 pm_runtime_put(map->dev);
 380
 381 exit:
 382         if (chip->handle_post_irq)
 383                 chip->handle_post_irq(chip->irq_drv_data);
 384
 385         if (handled)
 386                 return IRQ_HANDLED;
 387         else
 388                 return IRQ_NONE;
 389 }
 390
 391 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 392                           irq_hw_number_t hw)
 393 {
 394         struct regmap_irq_chip_data *data = h->host_data;
 395
 396         irq_set_chip_data(virq, data);
 397         irq_set_chip(virq, &data->irq_chip);
 398         irq_set_nested_thread(virq, 1);
 399         irq_set_parent(virq, data->irq);
 400         irq_set_noprobe(virq);
 401
 402         return 0;
 403 }
 404
 405 static const struct irq_domain_ops regmap_domain_ops = {
 406         .map    = regmap_irq_map,
 407         .xlate  = irq_domain_xlate_onetwocell,
 408 };
 409
 410 /**
 411  * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
 412  *
 413  * @map: The regmap for the device.
 414  * @irq: The IRQ the device uses to signal interrupts.
 415  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 416  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 417  * @chip: Configuration for the interrupt controller.
 418  * @data: Runtime data structure for the controller, allocated on success.
 419  *
 420  * Returns 0 on success or an errno on failure.
 421  *
 422  * In order for this to be efficient the chip really should use a
 423  * register cache.  The chip driver is responsible for restoring the
 424  * register values used by the IRQ controller over suspend and resume.
 425  */
 426 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 427                         int irq_base, const struct regmap_irq_chip *chip,
 428                         struct regmap_irq_chip_data **data)
 429 {
 430         struct regmap_irq_chip_data *d;
 431         int i;
 432         int ret = -ENOMEM;
 433         u32 reg;
 434         u32 unmask_offset;
 435
 436         if (chip->num_regs <= 0)
 437                 return -EINVAL;
 438
 439         for (i = 0; i < chip->num_irqs; i++) {
 440                 if (chip->irqs[i].reg_offset % map->reg_stride)
 441                         return -EINVAL;
 442                 if (chip->irqs[i].reg_offset / map->reg_stride >=
 443                     chip->num_regs)
 444                         return -EINVAL;
 445         }
 446
 447         if (irq_base) {
 448                 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 449                 if (irq_base < 0) {
 450                         dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 451                                  irq_base);
 452                         return irq_base;
 453                 }
 454         }
 455
 456         d = kzalloc(sizeof(*d), GFP_KERNEL);
 457         if (!d)
 458                 return -ENOMEM;
 459
 460         d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 461                                 GFP_KERNEL);
 462         if (!d->status_buf)
 463                 goto err_alloc;
 464
 465         d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 466                               GFP_KERNEL);
 467         if (!d->mask_buf)
 468                 goto err_alloc;
 469
 470         d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
 471                                   GFP_KERNEL);
 472         if (!d->mask_buf_def)
 473                 goto err_alloc;
 474
 475         if (chip->wake_base) {
 476                 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 477                                       GFP_KERNEL);
 478                 if (!d->wake_buf)
 479                         goto err_alloc;
 480         }
 481
 482         if (chip->num_type_reg) {
 483                 d->type_buf_def = kcalloc(chip->num_type_reg,
 484                                         sizeof(unsigned int), GFP_KERNEL);
 485                 if (!d->type_buf_def)
 486                         goto err_alloc;
 487
 488                 d->type_buf = kcalloc(chip->num_type_reg, sizeof(unsigned int),
 489                                       GFP_KERNEL);
 490                 if (!d->type_buf)
 491                         goto err_alloc;
 492         }
 493
 494         d->irq_chip = regmap_irq_chip;
 495         d->irq_chip.name = chip->name;
 496         d->irq = irq;
 497         d->map = map;
 498         d->chip = chip;
 499         d->irq_base = irq_base;
 500
 501         if (chip->irq_reg_stride)
 502                 d->irq_reg_stride = chip->irq_reg_stride;
 503         else
 504                 d->irq_reg_stride = 1;
 505
 506         if (chip->type_reg_stride)
 507                 d->type_reg_stride = chip->type_reg_stride;
 508         else
 509                 d->type_reg_stride = 1;
 510
 511         if (!map->use_single_read && map->reg_stride == 1 &&
 512             d->irq_reg_stride == 1) {
 513                 d->status_reg_buf = kmalloc_array(chip->num_regs,
 514                                                   map->format.val_bytes,
 515                                                   GFP_KERNEL);
 516                 if (!d->status_reg_buf)
 517                         goto err_alloc;
 518         }
 519
 520         mutex_init(&d->lock);
 521
 522         for (i = 0; i < chip->num_irqs; i++)
 523                 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 524                         |= chip->irqs[i].mask;
 525
 526         /* Mask all the interrupts by default */
 527         for (i = 0; i < chip->num_regs; i++) {
 528                 d->mask_buf[i] = d->mask_buf_def[i];
 529                 reg = chip->mask_base +
 530                         (i * map->reg_stride * d->irq_reg_stride);
 531                 if (chip->mask_invert)
 532                         ret = regmap_irq_update_bits(d, reg,
 533                                          d->mask_buf[i], ~d->mask_buf[i]);
 534                 else if (d->chip->unmask_base) {
 535                         unmask_offset = d->chip->unmask_base -
 536                                         d->chip->mask_base;
 537                         ret = regmap_irq_update_bits(d,
 538                                         reg + unmask_offset,
 539                                         d->mask_buf[i],
 540                                         d->mask_buf[i]);
 541                 } else
 542                         ret = regmap_irq_update_bits(d, reg,
 543                                          d->mask_buf[i], d->mask_buf[i]);
 544                 if (ret != 0) {
 545                         dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 546                                 reg, ret);
 547                         goto err_alloc;
 548                 }
 549
 550                 if (!chip->init_ack_masked)
 551                         continue;
 552
 553                 /* Ack masked but set interrupts */
 554                 reg = chip->status_base +
 555                         (i * map->reg_stride * d->irq_reg_stride);
 556                 ret = regmap_read(map, reg, &d->status_buf[i]);
 557                 if (ret != 0) {
 558                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 559                                 ret);
 560                         goto err_alloc;
 561                 }
 562
 563                 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 564                         reg = chip->ack_base +
 565                                 (i * map->reg_stride * d->irq_reg_stride);
 566                         if (chip->ack_invert)
 567                                 ret = regmap_write(map, reg,
 568                                         ~(d->status_buf[i] & d->mask_buf[i]));
 569                         else
 570                                 ret = regmap_write(map, reg,
 571                                         d->status_buf[i] & d->mask_buf[i]);
 572                         if (ret != 0) {
 573                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 574                                         reg, ret);
 575                                 goto err_alloc;
 576                         }
 577                 }
 578         }
 579
 580         /* Wake is disabled by default */
 581         if (d->wake_buf) {
 582                 for (i = 0; i < chip->num_regs; i++) {
 583                         d->wake_buf[i] = d->mask_buf_def[i];
 584                         reg = chip->wake_base +
 585                                 (i * map->reg_stride * d->irq_reg_stride);
 586
 587                         if (chip->wake_invert)
 588                                 ret = regmap_irq_update_bits(d, reg,
 589                                                          d->mask_buf_def[i],
 590                                                          0);
 591                         else
 592                                 ret = regmap_irq_update_bits(d, reg,
 593                                                          d->mask_buf_def[i],
 594                                                          d->wake_buf[i]);
 595                         if (ret != 0) {
 596                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 597                                         reg, ret);
 598                                 goto err_alloc;
 599                         }
 600                 }
 601         }
 602
 603         if (chip->num_type_reg) {
 604                 for (i = 0; i < chip->num_irqs; i++) {
 605                         reg = chip->irqs[i].type_reg_offset / map->reg_stride;
 606                         d->type_buf_def[reg] |= chip->irqs[i].type_rising_mask |
 607                                         chip->irqs[i].type_falling_mask;
 608                 }
 609                 for (i = 0; i < chip->num_type_reg; ++i) {
 610                         if (!d->type_buf_def[i])
 611                                 continue;
 612
 613                         reg = chip->type_base +
 614                                 (i * map->reg_stride * d->type_reg_stride);
 615                         if (chip->type_invert)
 616                                 ret = regmap_irq_update_bits(d, reg,
 617                                         d->type_buf_def[i], 0xFF);
 618                         else
 619                                 ret = regmap_irq_update_bits(d, reg,
 620                                         d->type_buf_def[i], 0x0);
 621                         if (ret != 0) {
 622                                 dev_err(map->dev,
 623                                         "Failed to set type in 0x%x: %x\n",
 624                                         reg, ret);
 625                                 goto err_alloc;
 626                         }
 627                 }
 628         }
 629
 630         if (irq_base)
 631                 d->domain = irq_domain_add_legacy(map->dev->of_node,
 632                                                   chip->num_irqs, irq_base, 0,
 633                                                   &regmap_domain_ops, d);
 634         else
 635                 d->domain = irq_domain_add_linear(map->dev->of_node,
 636                                                   chip->num_irqs,
 637                                                   &regmap_domain_ops, d);
 638         if (!d->domain) {
 639                 dev_err(map->dev, "Failed to create IRQ domain\n");
 640                 ret = -ENOMEM;
 641                 goto err_alloc;
 642         }
 643
 644         ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 645                                    irq_flags | IRQF_ONESHOT,
 646                                    chip->name, d);
 647         if (ret != 0) {
 648                 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 649                         irq, chip->name, ret);
 650                 goto err_domain;
 651         }
 652
 653         *data = d;
 654
 655         return 0;
 656
 657 err_domain:
 658         /* Should really dispose of the domain but... */
 659 err_alloc:
 660         kfree(d->type_buf);
 661         kfree(d->type_buf_def);
 662         kfree(d->wake_buf);
 663         kfree(d->mask_buf_def);
 664         kfree(d->mask_buf);
 665         kfree(d->status_buf);
 666         kfree(d->status_reg_buf);
 667         kfree(d);
 668         return ret;
 669 }
 670 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 671
 672 /**
 673  * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
 674  *
 675  * @irq: Primary IRQ for the device
 676  * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
 677  *
 678  * This function also disposes of all mapped IRQs on the chip.
 679  */
 680 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 681 {
 682         unsigned int virq;
 683         int hwirq;
 684
 685         if (!d)
 686                 return;
 687
 688         free_irq(irq, d);
 689
 690         /* Dispose all virtual irq from irq domain before removing it */
 691         for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
 692                 /* Ignore hwirq if holes in the IRQ list */
 693                 if (!d->chip->irqs[hwirq].mask)
 694                         continue;
 695
 696                 /*
 697                  * Find the virtual irq of hwirq on chip and if it is
 698                  * there then dispose it
 699                  */
 700                 virq = irq_find_mapping(d->domain, hwirq);
 701                 if (virq)
 702                         irq_dispose_mapping(virq);
 703         }
 704
 705         irq_domain_remove(d->domain);
 706         kfree(d->type_buf);
 707         kfree(d->type_buf_def);
 708         kfree(d->wake_buf);
 709         kfree(d->mask_buf_def);
 710         kfree(d->mask_buf);
 711         kfree(d->status_reg_buf);
 712         kfree(d->status_buf);
 713         kfree(d);
 714 }
 715 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 716
 717 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
 718 {
 719         struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
 720
 721         regmap_del_irq_chip(d->irq, d);
 722 }
 723
 724 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
 725
 726 {
 727         struct regmap_irq_chip_data **r = res;
 728
 729         if (!r || !*r) {
 730                 WARN_ON(!r || !*r);
 731                 return 0;
 732         }
 733         return *r == data;
 734 }
 735
 736 /**
 737  * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
 738  *
 739  * @dev: The device pointer on which irq_chip belongs to.
 740  * @map: The regmap for the device.
 741  * @irq: The IRQ the device uses to signal interrupts
 742  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 743  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 744  * @chip: Configuration for the interrupt controller.
 745  * @data: Runtime data structure for the controller, allocated on success
 746  *
 747  * Returns 0 on success or an errno on failure.
 748  *
 749  * The &regmap_irq_chip_data will be automatically released when the device is
 750  * unbound.
 751  */
 752 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
 753                              int irq_flags, int irq_base,
 754                              const struct regmap_irq_chip *chip,
 755                              struct regmap_irq_chip_data **data)
 756 {
 757         struct regmap_irq_chip_data **ptr, *d;
 758         int ret;
 759
 760         ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
 761                            GFP_KERNEL);
 762         if (!ptr)
 763                 return -ENOMEM;
 764
 765         ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
 766                                   chip, &d);
 767         if (ret < 0) {
 768                 devres_free(ptr);
 769                 return ret;
 770         }
 771
 772         *ptr = d;
 773         devres_add(dev, ptr);
 774         *data = d;
 775         return 0;
 776 }
 777 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
 778
 779 /**
 780  * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
 781  *
 782  * @dev: Device for which which resource was allocated.
 783  * @irq: Primary IRQ for the device.
 784  * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
 785  *
 786  * A resource managed version of regmap_del_irq_chip().
 787  */
 788 void devm_regmap_del_irq_chip(struct device *dev, int irq,
 789                               struct regmap_irq_chip_data *data)
 790 {
 791         int rc;
 792
 793         WARN_ON(irq != data->irq);
 794         rc = devres_release(dev, devm_regmap_irq_chip_release,
 795                             devm_regmap_irq_chip_match, data);
 796
 797         if (rc != 0)
 798                 WARN_ON(rc);
 799 }
 800 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
 801
 802 /**
 803  * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
 804  *
 805  * @data: regmap irq controller to operate on.
 806  *
 807  * Useful for drivers to request their own IRQs.
 808  */
 809 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
 810 {
 811         WARN_ON(!data->irq_base);
 812         return data->irq_base;
 813 }
 814 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
 815
 816 /**
 817  * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
 818  *
 819  * @data: regmap irq controller to operate on.
 820  * @irq: index of the interrupt requested in the chip IRQs.
 821  *
 822  * Useful for drivers to request their own IRQs.
 823  */
 824 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
 825 {
 826         /* Handle holes in the IRQ list */
 827         if (!data->chip->irqs[irq].mask)
 828                 return -EINVAL;
 829
 830         return irq_create_mapping(data->domain, irq);
 831 }
 832 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
 833
 834 /**
 835  * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
 836  *
 837  * @data: regmap_irq controller to operate on.
 838  *
 839  * Useful for drivers to request their own IRQs and for integration
 840  * with subsystems.  For ease of integration NULL is accepted as a
 841  * domain, allowing devices to just call this even if no domain is
 842  * allocated.
 843  */
 844 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
 845 {
 846         if (data)
 847                 return data->domain;
 848         else
 849                 return NULL;
 850 }
 851 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);