drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31
  32 #include "vcn/vcn_1_0_offset.h"
  33 #include "vcn/vcn_1_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "mmhub/mmhub_9_1_offset.h"
  36 #include "mmhub/mmhub_9_1_sh_mask.h"
  37
  38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  39
  40 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  41 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  42 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  43 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
  44 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  45 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
  46
  47 /**
  48  * vcn_v1_0_early_init - set function pointers
  49  *
  50  * @handle: amdgpu_device pointer
  51  *
  52  * Set ring and irq function pointers
  53  */
  54 static int vcn_v1_0_early_init(void *handle)
  55 {
  56         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  57
  58         adev->vcn.num_enc_rings = 2;
  59
  60         vcn_v1_0_set_dec_ring_funcs(adev);
  61         vcn_v1_0_set_enc_ring_funcs(adev);
  62         vcn_v1_0_set_jpeg_ring_funcs(adev);
  63         vcn_v1_0_set_irq_funcs(adev);
  64
  65         return 0;
  66 }
  67
  68 /**
  69  * vcn_v1_0_sw_init - sw init for VCN block
  70  *
  71  * @handle: amdgpu_device pointer
  72  *
  73  * Load firmware and sw initialization
  74  */
  75 static int vcn_v1_0_sw_init(void *handle)
  76 {
  77         struct amdgpu_ring *ring;
  78         int i, r;
  79         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  80
  81         /* VCN DEC TRAP */
  82         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
  83         if (r)
  84                 return r;
  85
  86         /* VCN ENC TRAP */
  87         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
  88                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
  89                                         &adev->vcn.irq);
  90                 if (r)
  91                         return r;
  92         }
  93
  94         /* VCN JPEG TRAP */
  95         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
  96         if (r)
  97                 return r;
  98
  99         r = amdgpu_vcn_sw_init(adev);
 100         if (r)
 101                 return r;
 102
 103         r = amdgpu_vcn_resume(adev);
 104         if (r)
 105                 return r;
 106
 107         ring = &adev->vcn.ring_dec;
 108         sprintf(ring->name, "vcn_dec");
 109         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 110         if (r)
 111                 return r;
 112
 113         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 114                 ring = &adev->vcn.ring_enc[i];
 115                 sprintf(ring->name, "vcn_enc%d", i);
 116                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 117                 if (r)
 118                         return r;
 119         }
 120
 121         ring = &adev->vcn.ring_jpeg;
 122         sprintf(ring->name, "vcn_jpeg");
 123         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 124         if (r)
 125                 return r;
 126
 127         return r;
 128 }
 129
 130 /**
 131  * vcn_v1_0_sw_fini - sw fini for VCN block
 132  *
 133  * @handle: amdgpu_device pointer
 134  *
 135  * VCN suspend and free up sw allocation
 136  */
 137 static int vcn_v1_0_sw_fini(void *handle)
 138 {
 139         int r;
 140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 141
 142         r = amdgpu_vcn_suspend(adev);
 143         if (r)
 144                 return r;
 145
 146         r = amdgpu_vcn_sw_fini(adev);
 147
 148         return r;
 149 }
 150
 151 /**
 152  * vcn_v1_0_hw_init - start and test VCN block
 153  *
 154  * @handle: amdgpu_device pointer
 155  *
 156  * Initialize the hardware, boot up the VCPU and do some testing
 157  */
 158 static int vcn_v1_0_hw_init(void *handle)
 159 {
 160         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 161         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 162         int i, r;
 163
 164         ring->ready = true;
 165         r = amdgpu_ring_test_ring(ring);
 166         if (r) {
 167                 ring->ready = false;
 168                 goto done;
 169         }
 170
 171         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 172                 ring = &adev->vcn.ring_enc[i];
 173                 ring->ready = true;
 174                 r = amdgpu_ring_test_ring(ring);
 175                 if (r) {
 176                         ring->ready = false;
 177                         goto done;
 178                 }
 179         }
 180
 181         ring = &adev->vcn.ring_jpeg;
 182         ring->ready = true;
 183         r = amdgpu_ring_test_ring(ring);
 184         if (r) {
 185                 ring->ready = false;
 186                 goto done;
 187         }
 188
 189 done:
 190         if (!r)
 191                 DRM_INFO("VCN decode and encode initialized successfully.\n");
 192
 193         return r;
 194 }
 195
 196 /**
 197  * vcn_v1_0_hw_fini - stop the hardware block
 198  *
 199  * @handle: amdgpu_device pointer
 200  *
 201  * Stop the VCN block, mark ring as not ready any more
 202  */
 203 static int vcn_v1_0_hw_fini(void *handle)
 204 {
 205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 206         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 207
 208         if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 209                 vcn_v1_0_stop(adev);
 210
 211         ring->ready = false;
 212
 213         return 0;
 214 }
 215
 216 /**
 217  * vcn_v1_0_suspend - suspend VCN block
 218  *
 219  * @handle: amdgpu_device pointer
 220  *
 221  * HW fini and suspend VCN block
 222  */
 223 static int vcn_v1_0_suspend(void *handle)
 224 {
 225         int r;
 226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 227
 228         r = vcn_v1_0_hw_fini(adev);
 229         if (r)
 230                 return r;
 231
 232         r = amdgpu_vcn_suspend(adev);
 233
 234         return r;
 235 }
 236
 237 /**
 238  * vcn_v1_0_resume - resume VCN block
 239  *
 240  * @handle: amdgpu_device pointer
 241  *
 242  * Resume firmware and hw init VCN block
 243  */
 244 static int vcn_v1_0_resume(void *handle)
 245 {
 246         int r;
 247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 248
 249         r = amdgpu_vcn_resume(adev);
 250         if (r)
 251                 return r;
 252
 253         r = vcn_v1_0_hw_init(adev);
 254
 255         return r;
 256 }
 257
 258 /**
 259  * vcn_v1_0_mc_resume - memory controller programming
 260  *
 261  * @adev: amdgpu_device pointer
 262  *
 263  * Let the VCN memory controller know it's offsets
 264  */
 265 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
 266 {
 267         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 268
 269         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 270                         lower_32_bits(adev->vcn.gpu_addr));
 271         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 272                         upper_32_bits(adev->vcn.gpu_addr));
 273         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 274                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 275         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 276
 277         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 278                         lower_32_bits(adev->vcn.gpu_addr + size));
 279         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 280                         upper_32_bits(adev->vcn.gpu_addr + size));
 281         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 282         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);
 283
 284         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 285                         lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
 286         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 287                         upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
 288         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 289         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
 290                         AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));
 291
 292         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 293                         adev->gfx.config.gb_addr_config);
 294         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 295                         adev->gfx.config.gb_addr_config);
 296         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 297                         adev->gfx.config.gb_addr_config);
 298 }
 299
 300 /**
 301  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 302  *
 303  * @adev: amdgpu_device pointer
 304  * @sw: enable SW clock gating
 305  *
 306  * Disable clock gating for VCN block
 307  */
 308 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 309 {
 310         uint32_t data;
 311
 312         /* JPEG disable CGC */
 313         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 314
 315         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 316                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 317         else
 318                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 319
 320         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 321         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 322         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 323
 324         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 325         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 326         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 327
 328         /* UVD disable CGC */
 329         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 330         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 331                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 332         else
 333                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 334
 335         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 336         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 337         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 338
 339         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 340         data &= ~(UVD_CGC_GATE__SYS_MASK
 341                 | UVD_CGC_GATE__UDEC_MASK
 342                 | UVD_CGC_GATE__MPEG2_MASK
 343                 | UVD_CGC_GATE__REGS_MASK
 344                 | UVD_CGC_GATE__RBC_MASK
 345                 | UVD_CGC_GATE__LMI_MC_MASK
 346                 | UVD_CGC_GATE__LMI_UMC_MASK
 347                 | UVD_CGC_GATE__IDCT_MASK
 348                 | UVD_CGC_GATE__MPRD_MASK
 349                 | UVD_CGC_GATE__MPC_MASK
 350                 | UVD_CGC_GATE__LBSI_MASK
 351                 | UVD_CGC_GATE__LRBBM_MASK
 352                 | UVD_CGC_GATE__UDEC_RE_MASK
 353                 | UVD_CGC_GATE__UDEC_CM_MASK
 354                 | UVD_CGC_GATE__UDEC_IT_MASK
 355                 | UVD_CGC_GATE__UDEC_DB_MASK
 356                 | UVD_CGC_GATE__UDEC_MP_MASK
 357                 | UVD_CGC_GATE__WCB_MASK
 358                 | UVD_CGC_GATE__VCPU_MASK
 359                 | UVD_CGC_GATE__SCPU_MASK);
 360         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 361
 362         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 363         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 364                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 365                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 366                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 367                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 368                 | UVD_CGC_CTRL__SYS_MODE_MASK
 369                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 370                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 371                 | UVD_CGC_CTRL__REGS_MODE_MASK
 372                 | UVD_CGC_CTRL__RBC_MODE_MASK
 373                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 374                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 375                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 376                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 377                 | UVD_CGC_CTRL__MPC_MODE_MASK
 378                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 379                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 380                 | UVD_CGC_CTRL__WCB_MODE_MASK
 381                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 382                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 383         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 384
 385         /* turn on */
 386         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 387         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 388                 | UVD_SUVD_CGC_GATE__SIT_MASK
 389                 | UVD_SUVD_CGC_GATE__SMP_MASK
 390                 | UVD_SUVD_CGC_GATE__SCM_MASK
 391                 | UVD_SUVD_CGC_GATE__SDB_MASK
 392                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 393                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 394                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 395                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 396                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 397                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 398                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 399                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 400                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 401                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 402                 | UVD_SUVD_CGC_GATE__ENT_MASK
 403                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 404                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 405                 | UVD_SUVD_CGC_GATE__SITE_MASK
 406                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 407                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 408                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 409                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 410                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 411         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 412
 413         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 414         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 415                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 416                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 417                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 418                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 419                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 420                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 421                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 422                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 423                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 424         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 425 }
 426
 427 /**
 428  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 429  *
 430  * @adev: amdgpu_device pointer
 431  * @sw: enable SW clock gating
 432  *
 433  * Enable clock gating for VCN block
 434  */
 435 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 436 {
 437         uint32_t data = 0;
 438
 439         /* enable JPEG CGC */
 440         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 441         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 442                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 443         else
 444                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 445         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 446         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 447         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 448
 449         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 450         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 451         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 452
 453         /* enable UVD CGC */
 454         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 455         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 456                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 457         else
 458                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 459         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 460         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 461         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 462
 463         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 464         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 465                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 466                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 467                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 468                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 469                 | UVD_CGC_CTRL__SYS_MODE_MASK
 470                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 471                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 472                 | UVD_CGC_CTRL__REGS_MODE_MASK
 473                 | UVD_CGC_CTRL__RBC_MODE_MASK
 474                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 475                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 476                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 477                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 478                 | UVD_CGC_CTRL__MPC_MODE_MASK
 479                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 480                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 481                 | UVD_CGC_CTRL__WCB_MODE_MASK
 482                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 483                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 484         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 485
 486         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 487         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 488                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 489                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 490                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 491                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 492                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 493                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 494                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 495                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 496                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 497         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 498 }
 499
 500 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 501 {
 502         uint32_t data = 0;
 503         int ret;
 504
 505         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 506                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 507                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 508                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 509                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 510                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 511                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 512                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 513                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 514                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 515                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 516                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 517
 518                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 519                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
 520         } else {
 521                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 522                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 523                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 524                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 525                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 526                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 527                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 528                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 529                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 530                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 531                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 532                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 533                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
 534         }
 535
 536         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 537
 538         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 539         data &= ~0x103;
 540         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 541                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 542
 543         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 544 }
 545
 546 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 547 {
 548         uint32_t data = 0;
 549         int ret;
 550
 551         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 552                 /* Before power off, this indicator has to be turned on */
 553                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 554                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 555                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 556                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 557
 558
 559                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 560                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 561                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 562                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 563                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 564                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 565                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 566                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 567                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 568                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 569                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 570
 571                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 572
 573                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 574                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 575                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 576                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 577                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 578                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 579                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 580                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 581                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 582                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 583                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 584                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
 585         }
 586 }
 587
 588 /**
 589  * vcn_v1_0_start - start VCN block
 590  *
 591  * @adev: amdgpu_device pointer
 592  *
 593  * Setup and start the VCN block
 594  */
 595 static int vcn_v1_0_start(struct amdgpu_device *adev)
 596 {
 597         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 598         uint32_t rb_bufsz, tmp;
 599         uint32_t lmi_swap_cntl;
 600         int i, j, r;
 601
 602         /* disable byte swapping */
 603         lmi_swap_cntl = 0;
 604
 605         vcn_1_0_disable_static_power_gating(adev);
 606         /* disable clock gating */
 607         vcn_v1_0_disable_clock_gating(adev);
 608
 609         vcn_v1_0_mc_resume(adev);
 610
 611         /* disable interupt */
 612         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 613                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 614
 615         /* stall UMC and register bus before resetting VCPU */
 616         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 617                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 618                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 619         mdelay(1);
 620
 621         /* put LMI, VCPU, RBC etc... into reset */
 622         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 623                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 624                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 625                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 626                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 627                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 628                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 629                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 630                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 631         mdelay(5);
 632
 633         /* initialize VCN memory controller */
 634         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
 635                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 636                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 637                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 638                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 639                 UVD_LMI_CTRL__REQ_MODE_MASK |
 640                 0x00100000L);
 641
 642 #ifdef __BIG_ENDIAN
 643         /* swap (8 in 32) RB and IB */
 644         lmi_swap_cntl = 0xa;
 645 #endif
 646         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 647
 648         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 649         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
 650         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 651         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
 652         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
 653         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
 654
 655         /* take all subblocks out of reset, except VCPU */
 656         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 657                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 658         mdelay(5);
 659
 660         /* enable VCPU clock */
 661         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
 662                         UVD_VCPU_CNTL__CLK_EN_MASK);
 663
 664         /* enable UMC */
 665         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 666                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 667
 668         /* boot up the VCPU */
 669         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
 670         mdelay(10);
 671
 672         for (i = 0; i < 10; ++i) {
 673                 uint32_t status;
 674
 675                 for (j = 0; j < 100; ++j) {
 676                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 677                         if (status & 2)
 678                                 break;
 679                         mdelay(10);
 680                 }
 681                 r = 0;
 682                 if (status & 2)
 683                         break;
 684
 685                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 686                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 687                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 688                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 689                 mdelay(10);
 690                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 691                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 692                 mdelay(10);
 693                 r = -1;
 694         }
 695
 696         if (r) {
 697                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 698                 return r;
 699         }
 700         /* enable master interrupt */
 701         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 702                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 703                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 704
 705         /* clear the bit 4 of VCN_STATUS */
 706         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
 707                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 708
 709         /* force RBC into idle state */
 710         rb_bufsz = order_base_2(ring->ring_size);
 711         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 712         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 713         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 714         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 715         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 716         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 717         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 718
 719         /* set the write pointer delay */
 720         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 721
 722         /* set the wb address */
 723         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 724                         (upper_32_bits(ring->gpu_addr) >> 2));
 725
 726         /* programm the RB_BASE for ring buffer */
 727         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 728                         lower_32_bits(ring->gpu_addr));
 729         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 730                         upper_32_bits(ring->gpu_addr));
 731
 732         /* Initialize the ring buffer's read and write pointers */
 733         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 734
 735         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 736         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 737                         lower_32_bits(ring->wptr));
 738
 739         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 740                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 741
 742         ring = &adev->vcn.ring_enc[0];
 743         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 744         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 745         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 746         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 747         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 748
 749         ring = &adev->vcn.ring_enc[1];
 750         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 751         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 752         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 753         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 754         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 755
 756         ring = &adev->vcn.ring_jpeg;
 757         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 758         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 759         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
 760         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
 761         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
 762         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
 763         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 764
 765         /* initialize wptr */
 766         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
 767
 768         /* copy patch commands to the jpeg ring */
 769         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
 770                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
 771
 772         return 0;
 773 }
 774
 775 /**
 776  * vcn_v1_0_stop - stop VCN block
 777  *
 778  * @adev: amdgpu_device pointer
 779  *
 780  * stop the VCN block
 781  */
 782 static int vcn_v1_0_stop(struct amdgpu_device *adev)
 783 {
 784         /* force RBC into idle state */
 785         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
 786
 787         /* Stall UMC and register bus before resetting VCPU */
 788         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 789                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 790                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 791         mdelay(1);
 792
 793         /* put VCPU into reset */
 794         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 795                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 796         mdelay(5);
 797
 798         /* disable VCPU clock */
 799         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
 800
 801         /* Unstall UMC and register bus */
 802         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 803                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 804
 805         WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
 806
 807         vcn_v1_0_enable_clock_gating(adev);
 808         vcn_1_0_enable_static_power_gating(adev);
 809         return 0;
 810 }
 811
 812 static bool vcn_v1_0_is_idle(void *handle)
 813 {
 814         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 815
 816         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2);
 817 }
 818
 819 static int vcn_v1_0_wait_for_idle(void *handle)
 820 {
 821         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 822         int ret = 0;
 823
 824         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret);
 825
 826         return ret;
 827 }
 828
 829 static int vcn_v1_0_set_clockgating_state(void *handle,
 830                                           enum amd_clockgating_state state)
 831 {
 832         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 833         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 834
 835         if (enable) {
 836                 /* wait for STATUS to clear */
 837                 if (vcn_v1_0_is_idle(handle))
 838                         return -EBUSY;
 839                 vcn_v1_0_enable_clock_gating(adev);
 840         } else {
 841                 /* disable HW gating and enable Sw gating */
 842                 vcn_v1_0_disable_clock_gating(adev);
 843         }
 844         return 0;
 845 }
 846
 847 /**
 848  * vcn_v1_0_dec_ring_get_rptr - get read pointer
 849  *
 850  * @ring: amdgpu_ring pointer
 851  *
 852  * Returns the current hardware read pointer
 853  */
 854 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
 855 {
 856         struct amdgpu_device *adev = ring->adev;
 857
 858         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 859 }
 860
 861 /**
 862  * vcn_v1_0_dec_ring_get_wptr - get write pointer
 863  *
 864  * @ring: amdgpu_ring pointer
 865  *
 866  * Returns the current hardware write pointer
 867  */
 868 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
 869 {
 870         struct amdgpu_device *adev = ring->adev;
 871
 872         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
 873 }
 874
 875 /**
 876  * vcn_v1_0_dec_ring_set_wptr - set write pointer
 877  *
 878  * @ring: amdgpu_ring pointer
 879  *
 880  * Commits the write pointer to the hardware
 881  */
 882 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 883 {
 884         struct amdgpu_device *adev = ring->adev;
 885
 886         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 887 }
 888
 889 /**
 890  * vcn_v1_0_dec_ring_insert_start - insert a start command
 891  *
 892  * @ring: amdgpu_ring pointer
 893  *
 894  * Write a start command to the ring.
 895  */
 896 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
 897 {
 898         struct amdgpu_device *adev = ring->adev;
 899
 900         amdgpu_ring_write(ring,
 901                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
 902         amdgpu_ring_write(ring, 0);
 903         amdgpu_ring_write(ring,
 904                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
 905         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
 906 }
 907
 908 /**
 909  * vcn_v1_0_dec_ring_insert_end - insert a end command
 910  *
 911  * @ring: amdgpu_ring pointer
 912  *
 913  * Write a end command to the ring.
 914  */
 915 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
 916 {
 917         struct amdgpu_device *adev = ring->adev;
 918
 919         amdgpu_ring_write(ring,
 920                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
 921         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
 922 }
 923
 924 /**
 925  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
 926  *
 927  * @ring: amdgpu_ring pointer
 928  * @fence: fence to emit
 929  *
 930  * Write a fence and a trap command to the ring.
 931  */
 932 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 933                                      unsigned flags)
 934 {
 935         struct amdgpu_device *adev = ring->adev;
 936
 937         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 938
 939         amdgpu_ring_write(ring,
 940                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
 941         amdgpu_ring_write(ring, seq);
 942         amdgpu_ring_write(ring,
 943                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
 944         amdgpu_ring_write(ring, addr & 0xffffffff);
 945         amdgpu_ring_write(ring,
 946                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
 947         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 948         amdgpu_ring_write(ring,
 949                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
 950         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
 951
 952         amdgpu_ring_write(ring,
 953                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
 954         amdgpu_ring_write(ring, 0);
 955         amdgpu_ring_write(ring,
 956                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
 957         amdgpu_ring_write(ring, 0);
 958         amdgpu_ring_write(ring,
 959                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
 960         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
 961 }
 962
 963 /**
 964  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
 965  *
 966  * @ring: amdgpu_ring pointer
 967  * @ib: indirect buffer to execute
 968  *
 969  * Write ring commands to execute the indirect buffer
 970  */
 971 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
 972                                   struct amdgpu_ib *ib,
 973                                   unsigned vmid, bool ctx_switch)
 974 {
 975         struct amdgpu_device *adev = ring->adev;
 976
 977         amdgpu_ring_write(ring,
 978                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
 979         amdgpu_ring_write(ring, vmid);
 980
 981         amdgpu_ring_write(ring,
 982                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
 983         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 984         amdgpu_ring_write(ring,
 985                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
 986         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 987         amdgpu_ring_write(ring,
 988                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
 989         amdgpu_ring_write(ring, ib->length_dw);
 990 }
 991
 992 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
 993                                             uint32_t reg, uint32_t val,
 994                                             uint32_t mask)
 995 {
 996         struct amdgpu_device *adev = ring->adev;
 997
 998         amdgpu_ring_write(ring,
 999                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1000         amdgpu_ring_write(ring, reg << 2);
1001         amdgpu_ring_write(ring,
1002                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1003         amdgpu_ring_write(ring, val);
1004         amdgpu_ring_write(ring,
1005                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1006         amdgpu_ring_write(ring, mask);
1007         amdgpu_ring_write(ring,
1008                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1009         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1010 }
1011
1012 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1013                                             unsigned vmid, uint64_t pd_addr)
1014 {
1015         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1016         uint32_t data0, data1, mask;
1017
1018         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1019
1020         /* wait for register write */
1021         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1022         data1 = lower_32_bits(pd_addr);
1023         mask = 0xffffffff;
1024         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1025 }
1026
1027 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1028                                         uint32_t reg, uint32_t val)
1029 {
1030         struct amdgpu_device *adev = ring->adev;
1031
1032         amdgpu_ring_write(ring,
1033                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1034         amdgpu_ring_write(ring, reg << 2);
1035         amdgpu_ring_write(ring,
1036                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1037         amdgpu_ring_write(ring, val);
1038         amdgpu_ring_write(ring,
1039                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1040         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1041 }
1042
1043 /**
1044  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1045  *
1046  * @ring: amdgpu_ring pointer
1047  *
1048  * Returns the current hardware enc read pointer
1049  */
1050 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1051 {
1052         struct amdgpu_device *adev = ring->adev;
1053
1054         if (ring == &adev->vcn.ring_enc[0])
1055                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1056         else
1057                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1058 }
1059
1060  /**
1061  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1062  *
1063  * @ring: amdgpu_ring pointer
1064  *
1065  * Returns the current hardware enc write pointer
1066  */
1067 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1068 {
1069         struct amdgpu_device *adev = ring->adev;
1070
1071         if (ring == &adev->vcn.ring_enc[0])
1072                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1073         else
1074                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1075 }
1076
1077  /**
1078  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1079  *
1080  * @ring: amdgpu_ring pointer
1081  *
1082  * Commits the enc write pointer to the hardware
1083  */
1084 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1085 {
1086         struct amdgpu_device *adev = ring->adev;
1087
1088         if (ring == &adev->vcn.ring_enc[0])
1089                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1090                         lower_32_bits(ring->wptr));
1091         else
1092                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1093                         lower_32_bits(ring->wptr));
1094 }
1095
1096 /**
1097  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1098  *
1099  * @ring: amdgpu_ring pointer
1100  * @fence: fence to emit
1101  *
1102  * Write enc a fence and a trap command to the ring.
1103  */
1104 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1105                         u64 seq, unsigned flags)
1106 {
1107         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1108
1109         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1110         amdgpu_ring_write(ring, addr);
1111         amdgpu_ring_write(ring, upper_32_bits(addr));
1112         amdgpu_ring_write(ring, seq);
1113         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1114 }
1115
1116 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1117 {
1118         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1119 }
1120
1121 /**
1122  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1123  *
1124  * @ring: amdgpu_ring pointer
1125  * @ib: indirect buffer to execute
1126  *
1127  * Write enc ring commands to execute the indirect buffer
1128  */
1129 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1130                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1131 {
1132         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1133         amdgpu_ring_write(ring, vmid);
1134         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1135         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1136         amdgpu_ring_write(ring, ib->length_dw);
1137 }
1138
1139 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1140                                             uint32_t reg, uint32_t val,
1141                                             uint32_t mask)
1142 {
1143         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1144         amdgpu_ring_write(ring, reg << 2);
1145         amdgpu_ring_write(ring, mask);
1146         amdgpu_ring_write(ring, val);
1147 }
1148
1149 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1150                                             unsigned int vmid, uint64_t pd_addr)
1151 {
1152         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1153
1154         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1155
1156         /* wait for reg writes */
1157         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1158                                         lower_32_bits(pd_addr), 0xffffffff);
1159 }
1160
1161 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1162                                         uint32_t reg, uint32_t val)
1163 {
1164         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1165         amdgpu_ring_write(ring, reg << 2);
1166         amdgpu_ring_write(ring, val);
1167 }
1168
1169
1170 /**
1171  * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1172  *
1173  * @ring: amdgpu_ring pointer
1174  *
1175  * Returns the current hardware read pointer
1176  */
1177 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1178 {
1179         struct amdgpu_device *adev = ring->adev;
1180
1181         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1182 }
1183
1184 /**
1185  * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1186  *
1187  * @ring: amdgpu_ring pointer
1188  *
1189  * Returns the current hardware write pointer
1190  */
1191 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1192 {
1193         struct amdgpu_device *adev = ring->adev;
1194
1195         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1196 }
1197
1198 /**
1199  * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1200  *
1201  * @ring: amdgpu_ring pointer
1202  *
1203  * Commits the write pointer to the hardware
1204  */
1205 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1206 {
1207         struct amdgpu_device *adev = ring->adev;
1208
1209         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1210 }
1211
1212 /**
1213  * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1214  *
1215  * @ring: amdgpu_ring pointer
1216  *
1217  * Write a start command to the ring.
1218  */
1219 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1220 {
1221         struct amdgpu_device *adev = ring->adev;
1222
1223         amdgpu_ring_write(ring,
1224                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1225         amdgpu_ring_write(ring, 0x68e04);
1226
1227         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1228         amdgpu_ring_write(ring, 0x80010000);
1229 }
1230
1231 /**
1232  * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1233  *
1234  * @ring: amdgpu_ring pointer
1235  *
1236  * Write a end command to the ring.
1237  */
1238 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1239 {
1240         struct amdgpu_device *adev = ring->adev;
1241
1242         amdgpu_ring_write(ring,
1243                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1244         amdgpu_ring_write(ring, 0x68e04);
1245
1246         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1247         amdgpu_ring_write(ring, 0x00010000);
1248 }
1249
1250 /**
1251  * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1252  *
1253  * @ring: amdgpu_ring pointer
1254  * @fence: fence to emit
1255  *
1256  * Write a fence and a trap command to the ring.
1257  */
1258 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1259                                      unsigned flags)
1260 {
1261         struct amdgpu_device *adev = ring->adev;
1262
1263         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1264
1265         amdgpu_ring_write(ring,
1266                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1267         amdgpu_ring_write(ring, seq);
1268
1269         amdgpu_ring_write(ring,
1270                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1271         amdgpu_ring_write(ring, seq);
1272
1273         amdgpu_ring_write(ring,
1274                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1275         amdgpu_ring_write(ring, lower_32_bits(addr));
1276
1277         amdgpu_ring_write(ring,
1278                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1279         amdgpu_ring_write(ring, upper_32_bits(addr));
1280
1281         amdgpu_ring_write(ring,
1282                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1283         amdgpu_ring_write(ring, 0x8);
1284
1285         amdgpu_ring_write(ring,
1286                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1287         amdgpu_ring_write(ring, 0);
1288
1289         amdgpu_ring_write(ring,
1290                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1291         amdgpu_ring_write(ring, 0x01400200);
1292
1293         amdgpu_ring_write(ring,
1294                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1295         amdgpu_ring_write(ring, seq);
1296
1297         amdgpu_ring_write(ring,
1298                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1299         amdgpu_ring_write(ring, lower_32_bits(addr));
1300
1301         amdgpu_ring_write(ring,
1302                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1303         amdgpu_ring_write(ring, upper_32_bits(addr));
1304
1305         amdgpu_ring_write(ring,
1306                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1307         amdgpu_ring_write(ring, 0xffffffff);
1308
1309         amdgpu_ring_write(ring,
1310                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1311         amdgpu_ring_write(ring, 0x3fbc);
1312
1313         amdgpu_ring_write(ring,
1314                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1315         amdgpu_ring_write(ring, 0x1);
1316 }
1317
1318 /**
1319  * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1320  *
1321  * @ring: amdgpu_ring pointer
1322  * @ib: indirect buffer to execute
1323  *
1324  * Write ring commands to execute the indirect buffer.
1325  */
1326 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1327                                   struct amdgpu_ib *ib,
1328                                   unsigned vmid, bool ctx_switch)
1329 {
1330         struct amdgpu_device *adev = ring->adev;
1331
1332         amdgpu_ring_write(ring,
1333                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1334         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1335
1336         amdgpu_ring_write(ring,
1337                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1338         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1339
1340         amdgpu_ring_write(ring,
1341                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1342         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1343
1344         amdgpu_ring_write(ring,
1345                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1346         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1347
1348         amdgpu_ring_write(ring,
1349                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1350         amdgpu_ring_write(ring, ib->length_dw);
1351
1352         amdgpu_ring_write(ring,
1353                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1354         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1355
1356         amdgpu_ring_write(ring,
1357                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1358         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1359
1360         amdgpu_ring_write(ring,
1361                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1362         amdgpu_ring_write(ring, 0);
1363
1364         amdgpu_ring_write(ring,
1365                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1366         amdgpu_ring_write(ring, 0x01400200);
1367
1368         amdgpu_ring_write(ring,
1369                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1370         amdgpu_ring_write(ring, 0x2);
1371
1372         amdgpu_ring_write(ring,
1373                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1374         amdgpu_ring_write(ring, 0x2);
1375 }
1376
1377 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1378                                             uint32_t reg, uint32_t val,
1379                                             uint32_t mask)
1380 {
1381         struct amdgpu_device *adev = ring->adev;
1382         uint32_t reg_offset = (reg << 2);
1383
1384         amdgpu_ring_write(ring,
1385                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1386         amdgpu_ring_write(ring, 0x01400200);
1387
1388         amdgpu_ring_write(ring,
1389                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1390         amdgpu_ring_write(ring, val);
1391
1392         amdgpu_ring_write(ring,
1393                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1394         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1395                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1396                 amdgpu_ring_write(ring, 0);
1397                 amdgpu_ring_write(ring,
1398                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1399         } else {
1400                 amdgpu_ring_write(ring, reg_offset);
1401                 amdgpu_ring_write(ring,
1402                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1403         }
1404         amdgpu_ring_write(ring, mask);
1405 }
1406
1407 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1408                 unsigned vmid, uint64_t pd_addr)
1409 {
1410         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1411         uint32_t data0, data1, mask;
1412
1413         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1414
1415         /* wait for register write */
1416         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1417         data1 = lower_32_bits(pd_addr);
1418         mask = 0xffffffff;
1419         vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1420 }
1421
1422 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1423                                         uint32_t reg, uint32_t val)
1424 {
1425         struct amdgpu_device *adev = ring->adev;
1426         uint32_t reg_offset = (reg << 2);
1427
1428         amdgpu_ring_write(ring,
1429                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1430         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1431                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1432                 amdgpu_ring_write(ring, 0);
1433                 amdgpu_ring_write(ring,
1434                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1435         } else {
1436                 amdgpu_ring_write(ring, reg_offset);
1437                 amdgpu_ring_write(ring,
1438                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1439         }
1440         amdgpu_ring_write(ring, val);
1441 }
1442
1443 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1444 {
1445         int i;
1446
1447         WARN_ON(ring->wptr % 2 || count % 2);
1448
1449         for (i = 0; i < count / 2; i++) {
1450                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1451                 amdgpu_ring_write(ring, 0);
1452         }
1453 }
1454
1455 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
1456 {
1457         struct amdgpu_device *adev = ring->adev;
1458         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1459         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1460                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1461                 ring->ring[(*ptr)++] = 0;
1462                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1463         } else {
1464                 ring->ring[(*ptr)++] = reg_offset;
1465                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1466         }
1467         ring->ring[(*ptr)++] = val;
1468 }
1469
1470 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1471 {
1472         struct amdgpu_device *adev = ring->adev;
1473
1474         uint32_t reg, reg_offset, val, mask, i;
1475
1476         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1477         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1478         reg_offset = (reg << 2);
1479         val = lower_32_bits(ring->gpu_addr);
1480         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1481
1482         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1483         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1484         reg_offset = (reg << 2);
1485         val = upper_32_bits(ring->gpu_addr);
1486         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1487
1488         // 3rd to 5th: issue MEM_READ commands
1489         for (i = 0; i <= 2; i++) {
1490                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1491                 ring->ring[ptr++] = 0;
1492         }
1493
1494         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1495         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1496         reg_offset = (reg << 2);
1497         val = 0x13;
1498         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1499
1500         // 7th: program mmUVD_JRBC_RB_REF_DATA
1501         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1502         reg_offset = (reg << 2);
1503         val = 0x1;
1504         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1505
1506         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1507         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1508         reg_offset = (reg << 2);
1509         val = 0x1;
1510         mask = 0x1;
1511
1512         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1513         ring->ring[ptr++] = 0x01400200;
1514         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1515         ring->ring[ptr++] = val;
1516         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1517         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1518                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1519                 ring->ring[ptr++] = 0;
1520                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1521         } else {
1522                 ring->ring[ptr++] = reg_offset;
1523                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1524         }
1525         ring->ring[ptr++] = mask;
1526
1527         //9th to 21st: insert no-op
1528         for (i = 0; i <= 12; i++) {
1529                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1530                 ring->ring[ptr++] = 0;
1531         }
1532
1533         //22nd: reset mmUVD_JRBC_RB_RPTR
1534         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1535         reg_offset = (reg << 2);
1536         val = 0;
1537         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1538
1539         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1540         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1541         reg_offset = (reg << 2);
1542         val = 0x12;
1543         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1544 }
1545
1546 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1547                                         struct amdgpu_irq_src *source,
1548                                         unsigned type,
1549                                         enum amdgpu_interrupt_state state)
1550 {
1551         return 0;
1552 }
1553
1554 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1555                                       struct amdgpu_irq_src *source,
1556                                       struct amdgpu_iv_entry *entry)
1557 {
1558         DRM_DEBUG("IH: VCN TRAP\n");
1559
1560         switch (entry->src_id) {
1561         case 124:
1562                 amdgpu_fence_process(&adev->vcn.ring_dec);
1563                 break;
1564         case 119:
1565                 amdgpu_fence_process(&adev->vcn.ring_enc[0]);
1566                 break;
1567         case 120:
1568                 amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1569                 break;
1570         case 126:
1571                 amdgpu_fence_process(&adev->vcn.ring_jpeg);
1572                 break;
1573         default:
1574                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1575                           entry->src_id, entry->src_data[0]);
1576                 break;
1577         }
1578
1579         return 0;
1580 }
1581
1582 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1583 {
1584         struct amdgpu_device *adev = ring->adev;
1585         int i;
1586
1587         WARN_ON(ring->wptr % 2 || count % 2);
1588
1589         for (i = 0; i < count / 2; i++) {
1590                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1591                 amdgpu_ring_write(ring, 0);
1592         }
1593 }
1594
1595 static int vcn_v1_0_set_powergating_state(void *handle,
1596                                           enum amd_powergating_state state)
1597 {
1598         /* This doesn't actually powergate the VCN block.
1599          * That's done in the dpm code via the SMC.  This
1600          * just re-inits the block as necessary.  The actual
1601          * gating still happens in the dpm code.  We should
1602          * revisit this when there is a cleaner line between
1603          * the smc and the hw blocks
1604          */
1605         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1606
1607         if (state == AMD_PG_STATE_GATE)
1608                 return vcn_v1_0_stop(adev);
1609         else
1610                 return vcn_v1_0_start(adev);
1611 }
1612
1613 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1614         .name = "vcn_v1_0",
1615         .early_init = vcn_v1_0_early_init,
1616         .late_init = NULL,
1617         .sw_init = vcn_v1_0_sw_init,
1618         .sw_fini = vcn_v1_0_sw_fini,
1619         .hw_init = vcn_v1_0_hw_init,
1620         .hw_fini = vcn_v1_0_hw_fini,
1621         .suspend = vcn_v1_0_suspend,
1622         .resume = vcn_v1_0_resume,
1623         .is_idle = vcn_v1_0_is_idle,
1624         .wait_for_idle = vcn_v1_0_wait_for_idle,
1625         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1626         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1627         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1628         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1629         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1630         .set_powergating_state = vcn_v1_0_set_powergating_state,
1631 };
1632
1633 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1634         .type = AMDGPU_RING_TYPE_VCN_DEC,
1635         .align_mask = 0xf,
1636         .support_64bit_ptrs = false,
1637         .vmhub = AMDGPU_MMHUB,
1638         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1639         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1640         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1641         .emit_frame_size =
1642                 6 + 6 + /* hdp invalidate / flush */
1643                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1644                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1645                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1646                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1647                 6,
1648         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1649         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1650         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1651         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1652         .test_ring = amdgpu_vcn_dec_ring_test_ring,
1653         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1654         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1655         .insert_start = vcn_v1_0_dec_ring_insert_start,
1656         .insert_end = vcn_v1_0_dec_ring_insert_end,
1657         .pad_ib = amdgpu_ring_generic_pad_ib,
1658         .begin_use = amdgpu_vcn_ring_begin_use,
1659         .end_use = amdgpu_vcn_ring_end_use,
1660         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1661         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1662         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1663 };
1664
1665 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1666         .type = AMDGPU_RING_TYPE_VCN_ENC,
1667         .align_mask = 0x3f,
1668         .nop = VCN_ENC_CMD_NO_OP,
1669         .support_64bit_ptrs = false,
1670         .vmhub = AMDGPU_MMHUB,
1671         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1672         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1673         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1674         .emit_frame_size =
1675                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1676                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1677                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1678                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1679                 1, /* vcn_v1_0_enc_ring_insert_end */
1680         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1681         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1682         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1683         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1684         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1685         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1686         .insert_nop = amdgpu_ring_insert_nop,
1687         .insert_end = vcn_v1_0_enc_ring_insert_end,
1688         .pad_ib = amdgpu_ring_generic_pad_ib,
1689         .begin_use = amdgpu_vcn_ring_begin_use,
1690         .end_use = amdgpu_vcn_ring_end_use,
1691         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1692         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1693         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1694 };
1695
1696 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
1697         .type = AMDGPU_RING_TYPE_VCN_JPEG,
1698         .align_mask = 0xf,
1699         .nop = PACKET0(0x81ff, 0),
1700         .support_64bit_ptrs = false,
1701         .vmhub = AMDGPU_MMHUB,
1702         .extra_dw = 64,
1703         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
1704         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
1705         .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
1706         .emit_frame_size =
1707                 6 + 6 + /* hdp invalidate / flush */
1708                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1709                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1710                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1711                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1712                 6,
1713         .emit_ib_size = 22, /* vcn_v1_0_dec_ring_emit_ib */
1714         .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
1715         .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
1716         .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
1717         .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
1718         .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
1719         .insert_nop = vcn_v1_0_jpeg_ring_nop,
1720         .insert_start = vcn_v1_0_jpeg_ring_insert_start,
1721         .insert_end = vcn_v1_0_jpeg_ring_insert_end,
1722         .pad_ib = amdgpu_ring_generic_pad_ib,
1723         .begin_use = amdgpu_vcn_ring_begin_use,
1724         .end_use = amdgpu_vcn_ring_end_use,
1725         .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
1726         .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
1727 };
1728
1729 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1730 {
1731         adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1732         DRM_INFO("VCN decode is enabled in VM mode\n");
1733 }
1734
1735 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1736 {
1737         int i;
1738
1739         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1740                 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1741
1742         DRM_INFO("VCN encode is enabled in VM mode\n");
1743 }
1744
1745 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
1746 {
1747         adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
1748         DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
1749 }
1750
1751 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1752         .set = vcn_v1_0_set_interrupt_state,
1753         .process = vcn_v1_0_process_interrupt,
1754 };
1755
1756 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1757 {
1758         adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1;
1759         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
1760 }
1761
1762 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1763 {
1764                 .type = AMD_IP_BLOCK_TYPE_VCN,
1765                 .major = 1,
1766                 .minor = 0,
1767                 .rev = 0,
1768                 .funcs = &vcn_v1_0_ip_funcs,
1769 };