drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39 #include "ivsrcid/ivsrcid_vislands30.h"
  40
  41 /* Polaris10/11/12 firmware version */
  42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
  43
  44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  46
  47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  48 static int uvd_v6_0_start(struct amdgpu_device *adev);
  49 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  51 static int uvd_v6_0_set_clockgating_state(void *handle,
  52                                           enum amd_clockgating_state state);
  53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  54                                  bool enable);
  55
  56 /**
  57 * uvd_v6_0_enc_support - get encode support status
  58 *
  59 * @adev: amdgpu_device pointer
  60 *
  61 * Returns the current hardware encode support status
  62 */
  63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  64 {
  65         return ((adev->asic_type >= CHIP_POLARIS10) &&
  66                         (adev->asic_type <= CHIP_VEGAM) &&
  67                         (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
  68 }
  69
  70 /**
  71  * uvd_v6_0_ring_get_rptr - get read pointer
  72  *
  73  * @ring: amdgpu_ring pointer
  74  *
  75  * Returns the current hardware read pointer
  76  */
  77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  78 {
  79         struct amdgpu_device *adev = ring->adev;
  80
  81         return RREG32(mmUVD_RBC_RB_RPTR);
  82 }
  83
  84 /**
  85  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  86  *
  87  * @ring: amdgpu_ring pointer
  88  *
  89  * Returns the current hardware enc read pointer
  90  */
  91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  92 {
  93         struct amdgpu_device *adev = ring->adev;
  94
  95         if (ring == &adev->uvd.inst->ring_enc[0])
  96                 return RREG32(mmUVD_RB_RPTR);
  97         else
  98                 return RREG32(mmUVD_RB_RPTR2);
  99 }
 100 /**
 101  * uvd_v6_0_ring_get_wptr - get write pointer
 102  *
 103  * @ring: amdgpu_ring pointer
 104  *
 105  * Returns the current hardware write pointer
 106  */
 107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 108 {
 109         struct amdgpu_device *adev = ring->adev;
 110
 111         return RREG32(mmUVD_RBC_RB_WPTR);
 112 }
 113
 114 /**
 115  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 116  *
 117  * @ring: amdgpu_ring pointer
 118  *
 119  * Returns the current hardware enc write pointer
 120  */
 121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 122 {
 123         struct amdgpu_device *adev = ring->adev;
 124
 125         if (ring == &adev->uvd.inst->ring_enc[0])
 126                 return RREG32(mmUVD_RB_WPTR);
 127         else
 128                 return RREG32(mmUVD_RB_WPTR2);
 129 }
 130
 131 /**
 132  * uvd_v6_0_ring_set_wptr - set write pointer
 133  *
 134  * @ring: amdgpu_ring pointer
 135  *
 136  * Commits the write pointer to the hardware
 137  */
 138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 139 {
 140         struct amdgpu_device *adev = ring->adev;
 141
 142         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 143 }
 144
 145 /**
 146  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 147  *
 148  * @ring: amdgpu_ring pointer
 149  *
 150  * Commits the enc write pointer to the hardware
 151  */
 152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 153 {
 154         struct amdgpu_device *adev = ring->adev;
 155
 156         if (ring == &adev->uvd.inst->ring_enc[0])
 157                 WREG32(mmUVD_RB_WPTR,
 158                         lower_32_bits(ring->wptr));
 159         else
 160                 WREG32(mmUVD_RB_WPTR2,
 161                         lower_32_bits(ring->wptr));
 162 }
 163
 164 /**
 165  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
 166  *
 167  * @ring: the engine to test on
 168  *
 169  */
 170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 171 {
 172         struct amdgpu_device *adev = ring->adev;
 173         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 174         unsigned i;
 175         int r;
 176
 177         r = amdgpu_ring_alloc(ring, 16);
 178         if (r) {
 179                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 180                           ring->idx, r);
 181                 return r;
 182         }
 183         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 184         amdgpu_ring_commit(ring);
 185
 186         for (i = 0; i < adev->usec_timeout; i++) {
 187                 if (amdgpu_ring_get_rptr(ring) != rptr)
 188                         break;
 189                 DRM_UDELAY(1);
 190         }
 191
 192         if (i < adev->usec_timeout) {
 193                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 194                          ring->idx, i);
 195         } else {
 196                 DRM_ERROR("amdgpu: ring %d test failed\n",
 197                           ring->idx);
 198                 r = -ETIMEDOUT;
 199         }
 200
 201         return r;
 202 }
 203
 204 /**
 205  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
 206  *
 207  * @adev: amdgpu_device pointer
 208  * @ring: ring we should submit the msg to
 209  * @handle: session handle to use
 210  * @fence: optional fence to return
 211  *
 212  * Open up a stream for HW test
 213  */
 214 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 215                                        struct dma_fence **fence)
 216 {
 217         const unsigned ib_size_dw = 16;
 218         struct amdgpu_job *job;
 219         struct amdgpu_ib *ib;
 220         struct dma_fence *f = NULL;
 221         uint64_t dummy;
 222         int i, r;
 223
 224         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 225         if (r)
 226                 return r;
 227
 228         ib = &job->ibs[0];
 229         dummy = ib->gpu_addr + 1024;
 230
 231         ib->length_dw = 0;
 232         ib->ptr[ib->length_dw++] = 0x00000018;
 233         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 234         ib->ptr[ib->length_dw++] = handle;
 235         ib->ptr[ib->length_dw++] = 0x00010000;
 236         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 237         ib->ptr[ib->length_dw++] = dummy;
 238
 239         ib->ptr[ib->length_dw++] = 0x00000014;
 240         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 241         ib->ptr[ib->length_dw++] = 0x0000001c;
 242         ib->ptr[ib->length_dw++] = 0x00000001;
 243         ib->ptr[ib->length_dw++] = 0x00000000;
 244
 245         ib->ptr[ib->length_dw++] = 0x00000008;
 246         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 247
 248         for (i = ib->length_dw; i < ib_size_dw; ++i)
 249                 ib->ptr[i] = 0x0;
 250
 251         r = amdgpu_job_submit_direct(job, ring, &f);
 252         if (r)
 253                 goto err;
 254
 255         if (fence)
 256                 *fence = dma_fence_get(f);
 257         dma_fence_put(f);
 258         return 0;
 259
 260 err:
 261         amdgpu_job_free(job);
 262         return r;
 263 }
 264
 265 /**
 266  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 267  *
 268  * @adev: amdgpu_device pointer
 269  * @ring: ring we should submit the msg to
 270  * @handle: session handle to use
 271  * @fence: optional fence to return
 272  *
 273  * Close up a stream for HW test or if userspace failed to do so
 274  */
 275 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
 276                                         uint32_t handle,
 277                                         bool direct, struct dma_fence **fence)
 278 {
 279         const unsigned ib_size_dw = 16;
 280         struct amdgpu_job *job;
 281         struct amdgpu_ib *ib;
 282         struct dma_fence *f = NULL;
 283         uint64_t dummy;
 284         int i, r;
 285
 286         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 287         if (r)
 288                 return r;
 289
 290         ib = &job->ibs[0];
 291         dummy = ib->gpu_addr + 1024;
 292
 293         ib->length_dw = 0;
 294         ib->ptr[ib->length_dw++] = 0x00000018;
 295         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 296         ib->ptr[ib->length_dw++] = handle;
 297         ib->ptr[ib->length_dw++] = 0x00010000;
 298         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 299         ib->ptr[ib->length_dw++] = dummy;
 300
 301         ib->ptr[ib->length_dw++] = 0x00000014;
 302         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 303         ib->ptr[ib->length_dw++] = 0x0000001c;
 304         ib->ptr[ib->length_dw++] = 0x00000001;
 305         ib->ptr[ib->length_dw++] = 0x00000000;
 306
 307         ib->ptr[ib->length_dw++] = 0x00000008;
 308         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 309
 310         for (i = ib->length_dw; i < ib_size_dw; ++i)
 311                 ib->ptr[i] = 0x0;
 312
 313         if (direct)
 314                 r = amdgpu_job_submit_direct(job, ring, &f);
 315         else
 316                 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
 317                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 318         if (r)
 319                 goto err;
 320
 321         if (fence)
 322                 *fence = dma_fence_get(f);
 323         dma_fence_put(f);
 324         return 0;
 325
 326 err:
 327         amdgpu_job_free(job);
 328         return r;
 329 }
 330
 331 /**
 332  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
 333  *
 334  * @ring: the engine to test on
 335  *
 336  */
 337 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 338 {
 339         struct dma_fence *fence = NULL;
 340         long r;
 341
 342         r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
 343         if (r) {
 344                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 345                 goto error;
 346         }
 347
 348         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
 349         if (r) {
 350                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 351                 goto error;
 352         }
 353
 354         r = dma_fence_wait_timeout(fence, false, timeout);
 355         if (r == 0) {
 356                 DRM_ERROR("amdgpu: IB test timed out.\n");
 357                 r = -ETIMEDOUT;
 358         } else if (r < 0) {
 359                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 360         } else {
 361                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 362                 r = 0;
 363         }
 364 error:
 365         dma_fence_put(fence);
 366         return r;
 367 }
 368 static int uvd_v6_0_early_init(void *handle)
 369 {
 370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 371         adev->uvd.num_uvd_inst = 1;
 372
 373         if (!(adev->flags & AMD_IS_APU) &&
 374             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
 375                 return -ENOENT;
 376
 377         uvd_v6_0_set_ring_funcs(adev);
 378
 379         if (uvd_v6_0_enc_support(adev)) {
 380                 adev->uvd.num_enc_rings = 2;
 381                 uvd_v6_0_set_enc_ring_funcs(adev);
 382         }
 383
 384         uvd_v6_0_set_irq_funcs(adev);
 385
 386         return 0;
 387 }
 388
 389 static int uvd_v6_0_sw_init(void *handle)
 390 {
 391         struct amdgpu_ring *ring;
 392         int i, r;
 393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 394
 395         /* UVD TRAP */
 396         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 397         if (r)
 398                 return r;
 399
 400         /* UVD ENC TRAP */
 401         if (uvd_v6_0_enc_support(adev)) {
 402                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 403                         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
 404                         if (r)
 405                                 return r;
 406                 }
 407         }
 408
 409         r = amdgpu_uvd_sw_init(adev);
 410         if (r)
 411                 return r;
 412
 413         if (!uvd_v6_0_enc_support(adev)) {
 414                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 415                         adev->uvd.inst->ring_enc[i].funcs = NULL;
 416
 417                 adev->uvd.inst->irq.num_types = 1;
 418                 adev->uvd.num_enc_rings = 0;
 419
 420                 DRM_INFO("UVD ENC is disabled\n");
 421         }
 422
 423         r = amdgpu_uvd_resume(adev);
 424         if (r)
 425                 return r;
 426
 427         ring = &adev->uvd.inst->ring;
 428         sprintf(ring->name, "uvd");
 429         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 430         if (r)
 431                 return r;
 432
 433         if (uvd_v6_0_enc_support(adev)) {
 434                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 435                         ring = &adev->uvd.inst->ring_enc[i];
 436                         sprintf(ring->name, "uvd_enc%d", i);
 437                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 438                         if (r)
 439                                 return r;
 440                 }
 441         }
 442
 443         return r;
 444 }
 445
 446 static int uvd_v6_0_sw_fini(void *handle)
 447 {
 448         int i, r;
 449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 450
 451         r = amdgpu_uvd_suspend(adev);
 452         if (r)
 453                 return r;
 454
 455         if (uvd_v6_0_enc_support(adev)) {
 456                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 457                         amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
 458         }
 459
 460         return amdgpu_uvd_sw_fini(adev);
 461 }
 462
 463 /**
 464  * uvd_v6_0_hw_init - start and test UVD block
 465  *
 466  * @adev: amdgpu_device pointer
 467  *
 468  * Initialize the hardware, boot up the VCPU and do some testing
 469  */
 470 static int uvd_v6_0_hw_init(void *handle)
 471 {
 472         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 473         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 474         uint32_t tmp;
 475         int i, r;
 476
 477         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 478         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 479         uvd_v6_0_enable_mgcg(adev, true);
 480
 481         ring->ready = true;
 482         r = amdgpu_ring_test_ring(ring);
 483         if (r) {
 484                 ring->ready = false;
 485                 goto done;
 486         }
 487
 488         r = amdgpu_ring_alloc(ring, 10);
 489         if (r) {
 490                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 491                 goto done;
 492         }
 493
 494         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 495         amdgpu_ring_write(ring, tmp);
 496         amdgpu_ring_write(ring, 0xFFFFF);
 497
 498         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 499         amdgpu_ring_write(ring, tmp);
 500         amdgpu_ring_write(ring, 0xFFFFF);
 501
 502         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 503         amdgpu_ring_write(ring, tmp);
 504         amdgpu_ring_write(ring, 0xFFFFF);
 505
 506         /* Clear timeout status bits */
 507         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 508         amdgpu_ring_write(ring, 0x8);
 509
 510         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 511         amdgpu_ring_write(ring, 3);
 512
 513         amdgpu_ring_commit(ring);
 514
 515         if (uvd_v6_0_enc_support(adev)) {
 516                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 517                         ring = &adev->uvd.inst->ring_enc[i];
 518                         ring->ready = true;
 519                         r = amdgpu_ring_test_ring(ring);
 520                         if (r) {
 521                                 ring->ready = false;
 522                                 goto done;
 523                         }
 524                 }
 525         }
 526
 527 done:
 528         if (!r) {
 529                 if (uvd_v6_0_enc_support(adev))
 530                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 531                 else
 532                         DRM_INFO("UVD initialized successfully.\n");
 533         }
 534
 535         return r;
 536 }
 537
 538 /**
 539  * uvd_v6_0_hw_fini - stop the hardware block
 540  *
 541  * @adev: amdgpu_device pointer
 542  *
 543  * Stop the UVD block, mark ring as not ready any more
 544  */
 545 static int uvd_v6_0_hw_fini(void *handle)
 546 {
 547         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 548         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 549
 550         if (RREG32(mmUVD_STATUS) != 0)
 551                 uvd_v6_0_stop(adev);
 552
 553         ring->ready = false;
 554
 555         return 0;
 556 }
 557
 558 static int uvd_v6_0_suspend(void *handle)
 559 {
 560         int r;
 561         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 562
 563         r = uvd_v6_0_hw_fini(adev);
 564         if (r)
 565                 return r;
 566
 567         return amdgpu_uvd_suspend(adev);
 568 }
 569
 570 static int uvd_v6_0_resume(void *handle)
 571 {
 572         int r;
 573         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 574
 575         r = amdgpu_uvd_resume(adev);
 576         if (r)
 577                 return r;
 578
 579         return uvd_v6_0_hw_init(adev);
 580 }
 581
 582 /**
 583  * uvd_v6_0_mc_resume - memory controller programming
 584  *
 585  * @adev: amdgpu_device pointer
 586  *
 587  * Let the UVD memory controller know it's offsets
 588  */
 589 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 590 {
 591         uint64_t offset;
 592         uint32_t size;
 593
 594         /* programm memory controller bits 0-27 */
 595         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 596                         lower_32_bits(adev->uvd.inst->gpu_addr));
 597         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 598                         upper_32_bits(adev->uvd.inst->gpu_addr));
 599
 600         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 601         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 602         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 603         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 604
 605         offset += size;
 606         size = AMDGPU_UVD_HEAP_SIZE;
 607         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 608         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 609
 610         offset += size;
 611         size = AMDGPU_UVD_STACK_SIZE +
 612                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 613         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 614         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 615
 616         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 617         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 618         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 619
 620         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 621 }
 622
 623 #if 0
 624 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 625                 bool enable)
 626 {
 627         u32 data, data1;
 628
 629         data = RREG32(mmUVD_CGC_GATE);
 630         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 631         if (enable) {
 632                 data |= UVD_CGC_GATE__SYS_MASK |
 633                                 UVD_CGC_GATE__UDEC_MASK |
 634                                 UVD_CGC_GATE__MPEG2_MASK |
 635                                 UVD_CGC_GATE__RBC_MASK |
 636                                 UVD_CGC_GATE__LMI_MC_MASK |
 637                                 UVD_CGC_GATE__IDCT_MASK |
 638                                 UVD_CGC_GATE__MPRD_MASK |
 639                                 UVD_CGC_GATE__MPC_MASK |
 640                                 UVD_CGC_GATE__LBSI_MASK |
 641                                 UVD_CGC_GATE__LRBBM_MASK |
 642                                 UVD_CGC_GATE__UDEC_RE_MASK |
 643                                 UVD_CGC_GATE__UDEC_CM_MASK |
 644                                 UVD_CGC_GATE__UDEC_IT_MASK |
 645                                 UVD_CGC_GATE__UDEC_DB_MASK |
 646                                 UVD_CGC_GATE__UDEC_MP_MASK |
 647                                 UVD_CGC_GATE__WCB_MASK |
 648                                 UVD_CGC_GATE__VCPU_MASK |
 649                                 UVD_CGC_GATE__SCPU_MASK;
 650                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 651                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 652                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 653                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 654                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 655                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 656                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 657                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 658                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 659                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 660                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 661                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 662                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 663         } else {
 664                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 665                                 UVD_CGC_GATE__UDEC_MASK |
 666                                 UVD_CGC_GATE__MPEG2_MASK |
 667                                 UVD_CGC_GATE__RBC_MASK |
 668                                 UVD_CGC_GATE__LMI_MC_MASK |
 669                                 UVD_CGC_GATE__LMI_UMC_MASK |
 670                                 UVD_CGC_GATE__IDCT_MASK |
 671                                 UVD_CGC_GATE__MPRD_MASK |
 672                                 UVD_CGC_GATE__MPC_MASK |
 673                                 UVD_CGC_GATE__LBSI_MASK |
 674                                 UVD_CGC_GATE__LRBBM_MASK |
 675                                 UVD_CGC_GATE__UDEC_RE_MASK |
 676                                 UVD_CGC_GATE__UDEC_CM_MASK |
 677                                 UVD_CGC_GATE__UDEC_IT_MASK |
 678                                 UVD_CGC_GATE__UDEC_DB_MASK |
 679                                 UVD_CGC_GATE__UDEC_MP_MASK |
 680                                 UVD_CGC_GATE__WCB_MASK |
 681                                 UVD_CGC_GATE__VCPU_MASK |
 682                                 UVD_CGC_GATE__SCPU_MASK);
 683                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 684                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 685                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 686                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 687                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 688                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 689                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 690                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 691                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 692                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 693                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 694                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 695                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 696         }
 697         WREG32(mmUVD_CGC_GATE, data);
 698         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 699 }
 700 #endif
 701
 702 /**
 703  * uvd_v6_0_start - start UVD block
 704  *
 705  * @adev: amdgpu_device pointer
 706  *
 707  * Setup and start the UVD block
 708  */
 709 static int uvd_v6_0_start(struct amdgpu_device *adev)
 710 {
 711         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 712         uint32_t rb_bufsz, tmp;
 713         uint32_t lmi_swap_cntl;
 714         uint32_t mp_swap_cntl;
 715         int i, j, r;
 716
 717         /* disable DPG */
 718         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 719
 720         /* disable byte swapping */
 721         lmi_swap_cntl = 0;
 722         mp_swap_cntl = 0;
 723
 724         uvd_v6_0_mc_resume(adev);
 725
 726         /* disable interupt */
 727         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 728
 729         /* stall UMC and register bus before resetting VCPU */
 730         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 731         mdelay(1);
 732
 733         /* put LMI, VCPU, RBC etc... into reset */
 734         WREG32(mmUVD_SOFT_RESET,
 735                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 736                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 737                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 738                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 739                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 740                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 741                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 742                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 743         mdelay(5);
 744
 745         /* take UVD block out of reset */
 746         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 747         mdelay(5);
 748
 749         /* initialize UVD memory controller */
 750         WREG32(mmUVD_LMI_CTRL,
 751                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 752                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 753                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 754                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 755                 UVD_LMI_CTRL__REQ_MODE_MASK |
 756                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 757
 758 #ifdef __BIG_ENDIAN
 759         /* swap (8 in 32) RB and IB */
 760         lmi_swap_cntl = 0xa;
 761         mp_swap_cntl = 0;
 762 #endif
 763         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 764         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 765
 766         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 767         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 768         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 769         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 770         WREG32(mmUVD_MPC_SET_ALU, 0);
 771         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 772
 773         /* take all subblocks out of reset, except VCPU */
 774         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 775         mdelay(5);
 776
 777         /* enable VCPU clock */
 778         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 779
 780         /* enable UMC */
 781         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 782
 783         /* boot up the VCPU */
 784         WREG32(mmUVD_SOFT_RESET, 0);
 785         mdelay(10);
 786
 787         for (i = 0; i < 10; ++i) {
 788                 uint32_t status;
 789
 790                 for (j = 0; j < 100; ++j) {
 791                         status = RREG32(mmUVD_STATUS);
 792                         if (status & 2)
 793                                 break;
 794                         mdelay(10);
 795                 }
 796                 r = 0;
 797                 if (status & 2)
 798                         break;
 799
 800                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 801                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 802                 mdelay(10);
 803                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 804                 mdelay(10);
 805                 r = -1;
 806         }
 807
 808         if (r) {
 809                 DRM_ERROR("UVD not responding, giving up!!!\n");
 810                 return r;
 811         }
 812         /* enable master interrupt */
 813         WREG32_P(mmUVD_MASTINT_EN,
 814                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 815                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 816
 817         /* clear the bit 4 of UVD_STATUS */
 818         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 819
 820         /* force RBC into idle state */
 821         rb_bufsz = order_base_2(ring->ring_size);
 822         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 823         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 824         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 825         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 826         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 827         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 828         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 829
 830         /* set the write pointer delay */
 831         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 832
 833         /* set the wb address */
 834         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 835
 836         /* programm the RB_BASE for ring buffer */
 837         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 838                         lower_32_bits(ring->gpu_addr));
 839         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 840                         upper_32_bits(ring->gpu_addr));
 841
 842         /* Initialize the ring buffer's read and write pointers */
 843         WREG32(mmUVD_RBC_RB_RPTR, 0);
 844
 845         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 846         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 847
 848         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 849
 850         if (uvd_v6_0_enc_support(adev)) {
 851                 ring = &adev->uvd.inst->ring_enc[0];
 852                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 853                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 854                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 855                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 856                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 857
 858                 ring = &adev->uvd.inst->ring_enc[1];
 859                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 860                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 861                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 862                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 863                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 864         }
 865
 866         return 0;
 867 }
 868
 869 /**
 870  * uvd_v6_0_stop - stop UVD block
 871  *
 872  * @adev: amdgpu_device pointer
 873  *
 874  * stop the UVD block
 875  */
 876 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 877 {
 878         /* force RBC into idle state */
 879         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 880
 881         /* Stall UMC and register bus before resetting VCPU */
 882         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 883         mdelay(1);
 884
 885         /* put VCPU into reset */
 886         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 887         mdelay(5);
 888
 889         /* disable VCPU clock */
 890         WREG32(mmUVD_VCPU_CNTL, 0x0);
 891
 892         /* Unstall UMC and register bus */
 893         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 894
 895         WREG32(mmUVD_STATUS, 0);
 896 }
 897
 898 /**
 899  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 900  *
 901  * @ring: amdgpu_ring pointer
 902  * @fence: fence to emit
 903  *
 904  * Write a fence and a trap command to the ring.
 905  */
 906 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 907                                      unsigned flags)
 908 {
 909         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 910
 911         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 912         amdgpu_ring_write(ring, seq);
 913         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 914         amdgpu_ring_write(ring, addr & 0xffffffff);
 915         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 916         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 917         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 918         amdgpu_ring_write(ring, 0);
 919
 920         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 921         amdgpu_ring_write(ring, 0);
 922         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 923         amdgpu_ring_write(ring, 0);
 924         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 925         amdgpu_ring_write(ring, 2);
 926 }
 927
 928 /**
 929  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 930  *
 931  * @ring: amdgpu_ring pointer
 932  * @fence: fence to emit
 933  *
 934  * Write enc a fence and a trap command to the ring.
 935  */
 936 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 937                         u64 seq, unsigned flags)
 938 {
 939         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 940
 941         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 942         amdgpu_ring_write(ring, addr);
 943         amdgpu_ring_write(ring, upper_32_bits(addr));
 944         amdgpu_ring_write(ring, seq);
 945         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 946 }
 947
 948 /**
 949  * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
 950  *
 951  * @ring: amdgpu_ring pointer
 952  */
 953 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 954 {
 955         /* The firmware doesn't seem to like touching registers at this point. */
 956 }
 957
 958 /**
 959  * uvd_v6_0_ring_test_ring - register write test
 960  *
 961  * @ring: amdgpu_ring pointer
 962  *
 963  * Test if we can successfully write to the context register
 964  */
 965 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 966 {
 967         struct amdgpu_device *adev = ring->adev;
 968         uint32_t tmp = 0;
 969         unsigned i;
 970         int r;
 971
 972         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 973         r = amdgpu_ring_alloc(ring, 3);
 974         if (r) {
 975                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 976                           ring->idx, r);
 977                 return r;
 978         }
 979         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 980         amdgpu_ring_write(ring, 0xDEADBEEF);
 981         amdgpu_ring_commit(ring);
 982         for (i = 0; i < adev->usec_timeout; i++) {
 983                 tmp = RREG32(mmUVD_CONTEXT_ID);
 984                 if (tmp == 0xDEADBEEF)
 985                         break;
 986                 DRM_UDELAY(1);
 987         }
 988
 989         if (i < adev->usec_timeout) {
 990                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 991                          ring->idx, i);
 992         } else {
 993                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 994                           ring->idx, tmp);
 995                 r = -EINVAL;
 996         }
 997         return r;
 998 }
 999
1000 /**
1001  * uvd_v6_0_ring_emit_ib - execute indirect buffer
1002  *
1003  * @ring: amdgpu_ring pointer
1004  * @ib: indirect buffer to execute
1005  *
1006  * Write ring commands to execute the indirect buffer
1007  */
1008 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1009                                   struct amdgpu_ib *ib,
1010                                   unsigned vmid, bool ctx_switch)
1011 {
1012         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1013         amdgpu_ring_write(ring, vmid);
1014
1015         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1016         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1017         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1018         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1019         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1020         amdgpu_ring_write(ring, ib->length_dw);
1021 }
1022
1023 /**
1024  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1025  *
1026  * @ring: amdgpu_ring pointer
1027  * @ib: indirect buffer to execute
1028  *
1029  * Write enc ring commands to execute the indirect buffer
1030  */
1031 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1032                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1033 {
1034         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1035         amdgpu_ring_write(ring, vmid);
1036         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1037         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1038         amdgpu_ring_write(ring, ib->length_dw);
1039 }
1040
1041 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1042                                     uint32_t reg, uint32_t val)
1043 {
1044         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1045         amdgpu_ring_write(ring, reg << 2);
1046         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1047         amdgpu_ring_write(ring, val);
1048         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1049         amdgpu_ring_write(ring, 0x8);
1050 }
1051
1052 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1053                                         unsigned vmid, uint64_t pd_addr)
1054 {
1055         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1056
1057         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1058         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1059         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1060         amdgpu_ring_write(ring, 0);
1061         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1062         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1063         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1064         amdgpu_ring_write(ring, 0xC);
1065 }
1066
1067 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1068 {
1069         uint32_t seq = ring->fence_drv.sync_seq;
1070         uint64_t addr = ring->fence_drv.gpu_addr;
1071
1072         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1073         amdgpu_ring_write(ring, lower_32_bits(addr));
1074         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1075         amdgpu_ring_write(ring, upper_32_bits(addr));
1076         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1077         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1078         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1079         amdgpu_ring_write(ring, seq);
1080         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1081         amdgpu_ring_write(ring, 0xE);
1082 }
1083
1084 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1085 {
1086         int i;
1087
1088         WARN_ON(ring->wptr % 2 || count % 2);
1089
1090         for (i = 0; i < count / 2; i++) {
1091                 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
1092                 amdgpu_ring_write(ring, 0);
1093         }
1094 }
1095
1096 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1097 {
1098         uint32_t seq = ring->fence_drv.sync_seq;
1099         uint64_t addr = ring->fence_drv.gpu_addr;
1100
1101         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1102         amdgpu_ring_write(ring, lower_32_bits(addr));
1103         amdgpu_ring_write(ring, upper_32_bits(addr));
1104         amdgpu_ring_write(ring, seq);
1105 }
1106
1107 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1108 {
1109         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1110 }
1111
1112 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1113                                             unsigned int vmid, uint64_t pd_addr)
1114 {
1115         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1116         amdgpu_ring_write(ring, vmid);
1117         amdgpu_ring_write(ring, pd_addr >> 12);
1118
1119         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1120         amdgpu_ring_write(ring, vmid);
1121 }
1122
1123 static bool uvd_v6_0_is_idle(void *handle)
1124 {
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1128 }
1129
1130 static int uvd_v6_0_wait_for_idle(void *handle)
1131 {
1132         unsigned i;
1133         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1134
1135         for (i = 0; i < adev->usec_timeout; i++) {
1136                 if (uvd_v6_0_is_idle(handle))
1137                         return 0;
1138         }
1139         return -ETIMEDOUT;
1140 }
1141
1142 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1143 static bool uvd_v6_0_check_soft_reset(void *handle)
1144 {
1145         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146         u32 srbm_soft_reset = 0;
1147         u32 tmp = RREG32(mmSRBM_STATUS);
1148
1149         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1150             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1151             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1152                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1153
1154         if (srbm_soft_reset) {
1155                 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
1156                 return true;
1157         } else {
1158                 adev->uvd.inst->srbm_soft_reset = 0;
1159                 return false;
1160         }
1161 }
1162
1163 static int uvd_v6_0_pre_soft_reset(void *handle)
1164 {
1165         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1166
1167         if (!adev->uvd.inst->srbm_soft_reset)
1168                 return 0;
1169
1170         uvd_v6_0_stop(adev);
1171         return 0;
1172 }
1173
1174 static int uvd_v6_0_soft_reset(void *handle)
1175 {
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177         u32 srbm_soft_reset;
1178
1179         if (!adev->uvd.inst->srbm_soft_reset)
1180                 return 0;
1181         srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
1182
1183         if (srbm_soft_reset) {
1184                 u32 tmp;
1185
1186                 tmp = RREG32(mmSRBM_SOFT_RESET);
1187                 tmp |= srbm_soft_reset;
1188                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1189                 WREG32(mmSRBM_SOFT_RESET, tmp);
1190                 tmp = RREG32(mmSRBM_SOFT_RESET);
1191
1192                 udelay(50);
1193
1194                 tmp &= ~srbm_soft_reset;
1195                 WREG32(mmSRBM_SOFT_RESET, tmp);
1196                 tmp = RREG32(mmSRBM_SOFT_RESET);
1197
1198                 /* Wait a little for things to settle down */
1199                 udelay(50);
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int uvd_v6_0_post_soft_reset(void *handle)
1206 {
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209         if (!adev->uvd.inst->srbm_soft_reset)
1210                 return 0;
1211
1212         mdelay(5);
1213
1214         return uvd_v6_0_start(adev);
1215 }
1216
1217 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1218                                         struct amdgpu_irq_src *source,
1219                                         unsigned type,
1220                                         enum amdgpu_interrupt_state state)
1221 {
1222         // TODO
1223         return 0;
1224 }
1225
1226 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1227                                       struct amdgpu_irq_src *source,
1228                                       struct amdgpu_iv_entry *entry)
1229 {
1230         bool int_handled = true;
1231         DRM_DEBUG("IH: UVD TRAP\n");
1232
1233         switch (entry->src_id) {
1234         case 124:
1235                 amdgpu_fence_process(&adev->uvd.inst->ring);
1236                 break;
1237         case 119:
1238                 if (likely(uvd_v6_0_enc_support(adev)))
1239                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
1240                 else
1241                         int_handled = false;
1242                 break;
1243         case 120:
1244                 if (likely(uvd_v6_0_enc_support(adev)))
1245                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
1246                 else
1247                         int_handled = false;
1248                 break;
1249         }
1250
1251         if (false == int_handled)
1252                         DRM_ERROR("Unhandled interrupt: %d %d\n",
1253                           entry->src_id, entry->src_data[0]);
1254
1255         return 0;
1256 }
1257
1258 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1259 {
1260         uint32_t data1, data3;
1261
1262         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1263         data3 = RREG32(mmUVD_CGC_GATE);
1264
1265         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1266                      UVD_SUVD_CGC_GATE__SIT_MASK |
1267                      UVD_SUVD_CGC_GATE__SMP_MASK |
1268                      UVD_SUVD_CGC_GATE__SCM_MASK |
1269                      UVD_SUVD_CGC_GATE__SDB_MASK |
1270                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1271                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1272                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1273                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1274                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1275                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1276                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1277                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1278
1279         if (enable) {
1280                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1281                         UVD_CGC_GATE__UDEC_MASK      |
1282                         UVD_CGC_GATE__MPEG2_MASK     |
1283                         UVD_CGC_GATE__RBC_MASK       |
1284                         UVD_CGC_GATE__LMI_MC_MASK    |
1285                         UVD_CGC_GATE__LMI_UMC_MASK   |
1286                         UVD_CGC_GATE__IDCT_MASK      |
1287                         UVD_CGC_GATE__MPRD_MASK      |
1288                         UVD_CGC_GATE__MPC_MASK       |
1289                         UVD_CGC_GATE__LBSI_MASK      |
1290                         UVD_CGC_GATE__LRBBM_MASK     |
1291                         UVD_CGC_GATE__UDEC_RE_MASK   |
1292                         UVD_CGC_GATE__UDEC_CM_MASK   |
1293                         UVD_CGC_GATE__UDEC_IT_MASK   |
1294                         UVD_CGC_GATE__UDEC_DB_MASK   |
1295                         UVD_CGC_GATE__UDEC_MP_MASK   |
1296                         UVD_CGC_GATE__WCB_MASK       |
1297                         UVD_CGC_GATE__JPEG_MASK      |
1298                         UVD_CGC_GATE__SCPU_MASK      |
1299                         UVD_CGC_GATE__JPEG2_MASK);
1300                 /* only in pg enabled, we can gate clock to vcpu*/
1301                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1302                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1303
1304                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1305         } else {
1306                 data3 = 0;
1307         }
1308
1309         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1310         WREG32(mmUVD_CGC_GATE, data3);
1311 }
1312
1313 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1314 {
1315         uint32_t data, data2;
1316
1317         data = RREG32(mmUVD_CGC_CTRL);
1318         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1319
1320
1321         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1322                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1323
1324
1325         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1326                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1327                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1328
1329         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1330                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1331                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1332                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1333                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1334                         UVD_CGC_CTRL__SYS_MODE_MASK |
1335                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1336                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1337                         UVD_CGC_CTRL__REGS_MODE_MASK |
1338                         UVD_CGC_CTRL__RBC_MODE_MASK |
1339                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1340                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1341                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1342                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1343                         UVD_CGC_CTRL__MPC_MODE_MASK |
1344                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1345                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1346                         UVD_CGC_CTRL__WCB_MODE_MASK |
1347                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1348                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1349                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1350                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1351         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1352                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1353                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1354                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1355                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1356
1357         WREG32(mmUVD_CGC_CTRL, data);
1358         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1359 }
1360
1361 #if 0
1362 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1363 {
1364         uint32_t data, data1, cgc_flags, suvd_flags;
1365
1366         data = RREG32(mmUVD_CGC_GATE);
1367         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1368
1369         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1370                 UVD_CGC_GATE__UDEC_MASK |
1371                 UVD_CGC_GATE__MPEG2_MASK |
1372                 UVD_CGC_GATE__RBC_MASK |
1373                 UVD_CGC_GATE__LMI_MC_MASK |
1374                 UVD_CGC_GATE__IDCT_MASK |
1375                 UVD_CGC_GATE__MPRD_MASK |
1376                 UVD_CGC_GATE__MPC_MASK |
1377                 UVD_CGC_GATE__LBSI_MASK |
1378                 UVD_CGC_GATE__LRBBM_MASK |
1379                 UVD_CGC_GATE__UDEC_RE_MASK |
1380                 UVD_CGC_GATE__UDEC_CM_MASK |
1381                 UVD_CGC_GATE__UDEC_IT_MASK |
1382                 UVD_CGC_GATE__UDEC_DB_MASK |
1383                 UVD_CGC_GATE__UDEC_MP_MASK |
1384                 UVD_CGC_GATE__WCB_MASK |
1385                 UVD_CGC_GATE__VCPU_MASK |
1386                 UVD_CGC_GATE__SCPU_MASK |
1387                 UVD_CGC_GATE__JPEG_MASK |
1388                 UVD_CGC_GATE__JPEG2_MASK;
1389
1390         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1391                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1392                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1393                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1394                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1395
1396         data |= cgc_flags;
1397         data1 |= suvd_flags;
1398
1399         WREG32(mmUVD_CGC_GATE, data);
1400         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1401 }
1402 #endif
1403
1404 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1405                                  bool enable)
1406 {
1407         u32 orig, data;
1408
1409         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1410                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1411                 data |= 0xfff;
1412                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1413
1414                 orig = data = RREG32(mmUVD_CGC_CTRL);
1415                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1416                 if (orig != data)
1417                         WREG32(mmUVD_CGC_CTRL, data);
1418         } else {
1419                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1420                 data &= ~0xfff;
1421                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1422
1423                 orig = data = RREG32(mmUVD_CGC_CTRL);
1424                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1425                 if (orig != data)
1426                         WREG32(mmUVD_CGC_CTRL, data);
1427         }
1428 }
1429
1430 static int uvd_v6_0_set_clockgating_state(void *handle,
1431                                           enum amd_clockgating_state state)
1432 {
1433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1434         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1435
1436         if (enable) {
1437                 /* wait for STATUS to clear */
1438                 if (uvd_v6_0_wait_for_idle(handle))
1439                         return -EBUSY;
1440                 uvd_v6_0_enable_clock_gating(adev, true);
1441                 /* enable HW gates because UVD is idle */
1442 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1443         } else {
1444                 /* disable HW gating and enable Sw gating */
1445                 uvd_v6_0_enable_clock_gating(adev, false);
1446         }
1447         uvd_v6_0_set_sw_clock_gating(adev);
1448         return 0;
1449 }
1450
1451 static int uvd_v6_0_set_powergating_state(void *handle,
1452                                           enum amd_powergating_state state)
1453 {
1454         /* This doesn't actually powergate the UVD block.
1455          * That's done in the dpm code via the SMC.  This
1456          * just re-inits the block as necessary.  The actual
1457          * gating still happens in the dpm code.  We should
1458          * revisit this when there is a cleaner line between
1459          * the smc and the hw blocks
1460          */
1461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462         int ret = 0;
1463
1464         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1465
1466         if (state == AMD_PG_STATE_GATE) {
1467                 uvd_v6_0_stop(adev);
1468         } else {
1469                 ret = uvd_v6_0_start(adev);
1470                 if (ret)
1471                         goto out;
1472         }
1473
1474 out:
1475         return ret;
1476 }
1477
1478 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1479 {
1480         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1481         int data;
1482
1483         mutex_lock(&adev->pm.mutex);
1484
1485         if (adev->flags & AMD_IS_APU)
1486                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1487         else
1488                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1489
1490         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1491                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1492                 goto out;
1493         }
1494
1495         /* AMD_CG_SUPPORT_UVD_MGCG */
1496         data = RREG32(mmUVD_CGC_CTRL);
1497         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1498                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1499
1500 out:
1501         mutex_unlock(&adev->pm.mutex);
1502 }
1503
1504 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1505         .name = "uvd_v6_0",
1506         .early_init = uvd_v6_0_early_init,
1507         .late_init = NULL,
1508         .sw_init = uvd_v6_0_sw_init,
1509         .sw_fini = uvd_v6_0_sw_fini,
1510         .hw_init = uvd_v6_0_hw_init,
1511         .hw_fini = uvd_v6_0_hw_fini,
1512         .suspend = uvd_v6_0_suspend,
1513         .resume = uvd_v6_0_resume,
1514         .is_idle = uvd_v6_0_is_idle,
1515         .wait_for_idle = uvd_v6_0_wait_for_idle,
1516         .check_soft_reset = uvd_v6_0_check_soft_reset,
1517         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1518         .soft_reset = uvd_v6_0_soft_reset,
1519         .post_soft_reset = uvd_v6_0_post_soft_reset,
1520         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1521         .set_powergating_state = uvd_v6_0_set_powergating_state,
1522         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1523 };
1524
1525 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1526         .type = AMDGPU_RING_TYPE_UVD,
1527         .align_mask = 0xf,
1528         .support_64bit_ptrs = false,
1529         .get_rptr = uvd_v6_0_ring_get_rptr,
1530         .get_wptr = uvd_v6_0_ring_get_wptr,
1531         .set_wptr = uvd_v6_0_ring_set_wptr,
1532         .parse_cs = amdgpu_uvd_ring_parse_cs,
1533         .emit_frame_size =
1534                 6 + /* hdp invalidate */
1535                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1536                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1537         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1538         .emit_ib = uvd_v6_0_ring_emit_ib,
1539         .emit_fence = uvd_v6_0_ring_emit_fence,
1540         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1541         .test_ring = uvd_v6_0_ring_test_ring,
1542         .test_ib = amdgpu_uvd_ring_test_ib,
1543         .insert_nop = uvd_v6_0_ring_insert_nop,
1544         .pad_ib = amdgpu_ring_generic_pad_ib,
1545         .begin_use = amdgpu_uvd_ring_begin_use,
1546         .end_use = amdgpu_uvd_ring_end_use,
1547         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1548 };
1549
1550 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1551         .type = AMDGPU_RING_TYPE_UVD,
1552         .align_mask = 0xf,
1553         .support_64bit_ptrs = false,
1554         .get_rptr = uvd_v6_0_ring_get_rptr,
1555         .get_wptr = uvd_v6_0_ring_get_wptr,
1556         .set_wptr = uvd_v6_0_ring_set_wptr,
1557         .emit_frame_size =
1558                 6 + /* hdp invalidate */
1559                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1560                 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
1561                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1562         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1563         .emit_ib = uvd_v6_0_ring_emit_ib,
1564         .emit_fence = uvd_v6_0_ring_emit_fence,
1565         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1566         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1567         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1568         .test_ring = uvd_v6_0_ring_test_ring,
1569         .test_ib = amdgpu_uvd_ring_test_ib,
1570         .insert_nop = uvd_v6_0_ring_insert_nop,
1571         .pad_ib = amdgpu_ring_generic_pad_ib,
1572         .begin_use = amdgpu_uvd_ring_begin_use,
1573         .end_use = amdgpu_uvd_ring_end_use,
1574         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1575 };
1576
1577 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1578         .type = AMDGPU_RING_TYPE_UVD_ENC,
1579         .align_mask = 0x3f,
1580         .nop = HEVC_ENC_CMD_NO_OP,
1581         .support_64bit_ptrs = false,
1582         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1583         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1584         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1585         .emit_frame_size =
1586                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1587                 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1588                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1589                 1, /* uvd_v6_0_enc_ring_insert_end */
1590         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1591         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1592         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1593         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1594         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1595         .test_ring = uvd_v6_0_enc_ring_test_ring,
1596         .test_ib = uvd_v6_0_enc_ring_test_ib,
1597         .insert_nop = amdgpu_ring_insert_nop,
1598         .insert_end = uvd_v6_0_enc_ring_insert_end,
1599         .pad_ib = amdgpu_ring_generic_pad_ib,
1600         .begin_use = amdgpu_uvd_ring_begin_use,
1601         .end_use = amdgpu_uvd_ring_end_use,
1602 };
1603
1604 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1605 {
1606         if (adev->asic_type >= CHIP_POLARIS10) {
1607                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
1608                 DRM_INFO("UVD is enabled in VM mode\n");
1609         } else {
1610                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
1611                 DRM_INFO("UVD is enabled in physical mode\n");
1612         }
1613 }
1614
1615 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1616 {
1617         int i;
1618
1619         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1620                 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1621
1622         DRM_INFO("UVD ENC is enabled in VM mode\n");
1623 }
1624
1625 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1626         .set = uvd_v6_0_set_interrupt_state,
1627         .process = uvd_v6_0_process_interrupt,
1628 };
1629
1630 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1631 {
1632         if (uvd_v6_0_enc_support(adev))
1633                 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
1634         else
1635                 adev->uvd.inst->irq.num_types = 1;
1636
1637         adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
1638 }
1639
1640 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1641 {
1642                 .type = AMD_IP_BLOCK_TYPE_UVD,
1643                 .major = 6,
1644                 .minor = 0,
1645                 .rev = 0,
1646                 .funcs = &uvd_v6_0_ip_funcs,
1647 };
1648
1649 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1650 {
1651                 .type = AMD_IP_BLOCK_TYPE_UVD,
1652                 .major = 6,
1653                 .minor = 2,
1654                 .rev = 0,
1655                 .funcs = &uvd_v6_0_ip_funcs,
1656 };
1657
1658 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1659 {
1660                 .type = AMD_IP_BLOCK_TYPE_UVD,
1661                 .major = 6,
1662                 .minor = 3,
1663                 .rev = 0,
1664                 .funcs = &uvd_v6_0_ip_funcs,
1665 };