drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_cache.h>
  26 #include "amdgpu.h"
  27 #include "gmc_v8_0.h"
  28 #include "amdgpu_ucode.h"
  29
  30 #include "gmc/gmc_8_1_d.h"
  31 #include "gmc/gmc_8_1_sh_mask.h"
  32
  33 #include "bif/bif_5_0_d.h"
  34 #include "bif/bif_5_0_sh_mask.h"
  35
  36 #include "oss/oss_3_0_d.h"
  37 #include "oss/oss_3_0_sh_mask.h"
  38
  39 #include "dce/dce_10_0_d.h"
  40 #include "dce/dce_10_0_sh_mask.h"
  41
  42 #include "vid.h"
  43 #include "vi.h"
  44
  45 #include "amdgpu_atombios.h"
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  50 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  51 static int gmc_v8_0_wait_for_idle(void *handle);
  52
  53 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  54 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  55 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  56 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  57
  58 static const u32 golden_settings_tonga_a11[] =
  59 {
  60         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  61         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  62         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  63         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  67 };
  68
  69 static const u32 tonga_mgcg_cgcg_init[] =
  70 {
  71         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  72 };
  73
  74 static const u32 golden_settings_fiji_a10[] =
  75 {
  76         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  77         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  79         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  80 };
  81
  82 static const u32 fiji_mgcg_cgcg_init[] =
  83 {
  84         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  85 };
  86
  87 static const u32 golden_settings_polaris11_a11[] =
  88 {
  89         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  91         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  92         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  93 };
  94
  95 static const u32 golden_settings_polaris10_a11[] =
  96 {
  97         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  98         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  99         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 100         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 101         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 102 };
 103
 104 static const u32 cz_mgcg_cgcg_init[] =
 105 {
 106         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 107 };
 108
 109 static const u32 stoney_mgcg_cgcg_init[] =
 110 {
 111         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 112         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 113 };
 114
 115 static const u32 golden_settings_stoney_common[] =
 116 {
 117         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 118         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 119 };
 120
 121 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 122 {
 123         switch (adev->asic_type) {
 124         case CHIP_FIJI:
 125                 amdgpu_device_program_register_sequence(adev,
 126                                                         fiji_mgcg_cgcg_init,
 127                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 128                 amdgpu_device_program_register_sequence(adev,
 129                                                         golden_settings_fiji_a10,
 130                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 131                 break;
 132         case CHIP_TONGA:
 133                 amdgpu_device_program_register_sequence(adev,
 134                                                         tonga_mgcg_cgcg_init,
 135                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 136                 amdgpu_device_program_register_sequence(adev,
 137                                                         golden_settings_tonga_a11,
 138                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 139                 break;
 140         case CHIP_POLARIS11:
 141         case CHIP_POLARIS12:
 142         case CHIP_VEGAM:
 143                 amdgpu_device_program_register_sequence(adev,
 144                                                         golden_settings_polaris11_a11,
 145                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 146                 break;
 147         case CHIP_POLARIS10:
 148                 amdgpu_device_program_register_sequence(adev,
 149                                                         golden_settings_polaris10_a11,
 150                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 151                 break;
 152         case CHIP_CARRIZO:
 153                 amdgpu_device_program_register_sequence(adev,
 154                                                         cz_mgcg_cgcg_init,
 155                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 156                 break;
 157         case CHIP_STONEY:
 158                 amdgpu_device_program_register_sequence(adev,
 159                                                         stoney_mgcg_cgcg_init,
 160                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 161                 amdgpu_device_program_register_sequence(adev,
 162                                                         golden_settings_stoney_common,
 163                                                         ARRAY_SIZE(golden_settings_stoney_common));
 164                 break;
 165         default:
 166                 break;
 167         }
 168 }
 169
 170 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 171 {
 172         u32 blackout;
 173
 174         gmc_v8_0_wait_for_idle(adev);
 175
 176         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 177         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 178                 /* Block CPU access */
 179                 WREG32(mmBIF_FB_EN, 0);
 180                 /* blackout the MC */
 181                 blackout = REG_SET_FIELD(blackout,
 182                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 183                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 184         }
 185         /* wait for the MC to settle */
 186         udelay(100);
 187 }
 188
 189 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 190 {
 191         u32 tmp;
 192
 193         /* unblackout the MC */
 194         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 195         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 196         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 197         /* allow CPU access */
 198         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 199         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 200         WREG32(mmBIF_FB_EN, tmp);
 201 }
 202
 203 /**
 204  * gmc_v8_0_init_microcode - load ucode images from disk
 205  *
 206  * @adev: amdgpu_device pointer
 207  *
 208  * Use the firmware interface to load the ucode images into
 209  * the driver (not loaded into hw).
 210  * Returns 0 on success, error on failure.
 211  */
 212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 213 {
 214         const char *chip_name;
 215         char fw_name[30];
 216         int err;
 217
 218         DRM_DEBUG("\n");
 219
 220         switch (adev->asic_type) {
 221         case CHIP_TONGA:
 222                 chip_name = "tonga";
 223                 break;
 224         case CHIP_POLARIS11:
 225                 chip_name = "polaris11";
 226                 break;
 227         case CHIP_POLARIS10:
 228                 chip_name = "polaris10";
 229                 break;
 230         case CHIP_POLARIS12:
 231                 chip_name = "polaris12";
 232                 break;
 233         case CHIP_FIJI:
 234         case CHIP_CARRIZO:
 235         case CHIP_STONEY:
 236         case CHIP_VEGAM:
 237                 return 0;
 238         default: BUG();
 239         }
 240
 241         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 242         err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
 243         if (err)
 244                 goto out;
 245         err = amdgpu_ucode_validate(adev->gmc.fw);
 246
 247 out:
 248         if (err) {
 249                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 250                 release_firmware(adev->gmc.fw);
 251                 adev->gmc.fw = NULL;
 252         }
 253         return err;
 254 }
 255
 256 /**
 257  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 258  *
 259  * @adev: amdgpu_device pointer
 260  *
 261  * Load the GDDR MC ucode into the hw (CIK).
 262  * Returns 0 on success, error on failure.
 263  */
 264 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 265 {
 266         const struct mc_firmware_header_v1_0 *hdr;
 267         const __le32 *fw_data = NULL;
 268         const __le32 *io_mc_regs = NULL;
 269         u32 running;
 270         int i, ucode_size, regs_size;
 271
 272         /* Skip MC ucode loading on SR-IOV capable boards.
 273          * vbios does this for us in asic_init in that case.
 274          * Skip MC ucode loading on VF, because hypervisor will do that
 275          * for this adaptor.
 276          */
 277         if (amdgpu_sriov_bios(adev))
 278                 return 0;
 279
 280         if (!adev->gmc.fw)
 281                 return -EINVAL;
 282
 283         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 284         amdgpu_ucode_print_mc_hdr(&hdr->header);
 285
 286         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 287         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 288         io_mc_regs = (const __le32 *)
 289                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 290         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 291         fw_data = (const __le32 *)
 292                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 293
 294         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 295
 296         if (running == 0) {
 297                 /* reset the engine and set to writable */
 298                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 299                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 300
 301                 /* load mc io regs */
 302                 for (i = 0; i < regs_size; i++) {
 303                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 304                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 305                 }
 306                 /* load the MC ucode */
 307                 for (i = 0; i < ucode_size; i++)
 308                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 309
 310                 /* put the engine back into the active state */
 311                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 312                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 313                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 314
 315                 /* wait for training to complete */
 316                 for (i = 0; i < adev->usec_timeout; i++) {
 317                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 318                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 319                                 break;
 320                         udelay(1);
 321                 }
 322                 for (i = 0; i < adev->usec_timeout; i++) {
 323                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 324                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 325                                 break;
 326                         udelay(1);
 327                 }
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 334 {
 335         const struct mc_firmware_header_v1_0 *hdr;
 336         const __le32 *fw_data = NULL;
 337         const __le32 *io_mc_regs = NULL;
 338         u32 data, vbios_version;
 339         int i, ucode_size, regs_size;
 340
 341         /* Skip MC ucode loading on SR-IOV capable boards.
 342          * vbios does this for us in asic_init in that case.
 343          * Skip MC ucode loading on VF, because hypervisor will do that
 344          * for this adaptor.
 345          */
 346         if (amdgpu_sriov_bios(adev))
 347                 return 0;
 348
 349         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 350         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 351         vbios_version = data & 0xf;
 352
 353         if (vbios_version == 0)
 354                 return 0;
 355
 356         if (!adev->gmc.fw)
 357                 return -EINVAL;
 358
 359         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 360         amdgpu_ucode_print_mc_hdr(&hdr->header);
 361
 362         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 363         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 364         io_mc_regs = (const __le32 *)
 365                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 366         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 367         fw_data = (const __le32 *)
 368                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 369
 370         data = RREG32(mmMC_SEQ_MISC0);
 371         data &= ~(0x40);
 372         WREG32(mmMC_SEQ_MISC0, data);
 373
 374         /* load mc io regs */
 375         for (i = 0; i < regs_size; i++) {
 376                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 377                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 378         }
 379
 380         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 381         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 382
 383         /* load the MC ucode */
 384         for (i = 0; i < ucode_size; i++)
 385                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 386
 387         /* put the engine back into the active state */
 388         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 389         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 390         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 391
 392         /* wait for training to complete */
 393         for (i = 0; i < adev->usec_timeout; i++) {
 394                 data = RREG32(mmMC_SEQ_MISC0);
 395                 if (data & 0x80)
 396                         break;
 397                 udelay(1);
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 404                                        struct amdgpu_gmc *mc)
 405 {
 406         u64 base = 0;
 407
 408         if (!amdgpu_sriov_vf(adev))
 409                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 410         base <<= 24;
 411
 412         amdgpu_device_vram_location(adev, &adev->gmc, base);
 413         amdgpu_device_gart_location(adev, mc);
 414 }
 415
 416 /**
 417  * gmc_v8_0_mc_program - program the GPU memory controller
 418  *
 419  * @adev: amdgpu_device pointer
 420  *
 421  * Set the location of vram, gart, and AGP in the GPU's
 422  * physical address space (CIK).
 423  */
 424 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 425 {
 426         u32 tmp;
 427         int i, j;
 428
 429         /* Initialize HDP */
 430         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 431                 WREG32((0xb05 + j), 0x00000000);
 432                 WREG32((0xb06 + j), 0x00000000);
 433                 WREG32((0xb07 + j), 0x00000000);
 434                 WREG32((0xb08 + j), 0x00000000);
 435                 WREG32((0xb09 + j), 0x00000000);
 436         }
 437         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 438
 439         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 440                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 441         }
 442         if (adev->mode_info.num_crtc) {
 443                 /* Lockout access through VGA aperture*/
 444                 tmp = RREG32(mmVGA_HDP_CONTROL);
 445                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 446                 WREG32(mmVGA_HDP_CONTROL, tmp);
 447
 448                 /* disable VGA render */
 449                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 450                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 451                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 452         }
 453         /* Update configuration */
 454         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 455                adev->gmc.vram_start >> 12);
 456         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 457                adev->gmc.vram_end >> 12);
 458         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 459                adev->vram_scratch.gpu_addr >> 12);
 460
 461         if (amdgpu_sriov_vf(adev)) {
 462                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 463                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 464                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 465                 /* XXX double check these! */
 466                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 467                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 468                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 469         }
 470
 471         WREG32(mmMC_VM_AGP_BASE, 0);
 472         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 473         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 474         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 475                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 476         }
 477
 478         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 479
 480         tmp = RREG32(mmHDP_MISC_CNTL);
 481         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 482         WREG32(mmHDP_MISC_CNTL, tmp);
 483
 484         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 485         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 486 }
 487
 488 /**
 489  * gmc_v8_0_mc_init - initialize the memory controller driver params
 490  *
 491  * @adev: amdgpu_device pointer
 492  *
 493  * Look up the amount of vram, vram width, and decide how to place
 494  * vram and gart within the GPU's physical address space (CIK).
 495  * Returns 0 for success.
 496  */
 497 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 498 {
 499         int r;
 500
 501         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 502         if (!adev->gmc.vram_width) {
 503                 u32 tmp;
 504                 int chansize, numchan;
 505
 506                 /* Get VRAM informations */
 507                 tmp = RREG32(mmMC_ARB_RAMCFG);
 508                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 509                         chansize = 64;
 510                 } else {
 511                         chansize = 32;
 512                 }
 513                 tmp = RREG32(mmMC_SHARED_CHMAP);
 514                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 515                 case 0:
 516                 default:
 517                         numchan = 1;
 518                         break;
 519                 case 1:
 520                         numchan = 2;
 521                         break;
 522                 case 2:
 523                         numchan = 4;
 524                         break;
 525                 case 3:
 526                         numchan = 8;
 527                         break;
 528                 case 4:
 529                         numchan = 3;
 530                         break;
 531                 case 5:
 532                         numchan = 6;
 533                         break;
 534                 case 6:
 535                         numchan = 10;
 536                         break;
 537                 case 7:
 538                         numchan = 12;
 539                         break;
 540                 case 8:
 541                         numchan = 16;
 542                         break;
 543                 }
 544                 adev->gmc.vram_width = numchan * chansize;
 545         }
 546         /* size in MB on si */
 547         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 548         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 549
 550         if (!(adev->flags & AMD_IS_APU)) {
 551                 r = amdgpu_device_resize_fb_bar(adev);
 552                 if (r)
 553                         return r;
 554         }
 555         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 556         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 557
 558 #ifdef CONFIG_X86_64
 559         if (adev->flags & AMD_IS_APU) {
 560                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 561                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 562         }
 563 #endif
 564
 565         /* In case the PCI BAR is larger than the actual amount of vram */
 566         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 567         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 568                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 569
 570         /* set the gart size */
 571         if (amdgpu_gart_size == -1) {
 572                 switch (adev->asic_type) {
 573                 case CHIP_POLARIS10: /* all engines support GPUVM */
 574                 case CHIP_POLARIS11: /* all engines support GPUVM */
 575                 case CHIP_POLARIS12: /* all engines support GPUVM */
 576                 case CHIP_VEGAM:     /* all engines support GPUVM */
 577                 default:
 578                         adev->gmc.gart_size = 256ULL << 20;
 579                         break;
 580                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 581                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 582                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 583                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 584                         adev->gmc.gart_size = 1024ULL << 20;
 585                         break;
 586                 }
 587         } else {
 588                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 589         }
 590
 591         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 592
 593         return 0;
 594 }
 595
 596 /*
 597  * GART
 598  * VMID 0 is the physical GPU addresses as used by the kernel.
 599  * VMIDs 1-15 are used for userspace clients and are handled
 600  * by the amdgpu vm/hsa code.
 601  */
 602
 603 /**
 604  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 605  *
 606  * @adev: amdgpu_device pointer
 607  * @vmid: vm instance to flush
 608  *
 609  * Flush the TLB for the requested page table (CIK).
 610  */
 611 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 612                                         uint32_t vmid)
 613 {
 614         /* bits 0-15 are the VM contexts0-15 */
 615         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 616 }
 617
 618 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 619                                             unsigned vmid, uint64_t pd_addr)
 620 {
 621         uint32_t reg;
 622
 623         if (vmid < 8)
 624                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 625         else
 626                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 627         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 628
 629         /* bits 0-15 are the VM contexts0-15 */
 630         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 631
 632         return pd_addr;
 633 }
 634
 635 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 636                                         unsigned pasid)
 637 {
 638         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 639 }
 640
 641 /**
 642  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
 643  *
 644  * @adev: amdgpu_device pointer
 645  * @cpu_pt_addr: cpu address of the page table
 646  * @gpu_page_idx: entry in the page table to update
 647  * @addr: dst addr to write into pte/pde
 648  * @flags: access flags
 649  *
 650  * Update the page tables using the CPU.
 651  */
 652 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 653                                 uint32_t gpu_page_idx, uint64_t addr,
 654                                 uint64_t flags)
 655 {
 656         void __iomem *ptr = (void *)cpu_pt_addr;
 657         uint64_t value;
 658
 659         /*
 660          * PTE format on VI:
 661          * 63:40 reserved
 662          * 39:12 4k physical page base address
 663          * 11:7 fragment
 664          * 6 write
 665          * 5 read
 666          * 4 exe
 667          * 3 reserved
 668          * 2 snooped
 669          * 1 system
 670          * 0 valid
 671          *
 672          * PDE format on VI:
 673          * 63:59 block fragment size
 674          * 58:40 reserved
 675          * 39:1 physical base address of PTE
 676          * bits 5:1 must be 0.
 677          * 0 valid
 678          */
 679         value = addr & 0x000000FFFFFFF000ULL;
 680         value |= flags;
 681         writeq(value, ptr + (gpu_page_idx * 8));
 682
 683         return 0;
 684 }
 685
 686 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 687                                           uint32_t flags)
 688 {
 689         uint64_t pte_flag = 0;
 690
 691         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 692                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 693         if (flags & AMDGPU_VM_PAGE_READABLE)
 694                 pte_flag |= AMDGPU_PTE_READABLE;
 695         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 696                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 697         if (flags & AMDGPU_VM_PAGE_PRT)
 698                 pte_flag |= AMDGPU_PTE_PRT;
 699
 700         return pte_flag;
 701 }
 702
 703 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 704                                 uint64_t *addr, uint64_t *flags)
 705 {
 706         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 707 }
 708
 709 /**
 710  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 711  *
 712  * @adev: amdgpu_device pointer
 713  * @value: true redirects VM faults to the default page
 714  */
 715 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 716                                               bool value)
 717 {
 718         u32 tmp;
 719
 720         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 721         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 722                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 723         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 724                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 725         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 726                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 727         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 728                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 729         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 730                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 731         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 732                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 733         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 734                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 735         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 736 }
 737
 738 /**
 739  * gmc_v8_0_set_prt - set PRT VM fault
 740  *
 741  * @adev: amdgpu_device pointer
 742  * @enable: enable/disable VM fault handling for PRT
 743 */
 744 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 745 {
 746         u32 tmp;
 747
 748         if (enable && !adev->gmc.prt_warning) {
 749                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 750                 adev->gmc.prt_warning = true;
 751         }
 752
 753         tmp = RREG32(mmVM_PRT_CNTL);
 754         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 755                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 756         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 757                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 758         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 759                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 760         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 761                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 762         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 763                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 764         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 765                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 766         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 767                             MASK_PDE0_FAULT, enable);
 768         WREG32(mmVM_PRT_CNTL, tmp);
 769
 770         if (enable) {
 771                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 772                 uint32_t high = adev->vm_manager.max_pfn -
 773                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 774
 775                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 776                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 777                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 778                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 779                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 780                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 781                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 782                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 783         } else {
 784                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 785                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 786                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 787                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 788                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 789                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 790                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 791                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 792         }
 793 }
 794
 795 /**
 796  * gmc_v8_0_gart_enable - gart enable
 797  *
 798  * @adev: amdgpu_device pointer
 799  *
 800  * This sets up the TLBs, programs the page tables for VMID0,
 801  * sets up the hw for VMIDs 1-15 which are allocated on
 802  * demand, and sets up the global locations for the LDS, GDS,
 803  * and GPUVM for FSA64 clients (CIK).
 804  * Returns 0 for success, errors for failure.
 805  */
 806 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 807 {
 808         int r, i;
 809         u32 tmp, field;
 810
 811         if (adev->gart.robj == NULL) {
 812                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 813                 return -EINVAL;
 814         }
 815         r = amdgpu_gart_table_vram_pin(adev);
 816         if (r)
 817                 return r;
 818         /* Setup TLB control */
 819         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 820         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 821         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 822         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 823         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 824         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 825         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 826         /* Setup L2 cache */
 827         tmp = RREG32(mmVM_L2_CNTL);
 828         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 829         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 830         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 833         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 834         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 835         WREG32(mmVM_L2_CNTL, tmp);
 836         tmp = RREG32(mmVM_L2_CNTL2);
 837         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 838         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 839         WREG32(mmVM_L2_CNTL2, tmp);
 840
 841         field = adev->vm_manager.fragment_size;
 842         tmp = RREG32(mmVM_L2_CNTL3);
 843         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 844         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 845         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 846         WREG32(mmVM_L2_CNTL3, tmp);
 847         /* XXX: set to enable PTE/PDE in system memory */
 848         tmp = RREG32(mmVM_L2_CNTL4);
 849         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 850         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 851         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 852         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 859         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 860         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 861         WREG32(mmVM_L2_CNTL4, tmp);
 862         /* setup context0 */
 863         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 864         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 865         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 866         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 867                         (u32)(adev->dummy_page_addr >> 12));
 868         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 869         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 870         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 871         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 872         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 873         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 874
 875         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 876         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 877         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 878
 879         /* empty context1-15 */
 880         /* FIXME start with 4G, once using 2 level pt switch to full
 881          * vm size space
 882          */
 883         /* set vm size, must be a multiple of 4 */
 884         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 885         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 886         for (i = 1; i < 16; i++) {
 887                 if (i < 8)
 888                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 889                                adev->gart.table_addr >> 12);
 890                 else
 891                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 892                                adev->gart.table_addr >> 12);
 893         }
 894
 895         /* enable context1-15 */
 896         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 897                (u32)(adev->dummy_page_addr >> 12));
 898         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 899         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 900         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 901         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 902         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 903         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 904         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 905         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 906         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 907         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 908         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 909         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 910                             adev->vm_manager.block_size - 9);
 911         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 912         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 913                 gmc_v8_0_set_fault_enable_default(adev, false);
 914         else
 915                 gmc_v8_0_set_fault_enable_default(adev, true);
 916
 917         gmc_v8_0_flush_gpu_tlb(adev, 0);
 918         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 919                  (unsigned)(adev->gmc.gart_size >> 20),
 920                  (unsigned long long)adev->gart.table_addr);
 921         adev->gart.ready = true;
 922         return 0;
 923 }
 924
 925 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 926 {
 927         int r;
 928
 929         if (adev->gart.robj) {
 930                 WARN(1, "R600 PCIE GART already initialized\n");
 931                 return 0;
 932         }
 933         /* Initialize common gart structure */
 934         r = amdgpu_gart_init(adev);
 935         if (r)
 936                 return r;
 937         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 938         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 939         return amdgpu_gart_table_vram_alloc(adev);
 940 }
 941
 942 /**
 943  * gmc_v8_0_gart_disable - gart disable
 944  *
 945  * @adev: amdgpu_device pointer
 946  *
 947  * This disables all VM page table (CIK).
 948  */
 949 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 950 {
 951         u32 tmp;
 952
 953         /* Disable all tables */
 954         WREG32(mmVM_CONTEXT0_CNTL, 0);
 955         WREG32(mmVM_CONTEXT1_CNTL, 0);
 956         /* Setup TLB control */
 957         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 958         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 959         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 960         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 961         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 962         /* Setup L2 cache */
 963         tmp = RREG32(mmVM_L2_CNTL);
 964         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 965         WREG32(mmVM_L2_CNTL, tmp);
 966         WREG32(mmVM_L2_CNTL2, 0);
 967         amdgpu_gart_table_vram_unpin(adev);
 968 }
 969
 970 /**
 971  * gmc_v8_0_gart_fini - vm fini callback
 972  *
 973  * @adev: amdgpu_device pointer
 974  *
 975  * Tears down the driver GART/VM setup (CIK).
 976  */
 977 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 978 {
 979         amdgpu_gart_table_vram_free(adev);
 980         amdgpu_gart_fini(adev);
 981 }
 982
 983 /**
 984  * gmc_v8_0_vm_decode_fault - print human readable fault info
 985  *
 986  * @adev: amdgpu_device pointer
 987  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 988  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 989  *
 990  * Print human readable fault information (CIK).
 991  */
 992 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 993                                      u32 addr, u32 mc_client, unsigned pasid)
 994 {
 995         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 996         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 997                                         PROTECTIONS);
 998         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 999                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1000         u32 mc_id;
1001
1002         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1003                               MEMORY_CLIENT_ID);
1004
1005         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1006                protections, vmid, pasid, addr,
1007                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1008                              MEMORY_CLIENT_RW) ?
1009                "write" : "read", block, mc_client, mc_id);
1010 }
1011
1012 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1013 {
1014         switch (mc_seq_vram_type) {
1015         case MC_SEQ_MISC0__MT__GDDR1:
1016                 return AMDGPU_VRAM_TYPE_GDDR1;
1017         case MC_SEQ_MISC0__MT__DDR2:
1018                 return AMDGPU_VRAM_TYPE_DDR2;
1019         case MC_SEQ_MISC0__MT__GDDR3:
1020                 return AMDGPU_VRAM_TYPE_GDDR3;
1021         case MC_SEQ_MISC0__MT__GDDR4:
1022                 return AMDGPU_VRAM_TYPE_GDDR4;
1023         case MC_SEQ_MISC0__MT__GDDR5:
1024                 return AMDGPU_VRAM_TYPE_GDDR5;
1025         case MC_SEQ_MISC0__MT__HBM:
1026                 return AMDGPU_VRAM_TYPE_HBM;
1027         case MC_SEQ_MISC0__MT__DDR3:
1028                 return AMDGPU_VRAM_TYPE_DDR3;
1029         default:
1030                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1031         }
1032 }
1033
1034 static int gmc_v8_0_early_init(void *handle)
1035 {
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         gmc_v8_0_set_gmc_funcs(adev);
1039         gmc_v8_0_set_irq_funcs(adev);
1040
1041         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1042         adev->gmc.shared_aperture_end =
1043                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1044         adev->gmc.private_aperture_start =
1045                 adev->gmc.shared_aperture_end + 1;
1046         adev->gmc.private_aperture_end =
1047                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1048
1049         return 0;
1050 }
1051
1052 static int gmc_v8_0_late_init(void *handle)
1053 {
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056         amdgpu_bo_late_init(adev);
1057
1058         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1059                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1060         else
1061                 return 0;
1062 }
1063
1064 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1065 {
1066         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1067         unsigned size;
1068
1069         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1070                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1071         } else {
1072                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1073                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1074                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1075                         4);
1076         }
1077         /* return 0 if the pre-OS buffer uses up most of vram */
1078         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1079                 return 0;
1080         return size;
1081 }
1082
1083 #define mmMC_SEQ_MISC0_FIJI 0xA71
1084
1085 static int gmc_v8_0_sw_init(void *handle)
1086 {
1087         int r;
1088         int dma_bits;
1089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090
1091         if (adev->flags & AMD_IS_APU) {
1092                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1093         } else {
1094                 u32 tmp;
1095
1096                 if ((adev->asic_type == CHIP_FIJI) ||
1097                     (adev->asic_type == CHIP_VEGAM))
1098                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1099                 else
1100                         tmp = RREG32(mmMC_SEQ_MISC0);
1101                 tmp &= MC_SEQ_MISC0__MT__MASK;
1102                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1103         }
1104
1105         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1106         if (r)
1107                 return r;
1108
1109         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1110         if (r)
1111                 return r;
1112
1113         /* Adjust VM size here.
1114          * Currently set to 4GB ((1 << 20) 4k pages).
1115          * Max GPUVM size for cayman and SI is 40 bits.
1116          */
1117         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1118
1119         /* Set the internal MC address mask
1120          * This is the max address of the GPU's
1121          * internal address space.
1122          */
1123         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1124
1125         /* set DMA mask + need_dma32 flags.
1126          * PCIE - can handle 40-bits.
1127          * IGP - can handle 40-bits
1128          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1129          */
1130         adev->need_dma32 = false;
1131         dma_bits = adev->need_dma32 ? 32 : 40;
1132         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1133         if (r) {
1134                 adev->need_dma32 = true;
1135                 dma_bits = 32;
1136                 pr_warn("amdgpu: No suitable DMA available\n");
1137         }
1138         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1139         if (r) {
1140                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1141                 pr_warn("amdgpu: No coherent DMA available\n");
1142         }
1143         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1144
1145         r = gmc_v8_0_init_microcode(adev);
1146         if (r) {
1147                 DRM_ERROR("Failed to load mc firmware!\n");
1148                 return r;
1149         }
1150
1151         r = gmc_v8_0_mc_init(adev);
1152         if (r)
1153                 return r;
1154
1155         adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1156
1157         /* Memory manager */
1158         r = amdgpu_bo_init(adev);
1159         if (r)
1160                 return r;
1161
1162         r = gmc_v8_0_gart_init(adev);
1163         if (r)
1164                 return r;
1165
1166         /*
1167          * number of VMs
1168          * VMID 0 is reserved for System
1169          * amdgpu graphics/compute will use VMIDs 1-7
1170          * amdkfd will use VMIDs 8-15
1171          */
1172         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1173         amdgpu_vm_manager_init(adev);
1174
1175         /* base offset of vram pages */
1176         if (adev->flags & AMD_IS_APU) {
1177                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1178
1179                 tmp <<= 22;
1180                 adev->vm_manager.vram_base_offset = tmp;
1181         } else {
1182                 adev->vm_manager.vram_base_offset = 0;
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int gmc_v8_0_sw_fini(void *handle)
1189 {
1190         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1191
1192         amdgpu_gem_force_release(adev);
1193         amdgpu_vm_manager_fini(adev);
1194         gmc_v8_0_gart_fini(adev);
1195         amdgpu_bo_fini(adev);
1196         release_firmware(adev->gmc.fw);
1197         adev->gmc.fw = NULL;
1198
1199         return 0;
1200 }
1201
1202 static int gmc_v8_0_hw_init(void *handle)
1203 {
1204         int r;
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207         gmc_v8_0_init_golden_registers(adev);
1208
1209         gmc_v8_0_mc_program(adev);
1210
1211         if (adev->asic_type == CHIP_TONGA) {
1212                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1213                 if (r) {
1214                         DRM_ERROR("Failed to load MC firmware!\n");
1215                         return r;
1216                 }
1217         } else if (adev->asic_type == CHIP_POLARIS11 ||
1218                         adev->asic_type == CHIP_POLARIS10 ||
1219                         adev->asic_type == CHIP_POLARIS12) {
1220                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1221                 if (r) {
1222                         DRM_ERROR("Failed to load MC firmware!\n");
1223                         return r;
1224                 }
1225         }
1226
1227         r = gmc_v8_0_gart_enable(adev);
1228         if (r)
1229                 return r;
1230
1231         return r;
1232 }
1233
1234 static int gmc_v8_0_hw_fini(void *handle)
1235 {
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237
1238         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1239         gmc_v8_0_gart_disable(adev);
1240
1241         return 0;
1242 }
1243
1244 static int gmc_v8_0_suspend(void *handle)
1245 {
1246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247
1248         gmc_v8_0_hw_fini(adev);
1249
1250         return 0;
1251 }
1252
1253 static int gmc_v8_0_resume(void *handle)
1254 {
1255         int r;
1256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
1258         r = gmc_v8_0_hw_init(adev);
1259         if (r)
1260                 return r;
1261
1262         amdgpu_vmid_reset_all(adev);
1263
1264         return 0;
1265 }
1266
1267 static bool gmc_v8_0_is_idle(void *handle)
1268 {
1269         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270         u32 tmp = RREG32(mmSRBM_STATUS);
1271
1272         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1273                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1274                 return false;
1275
1276         return true;
1277 }
1278
1279 static int gmc_v8_0_wait_for_idle(void *handle)
1280 {
1281         unsigned i;
1282         u32 tmp;
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284
1285         for (i = 0; i < adev->usec_timeout; i++) {
1286                 /* read MC_STATUS */
1287                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1288                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1289                                                SRBM_STATUS__MCC_BUSY_MASK |
1290                                                SRBM_STATUS__MCD_BUSY_MASK |
1291                                                SRBM_STATUS__VMC_BUSY_MASK |
1292                                                SRBM_STATUS__VMC1_BUSY_MASK);
1293                 if (!tmp)
1294                         return 0;
1295                 udelay(1);
1296         }
1297         return -ETIMEDOUT;
1298
1299 }
1300
1301 static bool gmc_v8_0_check_soft_reset(void *handle)
1302 {
1303         u32 srbm_soft_reset = 0;
1304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305         u32 tmp = RREG32(mmSRBM_STATUS);
1306
1307         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1308                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1309                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1310
1311         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1312                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1313                 if (!(adev->flags & AMD_IS_APU))
1314                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1315                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1316         }
1317         if (srbm_soft_reset) {
1318                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1319                 return true;
1320         } else {
1321                 adev->gmc.srbm_soft_reset = 0;
1322                 return false;
1323         }
1324 }
1325
1326 static int gmc_v8_0_pre_soft_reset(void *handle)
1327 {
1328         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329
1330         if (!adev->gmc.srbm_soft_reset)
1331                 return 0;
1332
1333         gmc_v8_0_mc_stop(adev);
1334         if (gmc_v8_0_wait_for_idle(adev)) {
1335                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int gmc_v8_0_soft_reset(void *handle)
1342 {
1343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344         u32 srbm_soft_reset;
1345
1346         if (!adev->gmc.srbm_soft_reset)
1347                 return 0;
1348         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1349
1350         if (srbm_soft_reset) {
1351                 u32 tmp;
1352
1353                 tmp = RREG32(mmSRBM_SOFT_RESET);
1354                 tmp |= srbm_soft_reset;
1355                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1356                 WREG32(mmSRBM_SOFT_RESET, tmp);
1357                 tmp = RREG32(mmSRBM_SOFT_RESET);
1358
1359                 udelay(50);
1360
1361                 tmp &= ~srbm_soft_reset;
1362                 WREG32(mmSRBM_SOFT_RESET, tmp);
1363                 tmp = RREG32(mmSRBM_SOFT_RESET);
1364
1365                 /* Wait a little for things to settle down */
1366                 udelay(50);
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int gmc_v8_0_post_soft_reset(void *handle)
1373 {
1374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376         if (!adev->gmc.srbm_soft_reset)
1377                 return 0;
1378
1379         gmc_v8_0_mc_resume(adev);
1380         return 0;
1381 }
1382
1383 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1384                                              struct amdgpu_irq_src *src,
1385                                              unsigned type,
1386                                              enum amdgpu_interrupt_state state)
1387 {
1388         u32 tmp;
1389         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1390                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1391                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1392                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1393                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1394                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1395                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1396
1397         switch (state) {
1398         case AMDGPU_IRQ_STATE_DISABLE:
1399                 /* system context */
1400                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1401                 tmp &= ~bits;
1402                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1403                 /* VMs */
1404                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1405                 tmp &= ~bits;
1406                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1407                 break;
1408         case AMDGPU_IRQ_STATE_ENABLE:
1409                 /* system context */
1410                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1411                 tmp |= bits;
1412                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1413                 /* VMs */
1414                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1415                 tmp |= bits;
1416                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1417                 break;
1418         default:
1419                 break;
1420         }
1421
1422         return 0;
1423 }
1424
1425 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1426                                       struct amdgpu_irq_src *source,
1427                                       struct amdgpu_iv_entry *entry)
1428 {
1429         u32 addr, status, mc_client;
1430
1431         if (amdgpu_sriov_vf(adev)) {
1432                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1433                         entry->src_id, entry->src_data[0]);
1434                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1435                 return 0;
1436         }
1437
1438         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1439         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1440         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1441         /* reset addr and status */
1442         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1443
1444         if (!addr && !status)
1445                 return 0;
1446
1447         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1448                 gmc_v8_0_set_fault_enable_default(adev, false);
1449
1450         if (printk_ratelimit()) {
1451                 struct amdgpu_task_info task_info = { 0 };
1452
1453                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1454
1455                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1456                         entry->src_id, entry->src_data[0], task_info.process_name,
1457                         task_info.tgid, task_info.task_name, task_info.pid);
1458                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1459                         addr);
1460                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1461                         status);
1462                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1463                                          entry->pasid);
1464         }
1465
1466         return 0;
1467 }
1468
1469 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1470                                                      bool enable)
1471 {
1472         uint32_t data;
1473
1474         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1475                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1476                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1477                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1478
1479                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1480                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1481                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1482
1483                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1484                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1485                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1486
1487                 data = RREG32(mmMC_XPB_CLK_GAT);
1488                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1489                 WREG32(mmMC_XPB_CLK_GAT, data);
1490
1491                 data = RREG32(mmATC_MISC_CG);
1492                 data |= ATC_MISC_CG__ENABLE_MASK;
1493                 WREG32(mmATC_MISC_CG, data);
1494
1495                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1496                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1497                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1498
1499                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1500                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1501                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1502
1503                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1504                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1505                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1506
1507                 data = RREG32(mmVM_L2_CG);
1508                 data |= VM_L2_CG__ENABLE_MASK;
1509                 WREG32(mmVM_L2_CG, data);
1510         } else {
1511                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1512                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1513                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1514
1515                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1516                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1517                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1518
1519                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1520                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1521                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1522
1523                 data = RREG32(mmMC_XPB_CLK_GAT);
1524                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1525                 WREG32(mmMC_XPB_CLK_GAT, data);
1526
1527                 data = RREG32(mmATC_MISC_CG);
1528                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1529                 WREG32(mmATC_MISC_CG, data);
1530
1531                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1532                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1533                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1534
1535                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1536                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1537                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1538
1539                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1540                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1541                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1542
1543                 data = RREG32(mmVM_L2_CG);
1544                 data &= ~VM_L2_CG__ENABLE_MASK;
1545                 WREG32(mmVM_L2_CG, data);
1546         }
1547 }
1548
1549 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1550                                        bool enable)
1551 {
1552         uint32_t data;
1553
1554         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1555                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1556                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1557                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1558
1559                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1560                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1561                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1562
1563                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1564                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1565                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1566
1567                 data = RREG32(mmMC_XPB_CLK_GAT);
1568                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1569                 WREG32(mmMC_XPB_CLK_GAT, data);
1570
1571                 data = RREG32(mmATC_MISC_CG);
1572                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1573                 WREG32(mmATC_MISC_CG, data);
1574
1575                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1576                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1577                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1578
1579                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1580                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1581                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1582
1583                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1584                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1585                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1586
1587                 data = RREG32(mmVM_L2_CG);
1588                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1589                 WREG32(mmVM_L2_CG, data);
1590         } else {
1591                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1592                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1593                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1594
1595                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1596                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1597                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1598
1599                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1600                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1601                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1602
1603                 data = RREG32(mmMC_XPB_CLK_GAT);
1604                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1605                 WREG32(mmMC_XPB_CLK_GAT, data);
1606
1607                 data = RREG32(mmATC_MISC_CG);
1608                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1609                 WREG32(mmATC_MISC_CG, data);
1610
1611                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1612                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1613                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1614
1615                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1616                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1617                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1618
1619                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1620                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1621                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1622
1623                 data = RREG32(mmVM_L2_CG);
1624                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1625                 WREG32(mmVM_L2_CG, data);
1626         }
1627 }
1628
1629 static int gmc_v8_0_set_clockgating_state(void *handle,
1630                                           enum amd_clockgating_state state)
1631 {
1632         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1633
1634         if (amdgpu_sriov_vf(adev))
1635                 return 0;
1636
1637         switch (adev->asic_type) {
1638         case CHIP_FIJI:
1639                 fiji_update_mc_medium_grain_clock_gating(adev,
1640                                 state == AMD_CG_STATE_GATE);
1641                 fiji_update_mc_light_sleep(adev,
1642                                 state == AMD_CG_STATE_GATE);
1643                 break;
1644         default:
1645                 break;
1646         }
1647         return 0;
1648 }
1649
1650 static int gmc_v8_0_set_powergating_state(void *handle,
1651                                           enum amd_powergating_state state)
1652 {
1653         return 0;
1654 }
1655
1656 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1657 {
1658         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1659         int data;
1660
1661         if (amdgpu_sriov_vf(adev))
1662                 *flags = 0;
1663
1664         /* AMD_CG_SUPPORT_MC_MGCG */
1665         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1666         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1667                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1668
1669         /* AMD_CG_SUPPORT_MC_LS */
1670         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1671                 *flags |= AMD_CG_SUPPORT_MC_LS;
1672 }
1673
1674 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1675         .name = "gmc_v8_0",
1676         .early_init = gmc_v8_0_early_init,
1677         .late_init = gmc_v8_0_late_init,
1678         .sw_init = gmc_v8_0_sw_init,
1679         .sw_fini = gmc_v8_0_sw_fini,
1680         .hw_init = gmc_v8_0_hw_init,
1681         .hw_fini = gmc_v8_0_hw_fini,
1682         .suspend = gmc_v8_0_suspend,
1683         .resume = gmc_v8_0_resume,
1684         .is_idle = gmc_v8_0_is_idle,
1685         .wait_for_idle = gmc_v8_0_wait_for_idle,
1686         .check_soft_reset = gmc_v8_0_check_soft_reset,
1687         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1688         .soft_reset = gmc_v8_0_soft_reset,
1689         .post_soft_reset = gmc_v8_0_post_soft_reset,
1690         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1691         .set_powergating_state = gmc_v8_0_set_powergating_state,
1692         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1693 };
1694
1695 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1696         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1697         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1698         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1699         .set_pte_pde = gmc_v8_0_set_pte_pde,
1700         .set_prt = gmc_v8_0_set_prt,
1701         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1702         .get_vm_pde = gmc_v8_0_get_vm_pde
1703 };
1704
1705 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1706         .set = gmc_v8_0_vm_fault_interrupt_state,
1707         .process = gmc_v8_0_process_interrupt,
1708 };
1709
1710 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1711 {
1712         if (adev->gmc.gmc_funcs == NULL)
1713                 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1714 }
1715
1716 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1717 {
1718         adev->gmc.vm_fault.num_types = 1;
1719         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1720 }
1721
1722 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1723 {
1724         .type = AMD_IP_BLOCK_TYPE_GMC,
1725         .major = 8,
1726         .minor = 0,
1727         .rev = 0,
1728         .funcs = &gmc_v8_0_ip_funcs,
1729 };
1730
1731 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1732 {
1733         .type = AMD_IP_BLOCK_TYPE_GMC,
1734         .major = 8,
1735         .minor = 1,
1736         .rev = 0,
1737         .funcs = &gmc_v8_0_ip_funcs,
1738 };
1739
1740 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1741 {
1742         .type = AMD_IP_BLOCK_TYPE_GMC,
1743         .major = 8,
1744         .minor = 5,
1745         .rev = 0,
1746         .funcs = &gmc_v8_0_ip_funcs,
1747 };