drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <[email protected]>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  44
  45 /* Firmware versions for VI */
  46 #define FW_1_65_10      ((1 << 24) | (65 << 16) | (10 << 8))
  47 #define FW_1_87_11      ((1 << 24) | (87 << 16) | (11 << 8))
  48 #define FW_1_87_12      ((1 << 24) | (87 << 16) | (12 << 8))
  49 #define FW_1_37_15      ((1 << 24) | (37 << 16) | (15 << 8))
  50
  51 /* Polaris10/11 firmware version */
  52 #define FW_1_66_16      ((1 << 24) | (66 << 16) | (16 << 8))
  53
  54 /* Firmware Names */
  55 #ifdef CONFIG_DRM_AMDGPU_CIK
  56 #define FIRMWARE_BONAIRE        "amdgpu/bonaire_uvd.bin"
  57 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
  58 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
  59 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
  60 #define FIRMWARE_MULLINS        "amdgpu/mullins_uvd.bin"
  61 #endif
  62 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  63 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  64 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
  65 #define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
  66 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_uvd.bin"
  67 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_uvd.bin"
  68 #define FIRMWARE_POLARIS12      "amdgpu/polaris12_uvd.bin"
  69 #define FIRMWARE_VEGAM          "amdgpu/vegam_uvd.bin"
  70
  71 #define FIRMWARE_VEGA10         "amdgpu/vega10_uvd.bin"
  72 #define FIRMWARE_VEGA12         "amdgpu/vega12_uvd.bin"
  73 #define FIRMWARE_VEGA20         "amdgpu/vega20_uvd.bin"
  74
  75 /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
  76 #define UVD_GPCOM_VCPU_CMD              0x03c3
  77 #define UVD_GPCOM_VCPU_DATA0    0x03c4
  78 #define UVD_GPCOM_VCPU_DATA1    0x03c5
  79 #define UVD_NO_OP                               0x03ff
  80 #define UVD_BASE_SI                             0x3800
  81
  82 /**
  83  * amdgpu_uvd_cs_ctx - Command submission parser context
  84  *
  85  * Used for emulating virtual memory support on UVD 4.2.
  86  */
  87 struct amdgpu_uvd_cs_ctx {
  88         struct amdgpu_cs_parser *parser;
  89         unsigned reg, count;
  90         unsigned data0, data1;
  91         unsigned idx;
  92         unsigned ib_idx;
  93
  94         /* does the IB has a msg command */
  95         bool has_msg_cmd;
  96
  97         /* minimum buffer sizes */
  98         unsigned *buf_sizes;
  99 };
 100
 101 #ifdef CONFIG_DRM_AMDGPU_CIK
 102 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
 103 MODULE_FIRMWARE(FIRMWARE_KABINI);
 104 MODULE_FIRMWARE(FIRMWARE_KAVERI);
 105 MODULE_FIRMWARE(FIRMWARE_HAWAII);
 106 MODULE_FIRMWARE(FIRMWARE_MULLINS);
 107 #endif
 108 MODULE_FIRMWARE(FIRMWARE_TONGA);
 109 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 110 MODULE_FIRMWARE(FIRMWARE_FIJI);
 111 MODULE_FIRMWARE(FIRMWARE_STONEY);
 112 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 113 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 114 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
 115 MODULE_FIRMWARE(FIRMWARE_VEGAM);
 116
 117 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 118 MODULE_FIRMWARE(FIRMWARE_VEGA12);
 119 MODULE_FIRMWARE(FIRMWARE_VEGA20);
 120
 121 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 122
 123 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 124 {
 125         struct amdgpu_ring *ring;
 126         struct drm_sched_rq *rq;
 127         unsigned long bo_size;
 128         const char *fw_name;
 129         const struct common_firmware_header *hdr;
 130         unsigned family_id;
 131         int i, j, r;
 132
 133         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 134
 135         switch (adev->asic_type) {
 136 #ifdef CONFIG_DRM_AMDGPU_CIK
 137         case CHIP_BONAIRE:
 138                 fw_name = FIRMWARE_BONAIRE;
 139                 break;
 140         case CHIP_KABINI:
 141                 fw_name = FIRMWARE_KABINI;
 142                 break;
 143         case CHIP_KAVERI:
 144                 fw_name = FIRMWARE_KAVERI;
 145                 break;
 146         case CHIP_HAWAII:
 147                 fw_name = FIRMWARE_HAWAII;
 148                 break;
 149         case CHIP_MULLINS:
 150                 fw_name = FIRMWARE_MULLINS;
 151                 break;
 152 #endif
 153         case CHIP_TONGA:
 154                 fw_name = FIRMWARE_TONGA;
 155                 break;
 156         case CHIP_FIJI:
 157                 fw_name = FIRMWARE_FIJI;
 158                 break;
 159         case CHIP_CARRIZO:
 160                 fw_name = FIRMWARE_CARRIZO;
 161                 break;
 162         case CHIP_STONEY:
 163                 fw_name = FIRMWARE_STONEY;
 164                 break;
 165         case CHIP_POLARIS10:
 166                 fw_name = FIRMWARE_POLARIS10;
 167                 break;
 168         case CHIP_POLARIS11:
 169                 fw_name = FIRMWARE_POLARIS11;
 170                 break;
 171         case CHIP_POLARIS12:
 172                 fw_name = FIRMWARE_POLARIS12;
 173                 break;
 174         case CHIP_VEGA10:
 175                 fw_name = FIRMWARE_VEGA10;
 176                 break;
 177         case CHIP_VEGA12:
 178                 fw_name = FIRMWARE_VEGA12;
 179                 break;
 180         case CHIP_VEGAM:
 181                 fw_name = FIRMWARE_VEGAM;
 182                 break;
 183         case CHIP_VEGA20:
 184                 fw_name = FIRMWARE_VEGA20;
 185                 break;
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 191         if (r) {
 192                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 193                         fw_name);
 194                 return r;
 195         }
 196
 197         r = amdgpu_ucode_validate(adev->uvd.fw);
 198         if (r) {
 199                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 200                         fw_name);
 201                 release_firmware(adev->uvd.fw);
 202                 adev->uvd.fw = NULL;
 203                 return r;
 204         }
 205
 206         /* Set the default UVD handles that the firmware can handle */
 207         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
 208
 209         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 210         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 211
 212         if (adev->asic_type < CHIP_VEGA20) {
 213                 unsigned version_major, version_minor;
 214
 215                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 216                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 217                 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 218                         version_major, version_minor, family_id);
 219
 220                 /*
 221                  * Limit the number of UVD handles depending on microcode major
 222                  * and minor versions. The firmware version which has 40 UVD
 223                  * instances support is 1.80. So all subsequent versions should
 224                  * also have the same support.
 225                  */
 226                 if ((version_major > 0x01) ||
 227                     ((version_major == 0x01) && (version_minor >= 0x50)))
 228                         adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 229
 230                 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 231                                         (family_id << 8));
 232
 233                 if ((adev->asic_type == CHIP_POLARIS10 ||
 234                      adev->asic_type == CHIP_POLARIS11) &&
 235                     (adev->uvd.fw_version < FW_1_66_16))
 236                         DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
 237                                   version_major, version_minor);
 238         } else {
 239                 unsigned int enc_major, enc_minor, dec_minor;
 240
 241                 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 242                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
 243                 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
 244                 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n",
 245                         enc_major, enc_minor, dec_minor, family_id);
 246
 247                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 248
 249                 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
 250         }
 251
 252         bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
 253                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
 254         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 255                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 256
 257         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 258
 259                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 260                                             AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
 261                                             &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
 262                 if (r) {
 263                         dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 264                         return r;
 265                 }
 266         }
 267
 268         ring = &adev->uvd.inst[0].ring;
 269         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 270         r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
 271         if (r) {
 272                 DRM_ERROR("Failed setting up UVD kernel entity.\n");
 273                 return r;
 274         }
 275         for (i = 0; i < adev->uvd.max_handles; ++i) {
 276                 atomic_set(&adev->uvd.handles[i], 0);
 277                 adev->uvd.filp[i] = NULL;
 278         }
 279
 280         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 281         if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 282                 adev->uvd.address_64_bit = true;
 283
 284         switch (adev->asic_type) {
 285         case CHIP_TONGA:
 286                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
 287                 break;
 288         case CHIP_CARRIZO:
 289                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
 290                 break;
 291         case CHIP_FIJI:
 292                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
 293                 break;
 294         case CHIP_STONEY:
 295                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
 296                 break;
 297         default:
 298                 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
 299         }
 300
 301         return 0;
 302 }
 303
 304 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 305 {
 306         int i, j;
 307
 308         drm_sched_entity_destroy(&adev->uvd.inst->ring.sched,
 309                                  &adev->uvd.entity);
 310
 311         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 312                 kfree(adev->uvd.inst[j].saved_bo);
 313
 314                 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
 315                                       &adev->uvd.inst[j].gpu_addr,
 316                                       (void **)&adev->uvd.inst[j].cpu_addr);
 317
 318                 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
 319
 320                 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
 321                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 322         }
 323         release_firmware(adev->uvd.fw);
 324
 325         return 0;
 326 }
 327
 328 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 329 {
 330         unsigned size;
 331         void *ptr;
 332         int i, j;
 333
 334         cancel_delayed_work_sync(&adev->uvd.idle_work);
 335
 336         /* only valid for physical mode */
 337         if (adev->asic_type < CHIP_POLARIS10) {
 338                 for (i = 0; i < adev->uvd.max_handles; ++i)
 339                         if (atomic_read(&adev->uvd.handles[i]))
 340                                 break;
 341
 342                 if (i == adev->uvd.max_handles)
 343                         return 0;
 344         }
 345
 346         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 347                 if (adev->uvd.inst[j].vcpu_bo == NULL)
 348                         continue;
 349
 350                 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
 351                 ptr = adev->uvd.inst[j].cpu_addr;
 352
 353                 adev->uvd.inst[j].saved_bo = kmalloc(size, GFP_KERNEL);
 354                 if (!adev->uvd.inst[j].saved_bo)
 355                         return -ENOMEM;
 356
 357                 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
 358         }
 359         return 0;
 360 }
 361
 362 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 363 {
 364         unsigned size;
 365         void *ptr;
 366         int i;
 367
 368         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 369                 if (adev->uvd.inst[i].vcpu_bo == NULL)
 370                         return -EINVAL;
 371
 372                 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
 373                 ptr = adev->uvd.inst[i].cpu_addr;
 374
 375                 if (adev->uvd.inst[i].saved_bo != NULL) {
 376                         memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
 377                         kfree(adev->uvd.inst[i].saved_bo);
 378                         adev->uvd.inst[i].saved_bo = NULL;
 379                 } else {
 380                         const struct common_firmware_header *hdr;
 381                         unsigned offset;
 382
 383                         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 384                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 385                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 386                                 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
 387                                             le32_to_cpu(hdr->ucode_size_bytes));
 388                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 389                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 390                         }
 391                         memset_io(ptr, 0, size);
 392                         /* to restore uvd fence seq */
 393                         amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
 394                 }
 395         }
 396         return 0;
 397 }
 398
 399 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 400 {
 401         struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
 402         int i, r;
 403
 404         for (i = 0; i < adev->uvd.max_handles; ++i) {
 405                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 406
 407                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 408                         struct dma_fence *fence;
 409
 410                         r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
 411                                                        &fence);
 412                         if (r) {
 413                                 DRM_ERROR("Error destroying UVD %d!\n", r);
 414                                 continue;
 415                         }
 416
 417                         dma_fence_wait(fence, false);
 418                         dma_fence_put(fence);
 419
 420                         adev->uvd.filp[i] = NULL;
 421                         atomic_set(&adev->uvd.handles[i], 0);
 422                 }
 423         }
 424 }
 425
 426 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
 427 {
 428         int i;
 429         for (i = 0; i < abo->placement.num_placement; ++i) {
 430                 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 431                 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 432         }
 433 }
 434
 435 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
 436 {
 437         uint32_t lo, hi;
 438         uint64_t addr;
 439
 440         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 441         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 442         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 443
 444         return addr;
 445 }
 446
 447 /**
 448  * amdgpu_uvd_cs_pass1 - first parsing round
 449  *
 450  * @ctx: UVD parser context
 451  *
 452  * Make sure UVD message and feedback buffers are in VRAM and
 453  * nobody is violating an 256MB boundary.
 454  */
 455 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 456 {
 457         struct ttm_operation_ctx tctx = { false, false };
 458         struct amdgpu_bo_va_mapping *mapping;
 459         struct amdgpu_bo *bo;
 460         uint32_t cmd;
 461         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 462         int r = 0;
 463
 464         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 465         if (r) {
 466                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 467                 return r;
 468         }
 469
 470         if (!ctx->parser->adev->uvd.address_64_bit) {
 471                 /* check if it's a message or feedback command */
 472                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 473                 if (cmd == 0x0 || cmd == 0x3) {
 474                         /* yes, force it into VRAM */
 475                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 476                         amdgpu_ttm_placement_from_domain(bo, domain);
 477                 }
 478                 amdgpu_uvd_force_into_uvd_segment(bo);
 479
 480                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
 481         }
 482
 483         return r;
 484 }
 485
 486 /**
 487  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 488  *
 489  * @msg: pointer to message structure
 490  * @buf_sizes: returned buffer sizes
 491  *
 492  * Peek into the decode message and calculate the necessary buffer sizes.
 493  */
 494 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
 495         unsigned buf_sizes[])
 496 {
 497         unsigned stream_type = msg[4];
 498         unsigned width = msg[6];
 499         unsigned height = msg[7];
 500         unsigned dpb_size = msg[9];
 501         unsigned pitch = msg[28];
 502         unsigned level = msg[57];
 503
 504         unsigned width_in_mb = width / 16;
 505         unsigned height_in_mb = ALIGN(height / 16, 2);
 506         unsigned fs_in_mb = width_in_mb * height_in_mb;
 507
 508         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 509         unsigned min_ctx_size = ~0;
 510
 511         image_size = width * height;
 512         image_size += image_size / 2;
 513         image_size = ALIGN(image_size, 1024);
 514
 515         switch (stream_type) {
 516         case 0: /* H264 */
 517                 switch(level) {
 518                 case 30:
 519                         num_dpb_buffer = 8100 / fs_in_mb;
 520                         break;
 521                 case 31:
 522                         num_dpb_buffer = 18000 / fs_in_mb;
 523                         break;
 524                 case 32:
 525                         num_dpb_buffer = 20480 / fs_in_mb;
 526                         break;
 527                 case 41:
 528                         num_dpb_buffer = 32768 / fs_in_mb;
 529                         break;
 530                 case 42:
 531                         num_dpb_buffer = 34816 / fs_in_mb;
 532                         break;
 533                 case 50:
 534                         num_dpb_buffer = 110400 / fs_in_mb;
 535                         break;
 536                 case 51:
 537                         num_dpb_buffer = 184320 / fs_in_mb;
 538                         break;
 539                 default:
 540                         num_dpb_buffer = 184320 / fs_in_mb;
 541                         break;
 542                 }
 543                 num_dpb_buffer++;
 544                 if (num_dpb_buffer > 17)
 545                         num_dpb_buffer = 17;
 546
 547                 /* reference picture buffer */
 548                 min_dpb_size = image_size * num_dpb_buffer;
 549
 550                 /* macroblock context buffer */
 551                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 552
 553                 /* IT surface buffer */
 554                 min_dpb_size += width_in_mb * height_in_mb * 32;
 555                 break;
 556
 557         case 1: /* VC1 */
 558
 559                 /* reference picture buffer */
 560                 min_dpb_size = image_size * 3;
 561
 562                 /* CONTEXT_BUFFER */
 563                 min_dpb_size += width_in_mb * height_in_mb * 128;
 564
 565                 /* IT surface buffer */
 566                 min_dpb_size += width_in_mb * 64;
 567
 568                 /* DB surface buffer */
 569                 min_dpb_size += width_in_mb * 128;
 570
 571                 /* BP */
 572                 tmp = max(width_in_mb, height_in_mb);
 573                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 574                 break;
 575
 576         case 3: /* MPEG2 */
 577
 578                 /* reference picture buffer */
 579                 min_dpb_size = image_size * 3;
 580                 break;
 581
 582         case 4: /* MPEG4 */
 583
 584                 /* reference picture buffer */
 585                 min_dpb_size = image_size * 3;
 586
 587                 /* CM */
 588                 min_dpb_size += width_in_mb * height_in_mb * 64;
 589
 590                 /* IT surface buffer */
 591                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 592                 break;
 593
 594         case 7: /* H264 Perf */
 595                 switch(level) {
 596                 case 30:
 597                         num_dpb_buffer = 8100 / fs_in_mb;
 598                         break;
 599                 case 31:
 600                         num_dpb_buffer = 18000 / fs_in_mb;
 601                         break;
 602                 case 32:
 603                         num_dpb_buffer = 20480 / fs_in_mb;
 604                         break;
 605                 case 41:
 606                         num_dpb_buffer = 32768 / fs_in_mb;
 607                         break;
 608                 case 42:
 609                         num_dpb_buffer = 34816 / fs_in_mb;
 610                         break;
 611                 case 50:
 612                         num_dpb_buffer = 110400 / fs_in_mb;
 613                         break;
 614                 case 51:
 615                         num_dpb_buffer = 184320 / fs_in_mb;
 616                         break;
 617                 default:
 618                         num_dpb_buffer = 184320 / fs_in_mb;
 619                         break;
 620                 }
 621                 num_dpb_buffer++;
 622                 if (num_dpb_buffer > 17)
 623                         num_dpb_buffer = 17;
 624
 625                 /* reference picture buffer */
 626                 min_dpb_size = image_size * num_dpb_buffer;
 627
 628                 if (!adev->uvd.use_ctx_buf){
 629                         /* macroblock context buffer */
 630                         min_dpb_size +=
 631                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 632
 633                         /* IT surface buffer */
 634                         min_dpb_size += width_in_mb * height_in_mb * 32;
 635                 } else {
 636                         /* macroblock context buffer */
 637                         min_ctx_size =
 638                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 639                 }
 640                 break;
 641
 642         case 8: /* MJPEG */
 643                 min_dpb_size = 0;
 644                 break;
 645
 646         case 16: /* H265 */
 647                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 648                 image_size = ALIGN(image_size, 256);
 649
 650                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 651                 min_dpb_size = image_size * num_dpb_buffer;
 652                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 653                                            * 16 * num_dpb_buffer + 52 * 1024;
 654                 break;
 655
 656         default:
 657                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 658                 return -EINVAL;
 659         }
 660
 661         if (width > pitch) {
 662                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 663                 return -EINVAL;
 664         }
 665
 666         if (dpb_size < min_dpb_size) {
 667                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 668                           dpb_size, min_dpb_size);
 669                 return -EINVAL;
 670         }
 671
 672         buf_sizes[0x1] = dpb_size;
 673         buf_sizes[0x2] = image_size;
 674         buf_sizes[0x4] = min_ctx_size;
 675         return 0;
 676 }
 677
 678 /**
 679  * amdgpu_uvd_cs_msg - handle UVD message
 680  *
 681  * @ctx: UVD parser context
 682  * @bo: buffer object containing the message
 683  * @offset: offset into the buffer object
 684  *
 685  * Peek into the UVD message and extract the session id.
 686  * Make sure that we don't open up to many sessions.
 687  */
 688 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 689                              struct amdgpu_bo *bo, unsigned offset)
 690 {
 691         struct amdgpu_device *adev = ctx->parser->adev;
 692         int32_t *msg, msg_type, handle;
 693         void *ptr;
 694         long r;
 695         int i;
 696
 697         if (offset & 0x3F) {
 698                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 699                 return -EINVAL;
 700         }
 701
 702         r = amdgpu_bo_kmap(bo, &ptr);
 703         if (r) {
 704                 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
 705                 return r;
 706         }
 707
 708         msg = ptr + offset;
 709
 710         msg_type = msg[1];
 711         handle = msg[2];
 712
 713         if (handle == 0) {
 714                 DRM_ERROR("Invalid UVD handle!\n");
 715                 return -EINVAL;
 716         }
 717
 718         switch (msg_type) {
 719         case 0:
 720                 /* it's a create msg, calc image size (width * height) */
 721                 amdgpu_bo_kunmap(bo);
 722
 723                 /* try to alloc a new handle */
 724                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 725                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 726                                 DRM_ERROR(")Handle 0x%x already in use!\n",
 727                                           handle);
 728                                 return -EINVAL;
 729                         }
 730
 731                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 732                                 adev->uvd.filp[i] = ctx->parser->filp;
 733                                 return 0;
 734                         }
 735                 }
 736
 737                 DRM_ERROR("No more free UVD handles!\n");
 738                 return -ENOSPC;
 739
 740         case 1:
 741                 /* it's a decode msg, calc buffer sizes */
 742                 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
 743                 amdgpu_bo_kunmap(bo);
 744                 if (r)
 745                         return r;
 746
 747                 /* validate the handle */
 748                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 749                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 750                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 751                                         DRM_ERROR("UVD handle collision detected!\n");
 752                                         return -EINVAL;
 753                                 }
 754                                 return 0;
 755                         }
 756                 }
 757
 758                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 759                 return -ENOENT;
 760
 761         case 2:
 762                 /* it's a destroy msg, free the handle */
 763                 for (i = 0; i < adev->uvd.max_handles; ++i)
 764                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 765                 amdgpu_bo_kunmap(bo);
 766                 return 0;
 767
 768         default:
 769                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 770                 return -EINVAL;
 771         }
 772         BUG();
 773         return -EINVAL;
 774 }
 775
 776 /**
 777  * amdgpu_uvd_cs_pass2 - second parsing round
 778  *
 779  * @ctx: UVD parser context
 780  *
 781  * Patch buffer addresses, make sure buffer sizes are correct.
 782  */
 783 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 784 {
 785         struct amdgpu_bo_va_mapping *mapping;
 786         struct amdgpu_bo *bo;
 787         uint32_t cmd;
 788         uint64_t start, end;
 789         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 790         int r;
 791
 792         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 793         if (r) {
 794                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 795                 return r;
 796         }
 797
 798         start = amdgpu_bo_gpu_offset(bo);
 799
 800         end = (mapping->last + 1 - mapping->start);
 801         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 802
 803         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 804         start += addr;
 805
 806         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
 807                             lower_32_bits(start));
 808         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
 809                             upper_32_bits(start));
 810
 811         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 812         if (cmd < 0x4) {
 813                 if ((end - start) < ctx->buf_sizes[cmd]) {
 814                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 815                                   (unsigned)(end - start),
 816                                   ctx->buf_sizes[cmd]);
 817                         return -EINVAL;
 818                 }
 819
 820         } else if (cmd == 0x206) {
 821                 if ((end - start) < ctx->buf_sizes[4]) {
 822                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 823                                           (unsigned)(end - start),
 824                                           ctx->buf_sizes[4]);
 825                         return -EINVAL;
 826                 }
 827         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 828                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 829                 return -EINVAL;
 830         }
 831
 832         if (!ctx->parser->adev->uvd.address_64_bit) {
 833                 if ((start >> 28) != ((end - 1) >> 28)) {
 834                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 835                                   start, end);
 836                         return -EINVAL;
 837                 }
 838
 839                 if ((cmd == 0 || cmd == 0x3) &&
 840                     (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
 841                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 842                                   start, end);
 843                         return -EINVAL;
 844                 }
 845         }
 846
 847         if (cmd == 0) {
 848                 ctx->has_msg_cmd = true;
 849                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 850                 if (r)
 851                         return r;
 852         } else if (!ctx->has_msg_cmd) {
 853                 DRM_ERROR("Message needed before other commands are send!\n");
 854                 return -EINVAL;
 855         }
 856
 857         return 0;
 858 }
 859
 860 /**
 861  * amdgpu_uvd_cs_reg - parse register writes
 862  *
 863  * @ctx: UVD parser context
 864  * @cb: callback function
 865  *
 866  * Parse the register writes, call cb on each complete command.
 867  */
 868 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 869                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 870 {
 871         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 872         int i, r;
 873
 874         ctx->idx++;
 875         for (i = 0; i <= ctx->count; ++i) {
 876                 unsigned reg = ctx->reg + i;
 877
 878                 if (ctx->idx >= ib->length_dw) {
 879                         DRM_ERROR("Register command after end of CS!\n");
 880                         return -EINVAL;
 881                 }
 882
 883                 switch (reg) {
 884                 case mmUVD_GPCOM_VCPU_DATA0:
 885                         ctx->data0 = ctx->idx;
 886                         break;
 887                 case mmUVD_GPCOM_VCPU_DATA1:
 888                         ctx->data1 = ctx->idx;
 889                         break;
 890                 case mmUVD_GPCOM_VCPU_CMD:
 891                         r = cb(ctx);
 892                         if (r)
 893                                 return r;
 894                         break;
 895                 case mmUVD_ENGINE_CNTL:
 896                 case mmUVD_NO_OP:
 897                         break;
 898                 default:
 899                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 900                         return -EINVAL;
 901                 }
 902                 ctx->idx++;
 903         }
 904         return 0;
 905 }
 906
 907 /**
 908  * amdgpu_uvd_cs_packets - parse UVD packets
 909  *
 910  * @ctx: UVD parser context
 911  * @cb: callback function
 912  *
 913  * Parse the command stream packets.
 914  */
 915 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 916                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 917 {
 918         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 919         int r;
 920
 921         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 922                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 923                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 924                 switch (type) {
 925                 case PACKET_TYPE0:
 926                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 927                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 928                         r = amdgpu_uvd_cs_reg(ctx, cb);
 929                         if (r)
 930                                 return r;
 931                         break;
 932                 case PACKET_TYPE2:
 933                         ++ctx->idx;
 934                         break;
 935                 default:
 936                         DRM_ERROR("Unknown packet type %d !\n", type);
 937                         return -EINVAL;
 938                 }
 939         }
 940         return 0;
 941 }
 942
 943 /**
 944  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 945  *
 946  * @parser: Command submission parser context
 947  *
 948  * Parse the command stream, patch in addresses as necessary.
 949  */
 950 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 951 {
 952         struct amdgpu_uvd_cs_ctx ctx = {};
 953         unsigned buf_sizes[] = {
 954                 [0x00000000]    =       2048,
 955                 [0x00000001]    =       0xFFFFFFFF,
 956                 [0x00000002]    =       0xFFFFFFFF,
 957                 [0x00000003]    =       2048,
 958                 [0x00000004]    =       0xFFFFFFFF,
 959         };
 960         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
 961         int r;
 962
 963         parser->job->vm = NULL;
 964         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 965
 966         if (ib->length_dw % 16) {
 967                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 968                           ib->length_dw);
 969                 return -EINVAL;
 970         }
 971
 972         ctx.parser = parser;
 973         ctx.buf_sizes = buf_sizes;
 974         ctx.ib_idx = ib_idx;
 975
 976         /* first round only required on chips without UVD 64 bit address support */
 977         if (!parser->adev->uvd.address_64_bit) {
 978                 /* first round, make sure the buffers are actually in the UVD segment */
 979                 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 980                 if (r)
 981                         return r;
 982         }
 983
 984         /* second round, patch buffer addresses into the command stream */
 985         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 986         if (r)
 987                 return r;
 988
 989         if (!ctx.has_msg_cmd) {
 990                 DRM_ERROR("UVD-IBs need a msg command!\n");
 991                 return -EINVAL;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
 998                                bool direct, struct dma_fence **fence)
 999 {
1000         struct amdgpu_device *adev = ring->adev;
1001         struct dma_fence *f = NULL;
1002         struct amdgpu_job *job;
1003         struct amdgpu_ib *ib;
1004         uint32_t data[4];
1005         uint64_t addr;
1006         long r;
1007         int i;
1008         unsigned offset_idx = 0;
1009         unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1010
1011         amdgpu_bo_kunmap(bo);
1012         amdgpu_bo_unpin(bo);
1013
1014         if (!ring->adev->uvd.address_64_bit) {
1015                 struct ttm_operation_ctx ctx = { true, false };
1016
1017                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1018                 amdgpu_uvd_force_into_uvd_segment(bo);
1019                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1020                 if (r)
1021                         goto err;
1022         }
1023
1024         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1025         if (r)
1026                 goto err;
1027
1028         if (adev->asic_type >= CHIP_VEGA10) {
1029                 offset_idx = 1 + ring->me;
1030                 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1031                 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1032         }
1033
1034         data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1035         data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1036         data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1037         data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1038
1039         ib = &job->ibs[0];
1040         addr = amdgpu_bo_gpu_offset(bo);
1041         ib->ptr[0] = data[0];
1042         ib->ptr[1] = addr;
1043         ib->ptr[2] = data[1];
1044         ib->ptr[3] = addr >> 32;
1045         ib->ptr[4] = data[2];
1046         ib->ptr[5] = 0;
1047         for (i = 6; i < 16; i += 2) {
1048                 ib->ptr[i] = data[3];
1049                 ib->ptr[i+1] = 0;
1050         }
1051         ib->length_dw = 16;
1052
1053         if (direct) {
1054                 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1055                                                         true, false,
1056                                                         msecs_to_jiffies(10));
1057                 if (r == 0)
1058                         r = -ETIMEDOUT;
1059                 if (r < 0)
1060                         goto err_free;
1061
1062                 r = amdgpu_job_submit_direct(job, ring, &f);
1063                 if (r)
1064                         goto err_free;
1065         } else {
1066                 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1067                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1068                 if (r)
1069                         goto err_free;
1070
1071                 r = amdgpu_job_submit(job, &adev->uvd.entity,
1072                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1073                 if (r)
1074                         goto err_free;
1075         }
1076
1077         amdgpu_bo_fence(bo, f, false);
1078         amdgpu_bo_unreserve(bo);
1079         amdgpu_bo_unref(&bo);
1080
1081         if (fence)
1082                 *fence = dma_fence_get(f);
1083         dma_fence_put(f);
1084
1085         return 0;
1086
1087 err_free:
1088         amdgpu_job_free(job);
1089
1090 err:
1091         amdgpu_bo_unreserve(bo);
1092         amdgpu_bo_unref(&bo);
1093         return r;
1094 }
1095
1096 /* multiple fence commands without any stream commands in between can
1097    crash the vcpu so just try to emmit a dummy create/destroy msg to
1098    avoid this */
1099 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1100                               struct dma_fence **fence)
1101 {
1102         struct amdgpu_device *adev = ring->adev;
1103         struct amdgpu_bo *bo = NULL;
1104         uint32_t *msg;
1105         int r, i;
1106
1107         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1108                                       AMDGPU_GEM_DOMAIN_VRAM,
1109                                       &bo, NULL, (void **)&msg);
1110         if (r)
1111                 return r;
1112
1113         /* stitch together an UVD create msg */
1114         msg[0] = cpu_to_le32(0x00000de4);
1115         msg[1] = cpu_to_le32(0x00000000);
1116         msg[2] = cpu_to_le32(handle);
1117         msg[3] = cpu_to_le32(0x00000000);
1118         msg[4] = cpu_to_le32(0x00000000);
1119         msg[5] = cpu_to_le32(0x00000000);
1120         msg[6] = cpu_to_le32(0x00000000);
1121         msg[7] = cpu_to_le32(0x00000780);
1122         msg[8] = cpu_to_le32(0x00000440);
1123         msg[9] = cpu_to_le32(0x00000000);
1124         msg[10] = cpu_to_le32(0x01b37000);
1125         for (i = 11; i < 1024; ++i)
1126                 msg[i] = cpu_to_le32(0x0);
1127
1128         return amdgpu_uvd_send_msg(ring, bo, true, fence);
1129 }
1130
1131 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1132                                bool direct, struct dma_fence **fence)
1133 {
1134         struct amdgpu_device *adev = ring->adev;
1135         struct amdgpu_bo *bo = NULL;
1136         uint32_t *msg;
1137         int r, i;
1138
1139         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1140                                       AMDGPU_GEM_DOMAIN_VRAM,
1141                                       &bo, NULL, (void **)&msg);
1142         if (r)
1143                 return r;
1144
1145         /* stitch together an UVD destroy msg */
1146         msg[0] = cpu_to_le32(0x00000de4);
1147         msg[1] = cpu_to_le32(0x00000002);
1148         msg[2] = cpu_to_le32(handle);
1149         msg[3] = cpu_to_le32(0x00000000);
1150         for (i = 4; i < 1024; ++i)
1151                 msg[i] = cpu_to_le32(0x0);
1152
1153         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1154 }
1155
1156 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1157 {
1158         struct amdgpu_device *adev =
1159                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1160         unsigned fences = 0, i, j;
1161
1162         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1163                 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1164                 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1165                         fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1166                 }
1167         }
1168
1169         if (fences == 0) {
1170                 if (adev->pm.dpm_enabled) {
1171                         amdgpu_dpm_enable_uvd(adev, false);
1172                 } else {
1173                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1174                         /* shutdown the UVD block */
1175                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1176                                                                AMD_PG_STATE_GATE);
1177                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1178                                                                AMD_CG_STATE_GATE);
1179                 }
1180         } else {
1181                 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1182         }
1183 }
1184
1185 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1186 {
1187         struct amdgpu_device *adev = ring->adev;
1188         bool set_clocks;
1189
1190         if (amdgpu_sriov_vf(adev))
1191                 return;
1192
1193         set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1194         if (set_clocks) {
1195                 if (adev->pm.dpm_enabled) {
1196                         amdgpu_dpm_enable_uvd(adev, true);
1197                 } else {
1198                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1199                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1200                                                                AMD_CG_STATE_UNGATE);
1201                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1202                                                                AMD_PG_STATE_UNGATE);
1203                 }
1204         }
1205 }
1206
1207 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1208 {
1209         if (!amdgpu_sriov_vf(ring->adev))
1210                 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1211 }
1212
1213 /**
1214  * amdgpu_uvd_ring_test_ib - test ib execution
1215  *
1216  * @ring: amdgpu_ring pointer
1217  *
1218  * Test if we can successfully execute an IB
1219  */
1220 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1221 {
1222         struct dma_fence *fence;
1223         long r;
1224         uint32_t ip_instance = ring->me;
1225
1226         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1227         if (r) {
1228                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ip_instance, r);
1229                 goto error;
1230         }
1231
1232         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1233         if (r) {
1234                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ip_instance, r);
1235                 goto error;
1236         }
1237
1238         r = dma_fence_wait_timeout(fence, false, timeout);
1239         if (r == 0) {
1240                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ip_instance);
1241                 r = -ETIMEDOUT;
1242         } else if (r < 0) {
1243                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ip_instance, r);
1244         } else {
1245                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ip_instance, ring->idx);
1246                 r = 0;
1247         }
1248
1249         dma_fence_put(fence);
1250
1251 error:
1252         return r;
1253 }
1254
1255 /**
1256  * amdgpu_uvd_used_handles - returns used UVD handles
1257  *
1258  * @adev: amdgpu_device pointer
1259  *
1260  * Returns the number of UVD handles in use
1261  */
1262 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1263 {
1264         unsigned i;
1265         uint32_t used_handles = 0;
1266
1267         for (i = 0; i < adev->uvd.max_handles; ++i) {
1268                 /*
1269                  * Handles can be freed in any order, and not
1270                  * necessarily linear. So we need to count
1271                  * all non-zero handles.
1272                  */
1273                 if (atomic_read(&adev->uvd.handles[i]))
1274                         used_handles++;
1275         }
1276
1277         return used_handles;
1278 }