drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <[email protected]>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <linux/clk.h>
  38 #include <linux/component.h>
  39 #include <linux/i2c.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_gpio.h>
  42 #include <linux/of_platform.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/rational.h>
  45 #include <sound/dmaengine_pcm.h>
  46 #include <sound/pcm_drm_eld.h>
  47 #include <sound/pcm_params.h>
  48 #include <sound/soc.h>
  49 #include "media/cec.h"
  50 #include "vc4_drv.h"
  51 #include "vc4_regs.h"
  52
  53 #define HSM_CLOCK_FREQ 163682864
  54 #define CEC_CLOCK_FREQ 40000
  55 #define CEC_CLOCK_DIV  (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
  56
  57 /* HDMI audio information */
  58 struct vc4_hdmi_audio {
  59         struct snd_soc_card card;
  60         struct snd_soc_dai_link link;
  61         struct snd_soc_dai_link_component cpu;
  62         struct snd_soc_dai_link_component codec;
  63         struct snd_soc_dai_link_component platform;
  64         int samplerate;
  65         int channels;
  66         struct snd_dmaengine_dai_dma_data dma_data;
  67         struct snd_pcm_substream *substream;
  68 };
  69
  70 /* General HDMI hardware state. */
  71 struct vc4_hdmi {
  72         struct platform_device *pdev;
  73
  74         struct drm_encoder *encoder;
  75         struct drm_connector *connector;
  76
  77         struct vc4_hdmi_audio audio;
  78
  79         struct i2c_adapter *ddc;
  80         void __iomem *hdmicore_regs;
  81         void __iomem *hd_regs;
  82         int hpd_gpio;
  83         bool hpd_active_low;
  84
  85         struct cec_adapter *cec_adap;
  86         struct cec_msg cec_rx_msg;
  87         bool cec_tx_ok;
  88         bool cec_irq_was_rx;
  89
  90         struct clk *pixel_clock;
  91         struct clk *hsm_clock;
  92
  93         struct debugfs_regset32 hdmi_regset;
  94         struct debugfs_regset32 hd_regset;
  95 };
  96
  97 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
  98 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
  99 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
 100 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
 101
 102 /* VC4 HDMI encoder KMS struct */
 103 struct vc4_hdmi_encoder {
 104         struct vc4_encoder base;
 105         bool hdmi_monitor;
 106         bool limited_rgb_range;
 107 };
 108
 109 static inline struct vc4_hdmi_encoder *
 110 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
 111 {
 112         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
 113 }
 114
 115 /* VC4 HDMI connector KMS struct */
 116 struct vc4_hdmi_connector {
 117         struct drm_connector base;
 118
 119         /* Since the connector is attached to just the one encoder,
 120          * this is the reference to it so we can do the best_encoder()
 121          * hook.
 122          */
 123         struct drm_encoder *encoder;
 124 };
 125
 126 static inline struct vc4_hdmi_connector *
 127 to_vc4_hdmi_connector(struct drm_connector *connector)
 128 {
 129         return container_of(connector, struct vc4_hdmi_connector, base);
 130 }
 131
 132 static const struct debugfs_reg32 hdmi_regs[] = {
 133         VC4_REG32(VC4_HDMI_CORE_REV),
 134         VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
 135         VC4_REG32(VC4_HDMI_HOTPLUG_INT),
 136         VC4_REG32(VC4_HDMI_HOTPLUG),
 137         VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP),
 138         VC4_REG32(VC4_HDMI_MAI_CONFIG),
 139         VC4_REG32(VC4_HDMI_MAI_FORMAT),
 140         VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG),
 141         VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG),
 142         VC4_REG32(VC4_HDMI_HORZA),
 143         VC4_REG32(VC4_HDMI_HORZB),
 144         VC4_REG32(VC4_HDMI_FIFO_CTL),
 145         VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL),
 146         VC4_REG32(VC4_HDMI_VERTA0),
 147         VC4_REG32(VC4_HDMI_VERTA1),
 148         VC4_REG32(VC4_HDMI_VERTB0),
 149         VC4_REG32(VC4_HDMI_VERTB1),
 150         VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL),
 151         VC4_REG32(VC4_HDMI_TX_PHY_CTL0),
 152
 153         VC4_REG32(VC4_HDMI_CEC_CNTRL_1),
 154         VC4_REG32(VC4_HDMI_CEC_CNTRL_2),
 155         VC4_REG32(VC4_HDMI_CEC_CNTRL_3),
 156         VC4_REG32(VC4_HDMI_CEC_CNTRL_4),
 157         VC4_REG32(VC4_HDMI_CEC_CNTRL_5),
 158         VC4_REG32(VC4_HDMI_CPU_STATUS),
 159         VC4_REG32(VC4_HDMI_CPU_MASK_STATUS),
 160
 161         VC4_REG32(VC4_HDMI_CEC_RX_DATA_1),
 162         VC4_REG32(VC4_HDMI_CEC_RX_DATA_2),
 163         VC4_REG32(VC4_HDMI_CEC_RX_DATA_3),
 164         VC4_REG32(VC4_HDMI_CEC_RX_DATA_4),
 165         VC4_REG32(VC4_HDMI_CEC_TX_DATA_1),
 166         VC4_REG32(VC4_HDMI_CEC_TX_DATA_2),
 167         VC4_REG32(VC4_HDMI_CEC_TX_DATA_3),
 168         VC4_REG32(VC4_HDMI_CEC_TX_DATA_4),
 169 };
 170
 171 static const struct debugfs_reg32 hd_regs[] = {
 172         VC4_REG32(VC4_HD_M_CTL),
 173         VC4_REG32(VC4_HD_MAI_CTL),
 174         VC4_REG32(VC4_HD_MAI_THR),
 175         VC4_REG32(VC4_HD_MAI_FMT),
 176         VC4_REG32(VC4_HD_MAI_SMP),
 177         VC4_REG32(VC4_HD_VID_CTL),
 178         VC4_REG32(VC4_HD_CSC_CTL),
 179         VC4_REG32(VC4_HD_FRAME_COUNT),
 180 };
 181
 182 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 183 {
 184         struct drm_info_node *node = (struct drm_info_node *)m->private;
 185         struct drm_device *dev = node->minor->dev;
 186         struct vc4_dev *vc4 = to_vc4_dev(dev);
 187         struct vc4_hdmi *hdmi = vc4->hdmi;
 188         struct drm_printer p = drm_seq_file_printer(m);
 189
 190         drm_print_regset32(&p, &hdmi->hdmi_regset);
 191         drm_print_regset32(&p, &hdmi->hd_regset);
 192
 193         return 0;
 194 }
 195
 196 static enum drm_connector_status
 197 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 198 {
 199         struct drm_device *dev = connector->dev;
 200         struct vc4_dev *vc4 = to_vc4_dev(dev);
 201
 202         if (vc4->hdmi->hpd_gpio) {
 203                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 204                     vc4->hdmi->hpd_active_low)
 205                         return connector_status_connected;
 206                 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 207                 return connector_status_disconnected;
 208         }
 209
 210         if (drm_probe_ddc(vc4->hdmi->ddc))
 211                 return connector_status_connected;
 212
 213         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 214                 return connector_status_connected;
 215         cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 216         return connector_status_disconnected;
 217 }
 218
 219 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 220 {
 221         drm_connector_unregister(connector);
 222         drm_connector_cleanup(connector);
 223 }
 224
 225 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 226 {
 227         struct vc4_hdmi_connector *vc4_connector =
 228                 to_vc4_hdmi_connector(connector);
 229         struct drm_encoder *encoder = vc4_connector->encoder;
 230         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 231         struct drm_device *dev = connector->dev;
 232         struct vc4_dev *vc4 = to_vc4_dev(dev);
 233         int ret = 0;
 234         struct edid *edid;
 235
 236         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 237         cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
 238         if (!edid)
 239                 return -ENODEV;
 240
 241         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 242
 243         drm_connector_update_edid_property(connector, edid);
 244         ret = drm_add_edid_modes(connector, edid);
 245         kfree(edid);
 246
 247         return ret;
 248 }
 249
 250 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 251 {
 252         drm_atomic_helper_connector_reset(connector);
 253         drm_atomic_helper_connector_tv_reset(connector);
 254 }
 255
 256 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 257         .detect = vc4_hdmi_connector_detect,
 258         .fill_modes = drm_helper_probe_single_connector_modes,
 259         .destroy = vc4_hdmi_connector_destroy,
 260         .reset = vc4_hdmi_connector_reset,
 261         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 262         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 263 };
 264
 265 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 266         .get_modes = vc4_hdmi_connector_get_modes,
 267 };
 268
 269 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 270                                                      struct drm_encoder *encoder)
 271 {
 272         struct drm_connector *connector;
 273         struct vc4_hdmi_connector *hdmi_connector;
 274         int ret;
 275
 276         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 277                                       GFP_KERNEL);
 278         if (!hdmi_connector)
 279                 return ERR_PTR(-ENOMEM);
 280         connector = &hdmi_connector->base;
 281
 282         hdmi_connector->encoder = encoder;
 283
 284         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 285                            DRM_MODE_CONNECTOR_HDMIA);
 286         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 287
 288         /* Create and attach TV margin props to this connector. */
 289         ret = drm_mode_create_tv_margin_properties(dev);
 290         if (ret)
 291                 return ERR_PTR(ret);
 292
 293         drm_connector_attach_tv_margin_properties(connector);
 294
 295         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 296                              DRM_CONNECTOR_POLL_DISCONNECT);
 297
 298         connector->interlace_allowed = 1;
 299         connector->doublescan_allowed = 0;
 300
 301         drm_connector_attach_encoder(connector, encoder);
 302
 303         return connector;
 304 }
 305
 306 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 307 {
 308         drm_encoder_cleanup(encoder);
 309 }
 310
 311 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 312         .destroy = vc4_hdmi_encoder_destroy,
 313 };
 314
 315 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 316                                 enum hdmi_infoframe_type type)
 317 {
 318         struct drm_device *dev = encoder->dev;
 319         struct vc4_dev *vc4 = to_vc4_dev(dev);
 320         u32 packet_id = type - 0x80;
 321
 322         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 323                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 324
 325         return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 326                           BIT(packet_id)), 100);
 327 }
 328
 329 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 330                                      union hdmi_infoframe *frame)
 331 {
 332         struct drm_device *dev = encoder->dev;
 333         struct vc4_dev *vc4 = to_vc4_dev(dev);
 334         u32 packet_id = frame->any.type - 0x80;
 335         u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
 336         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 337         ssize_t len, i;
 338         int ret;
 339
 340         WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 341                     VC4_HDMI_RAM_PACKET_ENABLE),
 342                   "Packet RAM has to be on to store the packet.");
 343
 344         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 345         if (len < 0)
 346                 return;
 347
 348         ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
 349         if (ret) {
 350                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 351                 return;
 352         }
 353
 354         for (i = 0; i < len; i += 7) {
 355                 HDMI_WRITE(packet_reg,
 356                            buffer[i + 0] << 0 |
 357                            buffer[i + 1] << 8 |
 358                            buffer[i + 2] << 16);
 359                 packet_reg += 4;
 360
 361                 HDMI_WRITE(packet_reg,
 362                            buffer[i + 3] << 0 |
 363                            buffer[i + 4] << 8 |
 364                            buffer[i + 5] << 16 |
 365                            buffer[i + 6] << 24);
 366                 packet_reg += 4;
 367         }
 368
 369         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 370                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 371         ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 372                         BIT(packet_id)), 100);
 373         if (ret)
 374                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 375 }
 376
 377 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 378 {
 379         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 380         struct vc4_dev *vc4 = encoder->dev->dev_private;
 381         struct vc4_hdmi *hdmi = vc4->hdmi;
 382         struct drm_connector_state *cstate = hdmi->connector->state;
 383         struct drm_crtc *crtc = encoder->crtc;
 384         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 385         union hdmi_infoframe frame;
 386         int ret;
 387
 388         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 389                                                        hdmi->connector, mode);
 390         if (ret < 0) {
 391                 DRM_ERROR("couldn't fill AVI infoframe\n");
 392                 return;
 393         }
 394
 395         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 396                                            hdmi->connector, mode,
 397                                            vc4_encoder->limited_rgb_range ?
 398                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 399                                            HDMI_QUANTIZATION_RANGE_FULL);
 400
 401         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 402
 403         vc4_hdmi_write_infoframe(encoder, &frame);
 404 }
 405
 406 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 407 {
 408         union hdmi_infoframe frame;
 409         int ret;
 410
 411         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 412         if (ret < 0) {
 413                 DRM_ERROR("couldn't fill SPD infoframe\n");
 414                 return;
 415         }
 416
 417         frame.spd.sdi = HDMI_SPD_SDI_PC;
 418
 419         vc4_hdmi_write_infoframe(encoder, &frame);
 420 }
 421
 422 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 423 {
 424         struct drm_device *drm = encoder->dev;
 425         struct vc4_dev *vc4 = drm->dev_private;
 426         struct vc4_hdmi *hdmi = vc4->hdmi;
 427         union hdmi_infoframe frame;
 428         int ret;
 429
 430         ret = hdmi_audio_infoframe_init(&frame.audio);
 431
 432         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 433         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 434         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 435         frame.audio.channels = hdmi->audio.channels;
 436
 437         vc4_hdmi_write_infoframe(encoder, &frame);
 438 }
 439
 440 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 441 {
 442         vc4_hdmi_set_avi_infoframe(encoder);
 443         vc4_hdmi_set_spd_infoframe(encoder);
 444 }
 445
 446 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 447 {
 448         struct drm_device *dev = encoder->dev;
 449         struct vc4_dev *vc4 = to_vc4_dev(dev);
 450         struct vc4_hdmi *hdmi = vc4->hdmi;
 451         int ret;
 452
 453         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
 454
 455         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 456         HD_WRITE(VC4_HD_VID_CTL,
 457                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 458
 459         clk_disable_unprepare(hdmi->pixel_clock);
 460
 461         ret = pm_runtime_put(&hdmi->pdev->dev);
 462         if (ret < 0)
 463                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 464 }
 465
 466 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 467 {
 468         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 469         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 470         struct drm_device *dev = encoder->dev;
 471         struct vc4_dev *vc4 = to_vc4_dev(dev);
 472         struct vc4_hdmi *hdmi = vc4->hdmi;
 473         bool debug_dump_regs = false;
 474         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 475         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 476         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 477         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 478         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 479                                    VC4_HDMI_VERTA_VSP) |
 480                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 481                                    VC4_HDMI_VERTA_VFP) |
 482                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 483         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 484                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 485                                    VC4_HDMI_VERTB_VBP));
 486         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 487                           VC4_SET_FIELD(mode->crtc_vtotal -
 488                                         mode->crtc_vsync_end -
 489                                         interlaced,
 490                                         VC4_HDMI_VERTB_VBP));
 491         u32 csc_ctl;
 492         int ret;
 493
 494         ret = pm_runtime_get_sync(&hdmi->pdev->dev);
 495         if (ret < 0) {
 496                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 497                 return;
 498         }
 499
 500         ret = clk_set_rate(hdmi->pixel_clock,
 501                            mode->clock * 1000 *
 502                            ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
 503         if (ret) {
 504                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 505                 return;
 506         }
 507
 508         ret = clk_prepare_enable(hdmi->pixel_clock);
 509         if (ret) {
 510                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 511                 return;
 512         }
 513
 514         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 515                    VC4_HDMI_SW_RESET_HDMI |
 516                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 517
 518         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 519
 520         /* PHY should be in reset, like
 521          * vc4_hdmi_encoder_disable() does.
 522          */
 523         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 524
 525         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 526
 527         if (debug_dump_regs) {
 528                 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
 529
 530                 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n");
 531                 drm_print_regset32(&p, &hdmi->hdmi_regset);
 532                 drm_print_regset32(&p, &hdmi->hd_regset);
 533         }
 534
 535         HD_WRITE(VC4_HD_VID_CTL, 0);
 536
 537         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 538                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 539                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 540                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 541
 542         HDMI_WRITE(VC4_HDMI_HORZA,
 543                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 544                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 545                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 546                                  VC4_HDMI_HORZA_HAP));
 547
 548         HDMI_WRITE(VC4_HDMI_HORZB,
 549                    VC4_SET_FIELD((mode->htotal -
 550                                   mode->hsync_end) * pixel_rep,
 551                                  VC4_HDMI_HORZB_HBP) |
 552                    VC4_SET_FIELD((mode->hsync_end -
 553                                   mode->hsync_start) * pixel_rep,
 554                                  VC4_HDMI_HORZB_HSP) |
 555                    VC4_SET_FIELD((mode->hsync_start -
 556                                   mode->hdisplay) * pixel_rep,
 557                                  VC4_HDMI_HORZB_HFP));
 558
 559         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 560         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 561
 562         HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
 563         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 564
 565         HD_WRITE(VC4_HD_VID_CTL,
 566                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 567                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 568
 569         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 570                                 VC4_HD_CSC_CTL_ORDER);
 571
 572         if (vc4_encoder->hdmi_monitor &&
 573             drm_default_rgb_quant_range(mode) ==
 574             HDMI_QUANTIZATION_RANGE_LIMITED) {
 575                 /* CEA VICs other than #1 requre limited range RGB
 576                  * output unless overridden by an AVI infoframe.
 577                  * Apply a colorspace conversion to squash 0-255 down
 578                  * to 16-235.  The matrix here is:
 579                  *
 580                  * [ 0      0      0.8594 16]
 581                  * [ 0      0.8594 0      16]
 582                  * [ 0.8594 0      0      16]
 583                  * [ 0      0      0       1]
 584                  */
 585                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 586                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 587                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 588                                          VC4_HD_CSC_CTL_MODE);
 589
 590                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 591                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 592                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 593                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 594                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 595                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 596                 vc4_encoder->limited_rgb_range = true;
 597         } else {
 598                 vc4_encoder->limited_rgb_range = false;
 599         }
 600
 601         /* The RGB order applies even when CSC is disabled. */
 602         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 603
 604         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 605
 606         if (debug_dump_regs) {
 607                 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
 608
 609                 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n");
 610                 drm_print_regset32(&p, &hdmi->hdmi_regset);
 611                 drm_print_regset32(&p, &hdmi->hd_regset);
 612         }
 613
 614         HD_WRITE(VC4_HD_VID_CTL,
 615                  HD_READ(VC4_HD_VID_CTL) |
 616                  VC4_HD_VID_CTL_ENABLE |
 617                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 618                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 619
 620         if (vc4_encoder->hdmi_monitor) {
 621                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 622                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 623                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 624
 625                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 626                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 627                 WARN_ONCE(ret, "Timeout waiting for "
 628                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 629         } else {
 630                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 631                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 632                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 633                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 634                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 635                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 636
 637                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 638                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 639                 WARN_ONCE(ret, "Timeout waiting for "
 640                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 641         }
 642
 643         if (vc4_encoder->hdmi_monitor) {
 644                 u32 drift;
 645
 646                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 647                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 648                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 649                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 650                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 651
 652                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 653                            VC4_HDMI_RAM_PACKET_ENABLE);
 654
 655                 vc4_hdmi_set_infoframes(encoder);
 656
 657                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 658                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 659
 660                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 661                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 662                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 663                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 664                 usleep_range(1000, 1100);
 665                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 666                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 667                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 668                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 669
 670                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 671                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 672                 WARN_ONCE(ret, "Timeout waiting for "
 673                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 674         }
 675 }
 676
 677 static enum drm_mode_status
 678 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
 679                             const struct drm_display_mode *mode)
 680 {
 681         /* HSM clock must be 108% of the pixel clock.  Additionally,
 682          * the AXI clock needs to be at least 25% of pixel clock, but
 683          * HSM ends up being the limiting factor.
 684          */
 685         if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
 686                 return MODE_CLOCK_HIGH;
 687
 688         return MODE_OK;
 689 }
 690
 691 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 692         .mode_valid = vc4_hdmi_encoder_mode_valid,
 693         .disable = vc4_hdmi_encoder_disable,
 694         .enable = vc4_hdmi_encoder_enable,
 695 };
 696
 697 /* HDMI audio codec callbacks */
 698 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
 699 {
 700         struct drm_device *drm = hdmi->encoder->dev;
 701         struct vc4_dev *vc4 = to_vc4_dev(drm);
 702         u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
 703         unsigned long n, m;
 704
 705         rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
 706                                     VC4_HD_MAI_SMP_N_MASK >>
 707                                     VC4_HD_MAI_SMP_N_SHIFT,
 708                                     (VC4_HD_MAI_SMP_M_MASK >>
 709                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 710                                     &n, &m);
 711
 712         HD_WRITE(VC4_HD_MAI_SMP,
 713                  VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 714                  VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 715 }
 716
 717 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
 718 {
 719         struct drm_encoder *encoder = hdmi->encoder;
 720         struct drm_crtc *crtc = encoder->crtc;
 721         struct drm_device *drm = encoder->dev;
 722         struct vc4_dev *vc4 = to_vc4_dev(drm);
 723         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 724         u32 samplerate = hdmi->audio.samplerate;
 725         u32 n, cts;
 726         u64 tmp;
 727
 728         n = 128 * samplerate / 1000;
 729         tmp = (u64)(mode->clock * 1000) * n;
 730         do_div(tmp, 128 * samplerate);
 731         cts = tmp;
 732
 733         HDMI_WRITE(VC4_HDMI_CRP_CFG,
 734                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 735                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 736
 737         /*
 738          * We could get slightly more accurate clocks in some cases by
 739          * providing a CTS_1 value.  The two CTS values are alternated
 740          * between based on the period fields
 741          */
 742         HDMI_WRITE(VC4_HDMI_CTS_0, cts);
 743         HDMI_WRITE(VC4_HDMI_CTS_1, cts);
 744 }
 745
 746 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 747 {
 748         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 749
 750         return snd_soc_card_get_drvdata(card);
 751 }
 752
 753 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 754                                   struct snd_soc_dai *dai)
 755 {
 756         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 757         struct drm_encoder *encoder = hdmi->encoder;
 758         struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
 759         int ret;
 760
 761         if (hdmi->audio.substream && hdmi->audio.substream != substream)
 762                 return -EINVAL;
 763
 764         hdmi->audio.substream = substream;
 765
 766         /*
 767          * If the HDMI encoder hasn't probed, or the encoder is
 768          * currently in DVI mode, treat the codec dai as missing.
 769          */
 770         if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 771                                 VC4_HDMI_RAM_PACKET_ENABLE))
 772                 return -ENODEV;
 773
 774         ret = snd_pcm_hw_constraint_eld(substream->runtime,
 775                                         hdmi->connector->eld);
 776         if (ret)
 777                 return ret;
 778
 779         return 0;
 780 }
 781
 782 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 783 {
 784         return 0;
 785 }
 786
 787 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
 788 {
 789         struct drm_encoder *encoder = hdmi->encoder;
 790         struct drm_device *drm = encoder->dev;
 791         struct device *dev = &hdmi->pdev->dev;
 792         struct vc4_dev *vc4 = to_vc4_dev(drm);
 793         int ret;
 794
 795         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
 796         if (ret)
 797                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
 798
 799         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
 800         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
 801         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
 802 }
 803
 804 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
 805                                     struct snd_soc_dai *dai)
 806 {
 807         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 808
 809         if (substream != hdmi->audio.substream)
 810                 return;
 811
 812         vc4_hdmi_audio_reset(hdmi);
 813
 814         hdmi->audio.substream = NULL;
 815 }
 816
 817 /* HDMI audio codec callbacks */
 818 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 819                                     struct snd_pcm_hw_params *params,
 820                                     struct snd_soc_dai *dai)
 821 {
 822         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 823         struct drm_encoder *encoder = hdmi->encoder;
 824         struct drm_device *drm = encoder->dev;
 825         struct device *dev = &hdmi->pdev->dev;
 826         struct vc4_dev *vc4 = to_vc4_dev(drm);
 827         u32 audio_packet_config, channel_mask;
 828         u32 channel_map, i;
 829
 830         if (substream != hdmi->audio.substream)
 831                 return -EINVAL;
 832
 833         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
 834                 params_rate(params), params_width(params),
 835                 params_channels(params));
 836
 837         hdmi->audio.channels = params_channels(params);
 838         hdmi->audio.samplerate = params_rate(params);
 839
 840         HD_WRITE(VC4_HD_MAI_CTL,
 841                  VC4_HD_MAI_CTL_RESET |
 842                  VC4_HD_MAI_CTL_FLUSH |
 843                  VC4_HD_MAI_CTL_DLATE |
 844                  VC4_HD_MAI_CTL_ERRORE |
 845                  VC4_HD_MAI_CTL_ERRORF);
 846
 847         vc4_hdmi_audio_set_mai_clock(hdmi);
 848
 849         audio_packet_config =
 850                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
 851                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
 852                 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
 853
 854         channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
 855         audio_packet_config |= VC4_SET_FIELD(channel_mask,
 856                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 857
 858         /* Set the MAI threshold.  This logic mimics the firmware's. */
 859         if (hdmi->audio.samplerate > 96000) {
 860                 HD_WRITE(VC4_HD_MAI_THR,
 861                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
 862                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 863         } else if (hdmi->audio.samplerate > 48000) {
 864                 HD_WRITE(VC4_HD_MAI_THR,
 865                          VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
 866                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 867         } else {
 868                 HD_WRITE(VC4_HD_MAI_THR,
 869                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
 870                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
 871                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
 872                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
 873         }
 874
 875         HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
 876                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
 877                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
 878
 879         channel_map = 0;
 880         for (i = 0; i < 8; i++) {
 881                 if (channel_mask & BIT(i))
 882                         channel_map |= i << (3 * i);
 883         }
 884
 885         HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
 886         HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
 887         vc4_hdmi_set_n_cts(hdmi);
 888
 889         return 0;
 890 }
 891
 892 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
 893                                   struct snd_soc_dai *dai)
 894 {
 895         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 896         struct drm_encoder *encoder = hdmi->encoder;
 897         struct drm_device *drm = encoder->dev;
 898         struct vc4_dev *vc4 = to_vc4_dev(drm);
 899
 900         switch (cmd) {
 901         case SNDRV_PCM_TRIGGER_START:
 902                 vc4_hdmi_set_audio_infoframe(encoder);
 903                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 904                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
 905                            ~VC4_HDMI_TX_PHY_RNG_PWRDN);
 906                 HD_WRITE(VC4_HD_MAI_CTL,
 907                          VC4_SET_FIELD(hdmi->audio.channels,
 908                                        VC4_HD_MAI_CTL_CHNUM) |
 909                          VC4_HD_MAI_CTL_ENABLE);
 910                 break;
 911         case SNDRV_PCM_TRIGGER_STOP:
 912                 HD_WRITE(VC4_HD_MAI_CTL,
 913                          VC4_HD_MAI_CTL_DLATE |
 914                          VC4_HD_MAI_CTL_ERRORE |
 915                          VC4_HD_MAI_CTL_ERRORF);
 916                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 917                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
 918                            VC4_HDMI_TX_PHY_RNG_PWRDN);
 919                 break;
 920         default:
 921                 break;
 922         }
 923
 924         return 0;
 925 }
 926
 927 static inline struct vc4_hdmi *
 928 snd_component_to_hdmi(struct snd_soc_component *component)
 929 {
 930         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
 931
 932         return snd_soc_card_get_drvdata(card);
 933 }
 934
 935 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
 936                                        struct snd_ctl_elem_info *uinfo)
 937 {
 938         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 939         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 940
 941         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 942         uinfo->count = sizeof(hdmi->connector->eld);
 943
 944         return 0;
 945 }
 946
 947 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
 948                                       struct snd_ctl_elem_value *ucontrol)
 949 {
 950         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 951         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 952
 953         memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
 954                sizeof(hdmi->connector->eld));
 955
 956         return 0;
 957 }
 958
 959 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
 960         {
 961                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
 962                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 963                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 964                 .name = "ELD",
 965                 .info = vc4_hdmi_audio_eld_ctl_info,
 966                 .get = vc4_hdmi_audio_eld_ctl_get,
 967         },
 968 };
 969
 970 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
 971         SND_SOC_DAPM_OUTPUT("TX"),
 972 };
 973
 974 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
 975         { "TX", NULL, "Playback" },
 976 };
 977
 978 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
 979         .controls               = vc4_hdmi_audio_controls,
 980         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
 981         .dapm_widgets           = vc4_hdmi_audio_widgets,
 982         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
 983         .dapm_routes            = vc4_hdmi_audio_routes,
 984         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
 985         .idle_bias_on           = 1,
 986         .use_pmdown_time        = 1,
 987         .endianness             = 1,
 988         .non_legacy_dai_naming  = 1,
 989 };
 990
 991 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
 992         .startup = vc4_hdmi_audio_startup,
 993         .shutdown = vc4_hdmi_audio_shutdown,
 994         .hw_params = vc4_hdmi_audio_hw_params,
 995         .set_fmt = vc4_hdmi_audio_set_fmt,
 996         .trigger = vc4_hdmi_audio_trigger,
 997 };
 998
 999 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1000         .name = "vc4-hdmi-hifi",
1001         .playback = {
1002                 .stream_name = "Playback",
1003                 .channels_min = 2,
1004                 .channels_max = 8,
1005                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1006                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1007                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1008                          SNDRV_PCM_RATE_192000,
1009                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1010         },
1011 };
1012
1013 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1014         .name = "vc4-hdmi-cpu-dai-component",
1015 };
1016
1017 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1018 {
1019         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1020
1021         snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1022
1023         return 0;
1024 }
1025
1026 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1027         .name = "vc4-hdmi-cpu-dai",
1028         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1029         .playback = {
1030                 .stream_name = "Playback",
1031                 .channels_min = 1,
1032                 .channels_max = 8,
1033                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1034                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1035                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1036                          SNDRV_PCM_RATE_192000,
1037                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1038         },
1039         .ops = &vc4_hdmi_audio_dai_ops,
1040 };
1041
1042 static const struct snd_dmaengine_pcm_config pcm_conf = {
1043         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1044         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1045 };
1046
1047 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1048 {
1049         struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1050         struct snd_soc_card *card = &hdmi->audio.card;
1051         struct device *dev = &hdmi->pdev->dev;
1052         const __be32 *addr;
1053         int ret;
1054
1055         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1056                 dev_warn(dev,
1057                          "'dmas' DT property is missing, no HDMI audio\n");
1058                 return 0;
1059         }
1060
1061         /*
1062          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1063          * the bus address specified in the DT, because the physical address
1064          * (the one returned by platform_get_resource()) is not appropriate
1065          * for DMA transfers.
1066          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1067          */
1068         addr = of_get_address(dev->of_node, 1, NULL, NULL);
1069         hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1070         hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1071         hdmi->audio.dma_data.maxburst = 2;
1072
1073         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1074         if (ret) {
1075                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1076                 return ret;
1077         }
1078
1079         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1080                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1081         if (ret) {
1082                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1083                 return ret;
1084         }
1085
1086         /* register component and codec dai */
1087         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1088                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1089         if (ret) {
1090                 dev_err(dev, "Could not register component: %d\n", ret);
1091                 return ret;
1092         }
1093
1094         dai_link->cpus          = &hdmi->audio.cpu;
1095         dai_link->codecs        = &hdmi->audio.codec;
1096         dai_link->platforms     = &hdmi->audio.platform;
1097
1098         dai_link->num_cpus      = 1;
1099         dai_link->num_codecs    = 1;
1100         dai_link->num_platforms = 1;
1101
1102         dai_link->name = "MAI";
1103         dai_link->stream_name = "MAI PCM";
1104         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1105         dai_link->cpus->dai_name = dev_name(dev);
1106         dai_link->codecs->name = dev_name(dev);
1107         dai_link->platforms->name = dev_name(dev);
1108
1109         card->dai_link = dai_link;
1110         card->num_links = 1;
1111         card->name = "vc4-hdmi";
1112         card->dev = dev;
1113
1114         /*
1115          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1116          * stores a pointer to the snd card object in dev->driver_data. This
1117          * means we cannot use it for something else. The hdmi back-pointer is
1118          * now stored in card->drvdata and should be retrieved with
1119          * snd_soc_card_get_drvdata() if needed.
1120          */
1121         snd_soc_card_set_drvdata(card, hdmi);
1122         ret = devm_snd_soc_register_card(dev, card);
1123         if (ret)
1124                 dev_err(dev, "Could not register sound card: %d\n", ret);
1125
1126         return ret;
1127
1128 }
1129
1130 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1131 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1132 {
1133         struct vc4_dev *vc4 = priv;
1134         struct vc4_hdmi *hdmi = vc4->hdmi;
1135
1136         if (hdmi->cec_irq_was_rx) {
1137                 if (hdmi->cec_rx_msg.len)
1138                         cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1139         } else if (hdmi->cec_tx_ok) {
1140                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1141                                   0, 0, 0, 0);
1142         } else {
1143                 /*
1144                  * This CEC implementation makes 1 retry, so if we
1145                  * get a NACK, then that means it made 2 attempts.
1146                  */
1147                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1148                                   0, 2, 0, 0);
1149         }
1150         return IRQ_HANDLED;
1151 }
1152
1153 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1154 {
1155         struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1156         unsigned int i;
1157
1158         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1159                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1160         for (i = 0; i < msg->len; i += 4) {
1161                 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1162
1163                 msg->msg[i] = val & 0xff;
1164                 msg->msg[i + 1] = (val >> 8) & 0xff;
1165                 msg->msg[i + 2] = (val >> 16) & 0xff;
1166                 msg->msg[i + 3] = (val >> 24) & 0xff;
1167         }
1168 }
1169
1170 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1171 {
1172         struct vc4_dev *vc4 = priv;
1173         struct vc4_hdmi *hdmi = vc4->hdmi;
1174         u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1175         u32 cntrl1, cntrl5;
1176
1177         if (!(stat & VC4_HDMI_CPU_CEC))
1178                 return IRQ_NONE;
1179         hdmi->cec_rx_msg.len = 0;
1180         cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1181         cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1182         hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1183         if (hdmi->cec_irq_was_rx) {
1184                 vc4_cec_read_msg(vc4, cntrl1);
1185                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1186                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1187                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1188         } else {
1189                 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1190                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1191         }
1192         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1193         HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1194
1195         return IRQ_WAKE_THREAD;
1196 }
1197
1198 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1199 {
1200         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1201         /* clock period in microseconds */
1202         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1203         u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1204
1205         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1206                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1207                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1208         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1209                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1210
1211         if (enable) {
1212                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1213                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1214                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1215                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1216                          ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1217                          ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1218                          ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1219                          ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1220                          ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1221                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1222                          ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1223                          ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1224                          ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1225                          ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1226                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1227                          ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1228                          ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1229                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1230                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1231
1232                 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1233         } else {
1234                 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1235                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1236                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1237         }
1238         return 0;
1239 }
1240
1241 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1242 {
1243         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1244
1245         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1246                    (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1247                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1248         return 0;
1249 }
1250
1251 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1252                                       u32 signal_free_time, struct cec_msg *msg)
1253 {
1254         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1255         u32 val;
1256         unsigned int i;
1257
1258         for (i = 0; i < msg->len; i += 4)
1259                 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1260                            (msg->msg[i]) |
1261                            (msg->msg[i + 1] << 8) |
1262                            (msg->msg[i + 2] << 16) |
1263                            (msg->msg[i + 3] << 24));
1264
1265         val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1266         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1267         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1268         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1269         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1270         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1271
1272         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1273         return 0;
1274 }
1275
1276 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1277         .adap_enable = vc4_hdmi_cec_adap_enable,
1278         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1279         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1280 };
1281 #endif
1282
1283 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1284 {
1285 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1286         struct cec_connector_info conn_info;
1287 #endif
1288         struct platform_device *pdev = to_platform_device(dev);
1289         struct drm_device *drm = dev_get_drvdata(master);
1290         struct vc4_dev *vc4 = drm->dev_private;
1291         struct vc4_hdmi *hdmi;
1292         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1293         struct device_node *ddc_node;
1294         u32 value;
1295         int ret;
1296
1297         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1298         if (!hdmi)
1299                 return -ENOMEM;
1300
1301         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1302                                         GFP_KERNEL);
1303         if (!vc4_hdmi_encoder)
1304                 return -ENOMEM;
1305         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1306         hdmi->encoder = &vc4_hdmi_encoder->base.base;
1307
1308         hdmi->pdev = pdev;
1309         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1310         if (IS_ERR(hdmi->hdmicore_regs))
1311                 return PTR_ERR(hdmi->hdmicore_regs);
1312
1313         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1314         if (IS_ERR(hdmi->hd_regs))
1315                 return PTR_ERR(hdmi->hd_regs);
1316
1317         hdmi->hdmi_regset.base = hdmi->hdmicore_regs;
1318         hdmi->hdmi_regset.regs = hdmi_regs;
1319         hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs);
1320         hdmi->hd_regset.base = hdmi->hd_regs;
1321         hdmi->hd_regset.regs = hd_regs;
1322         hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs);
1323
1324         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1325         if (IS_ERR(hdmi->pixel_clock)) {
1326                 DRM_ERROR("Failed to get pixel clock\n");
1327                 return PTR_ERR(hdmi->pixel_clock);
1328         }
1329         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1330         if (IS_ERR(hdmi->hsm_clock)) {
1331                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1332                 return PTR_ERR(hdmi->hsm_clock);
1333         }
1334
1335         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1336         if (!ddc_node) {
1337                 DRM_ERROR("Failed to find ddc node in device tree\n");
1338                 return -ENODEV;
1339         }
1340
1341         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1342         of_node_put(ddc_node);
1343         if (!hdmi->ddc) {
1344                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1345                 return -EPROBE_DEFER;
1346         }
1347
1348         /* This is the rate that is set by the firmware.  The number
1349          * needs to be a bit higher than the pixel clock rate
1350          * (generally 148.5Mhz).
1351          */
1352         ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1353         if (ret) {
1354                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1355                 goto err_put_i2c;
1356         }
1357
1358         ret = clk_prepare_enable(hdmi->hsm_clock);
1359         if (ret) {
1360                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1361                           ret);
1362                 goto err_put_i2c;
1363         }
1364
1365         /* Only use the GPIO HPD pin if present in the DT, otherwise
1366          * we'll use the HDMI core's register.
1367          */
1368         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1369                 enum of_gpio_flags hpd_gpio_flags;
1370
1371                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1372                                                          "hpd-gpios", 0,
1373                                                          &hpd_gpio_flags);
1374                 if (hdmi->hpd_gpio < 0) {
1375                         ret = hdmi->hpd_gpio;
1376                         goto err_unprepare_hsm;
1377                 }
1378
1379                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1380         }
1381
1382         vc4->hdmi = hdmi;
1383
1384         /* HDMI core must be enabled. */
1385         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1386                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1387                 udelay(1);
1388                 HD_WRITE(VC4_HD_M_CTL, 0);
1389
1390                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1391         }
1392         pm_runtime_enable(dev);
1393
1394         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1395                          DRM_MODE_ENCODER_TMDS, NULL);
1396         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1397
1398         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1399         if (IS_ERR(hdmi->connector)) {
1400                 ret = PTR_ERR(hdmi->connector);
1401                 goto err_destroy_encoder;
1402         }
1403 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1404         hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1405                                               vc4, "vc4",
1406                                               CEC_CAP_DEFAULTS |
1407                                               CEC_CAP_CONNECTOR_INFO, 1);
1408         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1409         if (ret < 0)
1410                 goto err_destroy_conn;
1411
1412         cec_fill_conn_info_from_drm(&conn_info, hdmi->connector);
1413         cec_s_conn_info(hdmi->cec_adap, &conn_info);
1414
1415         HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1416         value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1417         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1418         /*
1419          * Set the logical address to Unregistered and set the clock
1420          * divider: the hsm_clock rate and this divider setting will
1421          * give a 40 kHz CEC clock.
1422          */
1423         value |= VC4_HDMI_CEC_ADDR_MASK |
1424                  (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1425         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1426         ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1427                                         vc4_cec_irq_handler,
1428                                         vc4_cec_irq_handler_thread, 0,
1429                                         "vc4 hdmi cec", vc4);
1430         if (ret)
1431                 goto err_delete_cec_adap;
1432         ret = cec_register_adapter(hdmi->cec_adap, dev);
1433         if (ret < 0)
1434                 goto err_delete_cec_adap;
1435 #endif
1436
1437         ret = vc4_hdmi_audio_init(hdmi);
1438         if (ret)
1439                 goto err_destroy_encoder;
1440
1441         vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi);
1442
1443         return 0;
1444
1445 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1446 err_delete_cec_adap:
1447         cec_delete_adapter(hdmi->cec_adap);
1448 err_destroy_conn:
1449         vc4_hdmi_connector_destroy(hdmi->connector);
1450 #endif
1451 err_destroy_encoder:
1452         vc4_hdmi_encoder_destroy(hdmi->encoder);
1453 err_unprepare_hsm:
1454         clk_disable_unprepare(hdmi->hsm_clock);
1455         pm_runtime_disable(dev);
1456 err_put_i2c:
1457         put_device(&hdmi->ddc->dev);
1458
1459         return ret;
1460 }
1461
1462 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1463                             void *data)
1464 {
1465         struct drm_device *drm = dev_get_drvdata(master);
1466         struct vc4_dev *vc4 = drm->dev_private;
1467         struct vc4_hdmi *hdmi = vc4->hdmi;
1468
1469         cec_unregister_adapter(hdmi->cec_adap);
1470         vc4_hdmi_connector_destroy(hdmi->connector);
1471         vc4_hdmi_encoder_destroy(hdmi->encoder);
1472
1473         clk_disable_unprepare(hdmi->hsm_clock);
1474         pm_runtime_disable(dev);
1475
1476         put_device(&hdmi->ddc->dev);
1477
1478         vc4->hdmi = NULL;
1479 }
1480
1481 static const struct component_ops vc4_hdmi_ops = {
1482         .bind   = vc4_hdmi_bind,
1483         .unbind = vc4_hdmi_unbind,
1484 };
1485
1486 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1487 {
1488         return component_add(&pdev->dev, &vc4_hdmi_ops);
1489 }
1490
1491 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1492 {
1493         component_del(&pdev->dev, &vc4_hdmi_ops);
1494         return 0;
1495 }
1496
1497 static const struct of_device_id vc4_hdmi_dt_match[] = {
1498         { .compatible = "brcm,bcm2835-hdmi" },
1499         {}
1500 };
1501
1502 struct platform_driver vc4_hdmi_driver = {
1503         .probe = vc4_hdmi_dev_probe,
1504         .remove = vc4_hdmi_dev_remove,
1505         .driver = {
1506                 .name = "vc4_hdmi",
1507                 .of_match_table = vc4_hdmi_dt_match,
1508         },
1509 };