drivers/gpu/drm/omapdrm/omap_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/sort.h>
  10 #include <linux/sys_soc.h>
  11
  12 #include <drm/drm_atomic.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_bridge.h>
  15 #include <drm/drm_drv.h>
  16 #include <drm/drm_fb_helper.h>
  17 #include <drm/drm_file.h>
  18 #include <drm/drm_ioctl.h>
  19 #include <drm/drm_panel.h>
  20 #include <drm/drm_prime.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "omap_dmm_tiler.h"
  25 #include "omap_drv.h"
  26
  27 #define DRIVER_NAME             MODULE_NAME
  28 #define DRIVER_DESC             "OMAP DRM"
  29 #define DRIVER_DATE             "20110917"
  30 #define DRIVER_MAJOR            1
  31 #define DRIVER_MINOR            0
  32 #define DRIVER_PATCHLEVEL       0
  33
  34 /*
  35  * mode config funcs
  36  */
  37
  38 /* Notes about mapping DSS and DRM entities:
  39  *    CRTC:        overlay
  40  *    encoder:     manager.. with some extension to allow one primary CRTC
  41  *                 and zero or more video CRTC's to be mapped to one encoder?
  42  *    connector:   dssdev.. manager can be attached/detached from different
  43  *                 devices
  44  */
  45
  46 static void omap_atomic_wait_for_completion(struct drm_device *dev,
  47                                             struct drm_atomic_state *old_state)
  48 {
  49         struct drm_crtc_state *new_crtc_state;
  50         struct drm_crtc *crtc;
  51         unsigned int i;
  52         int ret;
  53
  54         for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  55                 if (!new_crtc_state->active)
  56                         continue;
  57
  58                 ret = omap_crtc_wait_pending(crtc);
  59
  60                 if (!ret)
  61                         dev_warn(dev->dev,
  62                                  "atomic complete timeout (pipe %u)!\n", i);
  63         }
  64 }
  65
  66 static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  67 {
  68         struct drm_device *dev = old_state->dev;
  69         struct omap_drm_private *priv = dev->dev_private;
  70
  71         priv->dispc_ops->runtime_get(priv->dispc);
  72
  73         /* Apply the atomic update. */
  74         drm_atomic_helper_commit_modeset_disables(dev, old_state);
  75
  76         if (priv->omaprev != 0x3430) {
  77                 /* With the current dss dispc implementation we have to enable
  78                  * the new modeset before we can commit planes. The dispc ovl
  79                  * configuration relies on the video mode configuration been
  80                  * written into the HW when the ovl configuration is
  81                  * calculated.
  82                  *
  83                  * This approach is not ideal because after a mode change the
  84                  * plane update is executed only after the first vblank
  85                  * interrupt. The dispc implementation should be fixed so that
  86                  * it is able use uncommitted drm state information.
  87                  */
  88                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
  89                 omap_atomic_wait_for_completion(dev, old_state);
  90
  91                 drm_atomic_helper_commit_planes(dev, old_state, 0);
  92
  93                 drm_atomic_helper_commit_hw_done(old_state);
  94         } else {
  95                 /*
  96                  * OMAP3 DSS seems to have issues with the work-around above,
  97                  * resulting in endless sync losts if a crtc is enabled without
  98                  * a plane. For now, skip the WA for OMAP3.
  99                  */
 100                 drm_atomic_helper_commit_planes(dev, old_state, 0);
 101
 102                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
 103
 104                 drm_atomic_helper_commit_hw_done(old_state);
 105         }
 106
 107         /*
 108          * Wait for completion of the page flips to ensure that old buffers
 109          * can't be touched by the hardware anymore before cleaning up planes.
 110          */
 111         omap_atomic_wait_for_completion(dev, old_state);
 112
 113         drm_atomic_helper_cleanup_planes(dev, old_state);
 114
 115         priv->dispc_ops->runtime_put(priv->dispc);
 116 }
 117
 118 static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
 119         .atomic_commit_tail = omap_atomic_commit_tail,
 120 };
 121
 122 static const struct drm_mode_config_funcs omap_mode_config_funcs = {
 123         .fb_create = omap_framebuffer_create,
 124         .output_poll_changed = drm_fb_helper_output_poll_changed,
 125         .atomic_check = drm_atomic_helper_check,
 126         .atomic_commit = drm_atomic_helper_commit,
 127 };
 128
 129 static void omap_disconnect_pipelines(struct drm_device *ddev)
 130 {
 131         struct omap_drm_private *priv = ddev->dev_private;
 132         unsigned int i;
 133
 134         for (i = 0; i < priv->num_pipes; i++) {
 135                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 136
 137                 if (pipe->output->panel)
 138                         drm_panel_detach(pipe->output->panel);
 139
 140                 omapdss_device_disconnect(NULL, pipe->output);
 141
 142                 omapdss_device_put(pipe->output);
 143                 pipe->output = NULL;
 144         }
 145
 146         memset(&priv->channels, 0, sizeof(priv->channels));
 147
 148         priv->num_pipes = 0;
 149 }
 150
 151 static int omap_connect_pipelines(struct drm_device *ddev)
 152 {
 153         struct omap_drm_private *priv = ddev->dev_private;
 154         struct omap_dss_device *output = NULL;
 155         int r;
 156
 157         for_each_dss_output(output) {
 158                 r = omapdss_device_connect(priv->dss, NULL, output);
 159                 if (r == -EPROBE_DEFER) {
 160                         omapdss_device_put(output);
 161                         return r;
 162                 } else if (r) {
 163                         dev_warn(output->dev, "could not connect output %s\n",
 164                                  output->name);
 165                 } else {
 166                         struct omap_drm_pipeline *pipe;
 167
 168                         pipe = &priv->pipes[priv->num_pipes++];
 169                         pipe->output = omapdss_device_get(output);
 170
 171                         if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
 172                                 /* To balance the 'for_each_dss_output' loop */
 173                                 omapdss_device_put(output);
 174                                 break;
 175                         }
 176                 }
 177         }
 178
 179         return 0;
 180 }
 181
 182 static int omap_compare_pipelines(const void *a, const void *b)
 183 {
 184         const struct omap_drm_pipeline *pipe1 = a;
 185         const struct omap_drm_pipeline *pipe2 = b;
 186
 187         if (pipe1->alias_id > pipe2->alias_id)
 188                 return 1;
 189         else if (pipe1->alias_id < pipe2->alias_id)
 190                 return -1;
 191         return 0;
 192 }
 193
 194 static int omap_modeset_init_properties(struct drm_device *dev)
 195 {
 196         struct omap_drm_private *priv = dev->dev_private;
 197         unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
 198
 199         priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
 200                                                       num_planes - 1);
 201         if (!priv->zorder_prop)
 202                 return -ENOMEM;
 203
 204         return 0;
 205 }
 206
 207 static int omap_display_id(struct omap_dss_device *output)
 208 {
 209         struct device_node *node = NULL;
 210
 211         if (output->next) {
 212                 struct omap_dss_device *display;
 213
 214                 display = omapdss_display_get(output);
 215                 node = display->dev->of_node;
 216                 omapdss_device_put(display);
 217         } else if (output->bridge) {
 218                 struct drm_bridge *bridge = output->bridge;
 219
 220                 while (bridge->next)
 221                         bridge = bridge->next;
 222
 223                 node = bridge->of_node;
 224         } else if (output->panel) {
 225                 node = output->panel->dev->of_node;
 226         }
 227
 228         return node ? of_alias_get_id(node, "display") : -ENODEV;
 229 }
 230
 231 static int omap_modeset_init(struct drm_device *dev)
 232 {
 233         struct omap_drm_private *priv = dev->dev_private;
 234         int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
 235         int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
 236         unsigned int i;
 237         int ret;
 238         u32 plane_crtc_mask;
 239
 240         if (!omapdss_stack_is_ready())
 241                 return -EPROBE_DEFER;
 242
 243         drm_mode_config_init(dev);
 244
 245         ret = omap_modeset_init_properties(dev);
 246         if (ret < 0)
 247                 return ret;
 248
 249         /*
 250          * This function creates exactly one connector, encoder, crtc,
 251          * and primary plane per each connected dss-device. Each
 252          * connector->encoder->crtc chain is expected to be separate
 253          * and each crtc is connect to a single dss-channel. If the
 254          * configuration does not match the expectations or exceeds
 255          * the available resources, the configuration is rejected.
 256          */
 257         ret = omap_connect_pipelines(dev);
 258         if (ret < 0)
 259                 return ret;
 260
 261         if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
 262                 dev_err(dev->dev, "%s(): Too many connected displays\n",
 263                         __func__);
 264                 return -EINVAL;
 265         }
 266
 267         /* Create all planes first. They can all be put to any CRTC. */
 268         plane_crtc_mask = (1 << priv->num_pipes) - 1;
 269
 270         for (i = 0; i < num_ovls; i++) {
 271                 enum drm_plane_type type = i < priv->num_pipes
 272                                          ? DRM_PLANE_TYPE_PRIMARY
 273                                          : DRM_PLANE_TYPE_OVERLAY;
 274                 struct drm_plane *plane;
 275
 276                 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
 277                         return -EINVAL;
 278
 279                 plane = omap_plane_init(dev, i, type, plane_crtc_mask);
 280                 if (IS_ERR(plane))
 281                         return PTR_ERR(plane);
 282
 283                 priv->planes[priv->num_planes++] = plane;
 284         }
 285
 286         /*
 287          * Create the encoders, attach the bridges and get the pipeline alias
 288          * IDs.
 289          */
 290         for (i = 0; i < priv->num_pipes; i++) {
 291                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 292                 int id;
 293
 294                 pipe->encoder = omap_encoder_init(dev, pipe->output);
 295                 if (!pipe->encoder)
 296                         return -ENOMEM;
 297
 298                 if (pipe->output->bridge) {
 299                         ret = drm_bridge_attach(pipe->encoder,
 300                                                 pipe->output->bridge, NULL);
 301                         if (ret < 0)
 302                                 return ret;
 303                 }
 304
 305                 id = omap_display_id(pipe->output);
 306                 pipe->alias_id = id >= 0 ? id : i;
 307         }
 308
 309         /* Sort the pipelines by DT aliases. */
 310         sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
 311              omap_compare_pipelines, NULL);
 312
 313         /*
 314          * Populate the pipeline lookup table by DISPC channel. Only one display
 315          * is allowed per channel.
 316          */
 317         for (i = 0; i < priv->num_pipes; ++i) {
 318                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 319                 enum omap_channel channel = pipe->output->dispc_channel;
 320
 321                 if (WARN_ON(priv->channels[channel] != NULL))
 322                         return -EINVAL;
 323
 324                 priv->channels[channel] = pipe;
 325         }
 326
 327         /* Create the connectors and CRTCs. */
 328         for (i = 0; i < priv->num_pipes; i++) {
 329                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 330                 struct drm_encoder *encoder = pipe->encoder;
 331                 struct drm_crtc *crtc;
 332
 333                 if (!pipe->output->bridge) {
 334                         pipe->connector = omap_connector_init(dev, pipe->output,
 335                                                               encoder);
 336                         if (!pipe->connector)
 337                                 return -ENOMEM;
 338
 339                         drm_connector_attach_encoder(pipe->connector, encoder);
 340
 341                         if (pipe->output->panel) {
 342                                 ret = drm_panel_attach(pipe->output->panel,
 343                                                        pipe->connector);
 344                                 if (ret < 0)
 345                                         return ret;
 346                         }
 347                 }
 348
 349                 crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
 350                 if (IS_ERR(crtc))
 351                         return PTR_ERR(crtc);
 352
 353                 encoder->possible_crtcs = 1 << i;
 354                 pipe->crtc = crtc;
 355         }
 356
 357         DBG("registered %u planes, %u crtcs/encoders/connectors\n",
 358             priv->num_planes, priv->num_pipes);
 359
 360         dev->mode_config.min_width = 8;
 361         dev->mode_config.min_height = 2;
 362
 363         /*
 364          * Note: these values are used for multiple independent things:
 365          * connector mode filtering, buffer sizes, crtc sizes...
 366          * Use big enough values here to cover all use cases, and do more
 367          * specific checking in the respective code paths.
 368          */
 369         dev->mode_config.max_width = 8192;
 370         dev->mode_config.max_height = 8192;
 371
 372         /* We want the zpos to be normalized */
 373         dev->mode_config.normalize_zpos = true;
 374
 375         dev->mode_config.funcs = &omap_mode_config_funcs;
 376         dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
 377
 378         drm_mode_config_reset(dev);
 379
 380         omap_drm_irq_install(dev);
 381
 382         return 0;
 383 }
 384
 385 /*
 386  * Enable the HPD in external components if supported
 387  */
 388 static void omap_modeset_enable_external_hpd(struct drm_device *ddev)
 389 {
 390         struct omap_drm_private *priv = ddev->dev_private;
 391         unsigned int i;
 392
 393         for (i = 0; i < priv->num_pipes; i++) {
 394                 if (priv->pipes[i].connector)
 395                         omap_connector_enable_hpd(priv->pipes[i].connector);
 396         }
 397 }
 398
 399 /*
 400  * Disable the HPD in external components if supported
 401  */
 402 static void omap_modeset_disable_external_hpd(struct drm_device *ddev)
 403 {
 404         struct omap_drm_private *priv = ddev->dev_private;
 405         unsigned int i;
 406
 407         for (i = 0; i < priv->num_pipes; i++) {
 408                 if (priv->pipes[i].connector)
 409                         omap_connector_disable_hpd(priv->pipes[i].connector);
 410         }
 411 }
 412
 413 /*
 414  * drm ioctl funcs
 415  */
 416
 417
 418 static int ioctl_get_param(struct drm_device *dev, void *data,
 419                 struct drm_file *file_priv)
 420 {
 421         struct omap_drm_private *priv = dev->dev_private;
 422         struct drm_omap_param *args = data;
 423
 424         DBG("%p: param=%llu", dev, args->param);
 425
 426         switch (args->param) {
 427         case OMAP_PARAM_CHIPSET_ID:
 428                 args->value = priv->omaprev;
 429                 break;
 430         default:
 431                 DBG("unknown parameter %lld", args->param);
 432                 return -EINVAL;
 433         }
 434
 435         return 0;
 436 }
 437
 438 #define OMAP_BO_USER_MASK       0x00ffffff      /* flags settable by userspace */
 439
 440 static int ioctl_gem_new(struct drm_device *dev, void *data,
 441                 struct drm_file *file_priv)
 442 {
 443         struct drm_omap_gem_new *args = data;
 444         u32 flags = args->flags & OMAP_BO_USER_MASK;
 445
 446         VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
 447              args->size.bytes, flags);
 448
 449         return omap_gem_new_handle(dev, file_priv, args->size, flags,
 450                                    &args->handle);
 451 }
 452
 453 static int ioctl_gem_info(struct drm_device *dev, void *data,
 454                 struct drm_file *file_priv)
 455 {
 456         struct drm_omap_gem_info *args = data;
 457         struct drm_gem_object *obj;
 458         int ret = 0;
 459
 460         VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
 461
 462         obj = drm_gem_object_lookup(file_priv, args->handle);
 463         if (!obj)
 464                 return -ENOENT;
 465
 466         args->size = omap_gem_mmap_size(obj);
 467         args->offset = omap_gem_mmap_offset(obj);
 468
 469         drm_gem_object_put_unlocked(obj);
 470
 471         return ret;
 472 }
 473
 474 static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
 475         DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
 476                           DRM_RENDER_ALLOW),
 477         DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
 478                           DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
 479         DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
 480                           DRM_RENDER_ALLOW),
 481         /* Deprecated, to be removed. */
 482         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
 483                           DRM_RENDER_ALLOW),
 484         /* Deprecated, to be removed. */
 485         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
 486                           DRM_RENDER_ALLOW),
 487         DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
 488                           DRM_RENDER_ALLOW),
 489 };
 490
 491 /*
 492  * drm driver funcs
 493  */
 494
 495 static int dev_open(struct drm_device *dev, struct drm_file *file)
 496 {
 497         file->driver_priv = NULL;
 498
 499         DBG("open: dev=%p, file=%p", dev, file);
 500
 501         return 0;
 502 }
 503
 504 static const struct vm_operations_struct omap_gem_vm_ops = {
 505         .fault = omap_gem_fault,
 506         .open = drm_gem_vm_open,
 507         .close = drm_gem_vm_close,
 508 };
 509
 510 static const struct file_operations omapdriver_fops = {
 511         .owner = THIS_MODULE,
 512         .open = drm_open,
 513         .unlocked_ioctl = drm_ioctl,
 514         .compat_ioctl = drm_compat_ioctl,
 515         .release = drm_release,
 516         .mmap = omap_gem_mmap,
 517         .poll = drm_poll,
 518         .read = drm_read,
 519         .llseek = noop_llseek,
 520 };
 521
 522 static struct drm_driver omap_drm_driver = {
 523         .driver_features = DRIVER_MODESET | DRIVER_GEM  |
 524                 DRIVER_ATOMIC | DRIVER_RENDER,
 525         .open = dev_open,
 526         .lastclose = drm_fb_helper_lastclose,
 527 #ifdef CONFIG_DEBUG_FS
 528         .debugfs_init = omap_debugfs_init,
 529 #endif
 530         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 531         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 532         .gem_prime_export = omap_gem_prime_export,
 533         .gem_prime_import = omap_gem_prime_import,
 534         .gem_free_object_unlocked = omap_gem_free_object,
 535         .gem_vm_ops = &omap_gem_vm_ops,
 536         .dumb_create = omap_gem_dumb_create,
 537         .dumb_map_offset = omap_gem_dumb_map_offset,
 538         .ioctls = ioctls,
 539         .num_ioctls = DRM_OMAP_NUM_IOCTLS,
 540         .fops = &omapdriver_fops,
 541         .name = DRIVER_NAME,
 542         .desc = DRIVER_DESC,
 543         .date = DRIVER_DATE,
 544         .major = DRIVER_MAJOR,
 545         .minor = DRIVER_MINOR,
 546         .patchlevel = DRIVER_PATCHLEVEL,
 547 };
 548
 549 static const struct soc_device_attribute omapdrm_soc_devices[] = {
 550         { .family = "OMAP3", .data = (void *)0x3430 },
 551         { .family = "OMAP4", .data = (void *)0x4430 },
 552         { .family = "OMAP5", .data = (void *)0x5430 },
 553         { .family = "DRA7",  .data = (void *)0x0752 },
 554         { /* sentinel */ }
 555 };
 556
 557 static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 558 {
 559         const struct soc_device_attribute *soc;
 560         struct drm_device *ddev;
 561         unsigned int i;
 562         int ret;
 563
 564         DBG("%s", dev_name(dev));
 565
 566         /* Allocate and initialize the DRM device. */
 567         ddev = drm_dev_alloc(&omap_drm_driver, dev);
 568         if (IS_ERR(ddev))
 569                 return PTR_ERR(ddev);
 570
 571         priv->ddev = ddev;
 572         ddev->dev_private = priv;
 573
 574         priv->dev = dev;
 575         priv->dss = omapdss_get_dss();
 576         priv->dispc = dispc_get_dispc(priv->dss);
 577         priv->dispc_ops = dispc_get_ops(priv->dss);
 578
 579         omap_crtc_pre_init(priv);
 580
 581         soc = soc_device_match(omapdrm_soc_devices);
 582         priv->omaprev = soc ? (unsigned int)soc->data : 0;
 583         priv->wq = alloc_ordered_workqueue("omapdrm", 0);
 584
 585         mutex_init(&priv->list_lock);
 586         INIT_LIST_HEAD(&priv->obj_list);
 587
 588         /* Get memory bandwidth limits */
 589         if (priv->dispc_ops->get_memory_bandwidth_limit)
 590                 priv->max_bandwidth =
 591                         priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
 592
 593         omap_gem_init(ddev);
 594
 595         ret = omap_modeset_init(ddev);
 596         if (ret) {
 597                 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
 598                 goto err_gem_deinit;
 599         }
 600
 601         /* Initialize vblank handling, start with all CRTCs disabled. */
 602         ret = drm_vblank_init(ddev, priv->num_pipes);
 603         if (ret) {
 604                 dev_err(priv->dev, "could not init vblank\n");
 605                 goto err_cleanup_modeset;
 606         }
 607
 608         for (i = 0; i < priv->num_pipes; i++)
 609                 drm_crtc_vblank_off(priv->pipes[i].crtc);
 610
 611         omap_fbdev_init(ddev);
 612
 613         drm_kms_helper_poll_init(ddev);
 614         omap_modeset_enable_external_hpd(ddev);
 615
 616         /*
 617          * Register the DRM device with the core and the connectors with
 618          * sysfs.
 619          */
 620         ret = drm_dev_register(ddev, 0);
 621         if (ret)
 622                 goto err_cleanup_helpers;
 623
 624         return 0;
 625
 626 err_cleanup_helpers:
 627         omap_modeset_disable_external_hpd(ddev);
 628         drm_kms_helper_poll_fini(ddev);
 629
 630         omap_fbdev_fini(ddev);
 631 err_cleanup_modeset:
 632         drm_mode_config_cleanup(ddev);
 633         omap_drm_irq_uninstall(ddev);
 634 err_gem_deinit:
 635         omap_gem_deinit(ddev);
 636         destroy_workqueue(priv->wq);
 637         omap_disconnect_pipelines(ddev);
 638         omap_crtc_pre_uninit(priv);
 639         drm_dev_put(ddev);
 640         return ret;
 641 }
 642
 643 static void omapdrm_cleanup(struct omap_drm_private *priv)
 644 {
 645         struct drm_device *ddev = priv->ddev;
 646
 647         DBG("");
 648
 649         drm_dev_unregister(ddev);
 650
 651         omap_modeset_disable_external_hpd(ddev);
 652         drm_kms_helper_poll_fini(ddev);
 653
 654         omap_fbdev_fini(ddev);
 655
 656         drm_atomic_helper_shutdown(ddev);
 657
 658         drm_mode_config_cleanup(ddev);
 659
 660         omap_drm_irq_uninstall(ddev);
 661         omap_gem_deinit(ddev);
 662
 663         destroy_workqueue(priv->wq);
 664
 665         omap_disconnect_pipelines(ddev);
 666         omap_crtc_pre_uninit(priv);
 667
 668         drm_dev_put(ddev);
 669 }
 670
 671 static int pdev_probe(struct platform_device *pdev)
 672 {
 673         struct omap_drm_private *priv;
 674         int ret;
 675
 676         if (omapdss_is_initialized() == false)
 677                 return -EPROBE_DEFER;
 678
 679         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 680         if (ret) {
 681                 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
 682                 return ret;
 683         }
 684
 685         /* Allocate and initialize the driver private structure. */
 686         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 687         if (!priv)
 688                 return -ENOMEM;
 689
 690         platform_set_drvdata(pdev, priv);
 691
 692         ret = omapdrm_init(priv, &pdev->dev);
 693         if (ret < 0)
 694                 kfree(priv);
 695
 696         return ret;
 697 }
 698
 699 static int pdev_remove(struct platform_device *pdev)
 700 {
 701         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 702
 703         omapdrm_cleanup(priv);
 704         kfree(priv);
 705
 706         return 0;
 707 }
 708
 709 #ifdef CONFIG_PM_SLEEP
 710 static int omap_drm_suspend(struct device *dev)
 711 {
 712         struct omap_drm_private *priv = dev_get_drvdata(dev);
 713         struct drm_device *drm_dev = priv->ddev;
 714
 715         return drm_mode_config_helper_suspend(drm_dev);
 716 }
 717
 718 static int omap_drm_resume(struct device *dev)
 719 {
 720         struct omap_drm_private *priv = dev_get_drvdata(dev);
 721         struct drm_device *drm_dev = priv->ddev;
 722
 723         drm_mode_config_helper_resume(drm_dev);
 724
 725         return omap_gem_resume(drm_dev);
 726 }
 727 #endif
 728
 729 static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
 730
 731 static struct platform_driver pdev = {
 732         .driver = {
 733                 .name = "omapdrm",
 734                 .pm = &omapdrm_pm_ops,
 735         },
 736         .probe = pdev_probe,
 737         .remove = pdev_remove,
 738 };
 739
 740 static struct platform_driver * const drivers[] = {
 741         &omap_dmm_driver,
 742         &pdev,
 743 };
 744
 745 static int __init omap_drm_init(void)
 746 {
 747         DBG("init");
 748
 749         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 750 }
 751
 752 static void __exit omap_drm_fini(void)
 753 {
 754         DBG("fini");
 755
 756         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 757 }
 758
 759 /* need late_initcall() so we load after dss_driver's are loaded */
 760 late_initcall(omap_drm_init);
 761 module_exit(omap_drm_fini);
 762
 763 MODULE_AUTHOR("Rob Clark <[email protected]>");
 764 MODULE_DESCRIPTION("OMAP DRM Display Driver");
 765 MODULE_ALIAS("platform:" DRIVER_NAME);
 766 MODULE_LICENSE("GPL v2");