drivers/gpu/drm/i915/display/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/i915_drm.h>
  36
  37 #include "i915_drv.h"
  38 #include "intel_connector.h"
  39 #include "intel_crt.h"
  40 #include "intel_ddi.h"
  41 #include "intel_display_types.h"
  42 #include "intel_fifo_underrun.h"
  43 #include "intel_gmbus.h"
  44 #include "intel_hotplug.h"
  45
  46 /* Here's the desired hotplug mode */
  47 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  48                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  49                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  50                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  51                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  52                            ADPA_CRT_HOTPLUG_ENABLE)
  53
  54 struct intel_crt {
  55         struct intel_encoder base;
  56         /* DPMS state is stored in the connector, which we need in the
  57          * encoder's enable/disable callbacks */
  58         struct intel_connector *connector;
  59         bool force_hotplug_required;
  60         i915_reg_t adpa_reg;
  61 };
  62
  63 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  64 {
  65         return container_of(encoder, struct intel_crt, base);
  66 }
  67
  68 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  69 {
  70         return intel_encoder_to_crt(intel_attached_encoder(connector));
  71 }
  72
  73 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  74                             i915_reg_t adpa_reg, enum pipe *pipe)
  75 {
  76         u32 val;
  77
  78         val = I915_READ(adpa_reg);
  79
  80         /* asserts want to know the pipe even if the port is disabled */
  81         if (HAS_PCH_CPT(dev_priv))
  82                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  83         else
  84                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  85
  86         return val & ADPA_DAC_ENABLE;
  87 }
  88
  89 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  90                                    enum pipe *pipe)
  91 {
  92         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  93         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  94         intel_wakeref_t wakeref;
  95         bool ret;
  96
  97         wakeref = intel_display_power_get_if_enabled(dev_priv,
  98                                                      encoder->power_domain);
  99         if (!wakeref)
 100                 return false;
 101
 102         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 103
 104         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 105
 106         return ret;
 107 }
 108
 109 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 110 {
 111         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 112         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 113         u32 tmp, flags = 0;
 114
 115         tmp = I915_READ(crt->adpa_reg);
 116
 117         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 118                 flags |= DRM_MODE_FLAG_PHSYNC;
 119         else
 120                 flags |= DRM_MODE_FLAG_NHSYNC;
 121
 122         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 123                 flags |= DRM_MODE_FLAG_PVSYNC;
 124         else
 125                 flags |= DRM_MODE_FLAG_NVSYNC;
 126
 127         return flags;
 128 }
 129
 130 static void intel_crt_get_config(struct intel_encoder *encoder,
 131                                  struct intel_crtc_state *pipe_config)
 132 {
 133         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 134
 135         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 136
 137         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 138 }
 139
 140 static void hsw_crt_get_config(struct intel_encoder *encoder,
 141                                struct intel_crtc_state *pipe_config)
 142 {
 143         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 144
 145         intel_ddi_get_config(encoder, pipe_config);
 146
 147         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 148                                               DRM_MODE_FLAG_NHSYNC |
 149                                               DRM_MODE_FLAG_PVSYNC |
 150                                               DRM_MODE_FLAG_NVSYNC);
 151         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 152
 153         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 154 }
 155
 156 /* Note: The caller is required to filter out dpms modes not supported by the
 157  * platform. */
 158 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 159                                const struct intel_crtc_state *crtc_state,
 160                                int mode)
 161 {
 162         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 163         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 164         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 165         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 166         u32 adpa;
 167
 168         if (INTEL_GEN(dev_priv) >= 5)
 169                 adpa = ADPA_HOTPLUG_BITS;
 170         else
 171                 adpa = 0;
 172
 173         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 174                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 175         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 176                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 177
 178         /* For CPT allow 3 pipe config, for others just use A or B */
 179         if (HAS_PCH_LPT(dev_priv))
 180                 ; /* Those bits don't exist here */
 181         else if (HAS_PCH_CPT(dev_priv))
 182                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 183         else
 184                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 185
 186         if (!HAS_PCH_SPLIT(dev_priv))
 187                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 188
 189         switch (mode) {
 190         case DRM_MODE_DPMS_ON:
 191                 adpa |= ADPA_DAC_ENABLE;
 192                 break;
 193         case DRM_MODE_DPMS_STANDBY:
 194                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 195                 break;
 196         case DRM_MODE_DPMS_SUSPEND:
 197                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 198                 break;
 199         case DRM_MODE_DPMS_OFF:
 200                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 201                 break;
 202         }
 203
 204         I915_WRITE(crt->adpa_reg, adpa);
 205 }
 206
 207 static void intel_disable_crt(struct intel_encoder *encoder,
 208                               const struct intel_crtc_state *old_crtc_state,
 209                               const struct drm_connector_state *old_conn_state)
 210 {
 211         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 212 }
 213
 214 static void pch_disable_crt(struct intel_encoder *encoder,
 215                             const struct intel_crtc_state *old_crtc_state,
 216                             const struct drm_connector_state *old_conn_state)
 217 {
 218 }
 219
 220 static void pch_post_disable_crt(struct intel_encoder *encoder,
 221                                  const struct intel_crtc_state *old_crtc_state,
 222                                  const struct drm_connector_state *old_conn_state)
 223 {
 224         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 225 }
 226
 227 static void hsw_disable_crt(struct intel_encoder *encoder,
 228                             const struct intel_crtc_state *old_crtc_state,
 229                             const struct drm_connector_state *old_conn_state)
 230 {
 231         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 232
 233         WARN_ON(!old_crtc_state->has_pch_encoder);
 234
 235         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 236 }
 237
 238 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 239                                  const struct intel_crtc_state *old_crtc_state,
 240                                  const struct drm_connector_state *old_conn_state)
 241 {
 242         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 243
 244         intel_ddi_disable_pipe_clock(old_crtc_state);
 245
 246         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 247
 248         lpt_disable_pch_transcoder(dev_priv);
 249         lpt_disable_iclkip(dev_priv);
 250
 251         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 252
 253         WARN_ON(!old_crtc_state->has_pch_encoder);
 254
 255         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 256 }
 257
 258 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 259                                    const struct intel_crtc_state *crtc_state,
 260                                    const struct drm_connector_state *conn_state)
 261 {
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263
 264         WARN_ON(!crtc_state->has_pch_encoder);
 265
 266         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 267 }
 268
 269 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 270                                const struct intel_crtc_state *crtc_state,
 271                                const struct drm_connector_state *conn_state)
 272 {
 273         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 275         enum pipe pipe = crtc->pipe;
 276
 277         WARN_ON(!crtc_state->has_pch_encoder);
 278
 279         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 280
 281         dev_priv->display.fdi_link_train(crtc, crtc_state);
 282
 283         intel_ddi_enable_pipe_clock(crtc_state);
 284 }
 285
 286 static void hsw_enable_crt(struct intel_encoder *encoder,
 287                            const struct intel_crtc_state *crtc_state,
 288                            const struct drm_connector_state *conn_state)
 289 {
 290         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 291         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 292         enum pipe pipe = crtc->pipe;
 293
 294         WARN_ON(!crtc_state->has_pch_encoder);
 295
 296         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 297
 298         intel_wait_for_vblank(dev_priv, pipe);
 299         intel_wait_for_vblank(dev_priv, pipe);
 300         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 301         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 302 }
 303
 304 static void intel_enable_crt(struct intel_encoder *encoder,
 305                              const struct intel_crtc_state *crtc_state,
 306                              const struct drm_connector_state *conn_state)
 307 {
 308         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 309 }
 310
 311 static enum drm_mode_status
 312 intel_crt_mode_valid(struct drm_connector *connector,
 313                      struct drm_display_mode *mode)
 314 {
 315         struct drm_device *dev = connector->dev;
 316         struct drm_i915_private *dev_priv = to_i915(dev);
 317         int max_dotclk = dev_priv->max_dotclk_freq;
 318         int max_clock;
 319
 320         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 321                 return MODE_NO_DBLESCAN;
 322
 323         if (mode->clock < 25000)
 324                 return MODE_CLOCK_LOW;
 325
 326         if (HAS_PCH_LPT(dev_priv))
 327                 max_clock = 180000;
 328         else if (IS_VALLEYVIEW(dev_priv))
 329                 /*
 330                  * 270 MHz due to current DPLL limits,
 331                  * DAC limit supposedly 355 MHz.
 332                  */
 333                 max_clock = 270000;
 334         else if (IS_GEN_RANGE(dev_priv, 3, 4))
 335                 max_clock = 400000;
 336         else
 337                 max_clock = 350000;
 338         if (mode->clock > max_clock)
 339                 return MODE_CLOCK_HIGH;
 340
 341         if (mode->clock > max_dotclk)
 342                 return MODE_CLOCK_HIGH;
 343
 344         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 345         if (HAS_PCH_LPT(dev_priv) &&
 346             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 347                 return MODE_CLOCK_HIGH;
 348
 349         /* HSW/BDW FDI limited to 4k */
 350         if (mode->hdisplay > 4096)
 351                 return MODE_H_ILLEGAL;
 352
 353         return MODE_OK;
 354 }
 355
 356 static int intel_crt_compute_config(struct intel_encoder *encoder,
 357                                     struct intel_crtc_state *pipe_config,
 358                                     struct drm_connector_state *conn_state)
 359 {
 360         struct drm_display_mode *adjusted_mode =
 361                 &pipe_config->base.adjusted_mode;
 362
 363         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 364                 return -EINVAL;
 365
 366         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 367
 368         return 0;
 369 }
 370
 371 static int pch_crt_compute_config(struct intel_encoder *encoder,
 372                                   struct intel_crtc_state *pipe_config,
 373                                   struct drm_connector_state *conn_state)
 374 {
 375         struct drm_display_mode *adjusted_mode =
 376                 &pipe_config->base.adjusted_mode;
 377
 378         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 379                 return -EINVAL;
 380
 381         pipe_config->has_pch_encoder = true;
 382         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 383
 384         return 0;
 385 }
 386
 387 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 388                                   struct intel_crtc_state *pipe_config,
 389                                   struct drm_connector_state *conn_state)
 390 {
 391         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 392         struct drm_display_mode *adjusted_mode =
 393                 &pipe_config->base.adjusted_mode;
 394
 395         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 396                 return -EINVAL;
 397
 398         /* HSW/BDW FDI limited to 4k */
 399         if (adjusted_mode->crtc_hdisplay > 4096 ||
 400             adjusted_mode->crtc_hblank_start > 4096)
 401                 return -EINVAL;
 402
 403         pipe_config->has_pch_encoder = true;
 404         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 405
 406         /* LPT FDI RX only supports 8bpc. */
 407         if (HAS_PCH_LPT(dev_priv)) {
 408                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 409                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 410                         return -EINVAL;
 411                 }
 412
 413                 pipe_config->pipe_bpp = 24;
 414         }
 415
 416         /* FDI must always be 2.7 GHz */
 417         pipe_config->port_clock = 135000 * 2;
 418
 419         return 0;
 420 }
 421
 422 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 423 {
 424         struct drm_device *dev = connector->dev;
 425         struct intel_crt *crt = intel_attached_crt(connector);
 426         struct drm_i915_private *dev_priv = to_i915(dev);
 427         u32 adpa;
 428         bool ret;
 429
 430         /* The first time through, trigger an explicit detection cycle */
 431         if (crt->force_hotplug_required) {
 432                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 433                 u32 save_adpa;
 434
 435                 crt->force_hotplug_required = 0;
 436
 437                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 438                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 439
 440                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 441                 if (turn_off_dac)
 442                         adpa &= ~ADPA_DAC_ENABLE;
 443
 444                 I915_WRITE(crt->adpa_reg, adpa);
 445
 446                 if (intel_de_wait_for_clear(dev_priv,
 447                                             crt->adpa_reg,
 448                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
 449                                             1000))
 450                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 451
 452                 if (turn_off_dac) {
 453                         I915_WRITE(crt->adpa_reg, save_adpa);
 454                         POSTING_READ(crt->adpa_reg);
 455                 }
 456         }
 457
 458         /* Check the status to see if both blue and green are on now */
 459         adpa = I915_READ(crt->adpa_reg);
 460         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 461                 ret = true;
 462         else
 463                 ret = false;
 464         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 465
 466         return ret;
 467 }
 468
 469 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 470 {
 471         struct drm_device *dev = connector->dev;
 472         struct intel_crt *crt = intel_attached_crt(connector);
 473         struct drm_i915_private *dev_priv = to_i915(dev);
 474         bool reenable_hpd;
 475         u32 adpa;
 476         bool ret;
 477         u32 save_adpa;
 478
 479         /*
 480          * Doing a force trigger causes a hpd interrupt to get sent, which can
 481          * get us stuck in a loop if we're polling:
 482          *  - We enable power wells and reset the ADPA
 483          *  - output_poll_exec does force probe on VGA, triggering a hpd
 484          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 485          *  - output_poll_exec shuts off the ADPA, unlocks
 486          *    dev->mode_config.mutex
 487          *  - HPD handler runs, resets ADPA and brings us back to the start
 488          *
 489          * Just disable HPD interrupts here to prevent this
 490          */
 491         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 492
 493         save_adpa = adpa = I915_READ(crt->adpa_reg);
 494         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 495
 496         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 497
 498         I915_WRITE(crt->adpa_reg, adpa);
 499
 500         if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
 501                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
 502                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 503                 I915_WRITE(crt->adpa_reg, save_adpa);
 504         }
 505
 506         /* Check the status to see if both blue and green are on now */
 507         adpa = I915_READ(crt->adpa_reg);
 508         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 509                 ret = true;
 510         else
 511                 ret = false;
 512
 513         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 514
 515         if (reenable_hpd)
 516                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 517
 518         return ret;
 519 }
 520
 521 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 522 {
 523         struct drm_device *dev = connector->dev;
 524         struct drm_i915_private *dev_priv = to_i915(dev);
 525         u32 stat;
 526         bool ret = false;
 527         int i, tries = 0;
 528
 529         if (HAS_PCH_SPLIT(dev_priv))
 530                 return intel_ironlake_crt_detect_hotplug(connector);
 531
 532         if (IS_VALLEYVIEW(dev_priv))
 533                 return valleyview_crt_detect_hotplug(connector);
 534
 535         /*
 536          * On 4 series desktop, CRT detect sequence need to be done twice
 537          * to get a reliable result.
 538          */
 539
 540         if (IS_G45(dev_priv))
 541                 tries = 2;
 542         else
 543                 tries = 1;
 544
 545         for (i = 0; i < tries ; i++) {
 546                 /* turn on the FORCE_DETECT */
 547                 i915_hotplug_interrupt_update(dev_priv,
 548                                               CRT_HOTPLUG_FORCE_DETECT,
 549                                               CRT_HOTPLUG_FORCE_DETECT);
 550                 /* wait for FORCE_DETECT to go off */
 551                 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
 552                                             CRT_HOTPLUG_FORCE_DETECT, 1000))
 553                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 554         }
 555
 556         stat = I915_READ(PORT_HOTPLUG_STAT);
 557         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 558                 ret = true;
 559
 560         /* clear the interrupt we just generated, if any */
 561         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 562
 563         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 564
 565         return ret;
 566 }
 567
 568 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 569                                 struct i2c_adapter *i2c)
 570 {
 571         struct edid *edid;
 572
 573         edid = drm_get_edid(connector, i2c);
 574
 575         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 576                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 577                 intel_gmbus_force_bit(i2c, true);
 578                 edid = drm_get_edid(connector, i2c);
 579                 intel_gmbus_force_bit(i2c, false);
 580         }
 581
 582         return edid;
 583 }
 584
 585 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 586 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 587                                 struct i2c_adapter *adapter)
 588 {
 589         struct edid *edid;
 590         int ret;
 591
 592         edid = intel_crt_get_edid(connector, adapter);
 593         if (!edid)
 594                 return 0;
 595
 596         ret = intel_connector_update_modes(connector, edid);
 597         kfree(edid);
 598
 599         return ret;
 600 }
 601
 602 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 603 {
 604         struct intel_crt *crt = intel_attached_crt(connector);
 605         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 606         struct edid *edid;
 607         struct i2c_adapter *i2c;
 608         bool ret = false;
 609
 610         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 611
 612         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 613         edid = intel_crt_get_edid(connector, i2c);
 614
 615         if (edid) {
 616                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 617
 618                 /*
 619                  * This may be a DVI-I connector with a shared DDC
 620                  * link between analog and digital outputs, so we
 621                  * have to check the EDID input spec of the attached device.
 622                  */
 623                 if (!is_digital) {
 624                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 625                         ret = true;
 626                 } else {
 627                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 628                 }
 629         } else {
 630                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 631         }
 632
 633         kfree(edid);
 634
 635         return ret;
 636 }
 637
 638 static enum drm_connector_status
 639 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
 640 {
 641         struct drm_device *dev = crt->base.base.dev;
 642         struct drm_i915_private *dev_priv = to_i915(dev);
 643         struct intel_uncore *uncore = &dev_priv->uncore;
 644         u32 save_bclrpat;
 645         u32 save_vtotal;
 646         u32 vtotal, vactive;
 647         u32 vsample;
 648         u32 vblank, vblank_start, vblank_end;
 649         u32 dsl;
 650         i915_reg_t bclrpat_reg, vtotal_reg,
 651                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 652         u8 st00;
 653         enum drm_connector_status status;
 654
 655         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 656
 657         bclrpat_reg = BCLRPAT(pipe);
 658         vtotal_reg = VTOTAL(pipe);
 659         vblank_reg = VBLANK(pipe);
 660         vsync_reg = VSYNC(pipe);
 661         pipeconf_reg = PIPECONF(pipe);
 662         pipe_dsl_reg = PIPEDSL(pipe);
 663
 664         save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
 665         save_vtotal = intel_uncore_read(uncore, vtotal_reg);
 666         vblank = intel_uncore_read(uncore, vblank_reg);
 667
 668         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 669         vactive = (save_vtotal & 0x7ff) + 1;
 670
 671         vblank_start = (vblank & 0xfff) + 1;
 672         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 673
 674         /* Set the border color to purple. */
 675         intel_uncore_write(uncore, bclrpat_reg, 0x500050);
 676
 677         if (!IS_GEN(dev_priv, 2)) {
 678                 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
 679                 intel_uncore_write(uncore,
 680                                    pipeconf_reg,
 681                                    pipeconf | PIPECONF_FORCE_BORDER);
 682                 intel_uncore_posting_read(uncore, pipeconf_reg);
 683                 /* Wait for next Vblank to substitue
 684                  * border color for Color info */
 685                 intel_wait_for_vblank(dev_priv, pipe);
 686                 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
 687                 status = ((st00 & (1 << 4)) != 0) ?
 688                         connector_status_connected :
 689                         connector_status_disconnected;
 690
 691                 intel_uncore_write(uncore, pipeconf_reg, pipeconf);
 692         } else {
 693                 bool restore_vblank = false;
 694                 int count, detect;
 695
 696                 /*
 697                 * If there isn't any border, add some.
 698                 * Yes, this will flicker
 699                 */
 700                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 701                         u32 vsync = I915_READ(vsync_reg);
 702                         u32 vsync_start = (vsync & 0xffff) + 1;
 703
 704                         vblank_start = vsync_start;
 705                         intel_uncore_write(uncore,
 706                                            vblank_reg,
 707                                            (vblank_start - 1) |
 708                                            ((vblank_end - 1) << 16));
 709                         restore_vblank = true;
 710                 }
 711                 /* sample in the vertical border, selecting the larger one */
 712                 if (vblank_start - vactive >= vtotal - vblank_end)
 713                         vsample = (vblank_start + vactive) >> 1;
 714                 else
 715                         vsample = (vtotal + vblank_end) >> 1;
 716
 717                 /*
 718                  * Wait for the border to be displayed
 719                  */
 720                 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
 721                         ;
 722                 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
 723                        vsample)
 724                         ;
 725                 /*
 726                  * Watch ST00 for an entire scanline
 727                  */
 728                 detect = 0;
 729                 count = 0;
 730                 do {
 731                         count++;
 732                         /* Read the ST00 VGA status register */
 733                         st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
 734                         if (st00 & (1 << 4))
 735                                 detect++;
 736                 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
 737
 738                 /* restore vblank if necessary */
 739                 if (restore_vblank)
 740                         intel_uncore_write(uncore, vblank_reg, vblank);
 741                 /*
 742                  * If more than 3/4 of the scanline detected a monitor,
 743                  * then it is assumed to be present. This works even on i830,
 744                  * where there isn't any way to force the border color across
 745                  * the screen
 746                  */
 747                 status = detect * 4 > count * 3 ?
 748                          connector_status_connected :
 749                          connector_status_disconnected;
 750         }
 751
 752         /* Restore previous settings */
 753         intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
 754
 755         return status;
 756 }
 757
 758 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 759 {
 760         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 761         return 1;
 762 }
 763
 764 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 765         {
 766                 .callback = intel_spurious_crt_detect_dmi_callback,
 767                 .ident = "ACER ZGB",
 768                 .matches = {
 769                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 770                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 771                 },
 772         },
 773         {
 774                 .callback = intel_spurious_crt_detect_dmi_callback,
 775                 .ident = "Intel DZ77BH-55K",
 776                 .matches = {
 777                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 778                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 779                 },
 780         },
 781         { }
 782 };
 783
 784 static int
 785 intel_crt_detect(struct drm_connector *connector,
 786                  struct drm_modeset_acquire_ctx *ctx,
 787                  bool force)
 788 {
 789         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 790         struct intel_crt *crt = intel_attached_crt(connector);
 791         struct intel_encoder *intel_encoder = &crt->base;
 792         intel_wakeref_t wakeref;
 793         int status, ret;
 794         struct intel_load_detect_pipe tmp;
 795
 796         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 797                       connector->base.id, connector->name,
 798                       force);
 799
 800         if (i915_modparams.load_detect_test) {
 801                 wakeref = intel_display_power_get(dev_priv,
 802                                                   intel_encoder->power_domain);
 803                 goto load_detect;
 804         }
 805
 806         /* Skip machines without VGA that falsely report hotplug events */
 807         if (dmi_check_system(intel_spurious_crt_detect))
 808                 return connector_status_disconnected;
 809
 810         wakeref = intel_display_power_get(dev_priv,
 811                                           intel_encoder->power_domain);
 812
 813         if (I915_HAS_HOTPLUG(dev_priv)) {
 814                 /* We can not rely on the HPD pin always being correctly wired
 815                  * up, for example many KVM do not pass it through, and so
 816                  * only trust an assertion that the monitor is connected.
 817                  */
 818                 if (intel_crt_detect_hotplug(connector)) {
 819                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 820                         status = connector_status_connected;
 821                         goto out;
 822                 } else
 823                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 824         }
 825
 826         if (intel_crt_detect_ddc(connector)) {
 827                 status = connector_status_connected;
 828                 goto out;
 829         }
 830
 831         /* Load detection is broken on HPD capable machines. Whoever wants a
 832          * broken monitor (without edid) to work behind a broken kvm (that fails
 833          * to have the right resistors for HP detection) needs to fix this up.
 834          * For now just bail out. */
 835         if (I915_HAS_HOTPLUG(dev_priv)) {
 836                 status = connector_status_disconnected;
 837                 goto out;
 838         }
 839
 840 load_detect:
 841         if (!force) {
 842                 status = connector->status;
 843                 goto out;
 844         }
 845
 846         /* for pre-945g platforms use load detect */
 847         ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
 848         if (ret > 0) {
 849                 if (intel_crt_detect_ddc(connector))
 850                         status = connector_status_connected;
 851                 else if (INTEL_GEN(dev_priv) < 4)
 852                         status = intel_crt_load_detect(crt,
 853                                 to_intel_crtc(connector->state->crtc)->pipe);
 854                 else if (i915_modparams.load_detect_test)
 855                         status = connector_status_disconnected;
 856                 else
 857                         status = connector_status_unknown;
 858                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 859         } else if (ret == 0) {
 860                 status = connector_status_unknown;
 861         } else {
 862                 status = ret;
 863         }
 864
 865 out:
 866         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 867
 868         /*
 869          * Make sure the refs for power wells enabled during detect are
 870          * dropped to avoid a new detect cycle triggered by HPD polling.
 871          */
 872         intel_display_power_flush_work(dev_priv);
 873
 874         return status;
 875 }
 876
 877 static int intel_crt_get_modes(struct drm_connector *connector)
 878 {
 879         struct drm_device *dev = connector->dev;
 880         struct drm_i915_private *dev_priv = to_i915(dev);
 881         struct intel_crt *crt = intel_attached_crt(connector);
 882         struct intel_encoder *intel_encoder = &crt->base;
 883         intel_wakeref_t wakeref;
 884         struct i2c_adapter *i2c;
 885         int ret;
 886
 887         wakeref = intel_display_power_get(dev_priv,
 888                                           intel_encoder->power_domain);
 889
 890         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 891         ret = intel_crt_ddc_get_modes(connector, i2c);
 892         if (ret || !IS_G4X(dev_priv))
 893                 goto out;
 894
 895         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 896         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 897         ret = intel_crt_ddc_get_modes(connector, i2c);
 898
 899 out:
 900         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 901
 902         return ret;
 903 }
 904
 905 void intel_crt_reset(struct drm_encoder *encoder)
 906 {
 907         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 908         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 909
 910         if (INTEL_GEN(dev_priv) >= 5) {
 911                 u32 adpa;
 912
 913                 adpa = I915_READ(crt->adpa_reg);
 914                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 915                 adpa |= ADPA_HOTPLUG_BITS;
 916                 I915_WRITE(crt->adpa_reg, adpa);
 917                 POSTING_READ(crt->adpa_reg);
 918
 919                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 920                 crt->force_hotplug_required = 1;
 921         }
 922
 923 }
 924
 925 /*
 926  * Routines for controlling stuff on the analog port
 927  */
 928
 929 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 930         .fill_modes = drm_helper_probe_single_connector_modes,
 931         .late_register = intel_connector_register,
 932         .early_unregister = intel_connector_unregister,
 933         .destroy = intel_connector_destroy,
 934         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 935         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 936 };
 937
 938 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 939         .detect_ctx = intel_crt_detect,
 940         .mode_valid = intel_crt_mode_valid,
 941         .get_modes = intel_crt_get_modes,
 942 };
 943
 944 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 945         .reset = intel_crt_reset,
 946         .destroy = intel_encoder_destroy,
 947 };
 948
 949 void intel_crt_init(struct drm_i915_private *dev_priv)
 950 {
 951         struct drm_connector *connector;
 952         struct intel_crt *crt;
 953         struct intel_connector *intel_connector;
 954         i915_reg_t adpa_reg;
 955         u32 adpa;
 956
 957         if (HAS_PCH_SPLIT(dev_priv))
 958                 adpa_reg = PCH_ADPA;
 959         else if (IS_VALLEYVIEW(dev_priv))
 960                 adpa_reg = VLV_ADPA;
 961         else
 962                 adpa_reg = ADPA;
 963
 964         adpa = I915_READ(adpa_reg);
 965         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 966                 /*
 967                  * On some machines (some IVB at least) CRT can be
 968                  * fused off, but there's no known fuse bit to
 969                  * indicate that. On these machine the ADPA register
 970                  * works normally, except the DAC enable bit won't
 971                  * take. So the only way to tell is attempt to enable
 972                  * it and see what happens.
 973                  */
 974                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 975                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 976                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 977                         return;
 978                 I915_WRITE(adpa_reg, adpa);
 979         }
 980
 981         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 982         if (!crt)
 983                 return;
 984
 985         intel_connector = intel_connector_alloc();
 986         if (!intel_connector) {
 987                 kfree(crt);
 988                 return;
 989         }
 990
 991         connector = &intel_connector->base;
 992         crt->connector = intel_connector;
 993         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 994                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 995
 996         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 997                          DRM_MODE_ENCODER_DAC, "CRT");
 998
 999         intel_connector_attach_encoder(intel_connector, &crt->base);
1000
1001         crt->base.type = INTEL_OUTPUT_ANALOG;
1002         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1003         if (IS_I830(dev_priv))
1004                 crt->base.pipe_mask = BIT(PIPE_A);
1005         else
1006                 crt->base.pipe_mask = ~0;
1007
1008         if (IS_GEN(dev_priv, 2))
1009                 connector->interlace_allowed = 0;
1010         else
1011                 connector->interlace_allowed = 1;
1012         connector->doublescan_allowed = 0;
1013
1014         crt->adpa_reg = adpa_reg;
1015
1016         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1017
1018         if (I915_HAS_HOTPLUG(dev_priv) &&
1019             !dmi_check_system(intel_spurious_crt_detect)) {
1020                 crt->base.hpd_pin = HPD_CRT;
1021                 crt->base.hotplug = intel_encoder_hotplug;
1022         }
1023
1024         if (HAS_DDI(dev_priv)) {
1025                 crt->base.port = PORT_E;
1026                 crt->base.get_config = hsw_crt_get_config;
1027                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1028                 crt->base.compute_config = hsw_crt_compute_config;
1029                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1030                 crt->base.pre_enable = hsw_pre_enable_crt;
1031                 crt->base.enable = hsw_enable_crt;
1032                 crt->base.disable = hsw_disable_crt;
1033                 crt->base.post_disable = hsw_post_disable_crt;
1034         } else {
1035                 if (HAS_PCH_SPLIT(dev_priv)) {
1036                         crt->base.compute_config = pch_crt_compute_config;
1037                         crt->base.disable = pch_disable_crt;
1038                         crt->base.post_disable = pch_post_disable_crt;
1039                 } else {
1040                         crt->base.compute_config = intel_crt_compute_config;
1041                         crt->base.disable = intel_disable_crt;
1042                 }
1043                 crt->base.port = PORT_NONE;
1044                 crt->base.get_config = intel_crt_get_config;
1045                 crt->base.get_hw_state = intel_crt_get_hw_state;
1046                 crt->base.enable = intel_enable_crt;
1047         }
1048         intel_connector->get_hw_state = intel_connector_get_hw_state;
1049
1050         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1051
1052         if (!I915_HAS_HOTPLUG(dev_priv))
1053                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1054
1055         /*
1056          * Configure the automatic hotplug detection stuff
1057          */
1058         crt->force_hotplug_required = 0;
1059
1060         /*
1061          * TODO: find a proper way to discover whether we need to set the the
1062          * polarity and link reversal bits or not, instead of relying on the
1063          * BIOS.
1064          */
1065         if (HAS_PCH_LPT(dev_priv)) {
1066                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1067                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1068
1069                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1070         }
1071
1072         intel_crt_reset(&crt->base.base);
1073 }