drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include <linux/hmm.h>
  47 #include "amdgpu.h"
  48 #include "amdgpu_object.h"
  49 #include "amdgpu_trace.h"
  50 #include "amdgpu_amdkfd.h"
  51 #include "amdgpu_sdma.h"
  52 #include "bif/bif_4_1_d.h"
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  64 {
  65         return 0;
  66 }
  67
  68 /**
  69  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  70  * memory request.
  71  *
  72  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  73  * @type: The type of memory requested
  74  * @man: The memory type manager for each domain
  75  *
  76  * This is called by ttm_bo_init_mm() when a buffer object is being
  77  * initialized.
  78  */
  79 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  80                                 struct ttm_mem_type_manager *man)
  81 {
  82         struct amdgpu_device *adev;
  83
  84         adev = amdgpu_ttm_adev(bdev);
  85
  86         switch (type) {
  87         case TTM_PL_SYSTEM:
  88                 /* System memory */
  89                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  90                 man->available_caching = TTM_PL_MASK_CACHING;
  91                 man->default_caching = TTM_PL_FLAG_CACHED;
  92                 break;
  93         case TTM_PL_TT:
  94                 /* GTT memory  */
  95                 man->func = &amdgpu_gtt_mgr_func;
  96                 man->gpu_offset = adev->gmc.gart_start;
  97                 man->available_caching = TTM_PL_MASK_CACHING;
  98                 man->default_caching = TTM_PL_FLAG_CACHED;
  99                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 100                 break;
 101         case TTM_PL_VRAM:
 102                 /* "On-card" video ram */
 103                 man->func = &amdgpu_vram_mgr_func;
 104                 man->gpu_offset = adev->gmc.vram_start;
 105                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 106                              TTM_MEMTYPE_FLAG_MAPPABLE;
 107                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 108                 man->default_caching = TTM_PL_FLAG_WC;
 109                 break;
 110         case AMDGPU_PL_GDS:
 111         case AMDGPU_PL_GWS:
 112         case AMDGPU_PL_OA:
 113                 /* On-chip GDS memory*/
 114                 man->func = &ttm_bo_manager_func;
 115                 man->gpu_offset = 0;
 116                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 117                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 118                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 119                 break;
 120         default:
 121                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 122                 return -EINVAL;
 123         }
 124         return 0;
 125 }
 126
 127 /**
 128  * amdgpu_evict_flags - Compute placement flags
 129  *
 130  * @bo: The buffer object to evict
 131  * @placement: Possible destination(s) for evicted BO
 132  *
 133  * Fill in placement data when ttm_bo_evict() is called
 134  */
 135 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 136                                 struct ttm_placement *placement)
 137 {
 138         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 139         struct amdgpu_bo *abo;
 140         static const struct ttm_place placements = {
 141                 .fpfn = 0,
 142                 .lpfn = 0,
 143                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 144         };
 145
 146         /* Don't handle scatter gather BOs */
 147         if (bo->type == ttm_bo_type_sg) {
 148                 placement->num_placement = 0;
 149                 placement->num_busy_placement = 0;
 150                 return;
 151         }
 152
 153         /* Object isn't an AMDGPU object so ignore */
 154         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 155                 placement->placement = &placements;
 156                 placement->busy_placement = &placements;
 157                 placement->num_placement = 1;
 158                 placement->num_busy_placement = 1;
 159                 return;
 160         }
 161
 162         abo = ttm_to_amdgpu_bo(bo);
 163         switch (bo->mem.mem_type) {
 164         case AMDGPU_PL_GDS:
 165         case AMDGPU_PL_GWS:
 166         case AMDGPU_PL_OA:
 167                 placement->num_placement = 0;
 168                 placement->num_busy_placement = 0;
 169                 return;
 170
 171         case TTM_PL_VRAM:
 172                 if (!adev->mman.buffer_funcs_enabled) {
 173                         /* Move to system memory */
 174                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 175                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 176                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 177                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 178
 179                         /* Try evicting to the CPU inaccessible part of VRAM
 180                          * first, but only set GTT as busy placement, so this
 181                          * BO will be evicted to GTT rather than causing other
 182                          * BOs to be evicted from VRAM
 183                          */
 184                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 185                                                          AMDGPU_GEM_DOMAIN_GTT);
 186                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 187                         abo->placements[0].lpfn = 0;
 188                         abo->placement.busy_placement = &abo->placements[1];
 189                         abo->placement.num_busy_placement = 1;
 190                 } else {
 191                         /* Move to GTT memory */
 192                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 193                 }
 194                 break;
 195         case TTM_PL_TT:
 196         default:
 197                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 198                 break;
 199         }
 200         *placement = abo->placement;
 201 }
 202
 203 /**
 204  * amdgpu_verify_access - Verify access for a mmap call
 205  *
 206  * @bo: The buffer object to map
 207  * @filp: The file pointer from the process performing the mmap
 208  *
 209  * This is called by ttm_bo_mmap() to verify whether a process
 210  * has the right to mmap a BO to their process space.
 211  */
 212 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 213 {
 214         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 215
 216         /*
 217          * Don't verify access for KFD BOs. They don't have a GEM
 218          * object associated with them.
 219          */
 220         if (abo->kfd_bo)
 221                 return 0;
 222
 223         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 224                 return -EPERM;
 225         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 226                                           filp->private_data);
 227 }
 228
 229 /**
 230  * amdgpu_move_null - Register memory for a buffer object
 231  *
 232  * @bo: The bo to assign the memory to
 233  * @new_mem: The memory to be assigned.
 234  *
 235  * Assign the memory from new_mem to the memory of the buffer object bo.
 236  */
 237 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 238                              struct ttm_mem_reg *new_mem)
 239 {
 240         struct ttm_mem_reg *old_mem = &bo->mem;
 241
 242         BUG_ON(old_mem->mm_node != NULL);
 243         *old_mem = *new_mem;
 244         new_mem->mm_node = NULL;
 245 }
 246
 247 /**
 248  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 249  *
 250  * @bo: The bo to assign the memory to.
 251  * @mm_node: Memory manager node for drm allocator.
 252  * @mem: The region where the bo resides.
 253  *
 254  */
 255 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 256                                     struct drm_mm_node *mm_node,
 257                                     struct ttm_mem_reg *mem)
 258 {
 259         uint64_t addr = 0;
 260
 261         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 262                 addr = mm_node->start << PAGE_SHIFT;
 263                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 264         }
 265         return addr;
 266 }
 267
 268 /**
 269  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 270  * @offset. It also modifies the offset to be within the drm_mm_node returned
 271  *
 272  * @mem: The region where the bo resides.
 273  * @offset: The offset that drm_mm_node is used for finding.
 274  *
 275  */
 276 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 277                                                unsigned long *offset)
 278 {
 279         struct drm_mm_node *mm_node = mem->mm_node;
 280
 281         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 282                 *offset -= (mm_node->size << PAGE_SHIFT);
 283                 ++mm_node;
 284         }
 285         return mm_node;
 286 }
 287
 288 /**
 289  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 290  *
 291  * The function copies @size bytes from {src->mem + src->offset} to
 292  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 293  * move and different for a BO to BO copy.
 294  *
 295  * @f: Returns the last fence if multiple jobs are submitted.
 296  */
 297 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 298                                struct amdgpu_copy_mem *src,
 299                                struct amdgpu_copy_mem *dst,
 300                                uint64_t size,
 301                                struct reservation_object *resv,
 302                                struct dma_fence **f)
 303 {
 304         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 305         struct drm_mm_node *src_mm, *dst_mm;
 306         uint64_t src_node_start, dst_node_start, src_node_size,
 307                  dst_node_size, src_page_offset, dst_page_offset;
 308         struct dma_fence *fence = NULL;
 309         int r = 0;
 310         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 311                                         AMDGPU_GPU_PAGE_SIZE);
 312
 313         if (!adev->mman.buffer_funcs_enabled) {
 314                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 315                 return -EINVAL;
 316         }
 317
 318         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 319         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 320                                              src->offset;
 321         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 322         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 323
 324         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 325         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 326                                              dst->offset;
 327         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 328         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 329
 330         mutex_lock(&adev->mman.gtt_window_lock);
 331
 332         while (size) {
 333                 unsigned long cur_size;
 334                 uint64_t from = src_node_start, to = dst_node_start;
 335                 struct dma_fence *next;
 336
 337                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 338                  * begins at an offset, then adjust the size accordingly
 339                  */
 340                 cur_size = min3(min(src_node_size, dst_node_size), size,
 341                                 GTT_MAX_BYTES);
 342                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 343                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 344                         cur_size -= max(src_page_offset, dst_page_offset);
 345
 346                 /* Map only what needs to be accessed. Map src to window 0 and
 347                  * dst to window 1
 348                  */
 349                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 350                         r = amdgpu_map_buffer(src->bo, src->mem,
 351                                         PFN_UP(cur_size + src_page_offset),
 352                                         src_node_start, 0, ring,
 353                                         &from);
 354                         if (r)
 355                                 goto error;
 356                         /* Adjust the offset because amdgpu_map_buffer returns
 357                          * start of mapped page
 358                          */
 359                         from += src_page_offset;
 360                 }
 361
 362                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 363                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 364                                         PFN_UP(cur_size + dst_page_offset),
 365                                         dst_node_start, 1, ring,
 366                                         &to);
 367                         if (r)
 368                                 goto error;
 369                         to += dst_page_offset;
 370                 }
 371
 372                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 373                                        resv, &next, false, true);
 374                 if (r)
 375                         goto error;
 376
 377                 dma_fence_put(fence);
 378                 fence = next;
 379
 380                 size -= cur_size;
 381                 if (!size)
 382                         break;
 383
 384                 src_node_size -= cur_size;
 385                 if (!src_node_size) {
 386                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 387                                                              src->mem);
 388                         src_node_size = (src_mm->size << PAGE_SHIFT);
 389                 } else {
 390                         src_node_start += cur_size;
 391                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 392                 }
 393                 dst_node_size -= cur_size;
 394                 if (!dst_node_size) {
 395                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 396                                                              dst->mem);
 397                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 398                 } else {
 399                         dst_node_start += cur_size;
 400                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 401                 }
 402         }
 403 error:
 404         mutex_unlock(&adev->mman.gtt_window_lock);
 405         if (f)
 406                 *f = dma_fence_get(fence);
 407         dma_fence_put(fence);
 408         return r;
 409 }
 410
 411 /**
 412  * amdgpu_move_blit - Copy an entire buffer to another buffer
 413  *
 414  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 415  * help move buffers to and from VRAM.
 416  */
 417 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 418                             bool evict, bool no_wait_gpu,
 419                             struct ttm_mem_reg *new_mem,
 420                             struct ttm_mem_reg *old_mem)
 421 {
 422         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 423         struct amdgpu_copy_mem src, dst;
 424         struct dma_fence *fence = NULL;
 425         int r;
 426
 427         src.bo = bo;
 428         dst.bo = bo;
 429         src.mem = old_mem;
 430         dst.mem = new_mem;
 431         src.offset = 0;
 432         dst.offset = 0;
 433
 434         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 435                                        new_mem->num_pages << PAGE_SHIFT,
 436                                        bo->resv, &fence);
 437         if (r)
 438                 goto error;
 439
 440         /* Always block for VM page tables before committing the new location */
 441         if (bo->type == ttm_bo_type_kernel)
 442                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 443         else
 444                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 445         dma_fence_put(fence);
 446         return r;
 447
 448 error:
 449         if (fence)
 450                 dma_fence_wait(fence, false);
 451         dma_fence_put(fence);
 452         return r;
 453 }
 454
 455 /**
 456  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 457  *
 458  * Called by amdgpu_bo_move().
 459  */
 460 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 461                                 struct ttm_operation_ctx *ctx,
 462                                 struct ttm_mem_reg *new_mem)
 463 {
 464         struct amdgpu_device *adev;
 465         struct ttm_mem_reg *old_mem = &bo->mem;
 466         struct ttm_mem_reg tmp_mem;
 467         struct ttm_place placements;
 468         struct ttm_placement placement;
 469         int r;
 470
 471         adev = amdgpu_ttm_adev(bo->bdev);
 472
 473         /* create space/pages for new_mem in GTT space */
 474         tmp_mem = *new_mem;
 475         tmp_mem.mm_node = NULL;
 476         placement.num_placement = 1;
 477         placement.placement = &placements;
 478         placement.num_busy_placement = 1;
 479         placement.busy_placement = &placements;
 480         placements.fpfn = 0;
 481         placements.lpfn = 0;
 482         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 483         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 484         if (unlikely(r)) {
 485                 return r;
 486         }
 487
 488         /* set caching flags */
 489         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 490         if (unlikely(r)) {
 491                 goto out_cleanup;
 492         }
 493
 494         /* Bind the memory to the GTT space */
 495         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 496         if (unlikely(r)) {
 497                 goto out_cleanup;
 498         }
 499
 500         /* blit VRAM to GTT */
 501         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 502         if (unlikely(r)) {
 503                 goto out_cleanup;
 504         }
 505
 506         /* move BO (in tmp_mem) to new_mem */
 507         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 508 out_cleanup:
 509         ttm_bo_mem_put(bo, &tmp_mem);
 510         return r;
 511 }
 512
 513 /**
 514  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 515  *
 516  * Called by amdgpu_bo_move().
 517  */
 518 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 519                                 struct ttm_operation_ctx *ctx,
 520                                 struct ttm_mem_reg *new_mem)
 521 {
 522         struct amdgpu_device *adev;
 523         struct ttm_mem_reg *old_mem = &bo->mem;
 524         struct ttm_mem_reg tmp_mem;
 525         struct ttm_placement placement;
 526         struct ttm_place placements;
 527         int r;
 528
 529         adev = amdgpu_ttm_adev(bo->bdev);
 530
 531         /* make space in GTT for old_mem buffer */
 532         tmp_mem = *new_mem;
 533         tmp_mem.mm_node = NULL;
 534         placement.num_placement = 1;
 535         placement.placement = &placements;
 536         placement.num_busy_placement = 1;
 537         placement.busy_placement = &placements;
 538         placements.fpfn = 0;
 539         placements.lpfn = 0;
 540         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 541         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 542         if (unlikely(r)) {
 543                 return r;
 544         }
 545
 546         /* move/bind old memory to GTT space */
 547         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 548         if (unlikely(r)) {
 549                 goto out_cleanup;
 550         }
 551
 552         /* copy to VRAM */
 553         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 554         if (unlikely(r)) {
 555                 goto out_cleanup;
 556         }
 557 out_cleanup:
 558         ttm_bo_mem_put(bo, &tmp_mem);
 559         return r;
 560 }
 561
 562 /**
 563  * amdgpu_bo_move - Move a buffer object to a new memory location
 564  *
 565  * Called by ttm_bo_handle_move_mem()
 566  */
 567 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 568                           struct ttm_operation_ctx *ctx,
 569                           struct ttm_mem_reg *new_mem)
 570 {
 571         struct amdgpu_device *adev;
 572         struct amdgpu_bo *abo;
 573         struct ttm_mem_reg *old_mem = &bo->mem;
 574         int r;
 575
 576         /* Can't move a pinned BO */
 577         abo = ttm_to_amdgpu_bo(bo);
 578         if (WARN_ON_ONCE(abo->pin_count > 0))
 579                 return -EINVAL;
 580
 581         adev = amdgpu_ttm_adev(bo->bdev);
 582
 583         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 584                 amdgpu_move_null(bo, new_mem);
 585                 return 0;
 586         }
 587         if ((old_mem->mem_type == TTM_PL_TT &&
 588              new_mem->mem_type == TTM_PL_SYSTEM) ||
 589             (old_mem->mem_type == TTM_PL_SYSTEM &&
 590              new_mem->mem_type == TTM_PL_TT)) {
 591                 /* bind is enough */
 592                 amdgpu_move_null(bo, new_mem);
 593                 return 0;
 594         }
 595         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 596             old_mem->mem_type == AMDGPU_PL_GWS ||
 597             old_mem->mem_type == AMDGPU_PL_OA ||
 598             new_mem->mem_type == AMDGPU_PL_GDS ||
 599             new_mem->mem_type == AMDGPU_PL_GWS ||
 600             new_mem->mem_type == AMDGPU_PL_OA) {
 601                 /* Nothing to save here */
 602                 amdgpu_move_null(bo, new_mem);
 603                 return 0;
 604         }
 605
 606         if (!adev->mman.buffer_funcs_enabled)
 607                 goto memcpy;
 608
 609         if (old_mem->mem_type == TTM_PL_VRAM &&
 610             new_mem->mem_type == TTM_PL_SYSTEM) {
 611                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 612         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 613                    new_mem->mem_type == TTM_PL_VRAM) {
 614                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 615         } else {
 616                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 617                                      new_mem, old_mem);
 618         }
 619
 620         if (r) {
 621 memcpy:
 622                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 623                 if (r) {
 624                         return r;
 625                 }
 626         }
 627
 628         if (bo->type == ttm_bo_type_device &&
 629             new_mem->mem_type == TTM_PL_VRAM &&
 630             old_mem->mem_type != TTM_PL_VRAM) {
 631                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 632                  * accesses the BO after it's moved.
 633                  */
 634                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 635         }
 636
 637         /* update statistics */
 638         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 639         return 0;
 640 }
 641
 642 /**
 643  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 644  *
 645  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 646  */
 647 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 648 {
 649         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 650         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 651         struct drm_mm_node *mm_node = mem->mm_node;
 652
 653         mem->bus.addr = NULL;
 654         mem->bus.offset = 0;
 655         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 656         mem->bus.base = 0;
 657         mem->bus.is_iomem = false;
 658         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 659                 return -EINVAL;
 660         switch (mem->mem_type) {
 661         case TTM_PL_SYSTEM:
 662                 /* system memory */
 663                 return 0;
 664         case TTM_PL_TT:
 665                 break;
 666         case TTM_PL_VRAM:
 667                 mem->bus.offset = mem->start << PAGE_SHIFT;
 668                 /* check if it's visible */
 669                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 670                         return -EINVAL;
 671                 /* Only physically contiguous buffers apply. In a contiguous
 672                  * buffer, size of the first mm_node would match the number of
 673                  * pages in ttm_mem_reg.
 674                  */
 675                 if (adev->mman.aper_base_kaddr &&
 676                     (mm_node->size == mem->num_pages))
 677                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 678                                         mem->bus.offset;
 679
 680                 mem->bus.base = adev->gmc.aper_base;
 681                 mem->bus.is_iomem = true;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686         return 0;
 687 }
 688
 689 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 690 {
 691 }
 692
 693 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 694                                            unsigned long page_offset)
 695 {
 696         struct drm_mm_node *mm;
 697         unsigned long offset = (page_offset << PAGE_SHIFT);
 698
 699         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 700         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 701                 (offset >> PAGE_SHIFT);
 702 }
 703
 704 /*
 705  * TTM backend functions.
 706  */
 707 struct amdgpu_ttm_tt {
 708         struct ttm_dma_tt       ttm;
 709         u64                     offset;
 710         uint64_t                userptr;
 711         struct task_struct      *usertask;
 712         uint32_t                userflags;
 713 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 714         struct hmm_range        *ranges;
 715         int                     nr_ranges;
 716 #endif
 717 };
 718
 719 /**
 720  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 721  * memory and start HMM tracking CPU page table update
 722  *
 723  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 724  * once afterwards to stop HMM tracking
 725  */
 726 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 727
 728 /* Support Userptr pages cross max 16 vmas */
 729 #define MAX_NR_VMAS     (16)
 730
 731 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 732 {
 733         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 734         struct mm_struct *mm = gtt->usertask->mm;
 735         unsigned long start = gtt->userptr;
 736         unsigned long end = start + ttm->num_pages * PAGE_SIZE;
 737         struct vm_area_struct *vma = NULL, *vmas[MAX_NR_VMAS];
 738         struct hmm_range *ranges;
 739         unsigned long nr_pages, i;
 740         uint64_t *pfns, f;
 741         int r = 0;
 742
 743         if (!mm) /* Happens during process shutdown */
 744                 return -ESRCH;
 745
 746         down_read(&mm->mmap_sem);
 747
 748         /* user pages may cross multiple VMAs */
 749         gtt->nr_ranges = 0;
 750         do {
 751                 unsigned long vm_start;
 752
 753                 if (gtt->nr_ranges >= MAX_NR_VMAS) {
 754                         DRM_ERROR("Too many VMAs in userptr range\n");
 755                         r = -EFAULT;
 756                         goto out;
 757                 }
 758
 759                 vm_start = vma ? vma->vm_end : start;
 760                 vma = find_vma(mm, vm_start);
 761                 if (unlikely(!vma || vm_start < vma->vm_start)) {
 762                         r = -EFAULT;
 763                         goto out;
 764                 }
 765                 vmas[gtt->nr_ranges++] = vma;
 766         } while (end > vma->vm_end);
 767
 768         DRM_DEBUG_DRIVER("0x%lx nr_ranges %d pages 0x%lx\n",
 769                 start, gtt->nr_ranges, ttm->num_pages);
 770
 771         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 772                 vmas[0]->vm_file)) {
 773                 r = -EPERM;
 774                 goto out;
 775         }
 776
 777         ranges = kvmalloc_array(gtt->nr_ranges, sizeof(*ranges), GFP_KERNEL);
 778         if (unlikely(!ranges)) {
 779                 r = -ENOMEM;
 780                 goto out;
 781         }
 782
 783         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 784         if (unlikely(!pfns)) {
 785                 r = -ENOMEM;
 786                 goto out_free_ranges;
 787         }
 788
 789         for (i = 0; i < gtt->nr_ranges; i++)
 790                 amdgpu_hmm_init_range(&ranges[i]);
 791
 792         f = ranges[0].flags[HMM_PFN_VALID];
 793         f |= amdgpu_ttm_tt_is_readonly(ttm) ?
 794                                 0 : ranges[0].flags[HMM_PFN_WRITE];
 795         memset64(pfns, f, ttm->num_pages);
 796
 797         for (nr_pages = 0, i = 0; i < gtt->nr_ranges; i++) {
 798                 ranges[i].vma = vmas[i];
 799                 ranges[i].start = max(start, vmas[i]->vm_start);
 800                 ranges[i].end = min(end, vmas[i]->vm_end);
 801                 ranges[i].pfns = pfns + nr_pages;
 802                 nr_pages += (ranges[i].end - ranges[i].start) / PAGE_SIZE;
 803
 804                 r = hmm_vma_fault(&ranges[i], true);
 805                 if (unlikely(r))
 806                         break;
 807         }
 808         if (unlikely(r)) {
 809                 while (i--)
 810                         hmm_vma_range_done(&ranges[i]);
 811
 812                 goto out_free_pfns;
 813         }
 814
 815         up_read(&mm->mmap_sem);
 816
 817         for (i = 0; i < ttm->num_pages; i++) {
 818                 pages[i] = hmm_pfn_to_page(&ranges[0], pfns[i]);
 819                 if (!pages[i]) {
 820                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 821                                i, pfns[i]);
 822                         goto out_invalid_pfn;
 823                 }
 824         }
 825         gtt->ranges = ranges;
 826
 827         return 0;
 828
 829 out_free_pfns:
 830         kvfree(pfns);
 831 out_free_ranges:
 832         kvfree(ranges);
 833 out:
 834         up_read(&mm->mmap_sem);
 835
 836         return r;
 837
 838 out_invalid_pfn:
 839         for (i = 0; i < gtt->nr_ranges; i++)
 840                 hmm_vma_range_done(&ranges[i]);
 841         kvfree(pfns);
 842         kvfree(ranges);
 843         return -ENOMEM;
 844 }
 845
 846 /**
 847  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 848  * Check if the pages backing this ttm range have been invalidated
 849  *
 850  * Returns: true if pages are still valid
 851  */
 852 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 853 {
 854         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 855         bool r = false;
 856         int i;
 857
 858         if (!gtt || !gtt->userptr)
 859                 return false;
 860
 861         DRM_DEBUG_DRIVER("user_pages_done 0x%llx nr_ranges %d pages 0x%lx\n",
 862                 gtt->userptr, gtt->nr_ranges, ttm->num_pages);
 863
 864         WARN_ONCE(!gtt->ranges || !gtt->ranges[0].pfns,
 865                 "No user pages to check\n");
 866
 867         if (gtt->ranges) {
 868                 for (i = 0; i < gtt->nr_ranges; i++)
 869                         r |= hmm_vma_range_done(&gtt->ranges[i]);
 870                 kvfree(gtt->ranges[0].pfns);
 871                 kvfree(gtt->ranges);
 872                 gtt->ranges = NULL;
 873         }
 874
 875         return r;
 876 }
 877 #endif
 878
 879 /**
 880  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 881  *
 882  * Called by amdgpu_cs_list_validate(). This creates the page list
 883  * that backs user memory and will ultimately be mapped into the device
 884  * address space.
 885  */
 886 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 887 {
 888         unsigned long i;
 889
 890         for (i = 0; i < ttm->num_pages; ++i)
 891                 ttm->pages[i] = pages ? pages[i] : NULL;
 892 }
 893
 894 /**
 895  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 896  *
 897  * Called by amdgpu_ttm_backend_bind()
 898  **/
 899 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 900 {
 901         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 902         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 903         unsigned nents;
 904         int r;
 905
 906         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 907         enum dma_data_direction direction = write ?
 908                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 909
 910         /* Allocate an SG array and squash pages into it */
 911         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 912                                       ttm->num_pages << PAGE_SHIFT,
 913                                       GFP_KERNEL);
 914         if (r)
 915                 goto release_sg;
 916
 917         /* Map SG to device */
 918         r = -ENOMEM;
 919         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 920         if (nents != ttm->sg->nents)
 921                 goto release_sg;
 922
 923         /* convert SG to linear array of pages and dma addresses */
 924         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 925                                          gtt->ttm.dma_address, ttm->num_pages);
 926
 927         return 0;
 928
 929 release_sg:
 930         kfree(ttm->sg);
 931         return r;
 932 }
 933
 934 /**
 935  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 936  */
 937 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 938 {
 939         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 940         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 941
 942         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 943         enum dma_data_direction direction = write ?
 944                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 945
 946         /* double check that we don't free the table twice */
 947         if (!ttm->sg->sgl)
 948                 return;
 949
 950         /* unmap the pages mapped to the device */
 951         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 952
 953         sg_free_table(ttm->sg);
 954
 955 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 956         if (gtt->ranges &&
 957             ttm->pages[0] == hmm_pfn_to_page(&gtt->ranges[0],
 958                                              gtt->ranges[0].pfns[0]))
 959                 WARN_ONCE(1, "Missing get_user_page_done\n");
 960 #endif
 961 }
 962
 963 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 964                                 struct ttm_buffer_object *tbo,
 965                                 uint64_t flags)
 966 {
 967         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 968         struct ttm_tt *ttm = tbo->ttm;
 969         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 970         int r;
 971
 972         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 973                 uint64_t page_idx = 1;
 974
 975                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 976                                 ttm->pages, gtt->ttm.dma_address, flags);
 977                 if (r)
 978                         goto gart_bind_fail;
 979
 980                 /* Patch mtype of the second part BO */
 981                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
 982                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
 983
 984                 r = amdgpu_gart_bind(adev,
 985                                 gtt->offset + (page_idx << PAGE_SHIFT),
 986                                 ttm->num_pages - page_idx,
 987                                 &ttm->pages[page_idx],
 988                                 &(gtt->ttm.dma_address[page_idx]), flags);
 989         } else {
 990                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 991                                      ttm->pages, gtt->ttm.dma_address, flags);
 992         }
 993
 994 gart_bind_fail:
 995         if (r)
 996                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 997                           ttm->num_pages, gtt->offset);
 998
 999         return r;
1000 }
1001
1002 /**
1003  * amdgpu_ttm_backend_bind - Bind GTT memory
1004  *
1005  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1006  * This handles binding GTT memory to the device address space.
1007  */
1008 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1009                                    struct ttm_mem_reg *bo_mem)
1010 {
1011         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1012         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1013         uint64_t flags;
1014         int r = 0;
1015
1016         if (gtt->userptr) {
1017                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1018                 if (r) {
1019                         DRM_ERROR("failed to pin userptr\n");
1020                         return r;
1021                 }
1022         }
1023         if (!ttm->num_pages) {
1024                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1025                      ttm->num_pages, bo_mem, ttm);
1026         }
1027
1028         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1029             bo_mem->mem_type == AMDGPU_PL_GWS ||
1030             bo_mem->mem_type == AMDGPU_PL_OA)
1031                 return -EINVAL;
1032
1033         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1034                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1035                 return 0;
1036         }
1037
1038         /* compute PTE flags relevant to this BO memory */
1039         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1040
1041         /* bind pages into GART page tables */
1042         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1043         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1044                 ttm->pages, gtt->ttm.dma_address, flags);
1045
1046         if (r)
1047                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1048                           ttm->num_pages, gtt->offset);
1049         return r;
1050 }
1051
1052 /**
1053  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1054  */
1055 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1056 {
1057         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1058         struct ttm_operation_ctx ctx = { false, false };
1059         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1060         struct ttm_mem_reg tmp;
1061         struct ttm_placement placement;
1062         struct ttm_place placements;
1063         uint64_t addr, flags;
1064         int r;
1065
1066         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1067                 return 0;
1068
1069         addr = amdgpu_gmc_agp_addr(bo);
1070         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1071                 bo->mem.start = addr >> PAGE_SHIFT;
1072         } else {
1073
1074                 /* allocate GART space */
1075                 tmp = bo->mem;
1076                 tmp.mm_node = NULL;
1077                 placement.num_placement = 1;
1078                 placement.placement = &placements;
1079                 placement.num_busy_placement = 1;
1080                 placement.busy_placement = &placements;
1081                 placements.fpfn = 0;
1082                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1083                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1084                         TTM_PL_FLAG_TT;
1085
1086                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1087                 if (unlikely(r))
1088                         return r;
1089
1090                 /* compute PTE flags for this buffer object */
1091                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1092
1093                 /* Bind pages */
1094                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1095                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1096                 if (unlikely(r)) {
1097                         ttm_bo_mem_put(bo, &tmp);
1098                         return r;
1099                 }
1100
1101                 ttm_bo_mem_put(bo, &bo->mem);
1102                 bo->mem = tmp;
1103         }
1104
1105         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1106                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1107
1108         return 0;
1109 }
1110
1111 /**
1112  * amdgpu_ttm_recover_gart - Rebind GTT pages
1113  *
1114  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1115  * rebind GTT pages during a GPU reset.
1116  */
1117 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1118 {
1119         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1120         uint64_t flags;
1121         int r;
1122
1123         if (!tbo->ttm)
1124                 return 0;
1125
1126         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1127         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1128
1129         return r;
1130 }
1131
1132 /**
1133  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1134  *
1135  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1136  * ttm_tt_destroy().
1137  */
1138 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1139 {
1140         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1141         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1142         int r;
1143
1144         /* if the pages have userptr pinning then clear that first */
1145         if (gtt->userptr)
1146                 amdgpu_ttm_tt_unpin_userptr(ttm);
1147
1148         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1149                 return 0;
1150
1151         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1152         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1153         if (r)
1154                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1155                           gtt->ttm.ttm.num_pages, gtt->offset);
1156         return r;
1157 }
1158
1159 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1160 {
1161         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1162
1163         if (gtt->usertask)
1164                 put_task_struct(gtt->usertask);
1165
1166         ttm_dma_tt_fini(&gtt->ttm);
1167         kfree(gtt);
1168 }
1169
1170 static struct ttm_backend_func amdgpu_backend_func = {
1171         .bind = &amdgpu_ttm_backend_bind,
1172         .unbind = &amdgpu_ttm_backend_unbind,
1173         .destroy = &amdgpu_ttm_backend_destroy,
1174 };
1175
1176 /**
1177  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1178  *
1179  * @bo: The buffer object to create a GTT ttm_tt object around
1180  *
1181  * Called by ttm_tt_create().
1182  */
1183 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1184                                            uint32_t page_flags)
1185 {
1186         struct amdgpu_device *adev;
1187         struct amdgpu_ttm_tt *gtt;
1188
1189         adev = amdgpu_ttm_adev(bo->bdev);
1190
1191         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1192         if (gtt == NULL) {
1193                 return NULL;
1194         }
1195         gtt->ttm.ttm.func = &amdgpu_backend_func;
1196
1197         /* allocate space for the uninitialized page entries */
1198         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1199                 kfree(gtt);
1200                 return NULL;
1201         }
1202         return &gtt->ttm.ttm;
1203 }
1204
1205 /**
1206  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1207  *
1208  * Map the pages of a ttm_tt object to an address space visible
1209  * to the underlying device.
1210  */
1211 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1212                         struct ttm_operation_ctx *ctx)
1213 {
1214         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1215         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1216         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1217
1218         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1219         if (gtt && gtt->userptr) {
1220                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1221                 if (!ttm->sg)
1222                         return -ENOMEM;
1223
1224                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1225                 ttm->state = tt_unbound;
1226                 return 0;
1227         }
1228
1229         if (slave && ttm->sg) {
1230                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1231                                                  gtt->ttm.dma_address,
1232                                                  ttm->num_pages);
1233                 ttm->state = tt_unbound;
1234                 return 0;
1235         }
1236
1237 #ifdef CONFIG_SWIOTLB
1238         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1239                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1240         }
1241 #endif
1242
1243         /* fall back to generic helper to populate the page array
1244          * and map them to the device */
1245         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1246 }
1247
1248 /**
1249  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1250  *
1251  * Unmaps pages of a ttm_tt object from the device address space and
1252  * unpopulates the page array backing it.
1253  */
1254 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1255 {
1256         struct amdgpu_device *adev;
1257         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1258         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1259
1260         if (gtt && gtt->userptr) {
1261                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1262                 kfree(ttm->sg);
1263                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1264                 return;
1265         }
1266
1267         if (slave)
1268                 return;
1269
1270         adev = amdgpu_ttm_adev(ttm->bdev);
1271
1272 #ifdef CONFIG_SWIOTLB
1273         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1274                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1275                 return;
1276         }
1277 #endif
1278
1279         /* fall back to generic helper to unmap and unpopulate array */
1280         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1281 }
1282
1283 /**
1284  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1285  * task
1286  *
1287  * @ttm: The ttm_tt object to bind this userptr object to
1288  * @addr:  The address in the current tasks VM space to use
1289  * @flags: Requirements of userptr object.
1290  *
1291  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1292  * to current task
1293  */
1294 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1295                               uint32_t flags)
1296 {
1297         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1298
1299         if (gtt == NULL)
1300                 return -EINVAL;
1301
1302         gtt->userptr = addr;
1303         gtt->userflags = flags;
1304
1305         if (gtt->usertask)
1306                 put_task_struct(gtt->usertask);
1307         gtt->usertask = current->group_leader;
1308         get_task_struct(gtt->usertask);
1309
1310         return 0;
1311 }
1312
1313 /**
1314  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1315  */
1316 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1317 {
1318         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1319
1320         if (gtt == NULL)
1321                 return NULL;
1322
1323         if (gtt->usertask == NULL)
1324                 return NULL;
1325
1326         return gtt->usertask->mm;
1327 }
1328
1329 /**
1330  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1331  * address range for the current task.
1332  *
1333  */
1334 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1335                                   unsigned long end)
1336 {
1337         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1338         unsigned long size;
1339
1340         if (gtt == NULL || !gtt->userptr)
1341                 return false;
1342
1343         /* Return false if no part of the ttm_tt object lies within
1344          * the range
1345          */
1346         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1347         if (gtt->userptr > end || gtt->userptr + size <= start)
1348                 return false;
1349
1350         return true;
1351 }
1352
1353 /**
1354  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1355  */
1356 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1357 {
1358         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1359
1360         if (gtt == NULL || !gtt->userptr)
1361                 return false;
1362
1363         return true;
1364 }
1365
1366 /**
1367  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1368  */
1369 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1370 {
1371         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1372
1373         if (gtt == NULL)
1374                 return false;
1375
1376         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1377 }
1378
1379 /**
1380  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1381  *
1382  * @ttm: The ttm_tt object to compute the flags for
1383  * @mem: The memory registry backing this ttm_tt object
1384  *
1385  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1386  */
1387 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1388 {
1389         uint64_t flags = 0;
1390
1391         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1392                 flags |= AMDGPU_PTE_VALID;
1393
1394         if (mem && mem->mem_type == TTM_PL_TT) {
1395                 flags |= AMDGPU_PTE_SYSTEM;
1396
1397                 if (ttm->caching_state == tt_cached)
1398                         flags |= AMDGPU_PTE_SNOOPED;
1399         }
1400
1401         return flags;
1402 }
1403
1404 /**
1405  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1406  *
1407  * @ttm: The ttm_tt object to compute the flags for
1408  * @mem: The memory registry backing this ttm_tt object
1409
1410  * Figure out the flags to use for a VM PTE (Page Table Entry).
1411  */
1412 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1413                                  struct ttm_mem_reg *mem)
1414 {
1415         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1416
1417         flags |= adev->gart.gart_pte_flags;
1418         flags |= AMDGPU_PTE_READABLE;
1419
1420         if (!amdgpu_ttm_tt_is_readonly(ttm))
1421                 flags |= AMDGPU_PTE_WRITEABLE;
1422
1423         return flags;
1424 }
1425
1426 /**
1427  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1428  * object.
1429  *
1430  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1431  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1432  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1433  * used to clean out a memory space.
1434  */
1435 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1436                                             const struct ttm_place *place)
1437 {
1438         unsigned long num_pages = bo->mem.num_pages;
1439         struct drm_mm_node *node = bo->mem.mm_node;
1440         struct reservation_object_list *flist;
1441         struct dma_fence *f;
1442         int i;
1443
1444         /* Don't evict VM page tables while they are busy, otherwise we can't
1445          * cleanly handle page faults.
1446          */
1447         if (bo->type == ttm_bo_type_kernel &&
1448             !reservation_object_test_signaled_rcu(bo->resv, true))
1449                 return false;
1450
1451         /* If bo is a KFD BO, check if the bo belongs to the current process.
1452          * If true, then return false as any KFD process needs all its BOs to
1453          * be resident to run successfully
1454          */
1455         flist = reservation_object_get_list(bo->resv);
1456         if (flist) {
1457                 for (i = 0; i < flist->shared_count; ++i) {
1458                         f = rcu_dereference_protected(flist->shared[i],
1459                                 reservation_object_held(bo->resv));
1460                         if (amdkfd_fence_check_mm(f, current->mm))
1461                                 return false;
1462                 }
1463         }
1464
1465         switch (bo->mem.mem_type) {
1466         case TTM_PL_TT:
1467                 return true;
1468
1469         case TTM_PL_VRAM:
1470                 /* Check each drm MM node individually */
1471                 while (num_pages) {
1472                         if (place->fpfn < (node->start + node->size) &&
1473                             !(place->lpfn && place->lpfn <= node->start))
1474                                 return true;
1475
1476                         num_pages -= node->size;
1477                         ++node;
1478                 }
1479                 return false;
1480
1481         default:
1482                 break;
1483         }
1484
1485         return ttm_bo_eviction_valuable(bo, place);
1486 }
1487
1488 /**
1489  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1490  *
1491  * @bo:  The buffer object to read/write
1492  * @offset:  Offset into buffer object
1493  * @buf:  Secondary buffer to write/read from
1494  * @len: Length in bytes of access
1495  * @write:  true if writing
1496  *
1497  * This is used to access VRAM that backs a buffer object via MMIO
1498  * access for debugging purposes.
1499  */
1500 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1501                                     unsigned long offset,
1502                                     void *buf, int len, int write)
1503 {
1504         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1505         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1506         struct drm_mm_node *nodes;
1507         uint32_t value = 0;
1508         int ret = 0;
1509         uint64_t pos;
1510         unsigned long flags;
1511
1512         if (bo->mem.mem_type != TTM_PL_VRAM)
1513                 return -EIO;
1514
1515         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1516         pos = (nodes->start << PAGE_SHIFT) + offset;
1517
1518         while (len && pos < adev->gmc.mc_vram_size) {
1519                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1520                 uint32_t bytes = 4 - (pos & 3);
1521                 uint32_t shift = (pos & 3) * 8;
1522                 uint32_t mask = 0xffffffff << shift;
1523
1524                 if (len < bytes) {
1525                         mask &= 0xffffffff >> (bytes - len) * 8;
1526                         bytes = len;
1527                 }
1528
1529                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1530                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1531                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1532                 if (!write || mask != 0xffffffff)
1533                         value = RREG32_NO_KIQ(mmMM_DATA);
1534                 if (write) {
1535                         value &= ~mask;
1536                         value |= (*(uint32_t *)buf << shift) & mask;
1537                         WREG32_NO_KIQ(mmMM_DATA, value);
1538                 }
1539                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1540                 if (!write) {
1541                         value = (value & mask) >> shift;
1542                         memcpy(buf, &value, bytes);
1543                 }
1544
1545                 ret += bytes;
1546                 buf = (uint8_t *)buf + bytes;
1547                 pos += bytes;
1548                 len -= bytes;
1549                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1550                         ++nodes;
1551                         pos = (nodes->start << PAGE_SHIFT);
1552                 }
1553         }
1554
1555         return ret;
1556 }
1557
1558 static struct ttm_bo_driver amdgpu_bo_driver = {
1559         .ttm_tt_create = &amdgpu_ttm_tt_create,
1560         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1561         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1562         .invalidate_caches = &amdgpu_invalidate_caches,
1563         .init_mem_type = &amdgpu_init_mem_type,
1564         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1565         .evict_flags = &amdgpu_evict_flags,
1566         .move = &amdgpu_bo_move,
1567         .verify_access = &amdgpu_verify_access,
1568         .move_notify = &amdgpu_bo_move_notify,
1569         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1570         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1571         .io_mem_free = &amdgpu_ttm_io_mem_free,
1572         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1573         .access_memory = &amdgpu_ttm_access_memory,
1574         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1575 };
1576
1577 /*
1578  * Firmware Reservation functions
1579  */
1580 /**
1581  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1582  *
1583  * @adev: amdgpu_device pointer
1584  *
1585  * free fw reserved vram if it has been reserved.
1586  */
1587 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1588 {
1589         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1590                 NULL, &adev->fw_vram_usage.va);
1591 }
1592
1593 /**
1594  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1595  *
1596  * @adev: amdgpu_device pointer
1597  *
1598  * create bo vram reservation from fw.
1599  */
1600 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1601 {
1602         struct ttm_operation_ctx ctx = { false, false };
1603         struct amdgpu_bo_param bp;
1604         int r = 0;
1605         int i;
1606         u64 vram_size = adev->gmc.visible_vram_size;
1607         u64 offset = adev->fw_vram_usage.start_offset;
1608         u64 size = adev->fw_vram_usage.size;
1609         struct amdgpu_bo *bo;
1610
1611         memset(&bp, 0, sizeof(bp));
1612         bp.size = adev->fw_vram_usage.size;
1613         bp.byte_align = PAGE_SIZE;
1614         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1615         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1616                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1617         bp.type = ttm_bo_type_kernel;
1618         bp.resv = NULL;
1619         adev->fw_vram_usage.va = NULL;
1620         adev->fw_vram_usage.reserved_bo = NULL;
1621
1622         if (adev->fw_vram_usage.size > 0 &&
1623                 adev->fw_vram_usage.size <= vram_size) {
1624
1625                 r = amdgpu_bo_create(adev, &bp,
1626                                      &adev->fw_vram_usage.reserved_bo);
1627                 if (r)
1628                         goto error_create;
1629
1630                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1631                 if (r)
1632                         goto error_reserve;
1633
1634                 /* remove the original mem node and create a new one at the
1635                  * request position
1636                  */
1637                 bo = adev->fw_vram_usage.reserved_bo;
1638                 offset = ALIGN(offset, PAGE_SIZE);
1639                 for (i = 0; i < bo->placement.num_placement; ++i) {
1640                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1641                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1642                 }
1643
1644                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1645                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1646                                      &bo->tbo.mem, &ctx);
1647                 if (r)
1648                         goto error_pin;
1649
1650                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1651                         AMDGPU_GEM_DOMAIN_VRAM,
1652                         adev->fw_vram_usage.start_offset,
1653                         (adev->fw_vram_usage.start_offset +
1654                         adev->fw_vram_usage.size));
1655                 if (r)
1656                         goto error_pin;
1657                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1658                         &adev->fw_vram_usage.va);
1659                 if (r)
1660                         goto error_kmap;
1661
1662                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1663         }
1664         return r;
1665
1666 error_kmap:
1667         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1668 error_pin:
1669         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1670 error_reserve:
1671         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1672 error_create:
1673         adev->fw_vram_usage.va = NULL;
1674         adev->fw_vram_usage.reserved_bo = NULL;
1675         return r;
1676 }
1677 /**
1678  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1679  * gtt/vram related fields.
1680  *
1681  * This initializes all of the memory space pools that the TTM layer
1682  * will need such as the GTT space (system memory mapped to the device),
1683  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1684  * can be mapped per VMID.
1685  */
1686 int amdgpu_ttm_init(struct amdgpu_device *adev)
1687 {
1688         uint64_t gtt_size;
1689         int r;
1690         u64 vis_vram_limit;
1691
1692         mutex_init(&adev->mman.gtt_window_lock);
1693
1694         /* No others user of address space so set it to 0 */
1695         r = ttm_bo_device_init(&adev->mman.bdev,
1696                                &amdgpu_bo_driver,
1697                                adev->ddev->anon_inode->i_mapping,
1698                                adev->need_dma32);
1699         if (r) {
1700                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1701                 return r;
1702         }
1703         adev->mman.initialized = true;
1704
1705         /* We opt to avoid OOM on system pages allocations */
1706         adev->mman.bdev.no_retry = true;
1707
1708         /* Initialize VRAM pool with all of VRAM divided into pages */
1709         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1710                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1711         if (r) {
1712                 DRM_ERROR("Failed initializing VRAM heap.\n");
1713                 return r;
1714         }
1715
1716         /* Reduce size of CPU-visible VRAM if requested */
1717         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1718         if (amdgpu_vis_vram_limit > 0 &&
1719             vis_vram_limit <= adev->gmc.visible_vram_size)
1720                 adev->gmc.visible_vram_size = vis_vram_limit;
1721
1722         /* Change the size here instead of the init above so only lpfn is affected */
1723         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1724 #ifdef CONFIG_64BIT
1725         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1726                                                 adev->gmc.visible_vram_size);
1727 #endif
1728
1729         /*
1730          *The reserved vram for firmware must be pinned to the specified
1731          *place on the VRAM, so reserve it early.
1732          */
1733         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1734         if (r) {
1735                 return r;
1736         }
1737
1738         /* allocate memory as required for VGA
1739          * This is used for VGA emulation and pre-OS scanout buffers to
1740          * avoid display artifacts while transitioning between pre-OS
1741          * and driver.  */
1742         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1743                                     AMDGPU_GEM_DOMAIN_VRAM,
1744                                     &adev->stolen_vga_memory,
1745                                     NULL, NULL);
1746         if (r)
1747                 return r;
1748         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1749                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1750
1751         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1752          * or whatever the user passed on module init */
1753         if (amdgpu_gtt_size == -1) {
1754                 struct sysinfo si;
1755
1756                 si_meminfo(&si);
1757                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1758                                adev->gmc.mc_vram_size),
1759                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1760         }
1761         else
1762                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1763
1764         /* Initialize GTT memory pool */
1765         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1766         if (r) {
1767                 DRM_ERROR("Failed initializing GTT heap.\n");
1768                 return r;
1769         }
1770         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1771                  (unsigned)(gtt_size / (1024 * 1024)));
1772
1773         /* Initialize various on-chip memory pools */
1774         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1775                            adev->gds.gds_size);
1776         if (r) {
1777                 DRM_ERROR("Failed initializing GDS heap.\n");
1778                 return r;
1779         }
1780
1781         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1782                            adev->gds.gws_size);
1783         if (r) {
1784                 DRM_ERROR("Failed initializing gws heap.\n");
1785                 return r;
1786         }
1787
1788         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1789                            adev->gds.oa_size);
1790         if (r) {
1791                 DRM_ERROR("Failed initializing oa heap.\n");
1792                 return r;
1793         }
1794
1795         /* Register debugfs entries for amdgpu_ttm */
1796         r = amdgpu_ttm_debugfs_init(adev);
1797         if (r) {
1798                 DRM_ERROR("Failed to init debugfs\n");
1799                 return r;
1800         }
1801         return 0;
1802 }
1803
1804 /**
1805  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1806  */
1807 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1808 {
1809         /* return the VGA stolen memory (if any) back to VRAM */
1810         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1811 }
1812
1813 /**
1814  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1815  */
1816 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1817 {
1818         if (!adev->mman.initialized)
1819                 return;
1820
1821         amdgpu_ttm_debugfs_fini(adev);
1822         amdgpu_ttm_fw_reserve_vram_fini(adev);
1823         if (adev->mman.aper_base_kaddr)
1824                 iounmap(adev->mman.aper_base_kaddr);
1825         adev->mman.aper_base_kaddr = NULL;
1826
1827         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1828         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1829         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1830         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1831         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1832         ttm_bo_device_release(&adev->mman.bdev);
1833         adev->mman.initialized = false;
1834         DRM_INFO("amdgpu: ttm finalized\n");
1835 }
1836
1837 /**
1838  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1839  *
1840  * @adev: amdgpu_device pointer
1841  * @enable: true when we can use buffer functions.
1842  *
1843  * Enable/disable use of buffer functions during suspend/resume. This should
1844  * only be called at bootup or when userspace isn't running.
1845  */
1846 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1847 {
1848         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1849         uint64_t size;
1850         int r;
1851
1852         if (!adev->mman.initialized || adev->in_gpu_reset ||
1853             adev->mman.buffer_funcs_enabled == enable)
1854                 return;
1855
1856         if (enable) {
1857                 struct amdgpu_ring *ring;
1858                 struct drm_sched_rq *rq;
1859
1860                 ring = adev->mman.buffer_funcs_ring;
1861                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1862                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1863                 if (r) {
1864                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1865                                   r);
1866                         return;
1867                 }
1868         } else {
1869                 drm_sched_entity_destroy(&adev->mman.entity);
1870                 dma_fence_put(man->move);
1871                 man->move = NULL;
1872         }
1873
1874         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1875         if (enable)
1876                 size = adev->gmc.real_vram_size;
1877         else
1878                 size = adev->gmc.visible_vram_size;
1879         man->size = size >> PAGE_SHIFT;
1880         adev->mman.buffer_funcs_enabled = enable;
1881 }
1882
1883 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1884 {
1885         struct drm_file *file_priv = filp->private_data;
1886         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1887
1888         if (adev == NULL)
1889                 return -EINVAL;
1890
1891         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1892 }
1893
1894 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1895                              struct ttm_mem_reg *mem, unsigned num_pages,
1896                              uint64_t offset, unsigned window,
1897                              struct amdgpu_ring *ring,
1898                              uint64_t *addr)
1899 {
1900         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1901         struct amdgpu_device *adev = ring->adev;
1902         struct ttm_tt *ttm = bo->ttm;
1903         struct amdgpu_job *job;
1904         unsigned num_dw, num_bytes;
1905         dma_addr_t *dma_address;
1906         struct dma_fence *fence;
1907         uint64_t src_addr, dst_addr;
1908         uint64_t flags;
1909         int r;
1910
1911         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1912                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1913
1914         *addr = adev->gmc.gart_start;
1915         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1916                 AMDGPU_GPU_PAGE_SIZE;
1917
1918         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1919         while (num_dw & 0x7)
1920                 num_dw++;
1921
1922         num_bytes = num_pages * 8;
1923
1924         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1925         if (r)
1926                 return r;
1927
1928         src_addr = num_dw * 4;
1929         src_addr += job->ibs[0].gpu_addr;
1930
1931         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1932         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1933         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1934                                 dst_addr, num_bytes);
1935
1936         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1937         WARN_ON(job->ibs[0].length_dw > num_dw);
1938
1939         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1940         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1941         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1942                             &job->ibs[0].ptr[num_dw]);
1943         if (r)
1944                 goto error_free;
1945
1946         r = amdgpu_job_submit(job, &adev->mman.entity,
1947                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1948         if (r)
1949                 goto error_free;
1950
1951         dma_fence_put(fence);
1952
1953         return r;
1954
1955 error_free:
1956         amdgpu_job_free(job);
1957         return r;
1958 }
1959
1960 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1961                        uint64_t dst_offset, uint32_t byte_count,
1962                        struct reservation_object *resv,
1963                        struct dma_fence **fence, bool direct_submit,
1964                        bool vm_needs_flush)
1965 {
1966         struct amdgpu_device *adev = ring->adev;
1967         struct amdgpu_job *job;
1968
1969         uint32_t max_bytes;
1970         unsigned num_loops, num_dw;
1971         unsigned i;
1972         int r;
1973
1974         if (direct_submit && !ring->sched.ready) {
1975                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1976                 return -EINVAL;
1977         }
1978
1979         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1980         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1981         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1982
1983         /* for IB padding */
1984         while (num_dw & 0x7)
1985                 num_dw++;
1986
1987         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1988         if (r)
1989                 return r;
1990
1991         if (vm_needs_flush) {
1992                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1993                 job->vm_needs_flush = true;
1994         }
1995         if (resv) {
1996                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1997                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1998                                      false);
1999                 if (r) {
2000                         DRM_ERROR("sync failed (%d).\n", r);
2001                         goto error_free;
2002                 }
2003         }
2004
2005         for (i = 0; i < num_loops; i++) {
2006                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2007
2008                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2009                                         dst_offset, cur_size_in_bytes);
2010
2011                 src_offset += cur_size_in_bytes;
2012                 dst_offset += cur_size_in_bytes;
2013                 byte_count -= cur_size_in_bytes;
2014         }
2015
2016         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2017         WARN_ON(job->ibs[0].length_dw > num_dw);
2018         if (direct_submit)
2019                 r = amdgpu_job_submit_direct(job, ring, fence);
2020         else
2021                 r = amdgpu_job_submit(job, &adev->mman.entity,
2022                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2023         if (r)
2024                 goto error_free;
2025
2026         return r;
2027
2028 error_free:
2029         amdgpu_job_free(job);
2030         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2031         return r;
2032 }
2033
2034 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2035                        uint32_t src_data,
2036                        struct reservation_object *resv,
2037                        struct dma_fence **fence)
2038 {
2039         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2040         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2041         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2042
2043         struct drm_mm_node *mm_node;
2044         unsigned long num_pages;
2045         unsigned int num_loops, num_dw;
2046
2047         struct amdgpu_job *job;
2048         int r;
2049
2050         if (!adev->mman.buffer_funcs_enabled) {
2051                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2052                 return -EINVAL;
2053         }
2054
2055         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2056                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2057                 if (r)
2058                         return r;
2059         }
2060
2061         num_pages = bo->tbo.num_pages;
2062         mm_node = bo->tbo.mem.mm_node;
2063         num_loops = 0;
2064         while (num_pages) {
2065                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2066
2067                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2068                 num_pages -= mm_node->size;
2069                 ++mm_node;
2070         }
2071         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2072
2073         /* for IB padding */
2074         num_dw += 64;
2075
2076         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2077         if (r)
2078                 return r;
2079
2080         if (resv) {
2081                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2082                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2083                 if (r) {
2084                         DRM_ERROR("sync failed (%d).\n", r);
2085                         goto error_free;
2086                 }
2087         }
2088
2089         num_pages = bo->tbo.num_pages;
2090         mm_node = bo->tbo.mem.mm_node;
2091
2092         while (num_pages) {
2093                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2094                 uint64_t dst_addr;
2095
2096                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2097                 while (byte_count) {
2098                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2099
2100                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2101                                                 dst_addr, cur_size_in_bytes);
2102
2103                         dst_addr += cur_size_in_bytes;
2104                         byte_count -= cur_size_in_bytes;
2105                 }
2106
2107                 num_pages -= mm_node->size;
2108                 ++mm_node;
2109         }
2110
2111         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2112         WARN_ON(job->ibs[0].length_dw > num_dw);
2113         r = amdgpu_job_submit(job, &adev->mman.entity,
2114                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2115         if (r)
2116                 goto error_free;
2117
2118         return 0;
2119
2120 error_free:
2121         amdgpu_job_free(job);
2122         return r;
2123 }
2124
2125 #if defined(CONFIG_DEBUG_FS)
2126
2127 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2128 {
2129         struct drm_info_node *node = (struct drm_info_node *)m->private;
2130         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2131         struct drm_device *dev = node->minor->dev;
2132         struct amdgpu_device *adev = dev->dev_private;
2133         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2134         struct drm_printer p = drm_seq_file_printer(m);
2135
2136         man->func->debug(man, &p);
2137         return 0;
2138 }
2139
2140 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2141         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2142         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2143         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2144         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2145         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2146         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2147 #ifdef CONFIG_SWIOTLB
2148         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2149 #endif
2150 };
2151
2152 /**
2153  * amdgpu_ttm_vram_read - Linear read access to VRAM
2154  *
2155  * Accesses VRAM via MMIO for debugging purposes.
2156  */
2157 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2158                                     size_t size, loff_t *pos)
2159 {
2160         struct amdgpu_device *adev = file_inode(f)->i_private;
2161         ssize_t result = 0;
2162         int r;
2163
2164         if (size & 0x3 || *pos & 0x3)
2165                 return -EINVAL;
2166
2167         if (*pos >= adev->gmc.mc_vram_size)
2168                 return -ENXIO;
2169
2170         while (size) {
2171                 unsigned long flags;
2172                 uint32_t value;
2173
2174                 if (*pos >= adev->gmc.mc_vram_size)
2175                         return result;
2176
2177                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2178                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2179                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2180                 value = RREG32_NO_KIQ(mmMM_DATA);
2181                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2182
2183                 r = put_user(value, (uint32_t *)buf);
2184                 if (r)
2185                         return r;
2186
2187                 result += 4;
2188                 buf += 4;
2189                 *pos += 4;
2190                 size -= 4;
2191         }
2192
2193         return result;
2194 }
2195
2196 /**
2197  * amdgpu_ttm_vram_write - Linear write access to VRAM
2198  *
2199  * Accesses VRAM via MMIO for debugging purposes.
2200  */
2201 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2202                                     size_t size, loff_t *pos)
2203 {
2204         struct amdgpu_device *adev = file_inode(f)->i_private;
2205         ssize_t result = 0;
2206         int r;
2207
2208         if (size & 0x3 || *pos & 0x3)
2209                 return -EINVAL;
2210
2211         if (*pos >= adev->gmc.mc_vram_size)
2212                 return -ENXIO;
2213
2214         while (size) {
2215                 unsigned long flags;
2216                 uint32_t value;
2217
2218                 if (*pos >= adev->gmc.mc_vram_size)
2219                         return result;
2220
2221                 r = get_user(value, (uint32_t *)buf);
2222                 if (r)
2223                         return r;
2224
2225                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2226                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2227                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2228                 WREG32_NO_KIQ(mmMM_DATA, value);
2229                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2230
2231                 result += 4;
2232                 buf += 4;
2233                 *pos += 4;
2234                 size -= 4;
2235         }
2236
2237         return result;
2238 }
2239
2240 static const struct file_operations amdgpu_ttm_vram_fops = {
2241         .owner = THIS_MODULE,
2242         .read = amdgpu_ttm_vram_read,
2243         .write = amdgpu_ttm_vram_write,
2244         .llseek = default_llseek,
2245 };
2246
2247 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2248
2249 /**
2250  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2251  */
2252 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2253                                    size_t size, loff_t *pos)
2254 {
2255         struct amdgpu_device *adev = file_inode(f)->i_private;
2256         ssize_t result = 0;
2257         int r;
2258
2259         while (size) {
2260                 loff_t p = *pos / PAGE_SIZE;
2261                 unsigned off = *pos & ~PAGE_MASK;
2262                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2263                 struct page *page;
2264                 void *ptr;
2265
2266                 if (p >= adev->gart.num_cpu_pages)
2267                         return result;
2268
2269                 page = adev->gart.pages[p];
2270                 if (page) {
2271                         ptr = kmap(page);
2272                         ptr += off;
2273
2274                         r = copy_to_user(buf, ptr, cur_size);
2275                         kunmap(adev->gart.pages[p]);
2276                 } else
2277                         r = clear_user(buf, cur_size);
2278
2279                 if (r)
2280                         return -EFAULT;
2281
2282                 result += cur_size;
2283                 buf += cur_size;
2284                 *pos += cur_size;
2285                 size -= cur_size;
2286         }
2287
2288         return result;
2289 }
2290
2291 static const struct file_operations amdgpu_ttm_gtt_fops = {
2292         .owner = THIS_MODULE,
2293         .read = amdgpu_ttm_gtt_read,
2294         .llseek = default_llseek
2295 };
2296
2297 #endif
2298
2299 /**
2300  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2301  *
2302  * This function is used to read memory that has been mapped to the
2303  * GPU and the known addresses are not physical addresses but instead
2304  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2305  */
2306 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2307                                  size_t size, loff_t *pos)
2308 {
2309         struct amdgpu_device *adev = file_inode(f)->i_private;
2310         struct iommu_domain *dom;
2311         ssize_t result = 0;
2312         int r;
2313
2314         /* retrieve the IOMMU domain if any for this device */
2315         dom = iommu_get_domain_for_dev(adev->dev);
2316
2317         while (size) {
2318                 phys_addr_t addr = *pos & PAGE_MASK;
2319                 loff_t off = *pos & ~PAGE_MASK;
2320                 size_t bytes = PAGE_SIZE - off;
2321                 unsigned long pfn;
2322                 struct page *p;
2323                 void *ptr;
2324
2325                 bytes = bytes < size ? bytes : size;
2326
2327                 /* Translate the bus address to a physical address.  If
2328                  * the domain is NULL it means there is no IOMMU active
2329                  * and the address translation is the identity
2330                  */
2331                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2332
2333                 pfn = addr >> PAGE_SHIFT;
2334                 if (!pfn_valid(pfn))
2335                         return -EPERM;
2336
2337                 p = pfn_to_page(pfn);
2338                 if (p->mapping != adev->mman.bdev.dev_mapping)
2339                         return -EPERM;
2340
2341                 ptr = kmap(p);
2342                 r = copy_to_user(buf, ptr + off, bytes);
2343                 kunmap(p);
2344                 if (r)
2345                         return -EFAULT;
2346
2347                 size -= bytes;
2348                 *pos += bytes;
2349                 result += bytes;
2350         }
2351
2352         return result;
2353 }
2354
2355 /**
2356  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2357  *
2358  * This function is used to write memory that has been mapped to the
2359  * GPU and the known addresses are not physical addresses but instead
2360  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2361  */
2362 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2363                                  size_t size, loff_t *pos)
2364 {
2365         struct amdgpu_device *adev = file_inode(f)->i_private;
2366         struct iommu_domain *dom;
2367         ssize_t result = 0;
2368         int r;
2369
2370         dom = iommu_get_domain_for_dev(adev->dev);
2371
2372         while (size) {
2373                 phys_addr_t addr = *pos & PAGE_MASK;
2374                 loff_t off = *pos & ~PAGE_MASK;
2375                 size_t bytes = PAGE_SIZE - off;
2376                 unsigned long pfn;
2377                 struct page *p;
2378                 void *ptr;
2379
2380                 bytes = bytes < size ? bytes : size;
2381
2382                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2383
2384                 pfn = addr >> PAGE_SHIFT;
2385                 if (!pfn_valid(pfn))
2386                         return -EPERM;
2387
2388                 p = pfn_to_page(pfn);
2389                 if (p->mapping != adev->mman.bdev.dev_mapping)
2390                         return -EPERM;
2391
2392                 ptr = kmap(p);
2393                 r = copy_from_user(ptr + off, buf, bytes);
2394                 kunmap(p);
2395                 if (r)
2396                         return -EFAULT;
2397
2398                 size -= bytes;
2399                 *pos += bytes;
2400                 result += bytes;
2401         }
2402
2403         return result;
2404 }
2405
2406 static const struct file_operations amdgpu_ttm_iomem_fops = {
2407         .owner = THIS_MODULE,
2408         .read = amdgpu_iomem_read,
2409         .write = amdgpu_iomem_write,
2410         .llseek = default_llseek
2411 };
2412
2413 static const struct {
2414         char *name;
2415         const struct file_operations *fops;
2416         int domain;
2417 } ttm_debugfs_entries[] = {
2418         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2419 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2420         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2421 #endif
2422         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2423 };
2424
2425 #endif
2426
2427 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2428 {
2429 #if defined(CONFIG_DEBUG_FS)
2430         unsigned count;
2431
2432         struct drm_minor *minor = adev->ddev->primary;
2433         struct dentry *ent, *root = minor->debugfs_root;
2434
2435         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2436                 ent = debugfs_create_file(
2437                                 ttm_debugfs_entries[count].name,
2438                                 S_IFREG | S_IRUGO, root,
2439                                 adev,
2440                                 ttm_debugfs_entries[count].fops);
2441                 if (IS_ERR(ent))
2442                         return PTR_ERR(ent);
2443                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2444                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2445                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2446                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2447                 adev->mman.debugfs_entries[count] = ent;
2448         }
2449
2450         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2451
2452 #ifdef CONFIG_SWIOTLB
2453         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2454                 --count;
2455 #endif
2456
2457         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2458 #else
2459         return 0;
2460 #endif
2461 }
2462
2463 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2464 {
2465 #if defined(CONFIG_DEBUG_FS)
2466         unsigned i;
2467
2468         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2469                 debugfs_remove(adev->mman.debugfs_entries[i]);
2470 #endif
2471 }