drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 static const struct hwmon_temp_label {
  71         enum PP_HWMON_TEMP channel;
  72         const char *label;
  73 } temp_label[] = {
  74         {PP_TEMP_EDGE, "edge"},
  75         {PP_TEMP_JUNCTION, "junction"},
  76         {PP_TEMP_MEM, "mem"},
  77 };
  78
  79 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  80 {
  81         if (adev->pm.dpm_enabled) {
  82                 mutex_lock(&adev->pm.mutex);
  83                 if (power_supply_is_system_supplied() > 0)
  84                         adev->pm.ac_power = true;
  85                 else
  86                         adev->pm.ac_power = false;
  87                 if (adev->powerplay.pp_funcs->enable_bapm)
  88                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  89                 mutex_unlock(&adev->pm.mutex);
  90         }
  91 }
  92
  93 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  94                            void *data, uint32_t *size)
  95 {
  96         int ret = 0;
  97
  98         if (!data || !size)
  99                 return -EINVAL;
 100
 101         if (is_support_sw_smu(adev))
 102                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 103         else {
 104                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 105                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 106                                                                     sensor, data, size);
 107                 else
 108                         ret = -EINVAL;
 109         }
 110
 111         return ret;
 112 }
 113
 114 /**
 115  * DOC: power_dpm_state
 116  *
 117  * The power_dpm_state file is a legacy interface and is only provided for
 118  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 119  * certain power related parameters.  The file power_dpm_state is used for this.
 120  * It accepts the following arguments:
 121  *
 122  * - battery
 123  *
 124  * - balanced
 125  *
 126  * - performance
 127  *
 128  * battery
 129  *
 130  * On older GPUs, the vbios provided a special power state for battery
 131  * operation.  Selecting battery switched to this state.  This is no
 132  * longer provided on newer GPUs so the option does nothing in that case.
 133  *
 134  * balanced
 135  *
 136  * On older GPUs, the vbios provided a special power state for balanced
 137  * operation.  Selecting balanced switched to this state.  This is no
 138  * longer provided on newer GPUs so the option does nothing in that case.
 139  *
 140  * performance
 141  *
 142  * On older GPUs, the vbios provided a special power state for performance
 143  * operation.  Selecting performance switched to this state.  This is no
 144  * longer provided on newer GPUs so the option does nothing in that case.
 145  *
 146  */
 147
 148 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 149                                     struct device_attribute *attr,
 150                                     char *buf)
 151 {
 152         struct drm_device *ddev = dev_get_drvdata(dev);
 153         struct amdgpu_device *adev = ddev->dev_private;
 154         enum amd_pm_state_type pm;
 155
 156         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 157                 pm = amdgpu_smu_get_current_power_state(adev);
 158         else if (adev->powerplay.pp_funcs->get_current_power_state)
 159                 pm = amdgpu_dpm_get_current_power_state(adev);
 160         else
 161                 pm = adev->pm.dpm.user_state;
 162
 163         return snprintf(buf, PAGE_SIZE, "%s\n",
 164                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 165                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 166 }
 167
 168 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 169                                     struct device_attribute *attr,
 170                                     const char *buf,
 171                                     size_t count)
 172 {
 173         struct drm_device *ddev = dev_get_drvdata(dev);
 174         struct amdgpu_device *adev = ddev->dev_private;
 175         enum amd_pm_state_type  state;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else {
 184                 count = -EINVAL;
 185                 goto fail;
 186         }
 187
 188         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 189                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 190         } else {
 191                 mutex_lock(&adev->pm.mutex);
 192                 adev->pm.dpm.user_state = state;
 193                 mutex_unlock(&adev->pm.mutex);
 194
 195                 /* Can't set dpm state when the card is off */
 196                 if (!(adev->flags & AMD_IS_PX) ||
 197                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 198                         amdgpu_pm_compute_clocks(adev);
 199         }
 200 fail:
 201         return count;
 202 }
 203
 204
 205 /**
 206  * DOC: power_dpm_force_performance_level
 207  *
 208  * The amdgpu driver provides a sysfs API for adjusting certain power
 209  * related parameters.  The file power_dpm_force_performance_level is
 210  * used for this.  It accepts the following arguments:
 211  *
 212  * - auto
 213  *
 214  * - low
 215  *
 216  * - high
 217  *
 218  * - manual
 219  *
 220  * - profile_standard
 221  *
 222  * - profile_min_sclk
 223  *
 224  * - profile_min_mclk
 225  *
 226  * - profile_peak
 227  *
 228  * auto
 229  *
 230  * When auto is selected, the driver will attempt to dynamically select
 231  * the optimal power profile for current conditions in the driver.
 232  *
 233  * low
 234  *
 235  * When low is selected, the clocks are forced to the lowest power state.
 236  *
 237  * high
 238  *
 239  * When high is selected, the clocks are forced to the highest power state.
 240  *
 241  * manual
 242  *
 243  * When manual is selected, the user can manually adjust which power states
 244  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 245  * and pp_dpm_pcie files and adjust the power state transition heuristics
 246  * via the pp_power_profile_mode sysfs file.
 247  *
 248  * profile_standard
 249  * profile_min_sclk
 250  * profile_min_mclk
 251  * profile_peak
 252  *
 253  * When the profiling modes are selected, clock and power gating are
 254  * disabled and the clocks are set for different profiling cases. This
 255  * mode is recommended for profiling specific work loads where you do
 256  * not want clock or power gating for clock fluctuation to interfere
 257  * with your results. profile_standard sets the clocks to a fixed clock
 258  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 259  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 260  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 261  *
 262  */
 263
 264 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 265                                                 struct device_attribute *attr,
 266                                                                 char *buf)
 267 {
 268         struct drm_device *ddev = dev_get_drvdata(dev);
 269         struct amdgpu_device *adev = ddev->dev_private;
 270         enum amd_dpm_forced_level level = 0xff;
 271
 272         if  ((adev->flags & AMD_IS_PX) &&
 273              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 274                 return snprintf(buf, PAGE_SIZE, "off\n");
 275
 276         if (is_support_sw_smu(adev))
 277                 level = smu_get_performance_level(&adev->smu);
 278         else if (adev->powerplay.pp_funcs->get_performance_level)
 279                 level = amdgpu_dpm_get_performance_level(adev);
 280         else
 281                 level = adev->pm.dpm.forced_level;
 282
 283         return snprintf(buf, PAGE_SIZE, "%s\n",
 284                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 285                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 286                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 287                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 288                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 289                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 290                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 291                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 292                         "unknown");
 293 }
 294
 295 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 296                                                        struct device_attribute *attr,
 297                                                        const char *buf,
 298                                                        size_t count)
 299 {
 300         struct drm_device *ddev = dev_get_drvdata(dev);
 301         struct amdgpu_device *adev = ddev->dev_private;
 302         enum amd_dpm_forced_level level;
 303         enum amd_dpm_forced_level current_level = 0xff;
 304         int ret = 0;
 305
 306         /* Can't force performance level when the card is off */
 307         if  ((adev->flags & AMD_IS_PX) &&
 308              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 309                 return -EINVAL;
 310
 311         if (is_support_sw_smu(adev))
 312                 current_level = smu_get_performance_level(&adev->smu);
 313         else if (adev->powerplay.pp_funcs->get_performance_level)
 314                 current_level = amdgpu_dpm_get_performance_level(adev);
 315
 316         if (strncmp("low", buf, strlen("low")) == 0) {
 317                 level = AMD_DPM_FORCED_LEVEL_LOW;
 318         } else if (strncmp("high", buf, strlen("high")) == 0) {
 319                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 320         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 321                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 322         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 323                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 324         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 325                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 326         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 327                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 328         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 329                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 330         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 331                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 332         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 333                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 334         }  else {
 335                 count = -EINVAL;
 336                 goto fail;
 337         }
 338
 339         if (amdgpu_sriov_vf(adev)) {
 340                 if (amdgim_is_hwperf(adev) &&
 341                     adev->virt.ops->force_dpm_level) {
 342                         mutex_lock(&adev->pm.mutex);
 343                         adev->virt.ops->force_dpm_level(adev, level);
 344                         mutex_unlock(&adev->pm.mutex);
 345                         return count;
 346                 } else {
 347                         return -EINVAL;
 348                 }
 349         }
 350
 351         if (current_level == level)
 352                 return count;
 353
 354         /* profile_exit setting is valid only when current mode is in profile mode */
 355         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 356             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 357             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 358             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 359             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 360                 pr_err("Currently not in any profile mode!\n");
 361                 return -EINVAL;
 362         }
 363
 364         if (is_support_sw_smu(adev)) {
 365                 mutex_lock(&adev->pm.mutex);
 366                 if (adev->pm.dpm.thermal_active) {
 367                         count = -EINVAL;
 368                         mutex_unlock(&adev->pm.mutex);
 369                         goto fail;
 370                 }
 371                 ret = smu_force_performance_level(&adev->smu, level);
 372                 if (ret)
 373                         count = -EINVAL;
 374                 else
 375                         adev->pm.dpm.forced_level = level;
 376                 mutex_unlock(&adev->pm.mutex);
 377         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 378                 mutex_lock(&adev->pm.mutex);
 379                 if (adev->pm.dpm.thermal_active) {
 380                         count = -EINVAL;
 381                         mutex_unlock(&adev->pm.mutex);
 382                         goto fail;
 383                 }
 384                 ret = amdgpu_dpm_force_performance_level(adev, level);
 385                 if (ret)
 386                         count = -EINVAL;
 387                 else
 388                         adev->pm.dpm.forced_level = level;
 389                 mutex_unlock(&adev->pm.mutex);
 390         }
 391
 392 fail:
 393         return count;
 394 }
 395
 396 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 397                 struct device_attribute *attr,
 398                 char *buf)
 399 {
 400         struct drm_device *ddev = dev_get_drvdata(dev);
 401         struct amdgpu_device *adev = ddev->dev_private;
 402         struct pp_states_info data;
 403         int i, buf_len, ret;
 404
 405         if (is_support_sw_smu(adev)) {
 406                 ret = smu_get_power_num_states(&adev->smu, &data);
 407                 if (ret)
 408                         return ret;
 409         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 410                 amdgpu_dpm_get_pp_num_states(adev, &data);
 411
 412         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 413         for (i = 0; i < data.nums; i++)
 414                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 415                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 416                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 417                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 418                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 419
 420         return buf_len;
 421 }
 422
 423 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 424                 struct device_attribute *attr,
 425                 char *buf)
 426 {
 427         struct drm_device *ddev = dev_get_drvdata(dev);
 428         struct amdgpu_device *adev = ddev->dev_private;
 429         struct pp_states_info data;
 430         struct smu_context *smu = &adev->smu;
 431         enum amd_pm_state_type pm = 0;
 432         int i = 0, ret = 0;
 433
 434         if (is_support_sw_smu(adev)) {
 435                 pm = smu_get_current_power_state(smu);
 436                 ret = smu_get_power_num_states(smu, &data);
 437                 if (ret)
 438                         return ret;
 439         } else if (adev->powerplay.pp_funcs->get_current_power_state
 440                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 441                 pm = amdgpu_dpm_get_current_power_state(adev);
 442                 amdgpu_dpm_get_pp_num_states(adev, &data);
 443         }
 444
 445         for (i = 0; i < data.nums; i++) {
 446                 if (pm == data.states[i])
 447                         break;
 448         }
 449
 450         if (i == data.nums)
 451                 i = -EINVAL;
 452
 453         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 454 }
 455
 456 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 457                 struct device_attribute *attr,
 458                 char *buf)
 459 {
 460         struct drm_device *ddev = dev_get_drvdata(dev);
 461         struct amdgpu_device *adev = ddev->dev_private;
 462
 463         if (adev->pp_force_state_enabled)
 464                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 465         else
 466                 return snprintf(buf, PAGE_SIZE, "\n");
 467 }
 468
 469 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 470                 struct device_attribute *attr,
 471                 const char *buf,
 472                 size_t count)
 473 {
 474         struct drm_device *ddev = dev_get_drvdata(dev);
 475         struct amdgpu_device *adev = ddev->dev_private;
 476         enum amd_pm_state_type state = 0;
 477         unsigned long idx;
 478         int ret;
 479
 480         if (strlen(buf) == 1)
 481                 adev->pp_force_state_enabled = false;
 482         else if (is_support_sw_smu(adev))
 483                 adev->pp_force_state_enabled = false;
 484         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 485                         adev->powerplay.pp_funcs->get_pp_num_states) {
 486                 struct pp_states_info data;
 487
 488                 ret = kstrtoul(buf, 0, &idx);
 489                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 490                         count = -EINVAL;
 491                         goto fail;
 492                 }
 493                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 494
 495                 amdgpu_dpm_get_pp_num_states(adev, &data);
 496                 state = data.states[idx];
 497                 /* only set user selected power states */
 498                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 499                     state != POWER_STATE_TYPE_DEFAULT) {
 500                         amdgpu_dpm_dispatch_task(adev,
 501                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 502                         adev->pp_force_state_enabled = true;
 503                 }
 504         }
 505 fail:
 506         return count;
 507 }
 508
 509 /**
 510  * DOC: pp_table
 511  *
 512  * The amdgpu driver provides a sysfs API for uploading new powerplay
 513  * tables.  The file pp_table is used for this.  Reading the file
 514  * will dump the current power play table.  Writing to the file
 515  * will attempt to upload a new powerplay table and re-initialize
 516  * powerplay using that new table.
 517  *
 518  */
 519
 520 static ssize_t amdgpu_get_pp_table(struct device *dev,
 521                 struct device_attribute *attr,
 522                 char *buf)
 523 {
 524         struct drm_device *ddev = dev_get_drvdata(dev);
 525         struct amdgpu_device *adev = ddev->dev_private;
 526         char *table = NULL;
 527         int size;
 528
 529         if (is_support_sw_smu(adev)) {
 530                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 531                 if (size < 0)
 532                         return size;
 533         }
 534         else if (adev->powerplay.pp_funcs->get_pp_table)
 535                 size = amdgpu_dpm_get_pp_table(adev, &table);
 536         else
 537                 return 0;
 538
 539         if (size >= PAGE_SIZE)
 540                 size = PAGE_SIZE - 1;
 541
 542         memcpy(buf, table, size);
 543
 544         return size;
 545 }
 546
 547 static ssize_t amdgpu_set_pp_table(struct device *dev,
 548                 struct device_attribute *attr,
 549                 const char *buf,
 550                 size_t count)
 551 {
 552         struct drm_device *ddev = dev_get_drvdata(dev);
 553         struct amdgpu_device *adev = ddev->dev_private;
 554         int ret = 0;
 555
 556         if (is_support_sw_smu(adev)) {
 557                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 558                 if (ret)
 559                         return ret;
 560         } else if (adev->powerplay.pp_funcs->set_pp_table)
 561                 amdgpu_dpm_set_pp_table(adev, buf, count);
 562
 563         return count;
 564 }
 565
 566 /**
 567  * DOC: pp_od_clk_voltage
 568  *
 569  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 570  * in each power level within a power state.  The pp_od_clk_voltage is used for
 571  * this.
 572  *
 573  * < For Vega10 and previous ASICs >
 574  *
 575  * Reading the file will display:
 576  *
 577  * - a list of engine clock levels and voltages labeled OD_SCLK
 578  *
 579  * - a list of memory clock levels and voltages labeled OD_MCLK
 580  *
 581  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 582  *
 583  * To manually adjust these settings, first select manual using
 584  * power_dpm_force_performance_level. Enter a new value for each
 585  * level by writing a string that contains "s/m level clock voltage" to
 586  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 587  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 588  * 810 mV.  When you have edited all of the states as needed, write
 589  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 590  * default power levels, write "r" (reset) to the file to reset them.
 591  *
 592  *
 593  * < For Vega20 >
 594  *
 595  * Reading the file will display:
 596  *
 597  * - minimum and maximum engine clock labeled OD_SCLK
 598  *
 599  * - maximum memory clock labeled OD_MCLK
 600  *
 601  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 602  *   They can be used to calibrate the sclk voltage curve.
 603  *
 604  * - a list of valid ranges for sclk, mclk, and voltage curve points
 605  *   labeled OD_RANGE
 606  *
 607  * To manually adjust these settings:
 608  *
 609  * - First select manual using power_dpm_force_performance_level
 610  *
 611  * - For clock frequency setting, enter a new value by writing a
 612  *   string that contains "s/m index clock" to the file. The index
 613  *   should be 0 if to set minimum clock. And 1 if to set maximum
 614  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 615  *   "m 1 800" will update maximum mclk to be 800Mhz.
 616  *
 617  *   For sclk voltage curve, enter the new values by writing a
 618  *   string that contains "vc point clock voltage" to the file. The
 619  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 620  *   update point1 with clock set as 300Mhz and voltage as
 621  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 622  *   as 1000Mhz and voltage 1000mV.
 623  *
 624  * - When you have edited all of the states as needed, write "c" (commit)
 625  *   to the file to commit your changes
 626  *
 627  * - If you want to reset to the default power levels, write "r" (reset)
 628  *   to the file to reset them
 629  *
 630  */
 631
 632 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 633                 struct device_attribute *attr,
 634                 const char *buf,
 635                 size_t count)
 636 {
 637         struct drm_device *ddev = dev_get_drvdata(dev);
 638         struct amdgpu_device *adev = ddev->dev_private;
 639         int ret;
 640         uint32_t parameter_size = 0;
 641         long parameter[64];
 642         char buf_cpy[128];
 643         char *tmp_str;
 644         char *sub_str;
 645         const char delimiter[3] = {' ', '\n', '\0'};
 646         uint32_t type;
 647
 648         if (count > 127)
 649                 return -EINVAL;
 650
 651         if (*buf == 's')
 652                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 653         else if (*buf == 'm')
 654                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 655         else if(*buf == 'r')
 656                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 657         else if (*buf == 'c')
 658                 type = PP_OD_COMMIT_DPM_TABLE;
 659         else if (!strncmp(buf, "vc", 2))
 660                 type = PP_OD_EDIT_VDDC_CURVE;
 661         else
 662                 return -EINVAL;
 663
 664         memcpy(buf_cpy, buf, count+1);
 665
 666         tmp_str = buf_cpy;
 667
 668         if (type == PP_OD_EDIT_VDDC_CURVE)
 669                 tmp_str++;
 670         while (isspace(*++tmp_str));
 671
 672         while (tmp_str[0]) {
 673                 sub_str = strsep(&tmp_str, delimiter);
 674                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 675                 if (ret)
 676                         return -EINVAL;
 677                 parameter_size++;
 678
 679                 while (isspace(*tmp_str))
 680                         tmp_str++;
 681         }
 682
 683         if (is_support_sw_smu(adev)) {
 684                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 685                                             parameter, parameter_size);
 686
 687                 if (ret)
 688                         return -EINVAL;
 689         } else {
 690                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 691                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 692                                                 parameter, parameter_size);
 693
 694                 if (ret)
 695                         return -EINVAL;
 696
 697                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 698                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 699                                 amdgpu_dpm_dispatch_task(adev,
 700                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 701                                                 NULL);
 702                                 return count;
 703                         } else {
 704                                 return -EINVAL;
 705                         }
 706                 }
 707         }
 708
 709         return count;
 710 }
 711
 712 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 713                 struct device_attribute *attr,
 714                 char *buf)
 715 {
 716         struct drm_device *ddev = dev_get_drvdata(dev);
 717         struct amdgpu_device *adev = ddev->dev_private;
 718         uint32_t size = 0;
 719
 720         if (is_support_sw_smu(adev)) {
 721                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 722                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 723                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 724                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 725                 return size;
 726         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 727                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 728                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 729                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 730                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 731                 return size;
 732         } else {
 733                 return snprintf(buf, PAGE_SIZE, "\n");
 734         }
 735
 736 }
 737
 738 /**
 739  * DOC: ppfeatures
 740  *
 741  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 742  * features to be enabled. The file ppfeatures is used for this. And
 743  * this is only available for Vega10 and later dGPUs.
 744  *
 745  * Reading back the file will show you the followings:
 746  * - Current ppfeature masks
 747  * - List of the all supported powerplay features with their naming,
 748  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 749  *
 750  * To manually enable or disable a specific feature, just set or clear
 751  * the corresponding bit from original ppfeature masks and input the
 752  * new ppfeature masks.
 753  */
 754 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 755                 struct device_attribute *attr,
 756                 const char *buf,
 757                 size_t count)
 758 {
 759         struct drm_device *ddev = dev_get_drvdata(dev);
 760         struct amdgpu_device *adev = ddev->dev_private;
 761         uint64_t featuremask;
 762         int ret;
 763
 764         ret = kstrtou64(buf, 0, &featuremask);
 765         if (ret)
 766                 return -EINVAL;
 767
 768         pr_debug("featuremask = 0x%llx\n", featuremask);
 769
 770         if (is_support_sw_smu(adev)) {
 771                 ret = smu_set_ppfeature_status(&adev->smu, featuremask);
 772                 if (ret)
 773                         return -EINVAL;
 774         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 775                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 776                 if (ret)
 777                         return -EINVAL;
 778         }
 779
 780         return count;
 781 }
 782
 783 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 784                 struct device_attribute *attr,
 785                 char *buf)
 786 {
 787         struct drm_device *ddev = dev_get_drvdata(dev);
 788         struct amdgpu_device *adev = ddev->dev_private;
 789
 790         if (is_support_sw_smu(adev)) {
 791                 return smu_get_ppfeature_status(&adev->smu, buf);
 792         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 793                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 794
 795         return snprintf(buf, PAGE_SIZE, "\n");
 796 }
 797
 798 /**
 799  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 800  * pp_dpm_pcie
 801  *
 802  * The amdgpu driver provides a sysfs API for adjusting what power levels
 803  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 804  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 805  * this.
 806  *
 807  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 808  * Vega10 and later ASICs.
 809  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 810  *
 811  * Reading back the files will show you the available power levels within
 812  * the power state and the clock information for those levels.
 813  *
 814  * To manually adjust these states, first select manual using
 815  * power_dpm_force_performance_level.
 816  * Secondly,Enter a new value for each level by inputing a string that
 817  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 818  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 819  *
 820  * NOTE: change to the dcefclk max dpm level is not supported now
 821  */
 822
 823 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 824                 struct device_attribute *attr,
 825                 char *buf)
 826 {
 827         struct drm_device *ddev = dev_get_drvdata(dev);
 828         struct amdgpu_device *adev = ddev->dev_private;
 829
 830         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 831             adev->virt.ops->get_pp_clk)
 832                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 833
 834         if (is_support_sw_smu(adev))
 835                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 836         else if (adev->powerplay.pp_funcs->print_clock_levels)
 837                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 838         else
 839                 return snprintf(buf, PAGE_SIZE, "\n");
 840 }
 841
 842 /*
 843  * Worst case: 32 bits individually specified, in octal at 12 characters
 844  * per line (+1 for \n).
 845  */
 846 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 847
 848 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 849 {
 850         int ret;
 851         long level;
 852         char *sub_str = NULL;
 853         char *tmp;
 854         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 855         const char delimiter[3] = {' ', '\n', '\0'};
 856         size_t bytes;
 857
 858         *mask = 0;
 859
 860         bytes = min(count, sizeof(buf_cpy) - 1);
 861         memcpy(buf_cpy, buf, bytes);
 862         buf_cpy[bytes] = '\0';
 863         tmp = buf_cpy;
 864         while (tmp[0]) {
 865                 sub_str = strsep(&tmp, delimiter);
 866                 if (strlen(sub_str)) {
 867                         ret = kstrtol(sub_str, 0, &level);
 868                         if (ret)
 869                                 return -EINVAL;
 870                         *mask |= 1 << level;
 871                 } else
 872                         break;
 873         }
 874
 875         return 0;
 876 }
 877
 878 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 879                 struct device_attribute *attr,
 880                 const char *buf,
 881                 size_t count)
 882 {
 883         struct drm_device *ddev = dev_get_drvdata(dev);
 884         struct amdgpu_device *adev = ddev->dev_private;
 885         int ret;
 886         uint32_t mask = 0;
 887
 888         ret = amdgpu_read_mask(buf, count, &mask);
 889         if (ret)
 890                 return ret;
 891
 892         if (is_support_sw_smu(adev))
 893                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 894         else if (adev->powerplay.pp_funcs->force_clock_level)
 895                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 896
 897         if (ret)
 898                 return -EINVAL;
 899
 900         return count;
 901 }
 902
 903 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 904                 struct device_attribute *attr,
 905                 char *buf)
 906 {
 907         struct drm_device *ddev = dev_get_drvdata(dev);
 908         struct amdgpu_device *adev = ddev->dev_private;
 909
 910         if (is_support_sw_smu(adev))
 911                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 912         else if (adev->powerplay.pp_funcs->print_clock_levels)
 913                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 914         else
 915                 return snprintf(buf, PAGE_SIZE, "\n");
 916 }
 917
 918 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 919                 struct device_attribute *attr,
 920                 const char *buf,
 921                 size_t count)
 922 {
 923         struct drm_device *ddev = dev_get_drvdata(dev);
 924         struct amdgpu_device *adev = ddev->dev_private;
 925         int ret;
 926         uint32_t mask = 0;
 927
 928         ret = amdgpu_read_mask(buf, count, &mask);
 929         if (ret)
 930                 return ret;
 931
 932         if (is_support_sw_smu(adev))
 933                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 934         else if (adev->powerplay.pp_funcs->force_clock_level)
 935                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 936
 937         if (ret)
 938                 return -EINVAL;
 939
 940         return count;
 941 }
 942
 943 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 944                 struct device_attribute *attr,
 945                 char *buf)
 946 {
 947         struct drm_device *ddev = dev_get_drvdata(dev);
 948         struct amdgpu_device *adev = ddev->dev_private;
 949
 950         if (is_support_sw_smu(adev))
 951                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 952         else if (adev->powerplay.pp_funcs->print_clock_levels)
 953                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 954         else
 955                 return snprintf(buf, PAGE_SIZE, "\n");
 956 }
 957
 958 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 959                 struct device_attribute *attr,
 960                 const char *buf,
 961                 size_t count)
 962 {
 963         struct drm_device *ddev = dev_get_drvdata(dev);
 964         struct amdgpu_device *adev = ddev->dev_private;
 965         int ret;
 966         uint32_t mask = 0;
 967
 968         ret = amdgpu_read_mask(buf, count, &mask);
 969         if (ret)
 970                 return ret;
 971
 972         if (is_support_sw_smu(adev))
 973                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 974         else if (adev->powerplay.pp_funcs->force_clock_level)
 975                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 976
 977         if (ret)
 978                 return -EINVAL;
 979
 980         return count;
 981 }
 982
 983 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 984                 struct device_attribute *attr,
 985                 char *buf)
 986 {
 987         struct drm_device *ddev = dev_get_drvdata(dev);
 988         struct amdgpu_device *adev = ddev->dev_private;
 989
 990         if (is_support_sw_smu(adev))
 991                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
 992         else if (adev->powerplay.pp_funcs->print_clock_levels)
 993                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 994         else
 995                 return snprintf(buf, PAGE_SIZE, "\n");
 996 }
 997
 998 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 999                 struct device_attribute *attr,
1000                 const char *buf,
1001                 size_t count)
1002 {
1003         struct drm_device *ddev = dev_get_drvdata(dev);
1004         struct amdgpu_device *adev = ddev->dev_private;
1005         int ret;
1006         uint32_t mask = 0;
1007
1008         ret = amdgpu_read_mask(buf, count, &mask);
1009         if (ret)
1010                 return ret;
1011
1012         if (is_support_sw_smu(adev))
1013                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
1014         else if (adev->powerplay.pp_funcs->force_clock_level)
1015                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1016
1017         if (ret)
1018                 return -EINVAL;
1019
1020         return count;
1021 }
1022
1023 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1024                 struct device_attribute *attr,
1025                 char *buf)
1026 {
1027         struct drm_device *ddev = dev_get_drvdata(dev);
1028         struct amdgpu_device *adev = ddev->dev_private;
1029
1030         if (is_support_sw_smu(adev))
1031                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
1032         else if (adev->powerplay.pp_funcs->print_clock_levels)
1033                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1034         else
1035                 return snprintf(buf, PAGE_SIZE, "\n");
1036 }
1037
1038 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1039                 struct device_attribute *attr,
1040                 const char *buf,
1041                 size_t count)
1042 {
1043         struct drm_device *ddev = dev_get_drvdata(dev);
1044         struct amdgpu_device *adev = ddev->dev_private;
1045         int ret;
1046         uint32_t mask = 0;
1047
1048         ret = amdgpu_read_mask(buf, count, &mask);
1049         if (ret)
1050                 return ret;
1051
1052         if (is_support_sw_smu(adev))
1053                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1054         else if (adev->powerplay.pp_funcs->force_clock_level)
1055                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1056
1057         if (ret)
1058                 return -EINVAL;
1059
1060         return count;
1061 }
1062
1063 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1064                 struct device_attribute *attr,
1065                 char *buf)
1066 {
1067         struct drm_device *ddev = dev_get_drvdata(dev);
1068         struct amdgpu_device *adev = ddev->dev_private;
1069
1070         if (is_support_sw_smu(adev))
1071                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1072         else if (adev->powerplay.pp_funcs->print_clock_levels)
1073                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1074         else
1075                 return snprintf(buf, PAGE_SIZE, "\n");
1076 }
1077
1078 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1079                 struct device_attribute *attr,
1080                 const char *buf,
1081                 size_t count)
1082 {
1083         struct drm_device *ddev = dev_get_drvdata(dev);
1084         struct amdgpu_device *adev = ddev->dev_private;
1085         int ret;
1086         uint32_t mask = 0;
1087
1088         ret = amdgpu_read_mask(buf, count, &mask);
1089         if (ret)
1090                 return ret;
1091
1092         if (is_support_sw_smu(adev))
1093                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1094         else if (adev->powerplay.pp_funcs->force_clock_level)
1095                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1096
1097         if (ret)
1098                 return -EINVAL;
1099
1100         return count;
1101 }
1102
1103 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1104                 struct device_attribute *attr,
1105                 char *buf)
1106 {
1107         struct drm_device *ddev = dev_get_drvdata(dev);
1108         struct amdgpu_device *adev = ddev->dev_private;
1109         uint32_t value = 0;
1110
1111         if (is_support_sw_smu(adev))
1112                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1113         else if (adev->powerplay.pp_funcs->get_sclk_od)
1114                 value = amdgpu_dpm_get_sclk_od(adev);
1115
1116         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1117 }
1118
1119 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1120                 struct device_attribute *attr,
1121                 const char *buf,
1122                 size_t count)
1123 {
1124         struct drm_device *ddev = dev_get_drvdata(dev);
1125         struct amdgpu_device *adev = ddev->dev_private;
1126         int ret;
1127         long int value;
1128
1129         ret = kstrtol(buf, 0, &value);
1130
1131         if (ret) {
1132                 count = -EINVAL;
1133                 goto fail;
1134         }
1135
1136         if (is_support_sw_smu(adev)) {
1137                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1138         } else {
1139                 if (adev->powerplay.pp_funcs->set_sclk_od)
1140                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1141
1142                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1143                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1144                 } else {
1145                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1146                         amdgpu_pm_compute_clocks(adev);
1147                 }
1148         }
1149
1150 fail:
1151         return count;
1152 }
1153
1154 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1155                 struct device_attribute *attr,
1156                 char *buf)
1157 {
1158         struct drm_device *ddev = dev_get_drvdata(dev);
1159         struct amdgpu_device *adev = ddev->dev_private;
1160         uint32_t value = 0;
1161
1162         if (is_support_sw_smu(adev))
1163                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1164         else if (adev->powerplay.pp_funcs->get_mclk_od)
1165                 value = amdgpu_dpm_get_mclk_od(adev);
1166
1167         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1168 }
1169
1170 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1171                 struct device_attribute *attr,
1172                 const char *buf,
1173                 size_t count)
1174 {
1175         struct drm_device *ddev = dev_get_drvdata(dev);
1176         struct amdgpu_device *adev = ddev->dev_private;
1177         int ret;
1178         long int value;
1179
1180         ret = kstrtol(buf, 0, &value);
1181
1182         if (ret) {
1183                 count = -EINVAL;
1184                 goto fail;
1185         }
1186
1187         if (is_support_sw_smu(adev)) {
1188                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1189         } else {
1190                 if (adev->powerplay.pp_funcs->set_mclk_od)
1191                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1192
1193                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1194                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1195                 } else {
1196                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1197                         amdgpu_pm_compute_clocks(adev);
1198                 }
1199         }
1200
1201 fail:
1202         return count;
1203 }
1204
1205 /**
1206  * DOC: pp_power_profile_mode
1207  *
1208  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1209  * related to switching between power levels in a power state.  The file
1210  * pp_power_profile_mode is used for this.
1211  *
1212  * Reading this file outputs a list of all of the predefined power profiles
1213  * and the relevant heuristics settings for that profile.
1214  *
1215  * To select a profile or create a custom profile, first select manual using
1216  * power_dpm_force_performance_level.  Writing the number of a predefined
1217  * profile to pp_power_profile_mode will enable those heuristics.  To
1218  * create a custom set of heuristics, write a string of numbers to the file
1219  * starting with the number of the custom profile along with a setting
1220  * for each heuristic parameter.  Due to differences across asic families
1221  * the heuristic parameters vary from family to family.
1222  *
1223  */
1224
1225 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1226                 struct device_attribute *attr,
1227                 char *buf)
1228 {
1229         struct drm_device *ddev = dev_get_drvdata(dev);
1230         struct amdgpu_device *adev = ddev->dev_private;
1231
1232         if (is_support_sw_smu(adev))
1233                 return smu_get_power_profile_mode(&adev->smu, buf);
1234         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1235                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1236
1237         return snprintf(buf, PAGE_SIZE, "\n");
1238 }
1239
1240
1241 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1242                 struct device_attribute *attr,
1243                 const char *buf,
1244                 size_t count)
1245 {
1246         int ret = 0xff;
1247         struct drm_device *ddev = dev_get_drvdata(dev);
1248         struct amdgpu_device *adev = ddev->dev_private;
1249         uint32_t parameter_size = 0;
1250         long parameter[64];
1251         char *sub_str, buf_cpy[128];
1252         char *tmp_str;
1253         uint32_t i = 0;
1254         char tmp[2];
1255         long int profile_mode = 0;
1256         const char delimiter[3] = {' ', '\n', '\0'};
1257
1258         tmp[0] = *(buf);
1259         tmp[1] = '\0';
1260         ret = kstrtol(tmp, 0, &profile_mode);
1261         if (ret)
1262                 goto fail;
1263
1264         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1265                 if (count < 2 || count > 127)
1266                         return -EINVAL;
1267                 while (isspace(*++buf))
1268                         i++;
1269                 memcpy(buf_cpy, buf, count-i);
1270                 tmp_str = buf_cpy;
1271                 while (tmp_str[0]) {
1272                         sub_str = strsep(&tmp_str, delimiter);
1273                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1274                         if (ret) {
1275                                 count = -EINVAL;
1276                                 goto fail;
1277                         }
1278                         parameter_size++;
1279                         while (isspace(*tmp_str))
1280                                 tmp_str++;
1281                 }
1282         }
1283         parameter[parameter_size] = profile_mode;
1284         if (is_support_sw_smu(adev))
1285                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1286         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1287                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1288         if (!ret)
1289                 return count;
1290 fail:
1291         return -EINVAL;
1292 }
1293
1294 /**
1295  * DOC: busy_percent
1296  *
1297  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1298  * is as a percentage.  The file gpu_busy_percent is used for this.
1299  * The SMU firmware computes a percentage of load based on the
1300  * aggregate activity level in the IP cores.
1301  */
1302 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1303                 struct device_attribute *attr,
1304                 char *buf)
1305 {
1306         struct drm_device *ddev = dev_get_drvdata(dev);
1307         struct amdgpu_device *adev = ddev->dev_private;
1308         int r, value, size = sizeof(value);
1309
1310         /* read the IP busy sensor */
1311         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1312                                    (void *)&value, &size);
1313
1314         if (r)
1315                 return r;
1316
1317         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1318 }
1319
1320 /**
1321  * DOC: mem_busy_percent
1322  *
1323  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1324  * is as a percentage.  The file mem_busy_percent is used for this.
1325  * The SMU firmware computes a percentage of load based on the
1326  * aggregate activity level in the IP cores.
1327  */
1328 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1329                 struct device_attribute *attr,
1330                 char *buf)
1331 {
1332         struct drm_device *ddev = dev_get_drvdata(dev);
1333         struct amdgpu_device *adev = ddev->dev_private;
1334         int r, value, size = sizeof(value);
1335
1336         /* read the IP busy sensor */
1337         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1338                                    (void *)&value, &size);
1339
1340         if (r)
1341                 return r;
1342
1343         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1344 }
1345
1346 /**
1347  * DOC: pcie_bw
1348  *
1349  * The amdgpu driver provides a sysfs API for estimating how much data
1350  * has been received and sent by the GPU in the last second through PCIe.
1351  * The file pcie_bw is used for this.
1352  * The Perf counters count the number of received and sent messages and return
1353  * those values, as well as the maximum payload size of a PCIe packet (mps).
1354  * Note that it is not possible to easily and quickly obtain the size of each
1355  * packet transmitted, so we output the max payload size (mps) to allow for
1356  * quick estimation of the PCIe bandwidth usage
1357  */
1358 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1359                 struct device_attribute *attr,
1360                 char *buf)
1361 {
1362         struct drm_device *ddev = dev_get_drvdata(dev);
1363         struct amdgpu_device *adev = ddev->dev_private;
1364         uint64_t count0, count1;
1365
1366         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1367         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1368                         count0, count1, pcie_get_mps(adev->pdev));
1369 }
1370
1371 /**
1372  * DOC: unique_id
1373  *
1374  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1375  * The file unique_id is used for this.
1376  * This will provide a Unique ID that will persist from machine to machine
1377  *
1378  * NOTE: This will only work for GFX9 and newer. This file will be absent
1379  * on unsupported ASICs (GFX8 and older)
1380  */
1381 static ssize_t amdgpu_get_unique_id(struct device *dev,
1382                 struct device_attribute *attr,
1383                 char *buf)
1384 {
1385         struct drm_device *ddev = dev_get_drvdata(dev);
1386         struct amdgpu_device *adev = ddev->dev_private;
1387
1388         if (adev->unique_id)
1389                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1390
1391         return 0;
1392 }
1393
1394 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1395 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1396                    amdgpu_get_dpm_forced_performance_level,
1397                    amdgpu_set_dpm_forced_performance_level);
1398 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1399 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1400 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1401                 amdgpu_get_pp_force_state,
1402                 amdgpu_set_pp_force_state);
1403 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1404                 amdgpu_get_pp_table,
1405                 amdgpu_set_pp_table);
1406 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1407                 amdgpu_get_pp_dpm_sclk,
1408                 amdgpu_set_pp_dpm_sclk);
1409 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1410                 amdgpu_get_pp_dpm_mclk,
1411                 amdgpu_set_pp_dpm_mclk);
1412 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1413                 amdgpu_get_pp_dpm_socclk,
1414                 amdgpu_set_pp_dpm_socclk);
1415 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1416                 amdgpu_get_pp_dpm_fclk,
1417                 amdgpu_set_pp_dpm_fclk);
1418 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1419                 amdgpu_get_pp_dpm_dcefclk,
1420                 amdgpu_set_pp_dpm_dcefclk);
1421 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1422                 amdgpu_get_pp_dpm_pcie,
1423                 amdgpu_set_pp_dpm_pcie);
1424 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1425                 amdgpu_get_pp_sclk_od,
1426                 amdgpu_set_pp_sclk_od);
1427 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1428                 amdgpu_get_pp_mclk_od,
1429                 amdgpu_set_pp_mclk_od);
1430 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1431                 amdgpu_get_pp_power_profile_mode,
1432                 amdgpu_set_pp_power_profile_mode);
1433 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1434                 amdgpu_get_pp_od_clk_voltage,
1435                 amdgpu_set_pp_od_clk_voltage);
1436 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1437                 amdgpu_get_busy_percent, NULL);
1438 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1439                 amdgpu_get_memory_busy_percent, NULL);
1440 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1441 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1442                 amdgpu_get_ppfeature_status,
1443                 amdgpu_set_ppfeature_status);
1444 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1445
1446 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1447                                       struct device_attribute *attr,
1448                                       char *buf)
1449 {
1450         struct amdgpu_device *adev = dev_get_drvdata(dev);
1451         struct drm_device *ddev = adev->ddev;
1452         int channel = to_sensor_dev_attr(attr)->index;
1453         int r, temp, size = sizeof(temp);
1454
1455         /* Can't get temperature when the card is off */
1456         if  ((adev->flags & AMD_IS_PX) &&
1457              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1458                 return -EINVAL;
1459
1460         if (channel >= PP_TEMP_MAX)
1461                 return -EINVAL;
1462
1463         switch (channel) {
1464         case PP_TEMP_JUNCTION:
1465                 /* get current junction temperature */
1466                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1467                                            (void *)&temp, &size);
1468                 if (r)
1469                         return r;
1470                 break;
1471         case PP_TEMP_EDGE:
1472                 /* get current edge temperature */
1473                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1474                                            (void *)&temp, &size);
1475                 if (r)
1476                         return r;
1477                 break;
1478         case PP_TEMP_MEM:
1479                 /* get current memory temperature */
1480                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1481                                            (void *)&temp, &size);
1482                 if (r)
1483                         return r;
1484                 break;
1485         }
1486
1487         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1488 }
1489
1490 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1491                                              struct device_attribute *attr,
1492                                              char *buf)
1493 {
1494         struct amdgpu_device *adev = dev_get_drvdata(dev);
1495         int hyst = to_sensor_dev_attr(attr)->index;
1496         int temp;
1497
1498         if (hyst)
1499                 temp = adev->pm.dpm.thermal.min_temp;
1500         else
1501                 temp = adev->pm.dpm.thermal.max_temp;
1502
1503         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1504 }
1505
1506 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1507                                              struct device_attribute *attr,
1508                                              char *buf)
1509 {
1510         struct amdgpu_device *adev = dev_get_drvdata(dev);
1511         int hyst = to_sensor_dev_attr(attr)->index;
1512         int temp;
1513
1514         if (hyst)
1515                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1516         else
1517                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1518
1519         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1520 }
1521
1522 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1523                                              struct device_attribute *attr,
1524                                              char *buf)
1525 {
1526         struct amdgpu_device *adev = dev_get_drvdata(dev);
1527         int hyst = to_sensor_dev_attr(attr)->index;
1528         int temp;
1529
1530         if (hyst)
1531                 temp = adev->pm.dpm.thermal.min_mem_temp;
1532         else
1533                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1534
1535         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1536 }
1537
1538 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1539                                              struct device_attribute *attr,
1540                                              char *buf)
1541 {
1542         int channel = to_sensor_dev_attr(attr)->index;
1543
1544         if (channel >= PP_TEMP_MAX)
1545                 return -EINVAL;
1546
1547         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1548 }
1549
1550 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1551                                              struct device_attribute *attr,
1552                                              char *buf)
1553 {
1554         struct amdgpu_device *adev = dev_get_drvdata(dev);
1555         int channel = to_sensor_dev_attr(attr)->index;
1556         int temp = 0;
1557
1558         if (channel >= PP_TEMP_MAX)
1559                 return -EINVAL;
1560
1561         switch (channel) {
1562         case PP_TEMP_JUNCTION:
1563                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1564                 break;
1565         case PP_TEMP_EDGE:
1566                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1567                 break;
1568         case PP_TEMP_MEM:
1569                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1570                 break;
1571         }
1572
1573         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1574 }
1575
1576 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1577                                             struct device_attribute *attr,
1578                                             char *buf)
1579 {
1580         struct amdgpu_device *adev = dev_get_drvdata(dev);
1581         u32 pwm_mode = 0;
1582         if (is_support_sw_smu(adev)) {
1583                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1584         } else {
1585                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1586                         return -EINVAL;
1587
1588                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1589         }
1590
1591         return sprintf(buf, "%i\n", pwm_mode);
1592 }
1593
1594 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1595                                             struct device_attribute *attr,
1596                                             const char *buf,
1597                                             size_t count)
1598 {
1599         struct amdgpu_device *adev = dev_get_drvdata(dev);
1600         int err;
1601         int value;
1602
1603         /* Can't adjust fan when the card is off */
1604         if  ((adev->flags & AMD_IS_PX) &&
1605              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1606                 return -EINVAL;
1607
1608         if (is_support_sw_smu(adev)) {
1609                 err = kstrtoint(buf, 10, &value);
1610                 if (err)
1611                         return err;
1612
1613                 smu_set_fan_control_mode(&adev->smu, value);
1614         } else {
1615                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1616                         return -EINVAL;
1617
1618                 err = kstrtoint(buf, 10, &value);
1619                 if (err)
1620                         return err;
1621
1622                 amdgpu_dpm_set_fan_control_mode(adev, value);
1623         }
1624
1625         return count;
1626 }
1627
1628 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1629                                          struct device_attribute *attr,
1630                                          char *buf)
1631 {
1632         return sprintf(buf, "%i\n", 0);
1633 }
1634
1635 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1636                                          struct device_attribute *attr,
1637                                          char *buf)
1638 {
1639         return sprintf(buf, "%i\n", 255);
1640 }
1641
1642 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1643                                      struct device_attribute *attr,
1644                                      const char *buf, size_t count)
1645 {
1646         struct amdgpu_device *adev = dev_get_drvdata(dev);
1647         int err;
1648         u32 value;
1649         u32 pwm_mode;
1650
1651         /* Can't adjust fan when the card is off */
1652         if  ((adev->flags & AMD_IS_PX) &&
1653              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1654                 return -EINVAL;
1655         if (is_support_sw_smu(adev))
1656                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1657         else
1658                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1659         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1660                 pr_info("manual fan speed control should be enabled first\n");
1661                 return -EINVAL;
1662         }
1663
1664         err = kstrtou32(buf, 10, &value);
1665         if (err)
1666                 return err;
1667
1668         value = (value * 100) / 255;
1669
1670         if (is_support_sw_smu(adev)) {
1671                 err = smu_set_fan_speed_percent(&adev->smu, value);
1672                 if (err)
1673                         return err;
1674         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1675                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1676                 if (err)
1677                         return err;
1678         }
1679
1680         return count;
1681 }
1682
1683 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1684                                      struct device_attribute *attr,
1685                                      char *buf)
1686 {
1687         struct amdgpu_device *adev = dev_get_drvdata(dev);
1688         int err;
1689         u32 speed = 0;
1690
1691         /* Can't adjust fan when the card is off */
1692         if  ((adev->flags & AMD_IS_PX) &&
1693              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1694                 return -EINVAL;
1695
1696         if (is_support_sw_smu(adev)) {
1697                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1698                 if (err)
1699                         return err;
1700         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1701                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1702                 if (err)
1703                         return err;
1704         }
1705
1706         speed = (speed * 255) / 100;
1707
1708         return sprintf(buf, "%i\n", speed);
1709 }
1710
1711 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1712                                            struct device_attribute *attr,
1713                                            char *buf)
1714 {
1715         struct amdgpu_device *adev = dev_get_drvdata(dev);
1716         int err;
1717         u32 speed = 0;
1718
1719         /* Can't adjust fan when the card is off */
1720         if  ((adev->flags & AMD_IS_PX) &&
1721              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1722                 return -EINVAL;
1723
1724         if (is_support_sw_smu(adev)) {
1725                 err = smu_get_current_rpm(&adev->smu, &speed);
1726                 if (err)
1727                         return err;
1728         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1729                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1730                 if (err)
1731                         return err;
1732         }
1733
1734         return sprintf(buf, "%i\n", speed);
1735 }
1736
1737 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1738                                          struct device_attribute *attr,
1739                                          char *buf)
1740 {
1741         struct amdgpu_device *adev = dev_get_drvdata(dev);
1742         u32 min_rpm = 0;
1743         u32 size = sizeof(min_rpm);
1744         int r;
1745
1746         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1747                                    (void *)&min_rpm, &size);
1748         if (r)
1749                 return r;
1750
1751         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1752 }
1753
1754 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1755                                          struct device_attribute *attr,
1756                                          char *buf)
1757 {
1758         struct amdgpu_device *adev = dev_get_drvdata(dev);
1759         u32 max_rpm = 0;
1760         u32 size = sizeof(max_rpm);
1761         int r;
1762
1763         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1764                                    (void *)&max_rpm, &size);
1765         if (r)
1766                 return r;
1767
1768         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1769 }
1770
1771 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1772                                            struct device_attribute *attr,
1773                                            char *buf)
1774 {
1775         struct amdgpu_device *adev = dev_get_drvdata(dev);
1776         int err;
1777         u32 rpm = 0;
1778
1779         /* Can't adjust fan when the card is off */
1780         if  ((adev->flags & AMD_IS_PX) &&
1781              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1782                 return -EINVAL;
1783
1784         if (is_support_sw_smu(adev)) {
1785                 err = smu_get_current_rpm(&adev->smu, &rpm);
1786                 if (err)
1787                         return err;
1788         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1789                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1790                 if (err)
1791                         return err;
1792         }
1793
1794         return sprintf(buf, "%i\n", rpm);
1795 }
1796
1797 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1798                                      struct device_attribute *attr,
1799                                      const char *buf, size_t count)
1800 {
1801         struct amdgpu_device *adev = dev_get_drvdata(dev);
1802         int err;
1803         u32 value;
1804         u32 pwm_mode;
1805
1806         if (is_support_sw_smu(adev))
1807                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1808         else
1809                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1810
1811         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1812                 return -ENODATA;
1813
1814         /* Can't adjust fan when the card is off */
1815         if  ((adev->flags & AMD_IS_PX) &&
1816              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1817                 return -EINVAL;
1818
1819         err = kstrtou32(buf, 10, &value);
1820         if (err)
1821                 return err;
1822
1823         if (is_support_sw_smu(adev)) {
1824                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1825                 if (err)
1826                         return err;
1827         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1828                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1829                 if (err)
1830                         return err;
1831         }
1832
1833         return count;
1834 }
1835
1836 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1837                                             struct device_attribute *attr,
1838                                             char *buf)
1839 {
1840         struct amdgpu_device *adev = dev_get_drvdata(dev);
1841         u32 pwm_mode = 0;
1842
1843         if (is_support_sw_smu(adev)) {
1844                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1845         } else {
1846                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1847                         return -EINVAL;
1848
1849                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1850         }
1851         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1852 }
1853
1854 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1855                                             struct device_attribute *attr,
1856                                             const char *buf,
1857                                             size_t count)
1858 {
1859         struct amdgpu_device *adev = dev_get_drvdata(dev);
1860         int err;
1861         int value;
1862         u32 pwm_mode;
1863
1864         /* Can't adjust fan when the card is off */
1865         if  ((adev->flags & AMD_IS_PX) &&
1866              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1867                 return -EINVAL;
1868
1869
1870         err = kstrtoint(buf, 10, &value);
1871         if (err)
1872                 return err;
1873
1874         if (value == 0)
1875                 pwm_mode = AMD_FAN_CTRL_AUTO;
1876         else if (value == 1)
1877                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1878         else
1879                 return -EINVAL;
1880
1881         if (is_support_sw_smu(adev)) {
1882                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1883         } else {
1884                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1885                         return -EINVAL;
1886                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1887         }
1888
1889         return count;
1890 }
1891
1892 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1893                                         struct device_attribute *attr,
1894                                         char *buf)
1895 {
1896         struct amdgpu_device *adev = dev_get_drvdata(dev);
1897         struct drm_device *ddev = adev->ddev;
1898         u32 vddgfx;
1899         int r, size = sizeof(vddgfx);
1900
1901         /* Can't get voltage when the card is off */
1902         if  ((adev->flags & AMD_IS_PX) &&
1903              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1904                 return -EINVAL;
1905
1906         /* get the voltage */
1907         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1908                                    (void *)&vddgfx, &size);
1909         if (r)
1910                 return r;
1911
1912         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1913 }
1914
1915 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1916                                               struct device_attribute *attr,
1917                                               char *buf)
1918 {
1919         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1920 }
1921
1922 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1923                                        struct device_attribute *attr,
1924                                        char *buf)
1925 {
1926         struct amdgpu_device *adev = dev_get_drvdata(dev);
1927         struct drm_device *ddev = adev->ddev;
1928         u32 vddnb;
1929         int r, size = sizeof(vddnb);
1930
1931         /* only APUs have vddnb */
1932         if  (!(adev->flags & AMD_IS_APU))
1933                 return -EINVAL;
1934
1935         /* Can't get voltage when the card is off */
1936         if  ((adev->flags & AMD_IS_PX) &&
1937              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1938                 return -EINVAL;
1939
1940         /* get the voltage */
1941         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1942                                    (void *)&vddnb, &size);
1943         if (r)
1944                 return r;
1945
1946         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1947 }
1948
1949 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1950                                               struct device_attribute *attr,
1951                                               char *buf)
1952 {
1953         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1954 }
1955
1956 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1957                                            struct device_attribute *attr,
1958                                            char *buf)
1959 {
1960         struct amdgpu_device *adev = dev_get_drvdata(dev);
1961         struct drm_device *ddev = adev->ddev;
1962         u32 query = 0;
1963         int r, size = sizeof(u32);
1964         unsigned uw;
1965
1966         /* Can't get power when the card is off */
1967         if  ((adev->flags & AMD_IS_PX) &&
1968              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1969                 return -EINVAL;
1970
1971         /* get the voltage */
1972         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1973                                    (void *)&query, &size);
1974         if (r)
1975                 return r;
1976
1977         /* convert to microwatts */
1978         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1979
1980         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1981 }
1982
1983 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1984                                          struct device_attribute *attr,
1985                                          char *buf)
1986 {
1987         return sprintf(buf, "%i\n", 0);
1988 }
1989
1990 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1991                                          struct device_attribute *attr,
1992                                          char *buf)
1993 {
1994         struct amdgpu_device *adev = dev_get_drvdata(dev);
1995         uint32_t limit = 0;
1996
1997         if (is_support_sw_smu(adev)) {
1998                 smu_get_power_limit(&adev->smu, &limit, true);
1999                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2000         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2001                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2002                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2003         } else {
2004                 return snprintf(buf, PAGE_SIZE, "\n");
2005         }
2006 }
2007
2008 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2009                                          struct device_attribute *attr,
2010                                          char *buf)
2011 {
2012         struct amdgpu_device *adev = dev_get_drvdata(dev);
2013         uint32_t limit = 0;
2014
2015         if (is_support_sw_smu(adev)) {
2016                 smu_get_power_limit(&adev->smu, &limit, false);
2017                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2018         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2019                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2020                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2021         } else {
2022                 return snprintf(buf, PAGE_SIZE, "\n");
2023         }
2024 }
2025
2026
2027 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2028                 struct device_attribute *attr,
2029                 const char *buf,
2030                 size_t count)
2031 {
2032         struct amdgpu_device *adev = dev_get_drvdata(dev);
2033         int err;
2034         u32 value;
2035
2036         err = kstrtou32(buf, 10, &value);
2037         if (err)
2038                 return err;
2039
2040         value = value / 1000000; /* convert to Watt */
2041         if (is_support_sw_smu(adev)) {
2042                 adev->smu.funcs->set_power_limit(&adev->smu, value);
2043         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2044                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2045                 if (err)
2046                         return err;
2047         } else {
2048                 return -EINVAL;
2049         }
2050
2051         return count;
2052 }
2053
2054 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2055                                       struct device_attribute *attr,
2056                                       char *buf)
2057 {
2058         struct amdgpu_device *adev = dev_get_drvdata(dev);
2059         struct drm_device *ddev = adev->ddev;
2060         uint32_t sclk;
2061         int r, size = sizeof(sclk);
2062
2063         /* Can't get voltage when the card is off */
2064         if  ((adev->flags & AMD_IS_PX) &&
2065              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2066                 return -EINVAL;
2067
2068         /* sanity check PP is enabled */
2069         if (!(adev->powerplay.pp_funcs &&
2070               adev->powerplay.pp_funcs->read_sensor))
2071               return -EINVAL;
2072
2073         /* get the sclk */
2074         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2075                                    (void *)&sclk, &size);
2076         if (r)
2077                 return r;
2078
2079         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2080 }
2081
2082 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2083                                             struct device_attribute *attr,
2084                                             char *buf)
2085 {
2086         return snprintf(buf, PAGE_SIZE, "sclk\n");
2087 }
2088
2089 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2090                                       struct device_attribute *attr,
2091                                       char *buf)
2092 {
2093         struct amdgpu_device *adev = dev_get_drvdata(dev);
2094         struct drm_device *ddev = adev->ddev;
2095         uint32_t mclk;
2096         int r, size = sizeof(mclk);
2097
2098         /* Can't get voltage when the card is off */
2099         if  ((adev->flags & AMD_IS_PX) &&
2100              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2101                 return -EINVAL;
2102
2103         /* sanity check PP is enabled */
2104         if (!(adev->powerplay.pp_funcs &&
2105               adev->powerplay.pp_funcs->read_sensor))
2106               return -EINVAL;
2107
2108         /* get the sclk */
2109         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2110                                    (void *)&mclk, &size);
2111         if (r)
2112                 return r;
2113
2114         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2115 }
2116
2117 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2118                                             struct device_attribute *attr,
2119                                             char *buf)
2120 {
2121         return snprintf(buf, PAGE_SIZE, "mclk\n");
2122 }
2123
2124 /**
2125  * DOC: hwmon
2126  *
2127  * The amdgpu driver exposes the following sensor interfaces:
2128  *
2129  * - GPU temperature (via the on-die sensor)
2130  *
2131  * - GPU voltage
2132  *
2133  * - Northbridge voltage (APUs only)
2134  *
2135  * - GPU power
2136  *
2137  * - GPU fan
2138  *
2139  * - GPU gfx/compute engine clock
2140  *
2141  * - GPU memory clock (dGPU only)
2142  *
2143  * hwmon interfaces for GPU temperature:
2144  *
2145  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2146  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2147  *
2148  * - temp[1-3]_label: temperature channel label
2149  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2150  *
2151  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2152  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2153  *
2154  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2155  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2156  *
2157  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2158  *   - these are supported on SOC15 dGPUs only
2159  *
2160  * hwmon interfaces for GPU voltage:
2161  *
2162  * - in0_input: the voltage on the GPU in millivolts
2163  *
2164  * - in1_input: the voltage on the Northbridge in millivolts
2165  *
2166  * hwmon interfaces for GPU power:
2167  *
2168  * - power1_average: average power used by the GPU in microWatts
2169  *
2170  * - power1_cap_min: minimum cap supported in microWatts
2171  *
2172  * - power1_cap_max: maximum cap supported in microWatts
2173  *
2174  * - power1_cap: selected power cap in microWatts
2175  *
2176  * hwmon interfaces for GPU fan:
2177  *
2178  * - pwm1: pulse width modulation fan level (0-255)
2179  *
2180  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2181  *
2182  * - pwm1_min: pulse width modulation fan control minimum level (0)
2183  *
2184  * - pwm1_max: pulse width modulation fan control maximum level (255)
2185  *
2186  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2187  *
2188  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2189  *
2190  * - fan1_input: fan speed in RPM
2191  *
2192  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2193  *
2194  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2195  *
2196  * hwmon interfaces for GPU clocks:
2197  *
2198  * - freq1_input: the gfx/compute clock in hertz
2199  *
2200  * - freq2_input: the memory clock in hertz
2201  *
2202  * You can use hwmon tools like sensors to view this information on your system.
2203  *
2204  */
2205
2206 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2207 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2208 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2209 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2210 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2211 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2212 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2213 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2214 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2215 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2216 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2217 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2218 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2219 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2220 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2221 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2222 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2223 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2224 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2225 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2226 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2227 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2228 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2229 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2230 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2231 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2232 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2233 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2234 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2235 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2236 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2237 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2238 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2239 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2240 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2241 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2242
2243 static struct attribute *hwmon_attributes[] = {
2244         &sensor_dev_attr_temp1_input.dev_attr.attr,
2245         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2246         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2247         &sensor_dev_attr_temp2_input.dev_attr.attr,
2248         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2249         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2250         &sensor_dev_attr_temp3_input.dev_attr.attr,
2251         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2252         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2253         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2254         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2255         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2256         &sensor_dev_attr_temp1_label.dev_attr.attr,
2257         &sensor_dev_attr_temp2_label.dev_attr.attr,
2258         &sensor_dev_attr_temp3_label.dev_attr.attr,
2259         &sensor_dev_attr_pwm1.dev_attr.attr,
2260         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2261         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2262         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2263         &sensor_dev_attr_fan1_input.dev_attr.attr,
2264         &sensor_dev_attr_fan1_min.dev_attr.attr,
2265         &sensor_dev_attr_fan1_max.dev_attr.attr,
2266         &sensor_dev_attr_fan1_target.dev_attr.attr,
2267         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2268         &sensor_dev_attr_in0_input.dev_attr.attr,
2269         &sensor_dev_attr_in0_label.dev_attr.attr,
2270         &sensor_dev_attr_in1_input.dev_attr.attr,
2271         &sensor_dev_attr_in1_label.dev_attr.attr,
2272         &sensor_dev_attr_power1_average.dev_attr.attr,
2273         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2274         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2275         &sensor_dev_attr_power1_cap.dev_attr.attr,
2276         &sensor_dev_attr_freq1_input.dev_attr.attr,
2277         &sensor_dev_attr_freq1_label.dev_attr.attr,
2278         &sensor_dev_attr_freq2_input.dev_attr.attr,
2279         &sensor_dev_attr_freq2_label.dev_attr.attr,
2280         NULL
2281 };
2282
2283 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2284                                         struct attribute *attr, int index)
2285 {
2286         struct device *dev = kobj_to_dev(kobj);
2287         struct amdgpu_device *adev = dev_get_drvdata(dev);
2288         umode_t effective_mode = attr->mode;
2289
2290         /* Skip fan attributes if fan is not present */
2291         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2292             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2293             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2294             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2295             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2296             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2297             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2298             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2299             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2300                 return 0;
2301
2302         /* Skip fan attributes on APU */
2303         if ((adev->flags & AMD_IS_APU) &&
2304             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2305              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2306              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2307              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2308              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2309              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2310              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2311              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2312              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2313                 return 0;
2314
2315         /* Skip limit attributes if DPM is not enabled */
2316         if (!adev->pm.dpm_enabled &&
2317             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2318              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2319              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2320              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2321              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2322              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2323              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2324              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2325              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2326              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2327              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2328                 return 0;
2329
2330         if (!is_support_sw_smu(adev)) {
2331                 /* mask fan attributes if we have no bindings for this asic to expose */
2332                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2333                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2334                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2335                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2336                         effective_mode &= ~S_IRUGO;
2337
2338                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2339                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2340                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2341                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2342                         effective_mode &= ~S_IWUSR;
2343         }
2344
2345         if ((adev->flags & AMD_IS_APU) &&
2346             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2347              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2348              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2349              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2350                 return 0;
2351
2352         if (!is_support_sw_smu(adev)) {
2353                 /* hide max/min values if we can't both query and manage the fan */
2354                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2355                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2356                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2357                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2358                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2359                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2360                         return 0;
2361
2362                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2363                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2364                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2365                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2366                         return 0;
2367         }
2368
2369         /* only APUs have vddnb */
2370         if (!(adev->flags & AMD_IS_APU) &&
2371             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2372              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2373                 return 0;
2374
2375         /* no mclk on APUs */
2376         if ((adev->flags & AMD_IS_APU) &&
2377             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2378              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2379                 return 0;
2380
2381         /* only SOC15 dGPUs support hotspot and mem temperatures */
2382         if (((adev->flags & AMD_IS_APU) ||
2383              adev->asic_type < CHIP_VEGA10) &&
2384             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2385              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2386              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2387              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2388              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2389              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2390              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2391              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2392              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2393              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2394              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2395                 return 0;
2396
2397         return effective_mode;
2398 }
2399
2400 static const struct attribute_group hwmon_attrgroup = {
2401         .attrs = hwmon_attributes,
2402         .is_visible = hwmon_attributes_visible,
2403 };
2404
2405 static const struct attribute_group *hwmon_groups[] = {
2406         &hwmon_attrgroup,
2407         NULL
2408 };
2409
2410 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2411 {
2412         struct amdgpu_device *adev =
2413                 container_of(work, struct amdgpu_device,
2414                              pm.dpm.thermal.work);
2415         /* switch to the thermal state */
2416         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2417         int temp, size = sizeof(temp);
2418
2419         if (!adev->pm.dpm_enabled)
2420                 return;
2421
2422         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2423                                     (void *)&temp, &size)) {
2424                 if (temp < adev->pm.dpm.thermal.min_temp)
2425                         /* switch back the user state */
2426                         dpm_state = adev->pm.dpm.user_state;
2427         } else {
2428                 if (adev->pm.dpm.thermal.high_to_low)
2429                         /* switch back the user state */
2430                         dpm_state = adev->pm.dpm.user_state;
2431         }
2432         mutex_lock(&adev->pm.mutex);
2433         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2434                 adev->pm.dpm.thermal_active = true;
2435         else
2436                 adev->pm.dpm.thermal_active = false;
2437         adev->pm.dpm.state = dpm_state;
2438         mutex_unlock(&adev->pm.mutex);
2439
2440         amdgpu_pm_compute_clocks(adev);
2441 }
2442
2443 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2444                                                      enum amd_pm_state_type dpm_state)
2445 {
2446         int i;
2447         struct amdgpu_ps *ps;
2448         u32 ui_class;
2449         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2450                 true : false;
2451
2452         /* check if the vblank period is too short to adjust the mclk */
2453         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2454                 if (amdgpu_dpm_vblank_too_short(adev))
2455                         single_display = false;
2456         }
2457
2458         /* certain older asics have a separare 3D performance state,
2459          * so try that first if the user selected performance
2460          */
2461         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2462                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2463         /* balanced states don't exist at the moment */
2464         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2465                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2466
2467 restart_search:
2468         /* Pick the best power state based on current conditions */
2469         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2470                 ps = &adev->pm.dpm.ps[i];
2471                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2472                 switch (dpm_state) {
2473                 /* user states */
2474                 case POWER_STATE_TYPE_BATTERY:
2475                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2476                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2477                                         if (single_display)
2478                                                 return ps;
2479                                 } else
2480                                         return ps;
2481                         }
2482                         break;
2483                 case POWER_STATE_TYPE_BALANCED:
2484                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2485                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2486                                         if (single_display)
2487                                                 return ps;
2488                                 } else
2489                                         return ps;
2490                         }
2491                         break;
2492                 case POWER_STATE_TYPE_PERFORMANCE:
2493                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2494                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2495                                         if (single_display)
2496                                                 return ps;
2497                                 } else
2498                                         return ps;
2499                         }
2500                         break;
2501                 /* internal states */
2502                 case POWER_STATE_TYPE_INTERNAL_UVD:
2503                         if (adev->pm.dpm.uvd_ps)
2504                                 return adev->pm.dpm.uvd_ps;
2505                         else
2506                                 break;
2507                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2508                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2509                                 return ps;
2510                         break;
2511                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2512                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2513                                 return ps;
2514                         break;
2515                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2516                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2517                                 return ps;
2518                         break;
2519                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2520                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2521                                 return ps;
2522                         break;
2523                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2524                         return adev->pm.dpm.boot_ps;
2525                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2526                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2527                                 return ps;
2528                         break;
2529                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2530                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2531                                 return ps;
2532                         break;
2533                 case POWER_STATE_TYPE_INTERNAL_ULV:
2534                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2535                                 return ps;
2536                         break;
2537                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2538                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2539                                 return ps;
2540                         break;
2541                 default:
2542                         break;
2543                 }
2544         }
2545         /* use a fallback state if we didn't match */
2546         switch (dpm_state) {
2547         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2548                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2549                 goto restart_search;
2550         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2551         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2552         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2553                 if (adev->pm.dpm.uvd_ps) {
2554                         return adev->pm.dpm.uvd_ps;
2555                 } else {
2556                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2557                         goto restart_search;
2558                 }
2559         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2560                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2561                 goto restart_search;
2562         case POWER_STATE_TYPE_INTERNAL_ACPI:
2563                 dpm_state = POWER_STATE_TYPE_BATTERY;
2564                 goto restart_search;
2565         case POWER_STATE_TYPE_BATTERY:
2566         case POWER_STATE_TYPE_BALANCED:
2567         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2568                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2569                 goto restart_search;
2570         default:
2571                 break;
2572         }
2573
2574         return NULL;
2575 }
2576
2577 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2578 {
2579         struct amdgpu_ps *ps;
2580         enum amd_pm_state_type dpm_state;
2581         int ret;
2582         bool equal = false;
2583
2584         /* if dpm init failed */
2585         if (!adev->pm.dpm_enabled)
2586                 return;
2587
2588         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2589                 /* add other state override checks here */
2590                 if ((!adev->pm.dpm.thermal_active) &&
2591                     (!adev->pm.dpm.uvd_active))
2592                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2593         }
2594         dpm_state = adev->pm.dpm.state;
2595
2596         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2597         if (ps)
2598                 adev->pm.dpm.requested_ps = ps;
2599         else
2600                 return;
2601
2602         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2603                 printk("switching from power state:\n");
2604                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2605                 printk("switching to power state:\n");
2606                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2607         }
2608
2609         /* update whether vce is active */
2610         ps->vce_active = adev->pm.dpm.vce_active;
2611         if (adev->powerplay.pp_funcs->display_configuration_changed)
2612                 amdgpu_dpm_display_configuration_changed(adev);
2613
2614         ret = amdgpu_dpm_pre_set_power_state(adev);
2615         if (ret)
2616                 return;
2617
2618         if (adev->powerplay.pp_funcs->check_state_equal) {
2619                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2620                         equal = false;
2621         }
2622
2623         if (equal)
2624                 return;
2625
2626         amdgpu_dpm_set_power_state(adev);
2627         amdgpu_dpm_post_set_power_state(adev);
2628
2629         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2630         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2631
2632         if (adev->powerplay.pp_funcs->force_performance_level) {
2633                 if (adev->pm.dpm.thermal_active) {
2634                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2635                         /* force low perf level for thermal */
2636                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2637                         /* save the user's level */
2638                         adev->pm.dpm.forced_level = level;
2639                 } else {
2640                         /* otherwise, user selected level */
2641                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2642                 }
2643         }
2644 }
2645
2646 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2647 {
2648         int ret = 0;
2649         if (is_support_sw_smu(adev)) {
2650             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2651             if (ret)
2652                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2653                           enable ? "true" : "false", ret);
2654         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2655                 /* enable/disable UVD */
2656                 mutex_lock(&adev->pm.mutex);
2657                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2658                 mutex_unlock(&adev->pm.mutex);
2659         }
2660         /* enable/disable Low Memory PState for UVD (4k videos) */
2661         if (adev->asic_type == CHIP_STONEY &&
2662                 adev->uvd.decode_image_width >= WIDTH_4K) {
2663                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2664
2665                 if (hwmgr && hwmgr->hwmgr_func &&
2666                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2667                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2668                                                                !enable,
2669                                                                true);
2670         }
2671 }
2672
2673 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2674 {
2675         int ret = 0;
2676         if (is_support_sw_smu(adev)) {
2677             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2678             if (ret)
2679                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2680                           enable ? "true" : "false", ret);
2681         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2682                 /* enable/disable VCE */
2683                 mutex_lock(&adev->pm.mutex);
2684                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2685                 mutex_unlock(&adev->pm.mutex);
2686         }
2687 }
2688
2689 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2690 {
2691         int i;
2692
2693         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2694                 return;
2695
2696         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2697                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2698
2699 }
2700
2701 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2702 {
2703         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2704         int ret;
2705
2706         if (adev->pm.sysfs_initialized)
2707                 return 0;
2708
2709         if (adev->pm.dpm_enabled == 0)
2710                 return 0;
2711
2712         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2713                                                                    DRIVER_NAME, adev,
2714                                                                    hwmon_groups);
2715         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2716                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2717                 dev_err(adev->dev,
2718                         "Unable to register hwmon device: %d\n", ret);
2719                 return ret;
2720         }
2721
2722         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2723         if (ret) {
2724                 DRM_ERROR("failed to create device file for dpm state\n");
2725                 return ret;
2726         }
2727         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2728         if (ret) {
2729                 DRM_ERROR("failed to create device file for dpm state\n");
2730                 return ret;
2731         }
2732
2733
2734         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2735         if (ret) {
2736                 DRM_ERROR("failed to create device file pp_num_states\n");
2737                 return ret;
2738         }
2739         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2740         if (ret) {
2741                 DRM_ERROR("failed to create device file pp_cur_state\n");
2742                 return ret;
2743         }
2744         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2745         if (ret) {
2746                 DRM_ERROR("failed to create device file pp_force_state\n");
2747                 return ret;
2748         }
2749         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2750         if (ret) {
2751                 DRM_ERROR("failed to create device file pp_table\n");
2752                 return ret;
2753         }
2754
2755         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2756         if (ret) {
2757                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2758                 return ret;
2759         }
2760         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2761         if (ret) {
2762                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2763                 return ret;
2764         }
2765         if (adev->asic_type >= CHIP_VEGA10) {
2766                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2767                 if (ret) {
2768                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2769                         return ret;
2770                 }
2771                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2772                 if (ret) {
2773                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2774                         return ret;
2775                 }
2776         }
2777         if (adev->asic_type >= CHIP_VEGA20) {
2778                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2779                 if (ret) {
2780                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2781                         return ret;
2782                 }
2783         }
2784         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2785         if (ret) {
2786                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2787                 return ret;
2788         }
2789         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2790         if (ret) {
2791                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2792                 return ret;
2793         }
2794         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2795         if (ret) {
2796                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2797                 return ret;
2798         }
2799         ret = device_create_file(adev->dev,
2800                         &dev_attr_pp_power_profile_mode);
2801         if (ret) {
2802                 DRM_ERROR("failed to create device file "
2803                                 "pp_power_profile_mode\n");
2804                 return ret;
2805         }
2806         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2807             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2808                 ret = device_create_file(adev->dev,
2809                                 &dev_attr_pp_od_clk_voltage);
2810                 if (ret) {
2811                         DRM_ERROR("failed to create device file "
2812                                         "pp_od_clk_voltage\n");
2813                         return ret;
2814                 }
2815         }
2816         ret = device_create_file(adev->dev,
2817                         &dev_attr_gpu_busy_percent);
2818         if (ret) {
2819                 DRM_ERROR("failed to create device file "
2820                                 "gpu_busy_level\n");
2821                 return ret;
2822         }
2823         /* APU does not have its own dedicated memory */
2824         if (!(adev->flags & AMD_IS_APU)) {
2825                 ret = device_create_file(adev->dev,
2826                                 &dev_attr_mem_busy_percent);
2827                 if (ret) {
2828                         DRM_ERROR("failed to create device file "
2829                                         "mem_busy_percent\n");
2830                         return ret;
2831                 }
2832         }
2833         /* PCIe Perf counters won't work on APU nodes */
2834         if (!(adev->flags & AMD_IS_APU)) {
2835                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2836                 if (ret) {
2837                         DRM_ERROR("failed to create device file pcie_bw\n");
2838                         return ret;
2839                 }
2840         }
2841         if (adev->unique_id)
2842                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
2843         if (ret) {
2844                 DRM_ERROR("failed to create device file unique_id\n");
2845                 return ret;
2846         }
2847         ret = amdgpu_debugfs_pm_init(adev);
2848         if (ret) {
2849                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2850                 return ret;
2851         }
2852
2853         if ((adev->asic_type >= CHIP_VEGA10) &&
2854             !(adev->flags & AMD_IS_APU)) {
2855                 ret = device_create_file(adev->dev,
2856                                 &dev_attr_ppfeatures);
2857                 if (ret) {
2858                         DRM_ERROR("failed to create device file "
2859                                         "ppfeatures\n");
2860                         return ret;
2861                 }
2862         }
2863
2864         adev->pm.sysfs_initialized = true;
2865
2866         return 0;
2867 }
2868
2869 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2870 {
2871         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2872
2873         if (adev->pm.dpm_enabled == 0)
2874                 return;
2875
2876         if (adev->pm.int_hwmon_dev)
2877                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2878         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2879         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2880
2881         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2882         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2883         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2884         device_remove_file(adev->dev, &dev_attr_pp_table);
2885
2886         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2887         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2888         if (adev->asic_type >= CHIP_VEGA10) {
2889                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2890                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2891         }
2892         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2893         if (adev->asic_type >= CHIP_VEGA20)
2894                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2895         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2896         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2897         device_remove_file(adev->dev,
2898                         &dev_attr_pp_power_profile_mode);
2899         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2900             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2901                 device_remove_file(adev->dev,
2902                                 &dev_attr_pp_od_clk_voltage);
2903         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2904         if (!(adev->flags & AMD_IS_APU))
2905                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2906         if (!(adev->flags & AMD_IS_APU))
2907                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2908         if (adev->unique_id)
2909                 device_remove_file(adev->dev, &dev_attr_unique_id);
2910         if ((adev->asic_type >= CHIP_VEGA10) &&
2911             !(adev->flags & AMD_IS_APU))
2912                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2913 }
2914
2915 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2916 {
2917         int i = 0;
2918
2919         if (!adev->pm.dpm_enabled)
2920                 return;
2921
2922         if (adev->mode_info.num_crtc)
2923                 amdgpu_display_bandwidth_update(adev);
2924
2925         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2926                 struct amdgpu_ring *ring = adev->rings[i];
2927                 if (ring && ring->sched.ready)
2928                         amdgpu_fence_wait_empty(ring);
2929         }
2930
2931         if (is_support_sw_smu(adev)) {
2932                 struct smu_context *smu = &adev->smu;
2933                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2934                 mutex_lock(&(smu->mutex));
2935                 smu_handle_task(&adev->smu,
2936                                 smu_dpm->dpm_level,
2937                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2938                 mutex_unlock(&(smu->mutex));
2939         } else {
2940                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2941                         if (!amdgpu_device_has_dc_support(adev)) {
2942                                 mutex_lock(&adev->pm.mutex);
2943                                 amdgpu_dpm_get_active_displays(adev);
2944                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2945                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2946                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2947                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2948                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
2949                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
2950                                 if (adev->powerplay.pp_funcs->display_configuration_change)
2951                                         adev->powerplay.pp_funcs->display_configuration_change(
2952                                                                         adev->powerplay.pp_handle,
2953                                                                         &adev->pm.pm_display_cfg);
2954                                 mutex_unlock(&adev->pm.mutex);
2955                         }
2956                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2957                 } else {
2958                         mutex_lock(&adev->pm.mutex);
2959                         amdgpu_dpm_get_active_displays(adev);
2960                         amdgpu_dpm_change_power_state_locked(adev);
2961                         mutex_unlock(&adev->pm.mutex);
2962                 }
2963         }
2964 }
2965
2966 /*
2967  * Debugfs info
2968  */
2969 #if defined(CONFIG_DEBUG_FS)
2970
2971 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2972 {
2973         uint32_t value;
2974         uint64_t value64;
2975         uint32_t query = 0;
2976         int size;
2977
2978         /* GPU Clocks */
2979         size = sizeof(value);
2980         seq_printf(m, "GFX Clocks and Power:\n");
2981         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2982                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2983         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2984                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2985         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2986                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2987         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2988                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2989         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2990                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2991         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2992                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2993         size = sizeof(uint32_t);
2994         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2995                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2996         size = sizeof(value);
2997         seq_printf(m, "\n");
2998
2999         /* GPU Temp */
3000         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3001                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3002
3003         /* GPU Load */
3004         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3005                 seq_printf(m, "GPU Load: %u %%\n", value);
3006         /* MEM Load */
3007         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3008                 seq_printf(m, "MEM Load: %u %%\n", value);
3009
3010         seq_printf(m, "\n");
3011
3012         /* SMC feature mask */
3013         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3014                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3015
3016         /* UVD clocks */
3017         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3018                 if (!value) {
3019                         seq_printf(m, "UVD: Disabled\n");
3020                 } else {
3021                         seq_printf(m, "UVD: Enabled\n");
3022                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3023                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3024                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3025                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3026                 }
3027         }
3028         seq_printf(m, "\n");
3029
3030         /* VCE clocks */
3031         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3032                 if (!value) {
3033                         seq_printf(m, "VCE: Disabled\n");
3034                 } else {
3035                         seq_printf(m, "VCE: Enabled\n");
3036                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3037                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3038                 }
3039         }
3040
3041         return 0;
3042 }
3043
3044 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3045 {
3046         int i;
3047
3048         for (i = 0; clocks[i].flag; i++)
3049                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3050                            (flags & clocks[i].flag) ? "On" : "Off");
3051 }
3052
3053 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3054 {
3055         struct drm_info_node *node = (struct drm_info_node *) m->private;
3056         struct drm_device *dev = node->minor->dev;
3057         struct amdgpu_device *adev = dev->dev_private;
3058         struct drm_device *ddev = adev->ddev;
3059         u32 flags = 0;
3060
3061         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3062         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3063         amdgpu_parse_cg_state(m, flags);
3064         seq_printf(m, "\n");
3065
3066         if (!adev->pm.dpm_enabled) {
3067                 seq_printf(m, "dpm not enabled\n");
3068                 return 0;
3069         }
3070         if  ((adev->flags & AMD_IS_PX) &&
3071              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3072                 seq_printf(m, "PX asic powered off\n");
3073         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3074                 mutex_lock(&adev->pm.mutex);
3075                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3076                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3077                 else
3078                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3079                 mutex_unlock(&adev->pm.mutex);
3080         } else {
3081                 return amdgpu_debugfs_pm_info_pp(m, adev);
3082         }
3083
3084         return 0;
3085 }
3086
3087 static const struct drm_info_list amdgpu_pm_info_list[] = {
3088         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3089 };
3090 #endif
3091
3092 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3093 {
3094 #if defined(CONFIG_DEBUG_FS)
3095         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3096 #else
3097         return 0;
3098 #endif
3099 }