drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/vmalloc.h>
  26 #include <drm/drm_drv.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ras.h"
  31 #include "amdgpu_ucode.h"
  32 #include "soc15_common.h"
  33 #include "psp_v11_0.h"
  34
  35 #include "mp/mp_11_0_offset.h"
  36 #include "mp/mp_11_0_sh_mask.h"
  37 #include "gc/gc_9_0_offset.h"
  38 #include "sdma0/sdma0_4_0_offset.h"
  39 #include "nbio/nbio_7_4_offset.h"
  40
  41 #include "oss/osssys_4_0_offset.h"
  42 #include "oss/osssys_4_0_sh_mask.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
  56 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  57 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  58 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
  59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
  60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
  61 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
  62 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
  63 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
  64 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
  65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
  66 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
  67 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
  68 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
  69
  70 /* address block */
  71 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  72 /* navi10 reg offset define */
  73 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  74 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  75 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  76 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  77 /* memory training timeout define */
  78 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  79
  80 /* For large FW files the time to complete can be very long */
  81 #define USBC_PD_POLLING_LIMIT_S 240
  82
  83 /* Read USB-PD from LFB */
  84 #define GFX_CMD_USB_PD_USE_LFB 0x480
  85
  86 static int psp_v11_0_init_microcode(struct psp_context *psp)
  87 {
  88         struct amdgpu_device *adev = psp->adev;
  89         const char *chip_name;
  90         char fw_name[PSP_FW_NAME_LEN];
  91         int err = 0;
  92         const struct ta_firmware_header_v1_0 *ta_hdr;
  93
  94         DRM_DEBUG("\n");
  95
  96         switch (adev->ip_versions[MP0_HWIP][0]) {
  97         case IP_VERSION(11, 0, 2):
  98                 chip_name = "vega20";
  99                 break;
 100         case IP_VERSION(11, 0, 0):
 101                 chip_name = "navi10";
 102                 break;
 103         case IP_VERSION(11, 0, 5):
 104                 chip_name = "navi14";
 105                 break;
 106         case IP_VERSION(11, 0, 9):
 107                 chip_name = "navi12";
 108                 break;
 109         case IP_VERSION(11, 0, 4):
 110                 chip_name = "arcturus";
 111                 break;
 112         case IP_VERSION(11, 0, 7):
 113                 chip_name = "sienna_cichlid";
 114                 break;
 115         case IP_VERSION(11, 0, 11):
 116                 chip_name = "navy_flounder";
 117                 break;
 118         case IP_VERSION(11, 5, 0):
 119                 chip_name = "vangogh";
 120                 break;
 121         case IP_VERSION(11, 0, 12):
 122                 chip_name = "dimgrey_cavefish";
 123                 break;
 124         case IP_VERSION(11, 0, 13):
 125                 chip_name = "beige_goby";
 126                 break;
 127         default:
 128                 BUG();
 129         }
 130
 131
 132         switch (adev->ip_versions[MP0_HWIP][0]) {
 133         case IP_VERSION(11, 0, 2):
 134         case IP_VERSION(11, 0, 4):
 135                 err = psp_init_sos_microcode(psp, chip_name);
 136                 if (err)
 137                         return err;
 138                 err = psp_init_asd_microcode(psp, chip_name);
 139                 if (err)
 140                         return err;
 141                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 142                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 143                 if (err) {
 144                         release_firmware(adev->psp.ta_fw);
 145                         adev->psp.ta_fw = NULL;
 146                         dev_info(adev->dev,
 147                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 148                 } else {
 149                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 150                         if (err)
 151                                 goto out2;
 152
 153                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 154                         adev->psp.xgmi_context.context.bin_desc.fw_version =
 155                                 le32_to_cpu(ta_hdr->xgmi.fw_version);
 156                         adev->psp.xgmi_context.context.bin_desc.size_bytes =
 157                                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
 158                         adev->psp.xgmi_context.context.bin_desc.start_addr =
 159                                 (uint8_t *)ta_hdr +
 160                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 161                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 162                         adev->psp.ras_context.context.bin_desc.fw_version =
 163                                 le32_to_cpu(ta_hdr->ras.fw_version);
 164                         adev->psp.ras_context.context.bin_desc.size_bytes =
 165                                 le32_to_cpu(ta_hdr->ras.size_bytes);
 166                         adev->psp.ras_context.context.bin_desc.start_addr =
 167                                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
 168                                 le32_to_cpu(ta_hdr->ras.offset_bytes);
 169                 }
 170                 break;
 171         case IP_VERSION(11, 0, 0):
 172         case IP_VERSION(11, 0, 5):
 173         case IP_VERSION(11, 0, 9):
 174                 err = psp_init_sos_microcode(psp, chip_name);
 175                 if (err)
 176                         return err;
 177                 err = psp_init_asd_microcode(psp, chip_name);
 178                 if (err)
 179                         return err;
 180                 if (amdgpu_sriov_vf(adev))
 181                         break;
 182                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 183                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 184                 if (err) {
 185                         release_firmware(adev->psp.ta_fw);
 186                         adev->psp.ta_fw = NULL;
 187                         dev_info(adev->dev,
 188                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 189                 } else {
 190                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 191                         if (err)
 192                                 goto out2;
 193
 194                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 195                         adev->psp.hdcp_context.context.bin_desc.fw_version =
 196                                 le32_to_cpu(ta_hdr->hdcp.fw_version);
 197                         adev->psp.hdcp_context.context.bin_desc.size_bytes =
 198                                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
 199                         adev->psp.hdcp_context.context.bin_desc.start_addr =
 200                                 (uint8_t *)ta_hdr +
 201                                 le32_to_cpu(
 202                                         ta_hdr->header.ucode_array_offset_bytes);
 203
 204                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 205
 206                         adev->psp.dtm_context.context.bin_desc.fw_version =
 207                                 le32_to_cpu(ta_hdr->dtm.fw_version);
 208                         adev->psp.dtm_context.context.bin_desc.size_bytes =
 209                                 le32_to_cpu(ta_hdr->dtm.size_bytes);
 210                         adev->psp.dtm_context.context.bin_desc.start_addr =
 211                                 (uint8_t *)adev->psp.hdcp_context.context
 212                                         .bin_desc.start_addr +
 213                                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
 214                 }
 215                 break;
 216         case IP_VERSION(11, 0, 7):
 217         case IP_VERSION(11, 0, 11):
 218         case IP_VERSION(11, 0, 12):
 219         case IP_VERSION(11, 0, 13):
 220                 err = psp_init_sos_microcode(psp, chip_name);
 221                 if (err)
 222                         return err;
 223                 err = psp_init_ta_microcode(psp, chip_name);
 224                 if (err)
 225                         return err;
 226                 break;
 227         case IP_VERSION(11, 5, 0):
 228                 err = psp_init_asd_microcode(psp, chip_name);
 229                 if (err)
 230                         return err;
 231                 err = psp_init_toc_microcode(psp, chip_name);
 232                 if (err)
 233                         return err;
 234                 break;
 235         default:
 236                 BUG();
 237         }
 238
 239         return 0;
 240
 241 out2:
 242         release_firmware(adev->psp.ta_fw);
 243         adev->psp.ta_fw = NULL;
 244         return err;
 245 }
 246
 247 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
 248 {
 249         struct amdgpu_device *adev = psp->adev;
 250
 251         int ret;
 252         int retry_loop;
 253
 254         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 255                 /* Wait for bootloader to signify that is
 256                     ready having bit 31 of C2PMSG_35 set to 1 */
 257                 ret = psp_wait_for(psp,
 258                                    SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 259                                    0x80000000,
 260                                    0x80000000,
 261                                    false);
 262
 263                 if (ret == 0)
 264                         return 0;
 265         }
 266
 267         return ret;
 268 }
 269
 270 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
 271 {
 272         struct amdgpu_device *adev = psp->adev;
 273         uint32_t sol_reg;
 274
 275         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 276
 277         return sol_reg != 0x0;
 278 }
 279
 280 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 281 {
 282         int ret;
 283         uint32_t psp_gfxdrv_command_reg = 0;
 284         struct amdgpu_device *adev = psp->adev;
 285
 286         /* Check tOS sign of life register to confirm sys driver and sOS
 287          * are already been loaded.
 288          */
 289         if (psp_v11_0_is_sos_alive(psp))
 290                 return 0;
 291
 292         ret = psp_v11_0_wait_for_bootloader(psp);
 293         if (ret)
 294                 return ret;
 295
 296         /* Copy PSP KDB binary to memory */
 297         psp_copy_fw(psp, psp->kdb.start_addr, psp->kdb.size_bytes);
 298
 299         /* Provide the PSP KDB to bootloader */
 300         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 301                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 302         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 303         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 304                psp_gfxdrv_command_reg);
 305
 306         ret = psp_v11_0_wait_for_bootloader(psp);
 307
 308         return ret;
 309 }
 310
 311 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
 312 {
 313         int ret;
 314         uint32_t psp_gfxdrv_command_reg = 0;
 315         struct amdgpu_device *adev = psp->adev;
 316
 317         /* Check tOS sign of life register to confirm sys driver and sOS
 318          * are already been loaded.
 319          */
 320         if (psp_v11_0_is_sos_alive(psp))
 321                 return 0;
 322
 323         ret = psp_v11_0_wait_for_bootloader(psp);
 324         if (ret)
 325                 return ret;
 326
 327         /* Copy PSP SPL binary to memory */
 328         psp_copy_fw(psp, psp->spl.start_addr, psp->spl.size_bytes);
 329
 330         /* Provide the PSP SPL to bootloader */
 331         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 332                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 333         psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE;
 334         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 335                psp_gfxdrv_command_reg);
 336
 337         ret = psp_v11_0_wait_for_bootloader(psp);
 338
 339         return ret;
 340 }
 341
 342 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 343 {
 344         int ret;
 345         uint32_t psp_gfxdrv_command_reg = 0;
 346         struct amdgpu_device *adev = psp->adev;
 347
 348         /* Check sOS sign of life register to confirm sys driver and sOS
 349          * are already been loaded.
 350          */
 351         if (psp_v11_0_is_sos_alive(psp))
 352                 return 0;
 353
 354         ret = psp_v11_0_wait_for_bootloader(psp);
 355         if (ret)
 356                 return ret;
 357
 358         /* Copy PSP System Driver binary to memory */
 359         psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
 360
 361         /* Provide the sys driver to bootloader */
 362         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 363                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 364         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 365         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 366                psp_gfxdrv_command_reg);
 367
 368         /* there might be handshake issue with hardware which needs delay */
 369         mdelay(20);
 370
 371         ret = psp_v11_0_wait_for_bootloader(psp);
 372
 373         return ret;
 374 }
 375
 376 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 377 {
 378         int ret;
 379         unsigned int psp_gfxdrv_command_reg = 0;
 380         struct amdgpu_device *adev = psp->adev;
 381
 382         /* Check sOS sign of life register to confirm sys driver and sOS
 383          * are already been loaded.
 384          */
 385         if (psp_v11_0_is_sos_alive(psp))
 386                 return 0;
 387
 388         ret = psp_v11_0_wait_for_bootloader(psp);
 389         if (ret)
 390                 return ret;
 391
 392         /* Copy Secure OS binary to PSP memory */
 393         psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
 394
 395         /* Provide the PSP secure OS to bootloader */
 396         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 397                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 398         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 399         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 400                psp_gfxdrv_command_reg);
 401
 402         /* there might be handshake issue with hardware which needs delay */
 403         mdelay(20);
 404         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 405                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 406                            0, true);
 407
 408         return ret;
 409 }
 410
 411 static int psp_v11_0_ring_init(struct psp_context *psp,
 412                               enum psp_ring_type ring_type)
 413 {
 414         int ret = 0;
 415         struct psp_ring *ring;
 416         struct amdgpu_device *adev = psp->adev;
 417
 418         ring = &psp->km_ring;
 419
 420         ring->ring_type = ring_type;
 421
 422         /* allocate 4k Page of Local Frame Buffer memory for ring */
 423         ring->ring_size = 0x1000;
 424         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 425                                       AMDGPU_GEM_DOMAIN_VRAM,
 426                                       &adev->firmware.rbuf,
 427                                       &ring->ring_mem_mc_addr,
 428                                       (void **)&ring->ring_mem);
 429         if (ret) {
 430                 ring->ring_size = 0;
 431                 return ret;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int psp_v11_0_ring_stop(struct psp_context *psp,
 438                               enum psp_ring_type ring_type)
 439 {
 440         int ret = 0;
 441         struct amdgpu_device *adev = psp->adev;
 442
 443         /* Write the ring destroy command*/
 444         if (amdgpu_sriov_vf(adev))
 445                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 446                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 447         else
 448                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 449                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 450
 451         /* there might be handshake issue with hardware which needs delay */
 452         mdelay(20);
 453
 454         /* Wait for response flag (bit 31) */
 455         if (amdgpu_sriov_vf(adev))
 456                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 457                                    0x80000000, 0x80000000, false);
 458         else
 459                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 460                                    0x80000000, 0x80000000, false);
 461
 462         return ret;
 463 }
 464
 465 static int psp_v11_0_ring_create(struct psp_context *psp,
 466                                 enum psp_ring_type ring_type)
 467 {
 468         int ret = 0;
 469         unsigned int psp_ring_reg = 0;
 470         struct psp_ring *ring = &psp->km_ring;
 471         struct amdgpu_device *adev = psp->adev;
 472
 473         if (amdgpu_sriov_vf(adev)) {
 474                 ring->ring_wptr = 0;
 475                 ret = psp_v11_0_ring_stop(psp, ring_type);
 476                 if (ret) {
 477                         DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
 478                         return ret;
 479                 }
 480
 481                 /* Write low address of the ring to C2PMSG_102 */
 482                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 483                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 484                 /* Write high address of the ring to C2PMSG_103 */
 485                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 486                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 487
 488                 /* Write the ring initialization command to C2PMSG_101 */
 489                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 490                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 491
 492                 /* there might be handshake issue with hardware which needs delay */
 493                 mdelay(20);
 494
 495                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 496                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 497                                    0x80000000, 0x8000FFFF, false);
 498
 499         } else {
 500                 /* Wait for sOS ready for ring creation */
 501                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 502                                    0x80000000, 0x80000000, false);
 503                 if (ret) {
 504                         DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
 505                         return ret;
 506                 }
 507
 508                 /* Write low address of the ring to C2PMSG_69 */
 509                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 510                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 511                 /* Write high address of the ring to C2PMSG_70 */
 512                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 513                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 514                 /* Write size of ring to C2PMSG_71 */
 515                 psp_ring_reg = ring->ring_size;
 516                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 517                 /* Write the ring initialization command to C2PMSG_64 */
 518                 psp_ring_reg = ring_type;
 519                 psp_ring_reg = psp_ring_reg << 16;
 520                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 521
 522                 /* there might be handshake issue with hardware which needs delay */
 523                 mdelay(20);
 524
 525                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 526                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 527                                    0x80000000, 0x8000FFFF, false);
 528         }
 529
 530         return ret;
 531 }
 532
 533
 534 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 535                                  enum psp_ring_type ring_type)
 536 {
 537         int ret = 0;
 538         struct psp_ring *ring = &psp->km_ring;
 539         struct amdgpu_device *adev = psp->adev;
 540
 541         ret = psp_v11_0_ring_stop(psp, ring_type);
 542         if (ret)
 543                 DRM_ERROR("Fail to stop psp ring\n");
 544
 545         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 546                               &ring->ring_mem_mc_addr,
 547                               (void **)&ring->ring_mem);
 548
 549         return ret;
 550 }
 551
 552 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 553 {
 554         int ret;
 555         uint32_t offset;
 556         struct amdgpu_device *adev = psp->adev;
 557
 558         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 559
 560         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 561
 562         if (ret) {
 563                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 564                 return -EINVAL;
 565         }
 566
 567         /*send the mode 1 reset command*/
 568         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 569
 570         msleep(500);
 571
 572         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 573
 574         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 575
 576         if (ret) {
 577                 DRM_INFO("psp mode 1 reset failed!\n");
 578                 return -EINVAL;
 579         }
 580
 581         DRM_INFO("psp mode1 reset succeed \n");
 582
 583         return 0;
 584 }
 585
 586 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 587 {
 588         int ret;
 589         int i;
 590         uint32_t data_32;
 591         int max_wait;
 592         struct amdgpu_device *adev = psp->adev;
 593
 594         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 595         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
 596         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
 597
 598         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 599         for (i = 0; i < max_wait; i++) {
 600                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 601                                    0x80000000, 0x80000000, false);
 602                 if (ret == 0)
 603                         break;
 604         }
 605         if (i < max_wait)
 606                 ret = 0;
 607         else
 608                 ret = -ETIME;
 609
 610         DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
 611                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 612                   (ret == 0) ? "succeed" : "failed",
 613                   i, adev->usec_timeout/1000);
 614         return ret;
 615 }
 616
 617 /*
 618  * save and restore process
 619  */
 620 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 621 {
 622         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 623         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 624         struct amdgpu_device *adev = psp->adev;
 625         uint32_t p2c_header[4];
 626         uint32_t sz;
 627         void *buf;
 628         int ret, idx;
 629
 630         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 631                 DRM_DEBUG("Memory training is not supported.\n");
 632                 return 0;
 633         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 634                 DRM_ERROR("Memory training initialization failure.\n");
 635                 return -EINVAL;
 636         }
 637
 638         if (psp_v11_0_is_sos_alive(psp)) {
 639                 DRM_DEBUG("SOS is alive, skip memory training.\n");
 640                 return 0;
 641         }
 642
 643         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 644         DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 645                   pcache[0], pcache[1], pcache[2], pcache[3],
 646                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 647
 648         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 649                 DRM_DEBUG("Short training depends on restore.\n");
 650                 ops |= PSP_MEM_TRAIN_RESTORE;
 651         }
 652
 653         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 654             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 655                 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
 656                 ops |= PSP_MEM_TRAIN_SAVE;
 657         }
 658
 659         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 660             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 661               pcache[3] == p2c_header[3])) {
 662                 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 663                 ops |= PSP_MEM_TRAIN_SAVE;
 664         }
 665
 666         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 667             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 668                 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
 669                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 670         }
 671
 672         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 673                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 674                 ops |= PSP_MEM_TRAIN_SAVE;
 675         }
 676
 677         DRM_DEBUG("Memory training ops:%x.\n", ops);
 678
 679         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 680                 /*
 681                  * Long training will encroach a certain amount on the bottom of VRAM;
 682                  * save the content from the bottom of VRAM to system memory
 683                  * before training, and restore it after training to avoid
 684                  * VRAM corruption.
 685                  */
 686                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 687
 688                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 689                         DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 690                                   adev->gmc.visible_vram_size,
 691                                   adev->mman.aper_base_kaddr);
 692                         return -EINVAL;
 693                 }
 694
 695                 buf = vmalloc(sz);
 696                 if (!buf) {
 697                         DRM_ERROR("failed to allocate system memory.\n");
 698                         return -ENOMEM;
 699                 }
 700
 701                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 702                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 703                         ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 704                         if (ret) {
 705                                 DRM_ERROR("Send long training msg failed.\n");
 706                                 vfree(buf);
 707                                 drm_dev_exit(idx);
 708                                 return ret;
 709                         }
 710
 711                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 712                         adev->hdp.funcs->flush_hdp(adev, NULL);
 713                         vfree(buf);
 714                         drm_dev_exit(idx);
 715                 } else {
 716                         vfree(buf);
 717                         return -ENODEV;
 718                 }
 719         }
 720
 721         if (ops & PSP_MEM_TRAIN_SAVE) {
 722                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 723         }
 724
 725         if (ops & PSP_MEM_TRAIN_RESTORE) {
 726                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 727         }
 728
 729         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 730                 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 731                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 732                 if (ret) {
 733                         DRM_ERROR("send training msg failed.\n");
 734                         return ret;
 735                 }
 736         }
 737         ctx->training_cnt++;
 738         return 0;
 739 }
 740
 741 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
 742 {
 743         uint32_t data;
 744         struct amdgpu_device *adev = psp->adev;
 745
 746         if (amdgpu_sriov_vf(adev))
 747                 data = psp->km_ring.ring_wptr;
 748         else
 749                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 750
 751         return data;
 752 }
 753
 754 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 755 {
 756         struct amdgpu_device *adev = psp->adev;
 757
 758         if (amdgpu_sriov_vf(adev)) {
 759                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
 760                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 761                 psp->km_ring.ring_wptr = value;
 762         } else
 763                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 764 }
 765
 766 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 767 {
 768         struct amdgpu_device *adev = psp->adev;
 769         uint32_t reg_status;
 770         int ret, i = 0;
 771
 772         /*
 773          * LFB address which is aligned to 1MB address and has to be
 774          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 775          * register
 776          */
 777         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 778
 779         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 780                              0x80000000, 0x80000000, false);
 781         if (ret)
 782                 return ret;
 783
 784         /* Fireup interrupt so PSP can pick up the address */
 785         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 786
 787         /* FW load takes very long time */
 788         do {
 789                 msleep(1000);
 790                 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
 791
 792                 if (reg_status & 0x80000000)
 793                         goto done;
 794
 795         } while (++i < USBC_PD_POLLING_LIMIT_S);
 796
 797         return -ETIME;
 798 done:
 799
 800         if ((reg_status & 0xFFFF) != 0) {
 801                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",
 802                                 reg_status & 0xFFFF);
 803                 return -EIO;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 810 {
 811         struct amdgpu_device *adev = psp->adev;
 812         int ret;
 813
 814         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 815
 816         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 817                                      0x80000000, 0x80000000, false);
 818         if (!ret)
 819                 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
 820
 821         return ret;
 822 }
 823
 824 static const struct psp_funcs psp_v11_0_funcs = {
 825         .init_microcode = psp_v11_0_init_microcode,
 826         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 827         .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
 828         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 829         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 830         .ring_init = psp_v11_0_ring_init,
 831         .ring_create = psp_v11_0_ring_create,
 832         .ring_stop = psp_v11_0_ring_stop,
 833         .ring_destroy = psp_v11_0_ring_destroy,
 834         .mode1_reset = psp_v11_0_mode1_reset,
 835         .mem_training = psp_v11_0_memory_training,
 836         .ring_get_wptr = psp_v11_0_ring_get_wptr,
 837         .ring_set_wptr = psp_v11_0_ring_set_wptr,
 838         .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
 839         .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
 840 };
 841
 842 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 843 {
 844         psp->funcs = &psp_v11_0_funcs;
 845 }